Altera Parallel Flash Loader IP User Manual
2015.01.23
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quartus - Contains the Quartus II software
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Parallel Flash Loader IP Core User Guide
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This document describes how to instantiate the Parallel Flash Loader (PFL) IP core in your design,
programming flash memory, and configuring your FPGA from the flash memory.
FPGAs’ increasing density requires larger configuration storage. If your system contains a flash memory
device, you can use your flash memory as the FPGA configuration storage as well. You can use the PFL IP
core in Altera® MAX® Series (MAX II, MAX V and MAX 10 devices) or all other FPGAs to program
flash memory devices efficiently through the JTAG interface and to control configuration from the flash
memory device to the Altera FPGA.
Features
Use the PFL IP core to:
• Program Common Flash Interface (CFI) flash, quad Serial Peripheral Interface (SPI) flash, or NAND
flash memory devices with the device JTAG interface.
• Control Altera FPGA configuration from a CFI flash, quad SPI flash, or NAND flash memory device
for Arria series, Cyclone series, and Stratix series FPGA devices.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II
software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions,
require that you purchase a separate license for production use. You can use the OpenCore Plus feature to
evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and
performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license
number for any Altera product.
Figure 1: IP Core Installation Path
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2
Device Support
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
Device Support
This user guide focuses on implementing the PFL IP core in an Altera CPLD. The PFL IP core supports all
Altera FPGAs. You can implement the PFL IP core in an Arria®, Cyclone®, or Stratix® device family
FPGA to program flash memory or to configure other FPGAs.
Related Information
AN478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software
Provides more information about using the FPGA-based PFL IP core to program a flash memory device.
Supported Flash Memory Devices
The Quartus II software generates the PFL IP core logic for the flash programming bridge and FPGA
configuration.
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Table 1: CFI Flash Memory Devices Supported by PFL IP Core
If your CFI device is not in the following table, but is compatible with an Intel or Spansion CFI flash device, Altera
recommends selecting Define CFI Flash Device in the Quartus II software.
Manufacturer Product Family Data Width Density (Megabit) Device Name
(1)(2)
8 28F800C3
16 28F160C3
C3 16
32 28F320C3
64 28F640C3
Micron
32 28F320J3
8 or 16
64 28F640J3
J3
128 28F128J3
16 256 JS29F256J3
(1)
Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend
using this flash memory device. For more information about an alternative recommendation, see related
information.
(2)
The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory
devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.
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Supported Flash Memory Devices
3
Manufacturer Product Family Data Width Density (Megabit) Device Name
64 28F640P30
128 28F128P30
256 28F256P30
P30 16
512 28F512P30
1000 28F00AP30
2000 28F00BP30
128 28F128P33
256 28F256P33
512 28F512P33
P33 16
640 28F640P33
1000 28F00AP33
2000 28F00BP33
256 28F256M29EW
M29EW 8 or 16
512 28F512M29EW
1000 28F00AM29EW
(1)(2)
M28W160CT
M28W160CB
16
M29W160F7
M29W160FB
M29W320E
M29W 8 or 16
32
M29W320FT
M29W320FB
M29W640F
64
M29W640G
128 M29W128G
256 M29W256G
M29DW323DT
M29DW 8 or 16 32
M29DW323DB
(1)
Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend
using this flash memory device. For more information about an alternative recommendation, see related
information.
(2)
The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory
devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.
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Supported Flash Memory Devices
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Manufacturer Product Family Data Width Density (Megabit) Device Name
512 MT28GU512AAA1E
GC-0SIT
G18 16
1024 MT28GU01GAAA1E
GC-0SIT
M58BW16FT
16
32
M58BW16FB
M58BW
32 M58BW32FT
16 or 32 32 M58BW32FB
128 S29GL128P
GL-P
(3)
8 or 16
256 S29GL256P
512 S29GL512P
1024 S29GL01GP
16 S29AL016D
AL-D 8 or 16
32 S29AL032D
AL-J 8 or 16 16 S29AL016J
Spansion
AL-M 8 or 16 16 S29AL016M
(1)(2)
JL-H 8 or 16
32 S29JL032H
64 S29JL064H
WS-N 16 128 S29WS128N
128 S29GL128S
256 S29GL256S
GL-S 16
512 S29GL512S
1024 S29GL01GS
16 MX29LV160D
32 MX29LV320D
MX29LV 16
MX29LV640D
Macronix
64
MX29LV640E
128 MX29GL128E
MX29GL 16
256 MX29GL256E
(1)
Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend
using this flash memory device. For more information about an alternative recommendation, see related
information.
(2)
The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory
devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.
(3)
Supports page mode.
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Supported Flash Memory Devices
5
Manufacturer Product Family Data Width Density (Megabit) Device Name
EN29LV 16 16 EN29LV160B
Eon Silicon
Solution
EN29GL 16
32 EN29LV320B
128 EN29GL128
Table 2: Quad SPI Flash Memory Device Supported by PFL IP Core
Manufacturer Product Family Density (Megabit) Device Name
N25Q 1.8V
Micron
128 N25Q128
N25Q 3.3V
32 S25FL032P
Spansion FL-P
64 S25FL064P
128 S25FL129P
(1)(2)
(1)
Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend
using this flash memory device. For more information about an alternative recommendation, see related
information.
(2)
The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory
devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.
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Supported Flash Memory Devices
Manufacturer Product Family Density (Megabit) Device Name
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Macronix
MX25L
8
16
32
64
128
MX25L8035E
MX25L8036E
MX25L1635D
MX25L1635E
MX25L1636D
MX25L1636E
MX25L3225D
MX25L3235D
MX25L3235D
MX25L3236D
MX25L3237D
MX25L6436E
MX25L6445E
MX25L6465E
MX25L12836E
MX25L12845E
256
8
MX25U
16 MX25U1635E
32 MX25U3235E
64 MX25U6435E
Table 3: NAND Flash Memory Device Supported by PFL IP Core
Manufacturer Density (Megabit) Device Name
NAND512 1.8V
NAND512 3.0V
Micron 512
NAND512 3.3V
Micron(MT29)
Samsung 512 K9F1208R0C
MX25L12865E
MX25L25635E
MX25L25735E
MX25U8035
MX25U8035E
Toshiba 1000 TC58DVG02A1
Hynix 512 HY27US0812(1/2)B
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Related Information
Spansion Website
Supported Schemes and Features
The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP)
scheme. The PFL IP core supports configuration with FPGA on-chip data compression and data
encryption.
When you use compressed or encrypted configuration data for FPP configuration, the PFL IP core holds
one data byte for one, two, four, or eight DCLK cycles to ensure the DCLK frequency runs at the required
data rate as specified by the DCLK-to-DATA[] Ratio. The PFL IP core checks if the compression or
encryption feature is turned on in the configuration image before configuring in FPP mode. Hence, no
additional setting is required in the PFL IP core to specify whether the configuration file stored in the
flash memory device is a compressed or uncompressed image.
Note: When you turn on the enhanced bitstream compression feature, data encryption is disabled.
Supported Schemes and Features
7
You can program the Altera CPLDs and flash memory device in Programmer Object File (.pof), Jam
Standard Test and Programming Language (STAPL) Format File (.jam), or JAM Byte Code File (.jbc) file
format. The PFL IP core does not support Raw Binary File (.rbf) format.
Logic element (LE) usage varies with different PFL IP core and Quartus II software settings. To determine
the exact LE usage number, compile a PFL design with your settings using the Quartus II software.
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter
editor and generate files representing your IP variation. The parameter editor prompts you to specify an
IP variation name, optional ports, and output file generation options. The parameter editor generates a
top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You
can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
™
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
partner IP information on the Altera website.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, andor view links to documentation.
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Search and filter IP for your target device
Double-click to customize, right-click for information
8
Using the Parameter Editor
Figure 2: Quartus II IP Catalog
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Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Using the Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file generation options.
• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values
for specific applications.
• View port and parameter descriptions, and links to documentation.
• Generate testbench systems or example designs (where provided).
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View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
Legacy parameter
editors
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Figure 3: IP Parameter Editors
Functional Description
9
Functional Description
The PFL IP core allows you to program flash memory devices with Altera CPLDs through the JTAG
interface and provides the logic to control configuration from the flash memory device to the Altera
FPGA.
Programming Flash Memory
You can use the PFL IP core to program the following flash memory devices with JTAG interface:
• Programming CFI Flash
• Programming Quad SPI Flash
• Programming NAND Flash
Related Information
• Supported Flash Memory Devices on page 2
• Third-party Programmer Support on page 39
Provides more information about programming the flash memory using third-party tools.
Programming CFI Flash
Altera configuration devices support programming through the JTAG interface to allow in-system
programming and updates. However, standard flash memory devices do not support the JTAG interface.
You can use the JTAG interface in Altera CPLDs to indirectly program the flash memory device.
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The Altera CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode
brings the JTAG chain through the logic array instead of the Altera CPLD boundary-scan cells (BSCs).
Altera Corporation
Altera CPLD
CFI Flash
Memory
Altera
FPGA
Configuration Data
Common
Flash
Interface
PFL
Quartus II
Software
via JTAG
Altera FPGA Not Used
for Flash Programming
V
CC
V
CC
V
CC
P30/P33 CFI Flash
Altera CPLD
Altera FPGA
P30/P33 CFI Flash
16
16
10kΩ
10kΩ
10kΩ
ADDR[24..0]
NCE
NWE
NOE
DATA[15..0]
ADDR[24..0]
NCE
NWE
NOE
DATA[15..0]
flash_addr[24..0]
flash_nce
flash_nwe
flash_noe
flash_data[31..0]
fpga_conf_done
fpga_nstatus
fpga_nconfig
fpga_data
fpga_dclk
CONF_DONE
nSTATUS
nCONFIG
DATA
nCE
DCLK
10
Programming Quad SPI Flash
The PFL IP core provides JTAG interface logic to convert the JTAG stream provided by the Quartus II
software and to program the CFI flash memory devices connected to the CPLD I/O pins.
Figure 4: Programming the CFI Flash Memory With the JTAG Interface
Figure shows an Altera CPLD configured as a bridge to program the CFI flash memory device through the
JTAG interface.
The PFL IP core supports dual P30 or P33 CFI flash memory devices in burst read mode to achieve faster
configuration time. Two identical P30 or P33 CFI flash memory devices connect to the CPLD in parallel
using the same data bus, clock, and control signals. During FPGA configuration, the FPGA DCLK
frequency is four times faster than the flash_clk frequency.
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Figure 5: PFL IP core With Dual P30 or P33 CFI Flash Memory Devices
The flash memory devices in the dual P30 or P33 CFI flash solution must have the same memory density
from the same device family and manufacturer. In the Quartus II software version 9.1 SP1 onwards, dual
P30 or P33 flash support is available in the PFL IP core.
Programming Quad SPI Flash
You can also use the JTAG interface in Altera CPLDs to program a quad SPI flash memory device with
the PFL IP core.
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V
CC
V
CC
V
CC
Quad SPI Flash
Altera CPLD
Altera FPGA
10kΩ
10kΩ
10kΩ
flash_sck
flash_io0
flash_io1
flash_io2
flash_io3
flash_sck[3..0]
flash_io0[3..0]
flash_io1[3..0]
flash_io2[3..0]
flash_io3[3..0]
fpga_conf_done
fpga_nstatus
fpga_nconfig
fpga_data
fpga_dclk
CONF_DONE
nSTATUS
nCONFIG
DATA
nCE
DCLK
flash_ncs
flash_ncs[3..0]
Quad SPI Flash
flash_sck
flash_io0
flash_io1
flash_io2
flash_io3
flash_ncs
Quad SPI Flash
flash_sck
flash_io0
flash_io1
flash_io2
flash_io3
flash_ncs
Quad SPI Flash
flash_sck
flash_io0
flash_io1
flash_io2
flash_io3
flash_ncs
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Programming Quad SPI Flash
The PFL IP core instantiated in the Altera CPLD functions as a bridge between the CPLD JTAG program‐
ming interface and the quad SPI flash memory device interface that connects to the Altera CPLD I/O pins.
You can connect up to four identical quad SPI flashes in parallel to implement more configuration data
storage.
Note: When connecting quad SPI flashes in parallel, use identical flash memory devices with the same
memory density from the same device family and manufacturer. In the Quartus II software version
10.0 onwards, quad SPI flash support is available in the PFL IP core.
Figure 6: Programming Quad SPI Flash Memory Devices With the CPLD JTAG Interface
Figure shows an Altera CPLD functioning as a bridge to program the quad SPI flash memory device
through the JTAG interface. The PFL IP core supports multiple quad SPI flash programming of up to four
devices.
11
Related Information
Supported Flash Memory Devices on page 2
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Altera CPLD
NAND Flash
Memory
Altera
FPGA
Configuration Data
Open NAND
Flash
Interface
PFL
Quartus II
Software
using JTAG
Altera FPGA Not Used
for Flash Programming
Altera CPLD
Flash
Memory
Altera
FPGA
Flash
Interface
PFL
Passive Serial or
Fast Passive Parallel
Interface
12
Programming NAND Flash
Programming NAND Flash
You can use the JTAG interface in Altera CPLDs to program the NAND flash memory device with the
PFL IP core. The NAND flash memory device is a simpler device that has faster erase and write speed with
higher memory density in comparison with the CFI flash.
You can use the JTAG interface in Altera CPLDs to indirectly program the flash memory device. The
CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode brings the
JTAG chain through the logic array instead of the Altera CPLD BSCs. The PFL IP core provides JTAG
interface logic to convert the JTAG stream from the Quartus II software and to program the NAND flash
memory device that connects to the CPLD I/O pins.
Figure 7: Programming NAND Flash Memory Devices With the JTAG Interface
Figure shows an Altera CPLD functioning as a bridge to program the NAND flash memory device
through the JTAG interface.
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Controlling Altera FPGA Configuration from Flash Memory
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You can use the PFL logic in Altera CPLDs as a configuration controller for FPGA configuration. The PFL
logic in the CPLD determines when to start the configuration process, read the data from the flash
memory device, and configure the Altera FPGA in PS or FPP configuration scheme.
Figure 8: FPGA Configuration With Flash Memory Data
Figure shows the Altera CPLD as the configuration controller for the FPGA. The flash memory includes
CFI, quad SPI and NAND flash.
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Mapping PFL and Flash Address
You can use the PFL IP core to either program the flash memory devices, configure your FPGA, or both;
however, to perform both functions, create separate PFL functions if any of the following conditions apply
to your design:
• You want to use fewer LEs.
• You modify the flash data infrequently.
• You have JTAG or In-System Programming (ISP) access to the Altera CPLD.
• You want to program the flash memory device with non-Altera data. For example, the flash memory
device contains initialization storage for an ASSP. You can use the PFL IP core to program the flash
memory device with the initialization data and also create your own design source code to implement
the read and initialization control with the CPLD logic.
Creating Separate PFL Functions
To create separate PFL functions, follow these steps:
1. To create a PFL instantiation, select Flash Programming Only mode.
2. Assign the pins appropriately.
3. Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
4. To create another PFL instantiation, select Configuration Control Only mode.
5. Instantiate this configuration controller into your production design.
6. Whenever you must program the flash memory device, program the CPLD with the flash memory
device .pof and update the flash memory device contents.
7. Reprogram the CPLD with the production design .pof that includes the configuration controller.
13
Note:
All unused pins are set to ground by default. When programming the configuration flash memory
device through the CPLD JTAG pins, you must tri-state the FPGA configuration pins common to
the CPLD and the configuration flash memory device. You can use the
pfl_flash_access_request and pfl_flash_access_granted signals of the PFL block to tri-state
the correct FPGA configuration pins.
Related Information
• Mapping PFL and Flash Address on page 13
• Implementing Page in the Flash .pof on page 15
• Using Enhanced Bitstream Compression and Decompression on page 18
• Using Remote System Upgrade on page 20
Mapping PFL and Flash Address
The address connections between the PFL IP core and the flash memory device vary depending on the
flash memory device vendor and data bus width.
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23
22
21
-
-
2
1
0
PFL
address: 24 bits
23
22
21
-
-
2
1
0
Flash Memory
address: 24 bits
22
21
20
-
-
2
1
0
PFL
address: 23 bits
23
22
21
-
-
3
2
1
Flash Memory
address: 23 bits
23
22
21
-
-
2
1
0
PFL
address: 24 bits
22
21
20
-
-
1
0
D15
Flash Memory
address: 24 bits
14
Mapping PFL and Flash Address
Figure 9: Micron J3 Flash Memory in 8-Bit Mode
The address connection between the PFL IP core and the flash memory device are the same.
Figure 10: Micron J3, P30, and P33 Flash Memories in 16-Bit Mode
The flash memory addresses in Micron J3, P30, and P33 16-bit flash memory shift one bit down in
comparison with the flash addresses in the PFL IP core. The flash address in the Micron J3, P30, and P33
flash memory starts from bit 1 instead of bit 0.
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Figure 11: Spansion and Micron M28, M29 Flash Memory in 8-Bit Mode
The flash memory addresses in Spansion 8-bit flash shifts one bit up. Address bit 0 of the PFL IP core
connects to data pin D15 of the flash memory.
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22
21
20
-
-
2
1
0
PFL
address: 23 bits
22
21
20
-
-
2
1
0
Flash Memory
address: 23 bits
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Figure 12: Spansion and Micron M28, M29 Flash Memory in 16-Bit Mode
The address bit numbers in the PFL IP core and the flash memory device are the same.
Implementing Page in the Flash .pof
The PFL IP core stores configuration data in a maximum of eight pages in a flash memory block. Each
page holds the configuration data for a single FPGA chain. A single FPGA chain can contain more than
one FPGA. For an FPGA chain with multiple FPGAs, the PFL IP core stores multiple SRAM Object Files
(.sof) in the same page.
Implementing Page in the Flash .pof
15
The total number of pages and the size of each page depends on the density of the flash. These pages allow
you to store designs for different FPGA chains or different designs for the same FPGA chain in different
pages.
Use the generated .sof files to create a flash memory device .pof. When converting these .sof files to a .pof,
use the following address modes to determine the page address:
• Block mode—Allows you to specify the start and end addresses for the page.
• Start mode—Allows you to specify only the start address. You can locate the start address for each page
on an 8-KB boundary. If the first valid start address is 0×000000, the next valid start address is an
increment of 0×2000.
• Auto mode—Allows the Quartus II software to automatically determine the start address of the page.
The Quartus II software aligns the pages on a 128-KB boundary; for example, if the first valid start
address is 0×000000, the next valid start address is an increment of 0×20000.
Note:
If you are programming NAND flash, you must specify the NAND flash memory device reserved
block start address and the start address to ensure the files reside within a 128-KB boundary
Storing Option Bits
The PFL IP core requires you to allocate space in the flash memory device for option bits. The option bits
sector contains information about the start address for each page, the .pof version used for flash
programming, and the Page-Valid bits. You must specify the options bits sector address in the flash
memory device when converting the .sof files to a .pof and creating a PFL design.
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Storing Option Bits
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Table 4: Option Bits Sector Format
Offset address 0x80 stores the .pof version required for programming flash memory. This .pof version applies to all
eight pages of the configuration data. The PFL IP core requires the .pof version to perform a successful FPGA
configuration process.
Sector Offset Value
0x00–0x03 Page 0 start address
0x04–0x07 Page 1 start address
0x08–0x0B Page 2 start address
0x0C–0x0F Page 3 start address
0x10–0x13 Page 4 start address
0x14–0x17 Page 5 start address
0x18–0x1B Page 6 start address
0x1C–0x1F Page 7 start address
0x20–0x7F Reserved
(4)
0x80
.pof version
0x81–0xFF Reserved
The Quartus II Convert Programming File tool generates the information for the .pof version when you
convert the .sof files to .pof files.
The value for the .pof version generated by the Quartus II software version 7.1 onwards is 0x03. However,
if you turn on the enhanced bitstream-compression feature, the value for the .pof version is 0x04.
Caution:
Do not overwrite any information in the option bits sector to prevent the PFL IP core from
malfunctioning, and always store the option bits in unused addresses in the flash memory
device.
(4)
.pof version occupies only one byte in the option bits sector.
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Parallel Flash Loader IP Core User Guide
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Option Bits
Configuration Data (Page 2)
Configuration Data (Page 1)
Configuration Data (Page 0)
Page 2 Address + Page-Valid
Page 1 Address + Page-Valid
Page 0 Address + Page-Valid
End Address
0x000000
8 Bits
32 Bits
Page Start Address [19:13] Page-Valid
Bit 7...Bit 1 Bit 0
Page Start Address [27:20]
Bit 7...Bit 0
0x002000
0x002001
Page End Address [19:13]
Bit 7...Bit 1
0x002002
Page End Address [27:20]
Bit 7...Bit 0
0x002003
(For flash byte addressing mode)
UG-01082
2015.01.23
Storing Option Bits
Figure 13: Implementing Page Mode and Option Bits in the CFI Flash Memory Device
• The end address depends on the density of the flash memory device. For the address range for devices
with different densities, refer Byte Address Range table.
• You must specify the byte address for the option bits sector.
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Figure 14: Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits
Bits 0 to 12 for the page start address are set to zero and are not stored as option bits. The Page-Valid bits
indicate whether each page is successfully programmed. The PFL IP core programs the Page-Valid bits
after successfully programming the pages.
Table 5: Byte Address Range for CFI Flash Memory Devices with Different Densities
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CFI Device (Megabit) Address Range
8 0x0000000–0x00FFFFF
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18
Using Enhanced Bitstream Compression and Decompression
CFI Device (Megabit) Address Range
16 0x0000000–0x01FFFFF
32 0x0000000–0x03FFFFF
64 0x0000000–0x07FFFFF
128 0x0000000–0x0FFFFFF
256 0x0000000–0x1FFFFFF
512 0x0000000–0x3FFFFFF
1024 0x0000000–0x7FFFFFF
Using Enhanced Bitstream Compression and Decompression
The enhanced bitstream compression and decompression feature in the PFL IP core reduces the size of
the configuration file in the flash memory device. On average, you can reduce the file size by as much as
50% depending on the designs. When you turn on the enhanced bitstream compression feature, the PFL
IP core disables data encryption.
Table 6: Comparison Between Typical, Enhanced, and Double Compression
UG-01082
2015.01.23
FPGA Configuration Typical Bitstream
Compression Feature
FPGA on-chip bitstream
Yes No Yes
Enhanced Bitstream
Compression Feature
Double Compression
Technique
decompression enabled
PFL enhanced bitstream
No Yes Yes
decompression enabled
Typical configuration file size
35%–55% 45%–75% 40%–60%
reduction
(6)
(5)
Slow Moderate
Very fast
(7)
Not supported
PS configuration time Moderate
FPP configuration time Fast
Note: When using the PFL with compression, set the device MSEL pins set for compression or
decompression. When generating or converting a programming file, you can enable compression.
In the first few bytes during the generation of the programming file (with compression enabled), a
bit set notifies the PFL that the incoming files is a compressed file. The ×4 DCLK-to-data are
handled automatically in the PFL.
Note: For more information about the typical data compression feature, refer to the Configuration Data
Decompression section in the configuration chapter of the relevant device handbook.
(5)
(5)
The FPGA receives compressed bitstream which decreases the duration to transmit the bitstream to the
FPGA.
(6)
For FPP with on-chip bitstream decompression enabled, the DCLK frequency is ×2, ×4, or ×8 the data rate,
depending on the device. You can check the relationship of the DCLK and data rate in the FPP
Configuration section in the configuration chapter of the respective device handbook.
(7)
For FPP with enhanced bitstream decompression enabled, the DCLK frequency is ×1 the data rate.
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Parallel Flash Loader IP Core User Guide
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