Altera Nios II Custom User Manual
Nios II Custom Instruction User Guide
Nios II Custom Instruction
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-N2CSTNST-2.0
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Nios II Custom Instruction User Guide January 2011 Altera Corporation
Contents
Chapter 1. Nios II Custom Instruction Overview
Custom Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Implementing Custom Instruction Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Implementing Custom Instruction Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Custom Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Combinational Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Multicycle Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Extended Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Internal Register File Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
External Interface Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Chapter 2. Software Interface
Custom Instruction Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Built-in Functions and User-defined Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Custom Instruction Assembly Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Chapter 3. Implementing a Nios II Custom Instruction in SOPC Builder
Design Example: Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Implementing Custom Instruction Hardware in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Setting up the Design Environment for the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Opening the Component Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Adding the HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Configuring the Custom Instruction Signal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Setting Up the Custom Instruction Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Setting the Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Saving and Adding the Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Generating the System and Compiling in the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Accessing the Custom Instruction from Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Using the User-defined Custom Instruction Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Chapter 4. Implementing a Nios II Custom Instruction in Qsys
Design Example: Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Implementing Custom Instruction Hardware in Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Setting up the Design Environment for the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Opening the Component Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Adding the HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Configuring the Custom Instruction Signal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Setting Up the Custom Instruction Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Setting the Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Saving and Adding the Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Generating the System and Compiling in the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Accessing the Custom Instruction from Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Using the User-defined Custom Instruction Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Appendix A. Custom Instruction Templates
VHDL Custom Instruction Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Verilog HDL Custom Instruction Template Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
January 2011 Altera Corporation Nios II Custom Instruction User Guide
iv Contents
Appendix B. Custom Instruction Built-in Functions
Built-in Functions that Return a Void Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Built-in Functions that Return a Value of Type Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Built-in Functions that Return a Value of Type Float . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2
Built-in Functions that Return a Pointer Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2
Appendix C. Floating Point Custom Instructions
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Nios II Custom Instruction User Guide January 2011 Altera Corporation
1. Nios II Custom Instruction Overview
Nios II Embedded Processor
+
-
&
<<
>>
Result
A
Nios II
ALU
B
Custom
Logic
When you design a system that includes an Altera Nios II embedded processor, you
can accelerate time-critical software algorithms by adding custom instructions to the
Nios II processor instruction set. Custom instructions allow you to reduce a complex
sequence of standard instructions to a single instruction implemented in hardware.
You can use this feature for a variety of applications, for example, to optimize
software inner loops for digital signal processing (DSP), packet header processing,
and computation-intensive applications. In SOPC Builder, the Nios II parameter
editor provides a GUI to add custom instructions to the Nios II processor. In Qsys,
each custom instruction is a separate component in the Qsys system. You can add as
many as 256 custom instructions to your system.
In SOPC Builder, the custom instruction logic connects directly to the Nios II
arithmetic logic unit (ALU) as shown in Figure 1–1.
Figure 1–1. Custom Instruction Logic Connects to the Nios II ALU in SOPC Builder Systems
This chapter contains the following sections:
■ “Custom Instruction Overview”
■ “Custom Instruction Types” on page 1–3
For information about the custom instruction software interface, refer to Chapter 2,
January 2011 Altera Corporation Nios II Custom Instruction User Guide
Software Interface. For step-by-step instructions for implementing a custom
instruction, refer to Chapter 3, Implementing a Nios II Custom Instruction in SOPC
Builder or Chapter 4, Implementing a Nios II Custom Instruction in Qsys.
1–2 Chapter 1: Nios II Custom Instruction Overview
Combinatorial
Conduit interface to external
memory, FIFO, or other logic
Multi-cycle
result
Extended
Internal
Register File
[31..0]
done
dataa[31..0]
datab[31..0]
clk
clk_en
reset
start
n[7..0]
a[4..0]
readra
b[4..0]
readrb
c[4..0]
writerc
Combinational
Custom
Logic
Custom Instruction Overview
Custom Instruction Overview
Nios II custom instructions are custom logic blocks adjacent to the ALU in the
processor’s datapath. Custom instructions give you the ability to tailor the Nios II
processor core to meet the needs of a particular application. You can accelerate time
critical software algorithms by converting them to custom hardware logic blocks.
Because it is easy to alter the design of the FPGA-based Nios II processor, custom
instructions provide an easy way to experiment with hardware-software tradeoffs at
any point in the design process.
Implementing Custom Instruction Hardware
Figure 1–2 is a hardware block diagram of a Nios II custom instruction.
Figure 1–2. Hardware Block Diagram of a Nios II Custom Instruction
Nios II Custom Instruction User Guide January 2011 Altera Corporation
A Nios II custom instruction logic receives input on its
datab
ports, and drives out the result on its
provides a result based on the inputs provided by the Nios II processor.
The Nios II processor supports different types of custom instructions. Figure 1–2 lists
the additional ports that accommodate different custom instruction types. Only the
ports used for the specific custom instruction implementation are required.
Figure 1–2 also shows a conduit interface to external logic. The interface to external
logic allows you to include a custom interface to system resources outside of the
Nios II processor datapath.
result
dataa
port, or on its
dataa
and
port. The custom instruction logic
Chapter 1: Nios II Custom Instruction Overview 1–3
Custom Instruction Types
Implementing Custom Instruction Software
The Nios II custom instruction software interface is simple and abstracts the details of
the custom instruction from the software developer. For each custom instruction, the
Nios II Embedded Design Suite (EDS) generates a macro in the system header file,
system.h. You can use the macro directly in your C or C++ application code, and you
do not need to program assembly code to access custom instructions. Software can
also invoke custom instructions in Nios II processor assembly language.
For more information about the custom instruction software interface, refer to
Chapter 2, Software Interface.
Custom Instruction Types
Different types of custom instructions are available to meet the requirements of your
application. The type you choose determines the hardware interface for your custom
instruction.
Tab le 1– 1 shows the available custom instruction types, applications, and associated
hardware ports.
Table 1–1. Custom Instruction Types, Applications, and Hardware Ports (Part 1 of 2)
Type Application Hardware Ports
■
dataa[31:0]
Combinational Single clock cycle custom logic blocks.
Multicycle
Extended
Multi-clock cycle custom logic blocks of fixed or
variable durations.
Custom logic blocks that are capable of
performing multiple operations
■
datab[31:0]
■
result[31:0]
■
dataa[31:0]
■
datab[31:0]
■
result[31:0]
■
clk
■
clk_en (1)
■
start
■
reset
■
done
■
dataa[31:0]
■
datab[31:0]
■
result[31:0]
■
clk
■
clk_en (1)
■
start
■
reset
■
done
■
n[7:0]
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Custom Instruction Types
Table 1–1. Custom Instruction Types, Applications, and Hardware Ports (Part 2 of 2)
Type Application Hardware Ports
■
dataa[31:0]
■
datab[31:0]
■
result[31:0]
■
clk
■
clk_en
■
start
■
Internal register file
External interface
Note to Table 1–1:
(1) The
clk_en
needs to stall the custom instruction during execution.
input signal must be connected to the
Custom logic blocks that access internal register
files for input or output or both.
Custom logic blocks that interface to logic
outside of the Nios II processor’s datapath
clk_en
signals of all the registers in the custom instruction, in case the Nios II processor
reset
■
done
■
n[7:0]
■
a[4:0]
■
readra
■
b[4:0]
■
readrb
■
c[4:0]
■
writerc
Standard custom instruction ports, plus
user-defined interface to external logic.
The following sections discuss the basic functionality and hardware interface of each
of the custom instruction types listed in Table 1–1.
Combinational Custom Instructions
A combinational custom instruction is a logic block that completes its logic function in
a single clock cycle. Figure 1–3 shows a block diagram of a combinational custom
instruction.
Figure 1–3. Combinational Custom Instruction Block Diagram
dataa[31..0]
datab[31..0]
dataa
and
In Figure 1–3 the
results on the
result
port. Because the logic function completes in a single clock cycle,
a combinational custom instruction does not require control ports.
datab
Combinational result[31..0]
ports are inputs to the logic block, which drives the
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Chapter 1: Nios II Custom Instruction Overview 1–5
clk
T0 T1 T3T2 T4
dataa[ ]
datab[ ]
result[ ]
dataa[ ] valid
datab[ ] valid
result valid
Custom Instruction Types
Tab le 1– 2 describes the combination custom instruction ports.
Table 1–2. Combinational Custom Instruction Ports
Port Name Direction Required Description
dataa[31:0]
datab[31:0]
result[31:0]
Input No Input operand to custom instruction
Input No Input operand to custom instruction
Output Yes Result of custom instruction
The only required port for combinational custom instructions is the
dataa
and
datab
ports are optional. Include them only if the custom instruction
result
port. The
functionality requires input operands. If the custom instruction requires only a single
input port, use
dataa
.
Figure 1–4 shows the combinational custom instruction hardware port timing
diagram.
In Figure 1–4, the processor presents the input data on the dataa and datab ports on
the rising edge of the processor clock. The processor reads the result port on the
rising edge of the following processor clock cycle.
Figure 1–4. Combinational Custom Instruction Timing Diagram
The Nios II processor issues a combinational custom instruction speculatively; that is,
it optimizes execution by issuing the instruction before knowing whether it is
necessary, and ignores the result if it is not required. Therefore, a combinational
custom instruction must not have side effects. In particular, a combinational custom
instruction cannot have an external interface.
You can further optimize combinational custom instructions by implementing the
extended custom instruction. Refer to “Extended Custom Instructions” on page 1–7.
Multicycle Custom Instructions
Multicycle or sequential, custom instructions consist of a logic block that requires two
or more clock cycles to complete an operation. Additional control ports are required
for multicycle custom instructions, as shown in Table 1–3.
January 2011 Altera Corporation Nios II Custom Instruction User Guide
1–6 Chapter 1: Nios II Custom Instruction Overview
Custom Instruction Types
Figure 1–5 shows the multicycle custom instruction block diagram.
Figure 1–5. Multicycle Custom Instruction Block Diagram
dataa[31..0]
datab[31..0]
clk
clk_en
reset
start
Multi-cycle
Multicycle custom instructions complete in either a fixed or variable number of clock
cycles. For a custom instruction that completes in a fixed number of clock cycles, you
specify the required number of clock cycles at system generation. For a custom
instruction that requires a variable number of clock cycles, you instantiate the
and
done
ports. These ports participate in a handshaking scheme to determine when
the custom instruction execution is complete.
Tab le 1– 3 describes the multicycle custom instruction ports.
Table 1–3. Multicycle Custom Instruction Ports
Port Name Direction Required Description
clk
clk_en
reset
start
done
dataa[31:0]
datab[31:0]
result[31:0]
Input Yes System clock
Input Yes Clock enable
Input Yes Synchronous reset
Input No Commands custom instruction logic to start execution
Output No
Custom instruction logic indicates to the processor that execution is
complete
Input No Input operand to custom instruction
Input No Input operand to custom instruction
Output No Result of custom instruction
result[31..0]
done
start
As indicated in Tab le 1– 3, the
custom instructions. However, the
clk, clk_en
, and
reset
start, done, dataa, datab
ports are required for multicycle
, and
result
ports are
optional. Implement them only if the custom instruction functionality requires them.
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Chapter 1: Nios II Custom Instruction Overview 1–7
clk
dataa[]
datab[]
result[]
valid
valid
T0 T1 T3T2 T4 T5 T6
valid
done
clk_en
start
reset
Custom Instruction Types
Figure 1–6 shows the multicycle custom instruction hardware port timing diagram.
Figure 1–6. Multicycle Custom Instruction Timing Diagram
start
The processor asserts the active high
instruction execution. At this time, the
remain valid throughout the duration of the custom instruction execution. The
port on the first clock cycle of the custom
dataa
and
datab
ports have valid values and
start
signal is asserted for a single clock cycle.
For a fixed length multicycle custom instruction, after the instruction starts, the
processor waits the specified number of clock cycles, and then reads the value on the
result
data on the n
signal. For an n-cycle operation, the custom logic block must present valid
th
rising edge after the custom instruction begins execution.
For a variable length multicycle custom instruction, the processor waits until the
active high
clock edge on which
result
done
signal is asserted. The processor reads the
done
is asserted. The custom logic block must present data on the
port on the same clock cycle on which it asserts the
The Nios II system clock feeds the custom logic block’s
system’s master reset feeds the active high
when the whole Nios II system is reset.
The custom logic block must treat the active high
qualifier signal, ignoring
clk
You can further optimize multicycle custom instructions by implementing the
extended internal register file, or by creating external interface custom instructions.
Refer to “Extended Custom Instructions”, “Internal Register File Custom
Instructions” on page 1–9, or “External Interface Custom Instructions” on page 1–10.
Extended Custom Instructions
Extended custom instruction allows a single custom logic block to implement several
different operations. Extended custom instructions use an index to specify which
operation the logic block performs. The index can be as many as eight bits wide,
allowing a single custom logic block to implement as many as 256 different
operations.
while
clk_en
reset
port. The
clk_en
is deasserted.
result
done
clk
port, and the Nios II
reset
port on the same
signal.
port is asserted only
port as a conventional clock
January 2011 Altera Corporation Nios II Custom Instruction User Guide
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Custom Instruction Types
Figure 1–7 is a block diagram of an extended custom instruction with bit-swap,
byte-swap, and half-word swap operations.
Figure 1–7. Extended Custom Instruction with Swap Operations
Custom
dataa[31..0]
n[1..0]
bit-swap
operation
byte-swap
operation
half-word-swap
operation
Instruction
0
1
2
result[31..0]
The custom instruction in Figure 1–7 performs swap operations on data received at
the
dataa
port. It uses the two-bit-wide n port to select the output from a multiplexer,
determining which result is presented to the
result
port.
1 This logic is just a simple example, using a multiplexer on the output. You can
implement function selection based on an index in any way that is appropriate for
your application.
Extended custom instructions can be combinational or multicycle custom
instructions. To implement an extended custom instruction, simply add an n port to
your custom instruction logic. The bit width of the
n
port is a function of the number
of operations the custom logic block can perform.
Extended custom instructions occupy multiple custom instruction indices. For
example, the custom instruction illustrated in Figure 1–7 occupies 4 indices, because
is two bits wide. Therefore, when this instruction is implemented in a Nios II system,
256 - 4 = 252 available indices remain.
For information about the custom instruction index, refer to “Custom Instruction
Assembly Software Interface” on page 2–3.
All extended custom instruction port operations are identical to those for the
combinational and multicycle custom instructions, with the exception of the
n
which is not present in combinational and multicycle custom instructions. The
timing is the same as that of the
multicycle custom instruction, the processor presents the index value to the
the same rising edge of the clock at which
dataa
port. For example, for an extended variable
start
is asserted, and the n port remains
n
stable during execution of the custom instruction.
port,
n
port
port on
n
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Chapter 1: Nios II Custom Instruction Overview 1–9
dataa[31..0]
datab[31..0]
writerc
result[31..0]
Multiplier
Adder
DQ
CLR
Custom Instruction Types
Internal Register File Custom Instructions
The Nios II processor allows custom instruction logic to access its own internal
register file. This provides you the flexibility to specify if the custom instruction reads
its operands from the Nios II processor’s register file or from the custom instruction’s
own internal register file. In addition, a custom instruction can write its results to the
local register file rather than to the Nios II processor’s register file.
Custom instructions containing internal register files use
signals to determine if the custom instruction should use the internal register file or
the
dataa, datab
, and
result
signals. Ports a, b, and c specify the internal registers
from which to read or to which to write. For example, if
(specifying a read operation from the internal register), the
index to the internal register file. Ports
a, b
, and c are five bits each, allowing you to
address as many as 32 registers.
f For further details of Nios II custom instruction implementation, refer to the
Instruction Set Reference chapter of the Nios II Processor Reference Handbook.
Tab le 1– 4 lists the internal register file custom instruction-specific optional ports. Use
the optional ports only if the custom instruction functionality requires them.
Table 1–4. Internal Register File Custom Instruction Ports
Port Name Direction Required Description
If
readra
is high, the Nios II processor supplies
readra
readrb
writerc
a[4:0]
b[4:0]
c[4:0]
Input No
Input No
Input No
readra
if
indexed by
If
if
indexed by
If
if
is low, custom instruction logic reads the internal register file
a
.
readrb
is high, the Nios II processor supplies
readrb
is low, custom instruction logic reads the internal register file
b
.
writerc
writerc
is high, the Nios II processor writes to the
is low, custom instruction logic writes to the internal
register file indexed by
c
.
Input No Custom instruction internal register file index
Input No Custom instruction internal register file index
Input No Custom instruction internal register file index
readra, readrb
readra
is deasserted
a
signal value provides an
dataa
datab
, and
;
;
result
writerc
port;
Figure 1–8 shows a simple multiply-accumulate custom logic block.
Figure 1–8. Multiply-accumulate Custom Logic Block
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1–10 Chapter 1: Nios II Custom Instruction Overview
When
writerc
result
port. The accumulated value is stored in an internal register. Alternatively, the
processor can read the value on the
is deasserted, the Nios II processor ignores the value driven on the
result
port by asserting
Custom Instruction Types
writerc
. At the same
time, the internal register is cleared so that it is ready for a new round of multiply and
accumulate operations.
The
readra, readrb, writerc, a, b
custom instruction begins, the processor presents the new values of the
readrb, writerc, a, b
, and c ports on the rising edge of the processor clock. All six of
, and c ports behave similarly to
dataa
. When the
readra
,
these ports remain stable during execution of the custom instructions.
To determine how to handle the register file, custom instruction logic reads the active
high
readra, readrb
file indexes. When
the corresponding
writerc
result
is asserted, the custom instruction logic ignores the c port and writes to the
port.
, and
writerc
readra
a
or
or b port, and receives data from the
ports. The logic uses the a, b, and c ports as register
readrb
is asserted, the custom instruction logic ignores
dataa
or
datab
port. When
All other custom instruction port operations behave the same as for combinational
and multicycle custom instructions.
External Interface Custom Instructions
Nios II custom instructions allow you to add an interface to communicate with logic
outside of the processor’s datapath. At system generation, conduits propagate out to
the top level of the SOPC Builder or Qsys system, where external logic can access the
signals.
By enabling custom instruction logic to access memory external to the processor,
external interface custom instructions extend the capabilities of the custom instruction
logic.
Figure 1–9 shows a multicycle custom instruction that has an external memory
interface.
Figure 1–9. Custom Instructions Allow the Addition of an External Interface
dataa[31..0]
datab[31..0]
clk
clk_en
reset
start
Conduit Interface
result[31..0]
done
Nios II Custom Instruction User Guide January 2011 Altera Corporation
Chapter 1: Nios II Custom Instruction Overview 1–11
Custom Instruction Types
Custom instruction logic can perform various tasks such as storing intermediate
results or reading memory to control the custom instruction operation. The conduit
interface also provides a dedicated path for data to flow into or out of the processor.
For example, custom instruction logic with an external interface can feed data directly
from the processor’s register file to an external first-in first-out (FIFO) memory buffer.
January 2011 Altera Corporation Nios II Custom Instruction User Guide
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