Altera Nios Development Board Stratix II Edition User Manual

Nios Development Board Stratix II Edition

Reference Manual

101 Innovation Drive
San Jose, CA 95134
www.altera.com

Development Board Version 6XX-40019R
Document Version 1.3
Document Date May 2007

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

Part Number MNL-01001-1.3

ii Altera Corporation

Contents

About this Manual................................................................................... v

How to Contact Altera .............................................................................................................................. v

Typographic Conventions ...................................................................................................................... vi

Chapter 1. Overview

Features Overview ................................................................................................................................. 1–1

General Description ............................................................................................................................... 1–1

Factory-Programmed Reference Design ............................................................................................ 1–2

Chapter 2. Board Components

Component List ...................................................................................................................................... 2–1

Stratix II EP2S60 Device (U60) ............................................................................................................. 2–3

Push-Button Switches (SW0 - SW3) .................................................................................................... 2–4

Individual LEDs (D0 - D7) .................................................................................................................... 2–5

Seven-Segment LEDs (U8 & U9) ........................................................................................................ 2–5

SSRAM Chip (U74) ................................................................................................................................ 2–6

DDR SDRAM Chip (U63) ..................................................................................................................... 2–9

Flash Memory (U5) .............................................................................................................................. 2–11

Ethernet MAC/PHY (U4) & RJ45 Connector (RJ1) ........................................................................ 2–13

Serial Connector (J19) ......................................................................................................................... 2–15

Expansion Prototype Connectors (PROTO1 & PROTO2) ............................................................. 2–16

CompactFlash Connector (CON3) .................................................................................................... 2–23

PMC Connector (JH1 & JH2) .............................................................................................................. 2–26

Mictor Connector (J25) ........................................................................................................................ 2–29

Test Points (TP1 – TP8) ....................................................................................................................... 2–31

EPCS64 Serial Configuration Device (U69) ..................................................................................... 2–32

Configuration Controller Device (U3) .............................................................................................. 2–33

Configuration-Status LEDs ........................................................................................................... 2–33

Configuration & Reset Buttons .................................................................................................... 2–34

SW8 – CPU Reset ...................................................................................................................... 2–34

SW9 – Factory Config ............................................................................................................... 2–35

SW10 – Reset, Config ................................................................................................................ 2–35

Reset Distribution ........................................................................................................................... 2–36

Starting Configuration ................................................................................................................... 2–36

Factory & User Configurations .................................................................................................... 2–36

Configuration Process ................................................................................................................... 2–37

Flash Memory Partitions ............................................................................................................... 2–38

User Application Space ............................................................................................................ 2–38

User Configuration ................................................................................................................... 2–39

Factory Configuration .............................................................................................................. 2–39

Persistent Data ........................................................................................................................... 2–39

Altera Corporation iii

Contents Nios Development Board Stratix II Edition

JTAG Connectors (J24 & J5) ............................................................................................................... 2–39

JTAG Connector to FPGA (J24) ....................................................................................................2–39

JTAG Connector to EPM7256AE Device (J5) .............................................................................. 2–41

Clock Circuitry ..................................................................................................................................... 2–41

Power-Supply Circuitry ...................................................................................................................... 2–44

Appendix A. Restoring the Factory Configuration

Introduction ........................................................................................................................................... A–1

Reprogramming the Flash Memory ................................................................................................... A–1

Reprogramming the EPM7256AE Configuration Controller Device ............................................ A–1

Appendix B. Connecting to the Board via Ethernet

Introduction ........................................................................................................................................... B–1

Connecting the Ethernet Cable ........................................................................................................... B–1

Connecting the LCD Screen ........................................................................................................... B–2

Obtaining an IP Address ................................................................................................................ B–2

LAN Connection ....................................................................................................................... B–3

DHCP .................................................................................................................................... B–3

Static IP Address .................................................................................................................. B–3

Point–to–Point Connections .................................................................................................... B–4

Browsing to Your Board ...................................................................................................................... B–5

iv Altera Corporation

About this Manual

This manual provides details about the Nios® development board,
Stratix™ II Edition.

The table shows this document’s revision history.

Date & Version Description

May 2007, 1.3 ● Corrected Figure 2-21.

● Revised “How to Contact Altera”.

● Updated headers and footers.

October 2006, 1.2

October 2006, 1.1

June 2006, 1.0 First publication.

● Corrected pin assignments for proto2_io1, proto2_io29,

proto2_io30 in Table 2-12.

● Changed Reference Designator for FPGA from U62 to

U60.

● Corrected statement: LEDs D0 - D7 turn on when driven

to 0 (not 1).

How to Contact

For the most up-to-date information about Altera products, refer to the
following table.

Altera

Contact (1)

Technical support Website www.altera.com/support

Technical training Website www.altera.com/training

Product literature Website www.altera.com/literature

Altera literature services Email [e-mail]

Non-technical support (General)

(Software Licensing)

Note to table:

(1) You can also contact your local Altera sales office or sales representative.

Altera Corporation v
May 2007 Preliminary

Contact
Method

Email [e-mail]

Email [e-mail]

Email [e-mail]

Address

About this Manual

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.

The warning indicates information that should be read prior to starting or
continuing the procedure or processes

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

vi Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

1. Overview

Features Overview

General Description

The Nios Development Board, Stratix II Edition, provides a hardware
platform for developing embedded systems based on Altera® Stratix II
devices. The Nios Development Board, Stratix II Edition provides the
following features:

■ A Stratix II FPGA with more than 13,500 adaptive logic modules

(ALM) and 1.3 million bits of on-chip memory

■ 16 MBytes of flash memory

■ 2 MBytes of synchronous SRAM

■ 32 MBytes of double data rate (DDR) SDRAM

■ On-board logic for configuring the FPGA from flash memory

■ On-board Ethernet MAC/PHY device and RJ45 connector

■ Two 5V-tolerant expansion/prototype headers each with access to 41

FPGA user I/O pins

■ CompactFlash connector for Type I CompactFlash cards

■ 32-bit PMC Connector capable of 33 MHz and 66 MHz operation

■ Mictor connector for hardware and software debug

■ RS-232 DB9 serial port

■ Four push-button switches connected to FPGA user I/O pins

■ Eight LEDs connected to FPGA user I/O pins

■ Dual 7-segment LED display

■ JTAG connectors to Altera devices via Altera download cables

■ 50 MHz oscillator and zero-skew clock distribution circuitry

■ Power-on reset circuitry

The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to build systems using the Nios II processor
and to gain familiarity with the features included. Software designers can
use the pre-programmed Nios II processor design on the board to begin
prototyping software immediately.

This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board. A complete set of schematics, a physical layout database, and
GERBER files for the development board are installed with the Nios II
development tools in the <Nios II EDS install path>/documents directory.

Altera Corporation 1–1
May 2007

Overview

f See the Nios II Development Kit, Getting Started User Guide for instructions

on setting up the Nios development board and installing Nios II
development tools.

Figure 1–1shows a block diagram of the Nios development board.

Figure 1–1. Nios Development Board, Stratix II Edition Block Diagram

50MHz Oscillator

5.0 V Regulators

Mictor Connector

Proto 1 Expansion

Prototype Connector

Proto 2 Expansion

Prototype Connector

Dual Seven-Segment Display

Factory­Programmed
Reference
Design

JTAG Connector

Compact Flash

Push-button
Switches (4)

User LEDs (8)

16 Mbyte DDR SDRAM

2 Mbyte SSRAM

Vccint 1.2-V

Vccio 3.3-V

27

41

4

8

16

Stratix II

EP2S60

FPGA

EPCS64 Configuration

Device

Configuration

Controller

16 Mbyte Flash Memory

Ethernet

MAC/PHY

PMC Connector

RS-232

RJ45

Connector

When power is applied to the board, on-board logic configures the FPGA
using hardware configuration data stored in flash memory. After
successful configuration, the Nios II processor design in the FPGA wakes
up and begins executing boot code from flash memory.

The board is factory-programmed with a default reference design. This
reference design is a web server that delivers web pages via the Ethernet
port. For further information on the default reference design, refer to
Appendix B: Connecting to the Board via Ethernet.

1–2 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

Overview

In the course of development, you might overwrite or erase the flash
memory space containing the default reference design. Altera provides
the flash image for the default reference design so you can return the
board to its default state. Refer to Appendix A: Restoring the Factory
Configuration for more information.

Altera Corporation Reference Manual 1–3
May 2007 Nios Development Board Stratix II Edition

Overview

1–4 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

2. Board Components

Optional Power

Supply

Component List

This section introduces all the important components on the Nios
development board. See Figure 2–1 and Table 2–1 for component
locations and brief descriptions of all board features.

Figure 2–1. Nios Development Board

J24

U63

TP1–

TP8

U5

CPU Reset

(SW8)

JH1

JH2

U74

Reset, Config

CON3

(SW10)

(J11, J12, J13)

PROTO1

(J15, J16, J17)

PROTO2

Y2

D0–D7

SW0 –SW3

J26

D34

J25

Optional Power

Optional Power

U9

U8

Supply

Supply

Factory Config

(SW9)

J4

J19

RJ1

U4

LED

7

LED

6

J5

J27

U3

U69

U62

Table 2–1. Nios Development Board, Stratix II Edition Components & Interfaces

Board Designation Name Description

U60 Stratix II FPGA EP2S60F672C3N device.

User Interface

SW0 – SW3 Push-button switches Four momentary contact switches for user input to the

FPGA.

D0 – D7 Individual LEDs Eight individual LEDs driven by the FPGA.

U8, U9 Seven-segment LEDs Two seven-segment LEDs that display numeric

output from the FPGA.

Altera Corporation 2–1
May 2007

Board Components

Table 2–1. Nios Development Board, Stratix II Edition Components & Interfaces (Continued)

Board Designation Name Description

Memory

U74 SSRAM memory 2 MBytes of synchronous SRAM.

U5, LED7 Flash memory 16 MBytes of nonvolatile memory for use by both the

U63 DDR SDRAM memory 32 MBytes of DDR SDRAM.

FPGA and the configuration controller. LED7 lights
whenever the flash chip-enable is asserted.

Connections & Interfaces

U4, RJ1 Ethernet MAC/PHY 10/100 Ethernet MAC/PHY chip connected to an RJ-

J19 Serial connector RS-232 serial connector with 5V-tolerant buffers.

PROTO1 (J11, J12, J13) Expansion prototype

connector

PROTO2 (J15, J16, J17) Expansion prototype

connector

CON3 CompactFlash connector CompactFlash connector for memory expansion.

JH1, JH2 PMC connector Expansion connector for a PCI mezzanine card.

J25 Mictor connector Mictor connector providing access to 27 I/O pins on

TP1 – TP8 Test Points Test points providing access to eight FPGA I/O pins.

J24 JTAG connector JTAG connection to the FPGA allowing hardware

J5 JTAG connector

J27 EPCS configuration header Connects to the EPCS serial configuration device for

45 Ethernet connector.

Supports all RS-232 signals.

Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3 V and 5.0 V for use by a
daughter card.

Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3 V and 5.0 V for use by a daughter
card.

the FPGA. Allows debugging Nios II systems using a
First Silicon Solutions (FS2) debug probe.

configuration using the Quartus
software debug using the Nios II IDE.

JTAG connection to the MAX
controller.

in-system programming.

®

II software and

®

configuration

Configuration & Reset

U3 MAX Configuration controller Altera MAX EPM7256AE device used to configure

the FPGA from flash memory.

U69 Serial configuration device Altera EPCS64 low-cost serial configuration device to

configure the FPGA.

SW8 CPU Reset button Push-button switch to reboot the Nios II processor

configured in the FPGA.

2–2 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

Board Components

Table 2–1. Nios Development Board, Stratix II Edition Components & Interfaces (Continued)

Board Designation Name Description

SW9 Factory Config button Push-button switch to reconfigure the FPGA with the

factory-programmed reference design.

SW10 Reset, Config Push-button switch to reset the board.

LED0 – LED3, LED6 Configuration status LEDs LEDs that display the current configuration status of

the FPGA.

Clock Circuitry

Y2 Oscillator 50 MHz clock signal driven to FPGA.

J4 External clock input Connector to FPGA clock pin.

Power Supply

J26 DC power jack 16 V DC unregulated power source.

D34 Bridge rectifier Power rectifier allows for center-negative or center-

positive power supplies.

J28, J29, J30, J33 (and
more)

Optional Power Supply External power supply can be connected for high-

current applications.

The sections that follow describe each component in detail.

Stratix II EP2S60

U60 is a Stratix II FPGA in a 672-pin FineLine BGA® package. The part
number is EP2S60F672C3N. Table 2–2 lists the device features.

Device (U60)

Table 2–2. Stratix II EP2S60 Device Features

LEs 60,440

M4K Memory Blocks 255

Total RAM Bits 2,544,192

Embedded 18x18 Multiplier Blocks 144

Enhanced PLLs 4

Fast PLLs 8

User I/O Pins 718

Altera Corporation Reference Manual 2–3
May 2007 Nios Development Board Stratix II Edition

Board Components

f For Stratix II-related documentation including pin out data for the

The development board provides two separate methods for configuring
the FPGA:

®

1. Using the Quartus

II software running on a host computer, a
designer configures the device directly via an Altera download
cable connected to the FPGA JTAG header (J24).

2. When power is applied to the board, a configuration controller
device (U3) attempts to configure the FPGA with hardware
configuration data stored in flash memory. For more information on
the configuration controller, refer to “Configuration Controller

Device (U3)” on page 2–33.

EP2S60 device, see the Altera Stratix II literature page at
www.altera.com/literature/lit-stx2.jsp.

Push-Button
Switches (SW0 ­SW3)

SW0 – SW3 are momentary-contact push-button switches to provide
stimulus to designs in the FPGA. Refer to Figure 2–2. Each switch is
connected to an FPGA general-purpose I/O pin with a pull-up resistor as
shown in Ta bl e 2– 3. Each I/O pin perceives a logic 0 when its
corresponding switch is pressed.

Figure 2–2. Push-Button Switches (SW0 – SW3)

D0

SW0

D1

D2

SW1

D3

D4

SW2

D5

D6

D7

SW3

Table 2–3. Push Button Switches Pin Table

Button FPGA Pin Board Net Name

SW0 P4 user_pb0

SW1 P5 user_pb1

SW2 N6 user_pb2

SW3 N7 user_pb3

2–4 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

Board Components

Individual LEDs (D0 - D7)

Seven-Segment LEDs (U8 & U9)

This Nios II development board provides eight individual LEDs
connected to the FPGA. Refer to “Push-Button Switches (SW0 - SW3)” on

page 2–4. D0 – D7 are connected to general purpose I/O pins on the

FPGA as shown in Tab le 2 –4 . When a pin drives logic 0, the
corresponding LED turns on.

Table 2–4. LED Pin Table

LED FPGA Pin Board Net Name

D0 W15 pld_led0

D1 V14 pld_led1

D2 AD17 pld_led2

D3 AA17 pld_led3

D4 V16 pld_led4

D5 AB17 pld_led5

D6 AD18 pld_led6

D7 V17 pld_led7

U8 and U9 connect to the FPGA, and each segment is individually
controlled by a general-purpose I/O pin. Refer to Figure 2–3. When a pin
drives logic 0, the corresponding U8 and U9 LED turns on. See Table 2–5
for pin-out details.

Figure 2–3. Dual Seven-Segment Display

U8 U9

a

b

f

g

c

e

d

Altera Corporation Reference Manual 2–5
May 2007 Nios Development Board Stratix II Edition

a

b

f

g

c

e

d

dp

dp

Board Components

Table 2–5. Dual Seven-Segment Display

FPGA Pin U8 & U9 Pin Pin Function Board Net Name

U8

L8 10 a hex_0A

L9 9 b hex_0B

M7 8 c hex_0C

M85dhex_0D

M54ehex_0E

M6 2 f hex_0F

N43ghex_0G

N5 7 dp hex_0DP

U9

K8 10 a hex_1A

K99bhex_1B

L4 8 c hex_1C

L5 5 d hex_1D

M34ehex_1E

M4 2 f hex_1F

L6 3 g hex_1G

L7 7 dp hex_1DP

SSRAM Chip (U74)

U74 is a 32-bit, 2 MByte Cypress SSRAM chip. The part number is
CY7C1380C-167AC or CY7C1380D-167AXC. The chip is rated for
synchronous accesses up to 167 MHz. U74 connects to the FPGA so it can
be used by a Nios II embedded processor as general-purpose memory.
The factory-programmed Nios II reference design identifies the SSRAM
devices in its address space as a contiguous 2 MByte, 32-bit word,
zero-wait-state main memory.

2–6 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

Board Components

Table 2–6 shows all connections between the FPGA and the SSRAM chip.

Table 2–6. SSRAM Pin Table

FPGA Pin U74 Pin Pin Function Board Net Name

G16 37 A0 ssram_a0

G17 36 A1 ssram_a1

E26 35 A2 ssram_a2

E25 34 A3 ssram_a3

E24 33 A4 ssram_a4

E23 32 A5 ssram_a5

F26 38 NC/A19 ssram_a6

F25 39 NC/A20 ssram_a7

C17 42 A6 ssram_a8

C18 43 A7 ssram_a9

C19 44 A8 ssram_a10

C20 45 A9 ssram_a11

G26 46 A10 ssram_a12

G25 47 A11 ssram_a13

G24 48 A12 ssram_a14

G23 49 A13 ssram_a15

G21 50 A14 ssram_a16

G20 81 A15 ssram_a17

H26 82 A16 ssram_a18

H25 99 A17 ssram_a19

H24 100 A18 ssram_a20

B16 85 ADSC_N ssram_adsc_n

H23 93 BE_n0 ssram_be_n0

J23 94 BE_n1 ssram_be_n1

K24 95 BE_n2 ssram_be_n2

F16 96 BE_n3 ssram_be_n3

C16 98 CE1_n ssram_ce1_n

A17 52 D0 ssram_d0

A18 53 D1 ssram_d1

A19 56 D2 ssram_d2

A20 57 D3 ssram_d3

B17 58 D4 ssram_d4

Altera Corporation Reference Manual 2–7
May 2007 Nios Development Board Stratix II Edition

Board Components

Table 2–6. SSRAM Pin Table (Continued)

FPGA Pin U74 Pin Pin Function Board Net Name

B18 59 D5 ssram_d5

B19 62 D6 ssram_d6

B20 63 D7 ssram_d7

B24 68 D8 ssram_d8

C22 69 D9 ssram_d9

B22 72 D10 ssram_d10

C21 73 D11 ssram_d11

E18 74 D12 ssram_d12

D18 75 D13 ssram_d13

E17 78 D14 ssram_d14

D17 79 D15 ssram_d15

F23 18 D24 ssram_d16

F22 19 D25 ssram_d17

F21 22 D26 ssram_d18

B23 23 D27 ssram_d19

D25 24 D28 ssram_d20

F24 25 D29 ssram_d21

H21 28 D30 ssram_d22

F19 29 D31 ssram_d23

B21 2 D16 ssram_d24

A21 3 D17 ssram_d25

A22 6 D18 ssram_d26

A24 7 D19 ssram_d27

C26 8 D20 ssram_d28

C25 9 D21 ssram_d29

J22 12 D22 ssram_d30

J21 13 D23 ssram_d31

J26 86 OE_n ssram_oe_n

F17 87 WE_n ssram_we_n

J25 84 ADSP_n ssram_adsp_n

J24 83 ADV_n ssram_adv_n

L25 97 CE2 ssram_ce2

L24 92 CE3_n ssram_ce3_n

2–8 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007

Board Components

Table 2–6. SSRAM Pin Table (Continued)

FPGA Pin U74 Pin Pin Function Board Net Name

G18 88 GW_n ssram_gw_n

A12 89 CLK sram_clk

The following pins on U74 have fixed connections, which restricts the
usable modes of operation:

■ MODE is pulled low to enable Linear Burst

■ ZZ is pulled low to leave the chip enabled

■ GLOBALW_n is pulled high to disable the global write.This is the

default behavior for GLOBALW_n that can be changed.

■ CE2 and CE3_n are wired high and low respectively to be enabled

and to make CE1_n the master chip enable.This is the default
behavior for GLOBALW_n that can be changed.

f See www.cypress.com for detailed information about the SSRAM chip.

DDR SDRAM Chip (U63)

U63 is a Micron DDR SDRAM chip. The part number is MT46V16M16P­6T. The DDR SDRAM pins are connected to the FPGA as shown in

Table 2–7. Altera provides a DDR SDRAM controller that allows a Nios II

processor to access the DDR SDRAM device as a large, linearly­addressable memory.

Table 2–7. DDR SDRAM Pin Table

FPGA Pin U63 Pin Board Net Name

DD9 2 sdram_dq0

D8 4 sdram_dq1

C8 5 sdram_dq2

A9 7 sdram_dq3

B11 8 sdram_dq4

C11 10 sdram_dq5

A10 11 sdram_dq6

D10 13 sdram_dq7

A5 54 sdram_dq8

B5 56 sdram_dq9

D6 57 sdram_dq10

A6 59 sdram_dq11

A8 60 sdram_dq12

Altera Corporation Reference Manual 2–9
May 2007 Nios Development Board Stratix II Edition