About this Manual................................................................................... v
How to Contact Altera .............................................................................................................................. v
Typographic Conventions ...................................................................................................................... vi
Chapter 1. Overview
Features Overview ................................................................................................................................. 1–1
General Description ............................................................................................................................... 1–1
Component List ...................................................................................................................................... 2–1
Cyclone II EP2C35 Device (U62) ......................................................................................................... 2–3
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital LettersKeyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.
1., 2., 3., and
a., b., c., etc.
● •Bullets are used in a list of items when the sequence of the items is not important.
■
v The checkmark indicates a procedure that consists of one step only.
viReference ManualAltera Corporation
Nios Development Board Cyclone II Edition May 2007
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Visual CueMeaning
1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
The caution indicates required information that needs special consideration and
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procedure or process.
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
About this Manual
Altera Corporation Reference Manualvii
May 2007Nios Development Board Cyclone II Edition
About this Manual
viiiReference ManualAltera Corporation
Nios Development Board Cyclone II Edition May 2007
1. Overview
Features
Overview
The Nios Development Board, Cyclone II Edition, provides a hardware
platform for developing embedded systems based on Altera® Cyclone II
devices. The Nios Development Board, Cyclone II Edition provides the
following features:
■Nios Development Board Cyclone II EditionA Cyclone II
EP2C35F672C5 or EP2C35F672C5N FPGA with 33,216 logic elements
(LE) and 483,840 bits of on-chip memory
■16 MBytes of flash memory
■2 MBytes of synchronous SRAM
■32 MBytes of double data rate (DDR) SDRAM
■On-board logic for configuring the FPGA from flash memory
■On-board Ethernet MAC/PHY device and RJ45 connector
■Two 5.0 V-tolerant expansion/prototype headers each with access to
41 FPGA user I/O pins
■CompactFlash connector for Type I CompactFlash cards
■32-bit PMC Connector capable of 33 MHz and 66 MHz operation
■Mictor connector for hardware and software debug
■RS-232 DB9 serial port
■Four push-button switches connected to FPGA user I/O pins
■Eight LEDs connected to FPGA user I/O pins
■Dual 7-segment LED display
■JTAG connectors to Altera devices via Altera download cables
■50 MHz oscillator and zero-skew clock distribution circuitry
■Power-on reset circuitry
General
Description
Altera Corporation 1–1
May 2007
The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to build systems using the Nios II processor
and to gain familiarity with the features included. Software designers can
use the pre-programmed Nios II processor design on the board to begin
prototyping software immediately.
This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board. A complete set of schematics, a physical layout database, and
GERBER files for the development board are installed with the Nios II
development tools in the <Nios II EDS install path>/documents directory.
Overview
fSee the Nios II Development Kit, Getting Started User Guide for instructions
on setting up the Nios development board and installing Nios II
development tools.
Figure 1–1shows a block diagram of the Nios development board.
Figure 1–1. Nios Development Board, Cyclone II Edition Block Diagram
Proto 1 Expansion
Prototype Connector
Proto 2 Expansion
Prototype Connector
Dual Seven-Segment Display
FactoryProgrammed
Reference
50MHz Oscillator
5.0 V Regulators
JTAG Connector
Mictor Connector
Compact Flash
Push-button
Switches (4)
User LEDs (8)
16 Mbyte DDR SDRAM
2 Mbyte SSRAM
Vccint 1.2-V
Vccio 3.3-V
27
41
4
8
16
Cyclone II
EP2C35
FPGA
EPCS64 Configuration
Device
Configuration
Controller
16 Mbyte Flash Memory
Ethernet
MAC/PHY
PMC Connector
RS-232
RJ45
Connector
When power is applied to the board, on-board logic configures the FPGA
using hardware configuration data stored in flash memory. After
successful configuration, the Nios II processor design in the FPGA wakes
up and begins executing boot code from flash memory.
Design
The board is factory-programmed with a default reference design. This
reference design is a web server that delivers web pages via the Ethernet
port. For further information on the default reference design, refer to
Appendix B: Connecting to the Board via Ethernet.
1–2Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Overview
In the course of development, you might overwrite or erase the flash
memory space containing the default reference design. Altera provides
the flash image for the default reference design so you can return the
board to its default state. Refer to Appendix A: Restoring the Factory Configuration for more information.
Altera Corporation Reference Manual1–3
May 2007Nios Development Board Cyclone II Edition
Overview
1–4Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
2. Board Components
Optional Power
Supply
Component List
This section introduces all the important components on the Nios
development board. See Figure 2–1 and Table 2–1 for component
locations and brief descriptions of all board features.
Figure 2–1. Nios Development Board
J24
U63
TP1–
TP8
U5
CPU Reset
(SW8)
JH1
JH2
U74
Reset, Config
CON3
(SW10)
(J11, J12, J13)
PROTO1
(J15, J16, J17)
PROTO2
Y2
D0–D7
SW0 –SW3
J26
D34
J25
Optional Power
Optional Power
U9
U8
Supply
Supply
Factory Config
(SW9)
J4
J19
RJ1
U4
LED
7
LED
6
J5
J27
U3
U69
U62
Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces
Board DesignationNameDescription
U62Cyclone II FPGAEP2C35F672C5 or EP2C35F672C5N device.
User Interface
SW0 – SW3Push-button switchesFour momentary contact switches for user input to the
FPGA.
D0 – D7Individual LEDsEight individual LEDs driven by the FPGA.
U8, U9Seven-segment LEDsTwo seven-segment LEDs that display numeric
output from the FPGA.
Altera Corporation 2–1
May 2007
Board Components
Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued)
Board DesignationNameDescription
Memory
U74SSRAM memory2 Mbytes of synchronous SRAM.
U5, LED7Flash memory16 Mbytes of nonvolatile memory for use by both the
U63DDR SDRAM memory32 Mbytes of DDR SDRAM.
FPGA and the configuration controller. LED7 lights
whenever the flash chip-enable is asserted.
Connections & Interfaces
U4, RJ1Ethernet MAC/PHY10/100 Ethernet MAC/PHY chip connected to an RJ-
J19Serial connectorRS-232 serial connector with 5 V-tolerant buffers.
PROTO1 (J11, J12, J13) Expansion prototype
connector
PROTO2 (J15, J16, J17) Expansion prototype
connector
CON3CompactFlash connectorCompactFlash connector for memory expansion.
JH1, JH2PMC connectorExpansion connector for a PCI mezzanine card.
J25Mictor connector Mictor connector providing access to 27 I/O pins on
J24JTAG connectorJTAG connection to the FPGA allowing hardware
J5JTAG connector
J27EPCS configuration headerConnects to the EPCS serial configuration device for
45 Ethernet connector.
Supports all RS-232 signals.
Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3V and 5.0V for use by a daughter
card.
Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3V and 5.0V for use by a daughter
card.
the FPGA. Allows debugging Nios II systems using a
First Silicon Solutions (FS2) debug probe.
configuration using the
®
Quartus
Nios II IDE.
JTAG connection to the MAX
controller.
in-system programming.
II software and software debug using the
®
configuration
Configuration & Reset
U3MAX Configuration controller Altera MAX EPM7256AE device used to configure
the FPGA from flash memory.
U69Serial configuration deviceAltera EPCS64 low-cost serial configuration device to
configure the FPGA.
SW8CPU Reset buttonPush-button switch to reboot the Nios II processor
configured in the FPGA.
2–2Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued)
Board DesignationNameDescription
SW9Factory Config buttonPush-button switch to reconfigure the FPGA with the
factory-programmed reference design.
SW10Reset, ConfigPush-button switch to reset the board.
LED0 – LED3, LED6Configuration status LEDsLEDs that display the current configuration status of
the FPGA.
Clock Circuitry
Y2Oscillator50 MHz clock signal driven to FPGA.
J4External clock inputConnector to FPGA clock pin.
Power Supply
J26DC power jack16V DC unregulated power source.
D34Bridge rectifierPower rectifier allows for center-negative or center-
positive power supplies.
J28, J29, J30, J33 (and
more)
Optional Power SupplyExternal power supply can be connected for high-
current applications.
The sections that follow describe each component in detail.
Cyclone II
U62 is a Cyclone II FPGA in a 672-pin FineLine BGA® package.
Depending on the board revision, the part number is EP2C35F672C5 or
EP2C35 Device
EP2C35F672C5N. Table 2–2 lists the device features.
(U62)
Table 2–2. Cyclone II EP2C35 Device Features
LEs 33,216
M4K Memory Blocks 105
Total RAM Bits 483,840
Embedded 18x18 Multiplier Blocks35
PLLs4
User I/O Pins475
1Preproduction builds of the Nios Development Board, Cyclone
II Editon have an EP2C35F6728ES device.
Altera Corporation Reference Manual2–3
May 2007Nios Development Board Cyclone II Edition
Board Components
fFor Cyclone II-related documentation including pin out data for the
The development board provides two separate methods for configuring
the FPGA:
®
1.Using the Quartus
II software running on a host computer, a
designer configures the device directly via an Altera download
cable connected to the FPGA JTAG header (J24).
2.When power is applied to the board, a configuration controller
device (U3) attempts to configure the FPGA with hardware
configuration data stored in flash memory. For more information on
the configuration controller, refer to “Configuration Controller
Device (U3)” on page 2–33.
EP2C35 device, see the Altera Cyclone II literature page at
www.altera.com/literature/lit-cyc2.jsp.
Push-Button
Switches (SW0 SW3)
SW0 – SW3 are momentary-contact push-button switches to provide
stimulus to designs in the FPGA. Refer to Figure 2–2. Each switch is
connected to an FPGA general-purpose I/O pin with a pull-up resistor as
shown in Ta bl e 2– 3. Each I/O pin perceives a logic 0 when its
corresponding switch is pressed.
Figure 2–2. Push-Button Switches (SW0 – SW3)
D0
SW0
D1
D2
SW1
D3
D4
SW2
D5
D6
D7
SW3
Table 2–3. Push Button Switches Pin Table
ButtonFPGA PinBoard Net Name
SW0Y11user_pb0
SW1AA10user_pb1
SW2AB10user_pb2
SW3AE6user_pb3
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Nios Development Board Cyclone II EditionMay 2007
Board Components
Individual LEDs
(D0 - D7)
Seven-Segment
LEDs (U8 & U9)
This Nios development board provides eight individual LEDs connected
to the FPGA. Refer to “Push-Button Switches (SW0 - SW3)” on page 2–4.
D0 – D7 are connected to general purpose I/O pins on the FPGA as
shown in Ta bl e 2– 4. When a pin drives logic 0, the corresponding LED
turns on.
Table 2–4. LED Pin Table
LEDFPGA PinBoard Net Name
D0AC10pld_led0
D1W11pld_led1
D2W12pld_led2
D3AE8pld_led3
D4AF8pld_led4
D5AE7pld_led5
D6AF7pld_led6
D7AA11pld_led7
U8 and U9 connect to the FPGA, and each segment is individually
controlled by a general-purpose I/O pin. Refer to Figure 2–3. When a pin
drives logic 0, the corresponding U8 and U9 LED turns on. See Table 2–5
for pin-out details.
Figure 2–3. Dual Seven-Segment Display
U8U9
a
b
f
g
c
e
d
Altera Corporation Reference Manual2–5
May 2007Nios Development Board Cyclone II Edition
a
b
f
g
c
e
d
dp
dp
Board Components
Table 2–5. Dual Seven-Segment Display
FPGA PinU8 & U9 Pin Pin Function Board Net Name
U8
AE1310ahex_0A
AF139bhex_0B
AD128chex_0C
AE125dhex_0D
AA124ehex_0E
Y122fhex_0F
V113ghex_0G
U127dphex_0DP
U9
V1410ahex_1A
V139bhex_1B
AD118chex_1C
AE115dhex_1D
AE104ehex_1E
AF102fhex_1F
AD103ghex_1G
AC117dphex_1DP
SSRAM Chip
(U74)
U74 is a 32-bit, 2 Mbyte Cypress SSRAM chip. Depending on the board
revision, the part number is CY7C1380C-167AC or CY7C1380D-167AXC.
The chip is rated for synchronous accesses up to 167 MHz. U74 connects
to the FPGA so it can be used by a Ni os II emb edded processor as generalpurpose memory. The factory-programmed Nios II reference design
identifies the SSRAM devices in its address space as a contiguous 2
Mbyte, 32-bit-wide, zero-wait-state main memory.
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Board Components
Table 2–6 shows all connections between the FPGA and the SSRAM chip.
Table 2–6. SSRAM Pin Table
FPGA Pin U74 Pin Pin Function Board Net Name
AB337A0ssram_a0
AB436A1ssram_a1
G535A2ssram_a2
G634A3ssram_a3
B233A4ssram_a4
B332A5ssram_a5
C238NC/A19ssram_a6
C339NC/A20ssram_a7
L942A6ssram_a8
F743A7ssram_a9
L1044A8ssram_a10
J545A9ssram_a11
L446A10ssram_a12
C647A11ssram_a13
A448A12ssram_a14
B449A13ssram_a15
A550A14ssram_a16
B581A15ssram_a17
B682A16ssram_a18
A699A17ssram_a19
C4100A18ssram_a20
G985ADSC_Nssram_adsc_n
M393BE_n0ssram_be_n0
M294BE_n1ssram_be_n1
M495BE_n2ssram_be_n2
M596BE_n3ssram_be_n3
C798CE1_nssram_ce1_n
L252D0ssram_d0
L353D1ssram_d1
L756D2ssram_d2
L657D3ssram_d3
N958D4ssram_d4
Altera Corporation Reference Manual2–7
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–6. SSRAM Pin Table (Continued)
FPGA Pin U74 Pin Pin Function Board Net Name
P959D5ssram_d5
K162D6ssram_d6
K263D7ssram_d7
K468D8ssram_d8
K369D9ssram_d9
J272D10ssram_d10
J173D11ssram_d11
H274D12ssram_d12
H175D13ssram_d13
J378D14ssram_d14
J479D15ssram_d15
H318D24ssram_d16
H419D25ssram_d17
G122D26ssram_d18
G223D27ssram_d19
F224D28ssram_d20
F125D29ssram_d21
K828D30ssram_d22
K729D31ssram_d23
G42D16ssram_d24
G33D17ssram_d25
K66D18ssram_d26
K57D19ssram_d27
E28D20ssram_d28
E19D21ssram_d29
J812D22ssram_d30
J713D23ssram_d31
D586OE_nssram_oe_n
J987WE_nssram_we_n
D784ADSP_nssram_adsp_n
H1083ADV_nssram_adv_n
B797CE2ssram_ce2
A792CE3_nssram_ce3_n
2–8Reference ManualAltera Corporation
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Board Components
Table 2–6. SSRAM Pin Table (Continued)
FPGA Pin U74 Pin Pin Function Board Net Name
K988GW_nssram_gw_n
E589CLKsram_clk
The following pins on U74 have fixed connections, which restricts the
usable modes of operation:
■MODE is pulled low to enable Linear Burst
■ZZ is pulled low to leave the chip enabled
■GLOBALW_n is pulled high to disable the global write
■CE2 and CE3_n are wired high and low respectively to be enabled
and to make CE1_n the master chip enable
fSee www.cypress.com for detailed information about the SSRAM chip.
DDR SDRAM
Chip (U63)
U63 is a Micron DDR SDRAM chip. Depending on the board revision, the
part number is MT46V16M16TG or MT46V16M16P-6T. The DDR
SDRAM pins are connected to the FPGA as shown in Table 2–7. Altera
provides a DDR SDRAM controller that allows a Nios II processor to
access the DDR SDRAM device as a large, linearly-addressable memory.
Table 2–7. DDR SDRAM Pin Table
FPGA PinU63 PinBoard Net Name
R22sdram_dq0
R34sdram_dq1
R45sdram_dq2
P77sdram_dq3
P68sdram_dq4
T210sdram_dq5
T311sdram_dq6
R613sdram_dq7
W254sdram_dq8
W156sdram_dq9
U657sdram_dq10
U759sdram_dq11
U560sdram_dq12
Y162sdram_dq13
Altera Corporation Reference Manual2–9
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–7. DDR SDRAM Pin Table (Continued)
FPGA PinU63 PinBoard Net Name
V563sdram_dq14
V665sdram_dq15
P316sdram_dqs0
W451sdram_dqs1
U220sdram_dm0
AA147sdram_dm1
T629sdram_a0
V230sdram_a1
R831sdram_a2
W332sdram_a3
R535sdram_a4
U1036sdram_a5
P437sdram_a6
V138sdram_a7
T939sdram_a8
T840sdram_a9
AA228sdram_a10
T1041sdram_a11
U342sdram_a12
U926sdram_ba0
Y427sdram_ba1
U122sdram_cas_n
R744sdram_cke
Y324sdram_cs_n
V423sdram_ras_n
U421sdram_we_n
AA646sdram_clk_n
AA745sdram_clk_p
fSee www.micron.com for detailed information.
2–10Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Flash Memory
(U5)
U5 is an 8-bit, 16 Mbyte AMD flash memory device connected to the
FPGA. Depending on the board revision, the part number is
AM29LV128M or S29GL128M10TFIR1. Refer to Table 2–8 for connections
between the FPGA and the flash memory chip. U5 can be used for two
purposes:
1.A Nios II embedded processor implemented on the FPGA can use
the flash memory as general-purpose memory and non-volatile
storage.
2.The flash memory can hold FPGA configuration data that is used by
the configuration controller to load the FPGA at power-up. Refer to
“Configuration Controller Device (U3)” on page 2–33 for related
information.
A Nios II processor design in the FPGA can identify the 16 Mbyte flash
memory in its address space, and can program new data (either new
FPGA configuration data, Nios II software, or both) into flash memory.
The Nios II development software includes subroutines for writing and
erasing flash memory.
1The flash memory device shares address and data connections
with the Ethernet MAC/PHY device.
Table 2–8. Flash Memory Pin Table
FPGA PinU5 Pin Board Net Name
F951fe_a0
H831fe_a1
D1126fe_a2
E825fe_a3
B1424fe_a4
A1423fe_a5
F1422fe_a6
G1421fe_a7
F1320fe_a8
G1310fe_a9
C159fe_a10
B158fe_a11
B167fe_a12
C166fe_a13
D155fe_a14
Altera Corporation Reference Manual2–11
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–8. Flash Memory Pin Table (Continued)
FPGA PinU5 Pin Board Net Name
E154fe_a15
H153fe_a16
H1654fe_a17
A1719fe_a18
B1718fe_a19
G1511fe_a20
F1512fe_a21
F1615fe_a22
G162fe_a23
D835fe_d0
C837fe_d1
F1039fe_d2
G1041fe_d3
D944fe_d4
C946fe_d5
B848fe_d6
A850fe_d7
H1732flash_cs_n
F1734flash_oe_n
G1713flash_rw_n
B1816flash_wp_n
C1753flash_byte_n (1)
D1717flash_ry_by_n
Note to Ta b l e 2 –8 :
(1) BYTE_n on U5 is pulled low to keep the flash memory in byte
mode which restricts the usable modes of operation.
The on-board configuration controller makes assumptions about whatresides-where in flash memory. For details refer to “SW10 – Reset,
Config” on page 2–35.
fSee www.amd.com for detailed information about the flash memory
device.
2–12Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Ethernet
MAC/PHY (U4) &
RJ45 Connector
(RJ1)
The LAN91C111 chip (U4) is a 10/100 Ethernet media access control and
physical interface (MAC/PHY) chip. The control pins of U4 are
connected to the FPGA so that Nios II systems can access Ethernet
networks via the RJ-45 connector (RJ1) as shown in Figure 2–4. The
Nios II development tools include hardware and software components
that allow Nios II processor systems to communicate with the
LAN91C111 Ethernet device.
Figure 2–4. Ethernet RJ-45 Connector
U4
RJ1
Refer to Tabl e 2– 9 for connections between the FPGA and the MAC/PHY
device.
1The Ethernet MAC/PHY device shares both address and data
connections with the flash memory.
Table 2–9. Ethernet MAC/PHY Pin Table
FPGA PinU4 PinPin FunctionBoard Net Name (1)
E2641Address Enable enet_aen
J1743Synchronous Readyenet_srdy_n
F1840VL Bus Accessenet_vlbus_n
G1845Local Deviceenet_ldev_n
D1838IO Char Readyenet_iochrdy
E1837Address Strobeenet_ads_n
A1942Local Bus Clockenet_lclk
B1946Ready/Returnenet_rdyrtn_n
D2035Bus Cycleenet_cycle_n
D1436Write/Readenet_w_r_n
Y1534Bus Chip Selectenet_datacs_n
AA1529Interruptenet_intr0
Altera Corporation Reference Manual2–13
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA PinU4 PinPin FunctionBoard Net Name (1)
C2594Byte Enable 0enet_be_n0
C2495Byte Enable 1enet_be_n1
D2696Byte Enable 2enet_be_n2
D2597Byte Enable 3enet_be_n3
E2031Readenet_ior_n
D1632Writeenet_iow_n
H878Address Linefe_a1
D1179Address Linefe_a2
E880Address Linefe_a3
B1481Address Linefe_a4
A1482Address Linefe_a5
F1483Address Linefe_a6
G1484Address Linefe_a7
F1385Address Linefe_a8
G1386Address Linefe_a9
C1587Address Linefe_a10
B1588Address Linefe_a11
B1689Address Linefe_a12
C1690Address Linefe_a13
D1591Address Linefe_a14
E1592Address Linefe_a15
D8107Data Linefe_d0
C8106Data Linefe_d1
F10105Data Linefe_d2
G10104Data Linefe_d3
D9102Data Linefe_d4
C9101Data Linefe_d5
B8100Data Linefe_d6
A899Data Linefe_d7
H1176Data Linefe_d8
H1275Data Linefe_d9
F1174Data Linefe_d10
E1073Data Linefe_d11
B971Data Linefe_d12
2–14Reference ManualAltera Corporation
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Board Components
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA PinU4 PinPin FunctionBoard Net Name (1)
A970Data Linefe_d13
C1069Data Linefe_d14
D1068Data Linefe_d15
B1066Data Linefe_d16
A1065Data Linefe_d17
E1264Data Linefe_d18
D1263Data Linefe_d19
J1361Data Linefe_d20
J1460Data Linefe_d21
F1259Data Linefe_d22
G1258Data Linefe_d23
J1056Data Linefe_d24
J1155Data Linefe_d25
C1154Data Linefe_d26
B1153Data Linefe_d27
C1251Data Linefe_d28
B1250Data Linefe_d29
D649Data Linefe_d30
G1148Data Linefe_d31
Note to Ta b l e 2 –9 :
(1) Nets fe_a0 and fe_a16 to fe_a23 do not connect to U4.
fSee www.smsc.com for detailed information about the LAN91C111
device.
Serial Connector
(J19)
Altera Corporation Reference Manual2–15
May 2007Nios Development Board Cyclone II Edition
J19 is a standard DB-9 serial connector, and is typically used for
communication between the FPGA and a host computer via an RS-232
serial cable. Level-shifting buffer (U52) is used between J19 and the
FPGA, because the FPGA device cannot interface to RS-232 voltage levels
directly.
J19 is able to transmit all RS-232 signals. Alternately, the FPGA design can
use only the signals it needs, such as J19’s RXD and TXD pins. LEDs are
connected to the RXD and TXD signals and visually indicate when data
is being transmitted or received. Figure 6 and Table 2–10 show the pin
connections between the serial connectors and the FPGA.
Board Components
Figure 2–5. Serial Connector J19
J19
Function
Direction
Connector Pin #
Connector Pin #
Direction
Function
GND5DTR
9
OUT
RI
Table 2–10. Serial Connector Pin Table
FPGA PinJ19 PinBoard Net Name
AB153serial_rxd
J222serial_txd
H214serial_dtr
K221serial_dcd
H196serial_dsr
L199serial_ri
L238serial_cts
AC157serial_rts
IN
4
RXD
8
OUT
CTS
TXD
7
IN
RTS
OUT
2
DCD
OUT
1
6
OUT
DSR
IN
3
Expansion
Prototype
Connectors
(PROTO1 &
PROTO2)
PROTO1 and PROTO2 are standard-footprint, mechanically-stable
connections that can be used (for example) as an interface to a specialfunction daughter card. Headers J11, J12, and J13collectively form
PROTO1, and J15, J16 and J17 collectively form PROTO2.
The expansion prototype connector interface includes:
■41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the FPGA. Each signal passes through analog switches to protect
the FPGA from 5V logic levels. These analog switches are
permanently enabled. The output logic-level on the expansion
prototype connector pins is 3.3V.
●PROTO1 switches: U19, U20, U21, U22 and U25
●PROTO2 switches: U27, U28, U29, U30 and U31
2–16Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
■A buffered, zero-skew copy of the on-board oscillator output from
U2.
■A buffered, zero-skew copy of the FPGA phase-locked loop (PLL)
output.
■A logic-negative power-on reset signal.
■Five regulated 3.3V power-supply pins (2A total max load for both
PROTO1 & PROTO2).
■One regulated 5V power-supply pin (1A total max load for both
PROTO1 & PROTO2).
■Numerous ground connections.
The PROTO1 expansion prototype connector shares FPGA I/O pins with
the CompactFlash connector (CON3). Designs can use either the PROTO1
connector or the CompactFlash connector.
1Do not connect cards to PROTO1 and CON3 at the same time.
Damage to one or both cards might result.
fSee the Altera web site for a list of available expansion daughter cards
that can be used with the Nios development board at
www.altera.com/devkits.
Table 2–11, Figure 2–6 andFigure 2–7show connections from the
PROTO1 expansion headers to the FPGA. Unless otherwise noted, labels
indicate FPGA pin numbers...
Table 2–11. PROTO1 Pin Table
FPGA PinPROTO1 PinConnectorBoard Net Name
J11
U3 pin 561J11proto1_RESET_n
E253J11proto1_io0
F244J11proto1_io1
F235J11proto1_io2
J216J11proto1_io3
J207J11proto1_io4
F258J11proto1_io5
F269J11proto1_io6
N1810J11proto1_io7
P1811J11proto1_io8
G2312J11proto1_io9
G2413J11proto1_io10
Altera Corporation Reference Manual2–17
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–11. PROTO1 Pin Table (Continued)
FPGA PinPROTO1 PinConnectorBoard Net Name
G2514J11proto1_io11
G2615J11proto1_io12
H2316J11proto1_io13
H2417J11proto1_io14
J2318J11proto1_io15
J2421J11proto1_io16
H2523J11proto1_io17
H2625J11proto1_io18
K1827J11proto1_io19
K1928J11proto1_io20
K2329J11proto1_io21
K2431J11proto1_io22
J2532J11proto1_io23
J2633J11proto1_io24
M2135J11proto1_io25
T2336J11proto1_io26
R1737J11proto1_io27
K2138J11proto1_cardsel_n
P1739J11proto1_io28
J12
Y223J12proto1_io40
T184J12proto1_io29
T175J12proto1_io30
U266J12proto1_io31
R197J12proto1_io32
T198J12proto1_io33
U209J12proto1_io34
U2110J12proto1_io35
V2611J12proto1_io36
V2512J12proto1_io37
V2413J12proto1_io38
V2314J12proto1_io39
J13
U2 pin 199J13proto1_osc
2–18Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
2–22Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Pin 1
Figure 2–9. PROTO2 Pin Information – J15, J16 & J17
J16
2 GND
4 proto2_io1
6 proto2_io3
8 proto2_io5
10 proto2_io7
12 proto2_io9
14 proto2_io11
16 proto2_io13
18 proto_2io15
20 NC
22 GND
24 GND
26 GND
28 proto2_io20
GND 19
proto2_io0 3
proto2_io2 5
proto2_io4 7
proto2_io6 9
proto2_io8 11
proto2_io10 13
proto2_io12 15
proto2_io14 17
proto2_io16 21
proto2_io17 23
proto2_io18 25
proto2_io19 27
proto2_RESET_n 1
Board Components
30 GND
32 proto2_io23
34 NC
36 proto2_io26
38 proto2_cardsel_n
proto2_io21 29
proto2_io22 31
proto2_io24 33
proto2_io25 35
proto2_io27 37
40 GND
proto2_io28 39
CompactFlash
Connector
(CON3)
J15
4 proto2_io29
2 VCC5
GND 1
proto2_io40 3
12 proto2_io37
10 proto2_io35
8 proto2_io33
6 proto2_io31
proto2_io36 11
proto2_io34 9
proto2_io32 7
proto2_io30 5
14 proto2_io39
proto2_io38 13
J17
2 GND
1
Vunreg
(1)
4 GND
6 GND
5
NC 3
VCC3_3
8 GND
10 GND
12 GND
lk 11
VCC3_3 7
proto2_osc 9
proto2_pllc
(2)
(3)
14 GND
16 GND
VCC3_3 15
proto2_clkout 13
(4)
18 GND
20 GND
VCC3_3 17
VCC3_3 19
Notes to Figure 2–9:
(1) Unregulated voltage from DC power supply.
(2) Clk from board oscillator.
(3) Clk from FPGA.
(4) Clk output from PROTO2 card to FPGA.
The CompactFlash connector header (CON3) enables hardware designs
to access a CompactFlash card. Refer to Figure 2–10. The following two
access modes are supported:
■ATA (hot swappable mode)
■IDE (IDE hard disk mode)
Altera Corporation Reference Manual2–23
May 2007Nios Development Board Cyclone II Edition
Board Components
Figure 2–10. CompactFlash Connector
Most pins of CON3 connect to I/O pins on the FPGA. The following pins
have special connections:
■Pin 13 and 38 of CON3 (VCC) are driven by a power MOSFET that is
controlled by an FPGA I/O pin. This allows the FPGA to control
power to the CompactFlash card for the IDE connection mode.
■Pin 26 of CON3 (-CD1) is pulled up to 5V through a 10 Kohm resistor.
This signal is used to detect the presence of a CompactFlash card;
when the card is not present, the signal is pulled high through the
pull-up resistor.
■Pin 41 of CON3 (RESET) is pulled up to 5V through a 10 Kohm
resistor, and is controlled by the EPM7256AE configuration
controller. The FPGA can cause the configuration controller to assert
RESET, but the FPGA does not drive this signal directly.
The CompactFlash connector shares several FPGA I/O pins with
expansion prototype connector PROTO1. Refer to “Expansion Prototype
Connectors (PROTO1 & PROTO2)” on page 2–16 for details on PROTO1.
1Do not connect cards to PROTO1 and CON3 at the same time.
Damage to one or both cards might result.
Table 2–13 lists connections between CON3 and the FPGA.
Table 2–13. CompactFlash Pin Table
FPGA Pin CON3 PinPin Function Board Net Name (1)
E256D7proto1_io0
F2447D8proto1_io1
2–24Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Table 2–13. CompactFlash Pin Table (Continued)
FPGA Pin CON3 PinPin Function Board Net Name (1)
F235D6proto1_io2
J2148D9proto1_io3
J204D5proto1_io4
F2549D10proto1_io5
F263D4proto1_io6
N1827D11proto1_io7
P182D3proto1_io8
G2328D12proto1_io9
G2423D2proto1_io10
G2529D13proto1_io11
G2622D1proto1_io12
H2330D14proto1_io13
H2421D0proto1_io14
J2331D15proto1_io15
H2535IOWR_nproto1_io17
H2634IORD_nproto1_io18
K1842IORDY_nproto1_io19
K2437INTRQproto1_io22
J2524IOCS16_nproto1_io23
J2619A1proto1_io24
M2120A0proto1_io25
T2318A2proto1_io26
R177CS0_nproto1_io27
P1745DASPproto1_io28
T188A10proto1_io29
T1746PDIAGproto1_io30
U2610A9proto1_io31
R1911A8proto1_io32
T1912A7proto1_io33
U2014A6proto1_io34
U2115A5proto1_io35
V2616A4proto1_io36
V2517A3proto1_io37
V2436WE_nproto1_io38
Altera Corporation Reference Manual2–25
May 2007Nios Development Board Cyclone II Edition
Board Components
fFor more information on the CompactFlash connector (CON3), see
Table 2–13. CompactFlash Pin Table (Continued)
FPGA Pin CON3 PinPin Function Board Net Name (1)
V2343INPACK_nproto1_io39
Y2244REG_nproto1_io40
W1632CS1_ncf_cs_n
AE169ATA_SEL_ncf_atasel_n
AD165Power supply
enable
W1526CD1_ncf_present_n
56 (U3)41RESET#proto1_RESET_n (3)
Notes to Ta b l e 2 –1 3 :
(1) Nets proto_io16, proto_io20, and proto_io21 do not connect to CON3.
(2) The FPGA I/O pin controls a power MOSFET that supplies 5V VCC to this net.
(3) proto1_RESET_n is driven by the EPM7256AE configuration controller device
(U3).
cf_power (2)
www.compactflash.org and www.molex.com.
PMC Connector
(JH1 & JH2)
The PCI mezzanine card (PMC) connector, formed by JH1 and JH2,
allows Nios II systems in the FPGA to interface to daughter cards using
the standard 32-bit PMC form factor. Refer to Figure 2–11. The PMC
connector is capable of 33MHz and 66 MHz, and is configured as the PMC
host.
wBefore connecting a daughter card to the PMC connector, the
FPGA must first be configured with a design that includes a
PMC interface. Damage to either the FPGA or daughter card can
result if the FPGA is not configured correctly.
The factory-programmed Nios II reference design does not include a
PMC interface.
2–26Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Figure 2–11. PMC Connector
Pin 1
Pin 1
JH1
JH2
The PMC connector supplies +3.3V, +5V and +/- 12V, as required by the
PCI specification. However, DC power regulators for these supplies
cannot provide enough power to fully satisfy the PCI power specification.
The current that the board can supply through JH1 and JH2 is dependent
on the design configured in the FPGA. As a general guideline, if the PMC
card power requirements exceed the specifications shown in Table 2–14,
you must connect an external power source.
Table 2–14. PMC Card Power Specifications
DC SupplyMaximum PowerApply External Power Source
+3.3V9.5 Watts J29
+5V15 WattsJ28
+12V45 WattsJ31
-12V1.2 WattsTP13
wWhen connecting an external power supply, the fuse for the
corresponding voltage should be removed to prevent the two
power supplies from interfering with each other. Refer to
“Power-Supply Circuitry” on page 2–44 for more information.
Table 2–15 lists the connections between the PMC connector and the
FPGA.
Table 2–15. PMC Connector Pin Table
FPGA PinJH1 & JH2 PinConnectorBoard Net Name
L2061JH1pmc_ad0
L2160JH1pmc_ad1
Altera Corporation Reference Manual2–27
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–15. PMC Connector Pin Table (Continued)
FPGA PinJH1 & JH2 PinConnectorBoard Net Name
L2459JH1pmc_ad2
L2558JH1pmc_ad3
M1955JH1pmc_ad4
M2254JH1pmc_ad5
M2353JH1pmc_ad6
R2451JH2pmc_ad7
U2249JH2pmc_ad8
U2549JH1pmc_ad9
W2148JH2pmc_ad10
W2348JH1pmc_ad11
W2447JH1pmc_ad12
W2546JH2pmc_ad13
Y2145JH2pmc_ad14
Y2346JH1pmc_ad15
Y2431JH2pmc_ad16
Y2532JH1pmc_ad17
Y2629JH2pmc_ad18
AA2329JH1pmc_ad19
AA2428JH2pmc_ad20
AA2528JH1pmc_ad21
AA2627JH1pmc_ad22
AB2326JH2pmc_ad23
AB2423JH2pmc_ad24
AB2523JH1pmc_ad25
AB2622JH2pmc_ad26
AC2322JH1pmc_ad27
AC2521JH1pmc_ad28
AC2620JH2pmc_ad29
AD2419JH2pmc_ad30
AD2520JH1pmc_ad31
R2052JH1pmc_be_n0
T2243JH2pmc_be_n1
T2432JH2pmc_be_n2
T2526JH1pmc_be_n3
2–28Reference ManualAltera Corporation
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Board Components
Table 2–15. PMC Connector Pin Table (Continued)
FPGA PinJH1 & JH2 PinConnectorBoard Net Name
T2043JH1pmc _par
W2613JH1pmc_clk
U2439JH2pmc_perr_n
U2342JH2pmc_serr_n
R2537JH1pmc_devsel_n
P2438JH2pmc_stop_n
P2336JH1pmc_irdy_n
M204JH1pmc_inta_n
Y145JH1pmc_intb_n
AA136JH1pmc_intc_n
Y139JH1pmc_intd_n
G2213JH2pmc_reset_n
N2433JH1pmc_frame_n
N2335JH2pmc_trdy_n
M2525JH2pmc_idsel
M2416JH1pmc_gnt_n
N2017JH1pmc_req_n
K2640JH1pmc_lock_n
K2547JH2pmc_m66en
AE1564JH1pmc_req64_n
Mictor
Connector (J25)
The Mictor connector (J25) can be used to transmit up to 27 high-speed
I/O signals with very low noise via a shielded Mictor cable. J25 can be
used as a debug port for the Nios II processor or as a general-purpose I/O
connector to the FPGA. Twenty five of the Mictor connector signals are
used as data, and two signals are used as clock input and clock output.
Most pins on J25 connect to I/O pins on the FPGA (U62). For systems that
do not use the Mictor connector for debugging the Nios II processor, any
on-chip signals can be routed to I/O pins and probed at J25. External
scopes and logic analyzers can connect to J25 and analyze a large number
of signals simultaneously.
fFor details on Nios II debugging products that use the Mictor connector,
see www.altera.com.
Altera Corporation Reference Manual2–29
May 2007Nios Development Board Cyclone II Edition
Board Components
Figure 2–12 shows an example of an in-target system analyzer ISA-
Nios/T by First Silicon Solutions (FS2) Inc. connected to the Mictor
connector. For details, see www.fs2.com.
Figure 2–12. An ISA-Nios/T Connecting to the Mictor Connector (J25)
J25
Fiveof the signals connect to both the JTAG pins on the FPGA (U62), and
the FPGA’s JTAG connector (J24). The JTAG signals have special usage
requirements. J25 and J24 cannot be used at the same time.
Figure 2–13 below shows connections from the Mictor connector to the
FPGA.
Figure 2–13. Mictor Connector Signaling
JTAG Connector
Mictor Connector
(J25)
(J24)
5
40
2–30Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
FPGA
(U62)
Board Components
Table 2–16 shows the pin out information for J25. Unless otherwise noted,
labels indicate FPGA pin numbers.
Table 2–16. Mictor Connector Pin Table
FPGA Pin J25 Pin Board Net Name
V215mictor_clk
AC838mictor0
AD836mictor1
W1034mictor2
Y1032mictor3
V1030mictor4
V928mictor5
AD626mictor6
AD724mictor7
AE522mictor8
AF520mictor9
AD418mictor10
AD516mictor11
AC510mictor12
AC68mictor13
AF437mictor14
AE435mictor15
B2133mictor16
B2231mictor17
A2229mictor18
A2327mictor19
B2325mictor20
D2123mictor21
C2113mictor22
C229mictor23
C237mictor24
B256mictor_trclk
Test Points
(TP1–TP8)
Altera Corporation Reference Manual2–31
May 2007Nios Development Board Cyclone II Edition
TP1 – TP8 are test points connected to I/O pins on the FPGA. FPGA
designs can route signals to these I/O pins to be probed. TP1 –TP8 also
connect to the configuration controller (U3).
Board Components
Table 2–17 lists the connections between the FPGA, U3, and the test
points.
Table 2–17. Test Point Pin Table
Test PointFPGA PinCPLD PinBoard Net Name
TP1D1975pld_user0
TP2C1976pld_user1
TP3A2077pld_user2
TP4B2078pld_user3
TP5K1679pld_user4
TP6J1680pld_user5
TP7K1781pld_user6
TP8J1883pld_user7
EPCS64 Serial
Configuration
Device (U69)
U69 is a serial configuration device connected to the FPGA. Serial
configuration devices are flash memory devices with a serial interface
which can store configuration data, and load the data into the FPGA upon
power up or reconfiguration. U69 can store FPGA configuration data, or
Nios II program data, or both.
Table 2–18 lists the connections between U69 and the FPGA.
Table 2–18. EPCS64 Pin Table
FPGA PinU69 PinBoard Net Name
N616pld_dclk
N38pld_data0
D37pld_cs_n
E315pld_asdo
The SOPC Builder EPCS Serial Flash Controller component enables
Nios II processor systems to access the EPCS device. Nios II processor
systems can read program code or data from the device, and can write
new data into the EPCS device.
U69 is blank by default. The Quartus II software can program FPGA
configuration data (a .pof file) into U69 through an Altera download
cable connected to J27. Alternately, software running on a Nios II
processor design can write configuration data to U69.
2–32Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
1The orientation of J27 is the reverse of J24.
fSee the Serial Configuration Devices chapter in Altera's Configuration
Device Handbook for more information about the EPCS64 device. See the
EPCS Device Controller Core with Avalon Interface chapter in the Quartus II
Handbook, Volume 5: Altera Embedded Peripherals for information about the
EPCS serial flash controller component in SOPC Builder.
Configuration
Controller
Device (U3)
fFor complete details on the configuration controller connections, see the
The configuration controller (U3) is an Altera MAX 7000 EPM7256AE
device. It comes preprogrammed with logic for managing board reset
conditions and configuring the FPGA from data stored in flash memory
and the EPCS64 serial configuration device (U69).
FPGA configuration data files are generated by the Quartus II software.
The Nios II integrated development environment (IDE) can write new
configuration data to the board's flash memory.
board schematic. For detailed information about the Altera EPM7256AE
device, see the MAX 7000 family literature at
www.altera.com/literature/lit-m7k.html. For details on programming
configuration data to flash memory, see the Nios II Flash Programmer User Guide, or refer to the Nios II IDE help system.
Configuration-Status LEDs
The configuration controller is connected to four status LEDs that show
the configuration status of the board at a glance as shown in Figure 2–14.
The LEDs indicate which configuration, if any, was loaded into the FPGA
at power-on as shown in Table 2–19.
Figure 2–14. LED1 – LED 4
FPGA Config
LED 3
Loading
LED 4
Error
LED 1
User
LED 2
Factory
SW9
Factory
Config
Altera Corporation Reference Manual2–33
May 2007Nios Development Board Cyclone II Edition
Board Components
Table 2–19. Configuration Status LED Indicators
LEDLed NameColorDescription
LED3Loading GreenThis LED blinks while the configuration controller is actively
transferring data from flash memory into the FPGA.
LED4ErrorRedIf this LED is on, then configuration was not transferred from flash
memory into the FPGA. This can happen if, for example, the flash
memory contains either a valid user or factory configuration.
LED1UserGreenThis LED turns on when the user configuration is being transferred
LED2FactoryAmberThis LED turns on when the factory configuration is being
LED6LED6RedThis LED is an indicator of the CONFIG_DONE_signal from the
LED7LED7RedThis LED is an indicator of the flash_CE_n line. It illuminates when
from flash memory and stays illuminated when the user
configuration data is successfully loaded into the FPGA. If the
FPGA was successfully configured by the EPCS64, LED1 will blink
slowly.
transferred from flash memory and stays illuminated if the factory
configuration was successfully loaded into the FPGA.
FPGA. This LED illuminates when FPGA configuration completes
successfully and CONFIG_DONE goes high.
the flash is being accessed and the CE_n line is being asserted.
Configuration & Reset Buttons
The Nios development board uses dedicated switches SW8, SW9 and
SW10 for the following fixed functions:
SW8 – CPU Reset
When SW8 is pressed, a logic-0 is driven onto the FPGA I/O pin C5
(DEV_CLRn). The result of pressing SW8 depends on how the FPGA is
configured. Refer to Figure 2–15.
The factory-programmed Nios II reference design treats SW8 as a CPUreset button. The Nios II reference design resets and starts executing code
from its reset address when SW8 is pressed.
2–34Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Figure 2–15. CPU Reset Button
SW8
CPU
Reset
SW9 – Factory Config
Pressing Factory Config (SW9) commands the configuration controller to
reconfigure the FPGA with the factory configuration. Refer to
Figure 2–16.
Figure 2–16. Factory Config Button
SW9
Factory
Config
SW10 – Reset, Config
Reset, Config (SW10) is the power-on reset button. Refer to Figure 2–17.
When SW10 is pressed, a logic 0 is driven to the power on reset controller
(U18). Refer to “Power-Supply Circuitry” on page 2–44 for more details.
Whenever SW10 is pressed, the configuration controller attempts to
reconfigure the FPGA.
Altera Corporation Reference Manual2–35
May 2007Nios Development Board Cyclone II Edition
Board Components
Figure 2–17. Reset, Config Button
SW10
Reset,
Config
Reset Distribution
The EPM7256AE device takes a power-on reset pulse from the Linear
Technologies 1326 power-sense/reset-generator chip (U18) and
distributes it (through internal logic) to other reset pins on the board, that
include the following:
■LAN91C111 (Ethernet MAC/PHY) reset
■Flash memory reset
■CompactFlash reset
■Reset signals delivered to the expansion prototype connectors
(PROTO1 & PROTO2)
Starting Configuration
The following four methods start a configuration sequence:
1.Board power-on
2.Pressing the Reset, Config button (SW10).
3.Asserting (driving 0 volts on) the pld_reconfigreq_n input pin
of the EPM7256AE device (U3 pin 94) from the FPGA (U62 pin
AA14).
4.Pressing the Factory Config button (SW9).
Factory & User Configurations
The configuration controller can manage two separate FPGA
configurations stored in flash memory U5. These two configurations are
referred to as the factory configuration and the user configuration. A
2–36Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
Nios II reference design is factory-programmed into the factory
configuration region of the flash memory. In addition, the FPGA can be
configured by the EPCS64 serial configuration device.
Configuration Process
At power-up or reset, the configuration controller attempts to configure
the FPGA with data from one of three sources, in the following order:
1.The EPCS64 serial configuration device
2.The user configuration from flash memory
3.The factory configuration from flash memory
First, the configuration controller puts the FPGA in active serial (AS)
configuration mode. The FPGA then attempt to read configuration data
from the EPCS64. If the FPGA finishes configuration successfully, the
configuration controller stops.
If configuration from the EPCS64 does not succeed, the configuration
controller puts the FPGA into passive serial (PS) mode and attempts to
load the user configuration from flash memory. If this also fails (because
the user configuration is either invalid or not present), the configuration
controller attempts to load the factory configuration from flash memory.
When SW9 (Factory Config) is pressed, the configuration controller
ignores the user configuration and EPCS64, and configures the FPGA
with the factory configuration. SW9 provides an escape from a situation
in which a valid-but-nonfunctional design is present in user flash
memory or the EPCS64.
Altera Corporation Reference Manual2–37
May 2007Nios Development Board Cyclone II Edition
Board Components
Flash Memory Partitions
The configuration controller expects user and factory configuration data
to be stored at fixed locations (offsets) in flash memory. In addition, the
factory-programmed reference design expects Nios II software and data
to exist at certain locations in flash memory. Table 2–20 shows the
expected flash memory partitioning.
Table 2–20. Flash Memory Partitions
OffsetUsageFactory-Programmed Content
0x00000000 – 0x00BFFFFFUser Application Space (11 MB)
0x00C00000 – 0x00CFFFFFUser Configuration (1 MB)
0x00D00000 –0x00DFFFFFFFree Space (1 MB)
0x00E00000 – 0x00EFFFFFFactory Configuration (1 MB)Nios II Processor Reference
Design
0x00F00000 – 0x00FAFFFFWeb Pages Web Pages
0x00FB0000 – 0x00FEFFFFWeb Server Software Web Server Software
0x00FF0000 – 0x00FFFFFFPersistent Data Network Settings for Web Server
1This partitioning scheme is merely a convention used by the
configuration controller and the factory-programmed reference
design. Custom FPGA designs can use the flash memory space
in any way necessary.
cAltera recommends that you do not overwrite the factory-
programmed flash memory contents. Without a valid factory
configuration, the configuration controller may not be able to
successfully configure the FPGA. If you alter the factory
configuration, you can restore the board to its factoryprogrammed state. Refer to Appendix B: Restoring the Factory
Configuration.
User Application Space
The lower 11 MB of flash memory is the user application space. This is
free space for user designs to store code and data for Nios II programs.
The Nios II IDE allows you to compile Nios II programs and program
them into the user application space.
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Nios Development Board Cyclone II EditionMay 2007
Board Components
User Configuration
The user configuration partition is 1 MB, starting at offset 0x00C00000.
This section contains the FPGA configuration data for the user
configuration. Nios II development tools include documentation on how
to create your own user configuration image and program it into flash
memory.
Factory Configuration
The factory configuration partition is 1 MB, starting at offset 0x00E00000.
This section contains the FPGA configuration data for the factory
configuration. The Nios II processor system in the factory configuration
is designed to start executing code from offset 0x00000000 in the flash
memory. The Nios II development tools include the source files for the
factory programmed hardware and software reference designs.
Persistent Data
The persistent data partition is 64 KB, starting at offset 0x00FF0000. This
partition is for maintaining nonvolatile settings and data, such as the
MAC address and IP address for the factory-programmed web server
reference design. Persistent data is technically no different than other
application data, but it is often convenient to think of certain data as
independent from the user hardware or software.
JTAG Connectors
(J24 & J5)
The Nios development board has two 10-pin JTAG headers (J24 and J5)
compatible with Altera download cables, such as the USB-Blaster™. On
the Nios development board, each JTAG header connects to one Altera
device and forms a single-device JTAG chain. J24 connects to the FPGA
(U62), and J5 connects to the EPM7256AE device (U3).
JTAG Connector to FPGA (J24)
J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the FPGA
(U62) as shown in Figure 2–18. Altera Quartus II software can directly
configure the FPGA with a new hardware image via an Altera download
cable as shown in Figure 2–19. In addition, the Nios II IDE can access the
Nios II processor JTAG debug module via a download cable connected to
the J24 JTAG connector.
Altera Corporation Reference Manual2–39
May 2007Nios Development Board Cyclone II Edition
Board Components
Figure 2–18. JTAG Connector (J24) to Cyclone II Device
To Mictor Connector (J25)
JTAG Signals
JTAG Connector
(J24)
TDI
TMS
TCK
TDO
TRST
FPGA
(U62)
Figure 2–19. USB Blaster Connected to J24 JTAG Connector
Pin 1
J24
The FPGA’s JTAG pins can also be accessed via the Mictor connector (J25).
The pins of J24 are connected directly to pins on J25, and care must be
taken so that signal contention does not occur between the two
connectors.
2–40Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
JTAG Connector to EPM7256AE Device (J5)
J5 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the
EPM7256AE device (U3). Altera Quartus II software can perform insystem programming (ISP) to reprogram the EPM7256AE device (U3)
with a new hardware image via an Altera download cable as shown in
Figure 2–20.
fTo restore the board to its factory-programmed condition, see Appendix
Clock Circuitry
1The orientation of J5 is rotated 180
Most users never need to reprogram the configuration controller design
in the EMP7256AE device. Reprogramming the configuration controller
can result in an inoperable development board.
B: Restoring the Factory Configuration.
Figure 2–20. JTAG Connector (J5) to MAX Device
J5
Pin 1
The Nios development board includes a 50 MHz free-running oscillator
(Y2) and a zero-skew, point-to-point clock distribution network that
drives the FPGA (U62), the EPM7256AE configuration controller device
(U3), and pins on the PROTO1 & PROTO2 connectors. The zero-skew
buffer (U2) drives the clock distribution network using the free-running
50 MHz clock. Refer to Figure 2–21.
degrees compared to J24.
Altera Corporation Reference Manual2–41
May 2007Nios Development Board Cyclone II Edition
Board Components
Figure 2–21. Clock Circuitry
osc_CLK0
sdram_CLK_p
sdram_CLK_n
DDR SDRAM (U63)
Oscillator (Y2)
Clock
Buffer
SMA External
Input (J4)
sram_CLKIN
sdram_CLKIN
(U2)
osc_CLK1
FPGA
(U62)
PLLs
sram_CLK
mictor_CLK
PMC_CLK
SSRAM (U74)
Mictor (J25)
PMC (JH1 & JH2)
proto1_PLLCLK
proto1_CLKOUT
PROTO1
proto1_OSCCLK
proto2_PLLCLK
proto2_CLKOUT
PROTO2
proto2_OSCCLK
cpld_CLKOSC
MAX (U3)
Note to Figure 2–21:
(1) To use an external clock signal, remove the crystal oscillator from its socket. Make
sure to note the correct orientation of the oscillator before removing it.
2–42Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Board Components
The FPGA receives clock input from buffer U2, and from the PROTO1 and
PROTO2 connectors, as shown in Table 2–21.
Table 2–21. FPGA Clock Input Pin Table
FPGA PinFPGA Pin NamePLL Signal SourceBoard Net Name
B25ION/AJ25 pin 6mictor_TRCLK
N26CLK5PLL2J13 pin 13proto1_CLKOUT
AF4CLK13PLL4J17 pin 13proto2_CLKOUT
P25CLK6PLL2U2 pin 2osc_CLK0
AC13CLK15PLL4U2 pin 3osc_CLK1
N2CLK0PLL1U2 pin 4sram_CLKIN
B13CLK8PLL3U2 pin 6sdram_CLKIN
The FPGA can synthesize new clock signals internally using on-chip
PLLs, and drive the clocks to various components on the board, as shown
in Ta bl e 2 –2 2.
Table 2–22. FPGA Clock Output Pin Table
FPGA PinFPGA Pin NamePLL (1)
AA7PLL1_OUTpPLL1U63 pin 45sdram_CLK_p
AA6PLL1_OUTnPLL1U63 pin 46sdram_CLK_n
E5PLL3_OUTpPLL3U74 pin 89sram_CLK
W26ION/AJH1 pin 13pmc_CLK
F21PLL2_OUTpPLL2J13 pin 11proto1_PLLCLK
F20PLL2_OUTnPLL2J17 pin 11proto2_PLLCLK
V21PLL4_OUTpPLL4J25 pin 5mictor_CLK
Note to Table 2–22:
(1) PLLs are only dedicated when using the Enhanced PLL. If you use the Fast PLL,
the PLL inputs and outputs are interchangeable. For more information on using
PLLs in the Cyclone II refer to the data sheet.
Signal
Destination
Board Net Name
The 50 MHz oscillator (Y2) is socketed and can be changed or removed by
the user. To drive the clock circuitry using the external clock connector
(J4), remove Y2.
1The factory-programmed configuration controller and Altera-
provided reference designs work only with the 50 MHz clock.
Altera Corporation Reference Manual2–43
May 2007Nios Development Board Cyclone II Edition
Board Components
Power-Supply
Circuitry
The Nios development board runs on a 16V, unregulated, input power
supply connected to J26. On-board circuitry generates +/-12V, +5V, +3.3V,
+2.5V, and +1.2V regulated power levels. For applications requiring high
current, separate voltage levels can be supplied from a workbench power
supply.
■The input power-supply on J26 can be either center-negative or
center-positive. A bridge rectifier (D34) presents the appropriate
polarity to the voltage regulators.
■The 5V supply is presented on pin 2 of J12 and J15 for use by any
device plugged into the PROTO1 & PROTO2 expansion connectors.
■The 3.3V supply is used as the power source for all FPGA I/O pins.
The 3.3V supply is also available for PROTO1 & PROTO2 daughter
cards.
■The 2.5V supply is used only as the power supply for the DDR
SDRAM chip and is not available on any connector or header.
■The 1.2V supply is used only as the power supply for the Cyclone II
device core (VCCINT) and it is not available on any connector or
header.
■The +/-12V supply is provided for the PMC connectors JH1 and JH2.
Refer to “PMC Connector (JH1 & JH2)” on page 2–26 for more
details. When workbench power supplies are connected to the board,
a corresponding fuse must be removed to decouple the on-board
voltage regulator. Each on-board regulator drives power through a
7A fuse. Refer to Table 2–23.
Table 2–23 lists the details of what voltage levels can be supplied to what
points on the board.
Table 2–23. Power Supply and Fuse Details
VoltagePadFuseNote
1.2VJ30F3Core power for FPGA.
1.2VTP12F7FPGA PLL power supply.
1.25VTP10F5DDR SDRAM I/O VTT.
1.25VTP9F4DDR SDRAM I/O VREF.
2.5VTP11F6DDR SDRAM VDD power supply. FPGA VCCIO for pins that
3.3VJ29F23.3V power for multiple components on the board.
5VJ28F15.0V power for multiple components on the board.
+12VJ31F8Power for the PMC connectors.
-12VTP13F9Power for the PMC connectors.
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Nios Development Board Cyclone II EditionMay 2007
interface to DDR SDRAM.
Appendix A. Restoring the
Factory Configuration
Introduction
Reprogramming
the Flash
Memory
To restore the factory configuration, you must reprogram the flash
memory on the board, and you must Nios Development Board Cyclone II
Edition the EPM7256AE configuration controller device.
Nios II Embedded Design Suite provides the files required for this
operation in the directory <Nios II EDS install path>/examples /factory_recovery.
To reprogram the flash memory on the development board, perform the
following steps:
1.Open a Nios II command shell.
On a Windows PC, click Windows Start, point to Programs, Altera,
Nios II EDS <installed version>, and then click Nios II Command
Shell.
2.From the examples directory, change to the factory_recovery
directory for your development kit.
cd factory_recovery/niosII_cycloneII_2c35
3.Run the flash-restoration script:
./restore_my_flash
4.Follow the script's instructions.
Reprogramming
the EPM7256AE
Configuration
If the configuration controller design was modified, you must also
reprogram the EMP7256AE device (U3). To reprogram the EMP7256AE
configuration controller, perform the following steps:
1.Move the programming cable from J24 to J5, labeled “For U3”.
Controller
Device
Altera Corporation A–1
May 2007
1The orientation of J5 is opposite that of J24. When properly
connected to J5, the programming cable lies naturally over
the clock oscillator and the dual seven-segment display.
2.Launch the Quartus II software, and click Programmer on the Tools
menu.
3.Click Add File and select the following programming file:
<Nios II EDS install path>/examples/
factory_recovery/niosII_cycloneII_2c35/config_controller.pof.
4.In the Programmer, turn on the Program/Configure checkbox, and
click Start to reprogram the EPM7256AE device.
5.Press the Factory Config button to perform a power on reset and
reconfigure the FPGA from flash memory. You should see the
Factory LED turned on and activity on LEDs D0 through D7.
Your board is now reconfigured to the default factory condition.
A–2Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
Appendix B. Connecting to
the Board via Ethernet
Introduction
The Nios development board is factory-programmed with a reference
design that implements a web server, among other functions as shown in
Figure B–1. This chapter describes how to connect a host computer to the
board's Ethernet port, assign an IP address to the board, and browse to the
web server from the host computer.
Figure B–1. Web Server Reference Design
Connecting the
Ethernet Cable
Altera Corporation B–1
May 2007
The Nios II development kit includes an Ethernet (RJ45) cable and a
male/female RJ45 crossover adapter. Before you connect these
components, you must decide how you want to use the network features
of your board. Select one of the two following connection methods:
1.LAN Connection — To use your Nios development board on a LAN (for
example, connecting to an Ethernet hub) do the following:
a.Connect one end of the RJ45 cable to the Ethernet connector on
the development board (RJ1).
b.Connect the other end to your LAN connection (hub, router,
wall plug, etc.).
2.Point-to-Point Connection — To use your Nios development board
connected directly to a host computer point-to-point (not on a
LAN), do the following:
a.Connect one end of your RJ45 cable to the female socket in the
crossover adapter and insert the male end of the crossover
adapter into RJ1 on the Nios development board as shown in
Figure B–2.
Figure B–2. Point-to-Point Connection
RJ1
b.Connect the other end of the RJ45 connector directly to the
network (Ethernet) port on your host computer.
Connecting the LCD Screen
The Nios II development kit includes a two-line x 16-character LCD text
screen. The web-server software displays useful status and progress
messages on this display. If you wish to use the network features of the
board, connect the LCD screen to expansion prototype connector J12.
Refer to the Nios II Development Kit, Getting Started User Guide for details.
Obtaining an IP Address
In order to function on a network (either LAN or point-to-point), your
board must have an IP address. This section describes the methods to
assign an IP address to your board.
B–2Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
LAN Connection
If you have connected your board to a LAN, the board will either obtain
a dynamic IP address using DHCP, or a static IP address stored in flash
memory. If you do not know whether or not your LAN supports DHCP,
it is easiest to try DHCP first.
DHCP
Upon reset, the web server attempts to acquire an IP address via the
DHCP protocol. The board continues to attempt DHCP self-configuration
for two minutes. You can determine if DHCP has succeeded, or if it is still
in progress, by reading status messages on the LCD screen. If your LAN
does not support DHCP then DHCP configuration ultimately fails, and
the web server defaults to a static IP address.
If DHCP succeeds, the board displays a success message and the IP
address on the LCD screen. The web server is now ready to display web
pages. See “Browsing to Your Board” on page B–5 to continue.
Static IP Address
If the DHCP process fails, the board uses a static IP address stored in flash
memory. You need to obtain a safe IP address in your LAN's subnet from
your system administrator. Once you know a safe IP address, you can
assign it to your board using the steps below.
These steps send IP configuration data to the board via an Altera JTAG
download cable, such as the USB-Blaster cable.
1.Install the Nios II development tools, connect the JTAG download
cable, and apply power to the board, as described in the Nios II Development Kit, Getting Started User Guide.
2.Open a Nios II command shell. On Windows PCs, On a Windows
PC, click Windows Start, point to Programs, Altera, Nios II EDS
<installed version>, and then click Nios II Command Shell. A shell
window appears with a command prompt.
3.Press the SW9 button labeled Factory Config on the board.
4.At the Nios II command shell command prompt, type:
nios2-terminal<Enter>
This command opens a terminal connection via the JTAG download
cable to a monitor program running on the board. The monitor
program displays status messages and text instructions that tell you
how to set the IP address for your board.
Altera Corporation Reference ManualB–3
May 2007Nios Development Board Cyclone II Edition
5.Press the ! key to abort the DHCP process and display a prompt. If
you don't abort the DHCP process, it will fail after two minutes, and
eventually a prompt will appear.
1The monitor's prompt is the + character. You can enter
h<Enter> at the prompt for a complete list of supported
commands.
6.At the prompt, type xip:<safe IP address><Enter>
The xip command saves the IP address in flash memory. In general,
you only need to assign an IP address to your board once. However,
you can change it at any time by issuing another xip command. You
can also use the commands xsubnet and xgateway to assign
subnet and gateway addresses, but setting these addresses is not
usually necessary.
7.Type xdhcp:off<Enter> to disable the board from attempting to
obtain the IP address using DHCP in the future. (You can re-enable
DHCP later, using the xdhcp:on command.)
8.Type CTRL+C to terminate the JTAG terminal session and
disconnect from the monitor program, then close the Nios II
command shell.
9.Press the SW8 button labeled CPU Reset to reboot the Nios II
processor and start the web server using the new IP address. The
LCD screen displays the static IP address assigned to the board,
along with other status messages.
The web server is now ready to display pages using the IP address you
assigned. See “Browsing to Your Board” on page B–5 to continue.
Point–to–Point Connections
All boards are factory programmed with a default IP address of 10.0.0.51
stored in flash memory. The 10.0.0.x subnet is conventionally reserved for
development, test, and prototyping. If DHCP fails or is aborted, the board
uses this static IP address. The LCD screen displays status messages to
indicate when the web server starts running using the default IP address.
Your host computer and the development board are the only two devices
connected to this simple point-to-point network. For most host operating
systems, it is necessary to assign your host computer an IP address on the
same subnet as the board. For example, the address 10.0.0.1 will work
fine. Any address in the 10.0.0.x subnet will work, and there is no
possibility of conflicting with another device on the network. After
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Nios Development Board Cyclone II EditionMay 2007
modifying the host computer's IP address, your computer is ready to
connect to the web server. Refer to “Browsing to Your Board” on page B–5
to continue.
If you don't have the ability to change the IP address of your host
computer, you can change the IP address of the board to match the subnet
of the host computer. For example, if your computer's IP address is
1.2.3.4, then you can assign the address 1.2.3.5 to your board. To change
the board IP address, follow the steps in “Static IP Address ” on page B–3.
Every time you reset the board, the web server will attempt to obtain an
IP address via DHCP, which takes two minutes to time out. You can abort
the DHCP process, or disable DHCP entirely by using the steps in “Static
IP Address ” on page B–3.
Browsing to Your
Board
Once your board has a valid IP address (obtained from either DHCP selfconfiguration or from flash memory), you can access the board via a web
browser (e.g., Microsoft Internet Explorer). To browse to this site, open a
web browser and type the IP address of the board (four numbers
separated by decimal-points) as a URL directly into the browser’s
Address input field. You can determine your board’s IP address by
reading the messages displayed on the LCD screen.
Altera Corporation Reference ManualB–5
May 2007Nios Development Board Cyclone II Edition
B–6Reference ManualAltera Corporation
Nios Development Board Cyclone II EditionMay 2007
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