Altera Nios Development Board User Manual

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San Jose, CA 95134
[phone]
http://www.altera.com

Nios Development Board

Reference Manual, Stratix II Edition

Preliminary Information

Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its se miconduc tor products to current specif ications in accordance with Altera's s tandard w arranty, b ut reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services

.

Printed on recycled paper

MNL-N832T4-1.2

ii Altera Corporation

Contents

About this Manual .................................................................................. v

How to Find Information ......................................................................................................................... v

How to Contact Altera ............................................................................................................................ vi

Typographic Conventions ..................................................................................................................... vii

Introduction ......................................................................................... 1

Features Overview ................................................................................................................................. 1–1

General Description ............................................................................................................................... 1–1

Board Components ................................................................................. 5

Component List ...................................................................................................................................... 2–5

Stratix II Device (U60) ........................................................................................................................... 2–7

Push-Button Switches (SW0 - SW3) .................................................................................................... 2–9

Individual LEDs (D0 - D7) .................................................................................................................... 2–9

Seven-Segment LEDs (U8 & U9) ....................................................................................................... 2–10

SRAM Memory (U35 & U36) ............................................................................................................. 2–10

Flash Memory (U5) .............................................................................................................................. 2–11

Serial Port Connectors (J19 & J27) ..................................................................................................... 2–14

Expansion Prototype Connectors (PROTO1 & PROTO2) ............................................................. 2–15

CompactFlash Connector (CON3) .................................................................................................... 2–20

Mictor Connector (J25) ........................................................................................................................ 2–22

Configuration Controller Device (U3) .............................................................................................. 2–25

Reset Distribution ........................................................................................................................... 2–25

Starting Configuration ................................................................................................................... 2–25

Stratix II Configuration .................................................................................................................. 2–25

Factory & User Configurations .......................................................................................................... 2–26

The Configuration Process ............................................................................................................ 2–26

Flash Memory Partitions ............................................................................................................... 2–27

User Application Space ............................................................................................................ 2–27

User Configuration ................................................................................................................... 2–28

Factory Configuration .............................................................................................................. 2–28

Persistent Data ........................................................................................................................... 2–28

Configuration-Status LEDs ........................................................................................................... 2–29

Configuration & Reset Buttons .................................................................................................... 2–30

SW8 – CPU Reset ...................................................................................................................... 2–30

SW9 – Factory Config ............................................................................................................... 2–30

SW10 – Reset, Config ................................................................................................................ 2–30

Altera Corporation iii

Contents

JTAG Connectors (J24 & J5) ................................................................................................................ 2–31

JTAG Connector to Stratix II Device (J24) ................................................................................... 2–31

JTAG Connector to EPM7128AE Device (J5) .............................................................................. 2–33

Power-Supply Circuitry ...................................................................................................................... 2–35

Shared Bus Table 1

Description ............................................................................................................................................. A–1

Restoring the Factory Configuration 1

Introduction ........................................................................................................................................... B–1

Reprogramming the Flash Memory ................................................................................................... B–1

Reprogramming the EPM7128AE Configuration Controller Device ............................................ B–1

Connecting to the Board via Ethernet 1

Introduction ........................................................................................................................................... C–1

Connecting the Ethernet Cable ........................................................................................................... C–1

Connecting the LCD Screen ................................................................................................................ C–2

Obtaining an IP Address ..................................................................................................................... C–2

LAN Connection .............................................................................................................................. C–3

DHCP ........................................................................................................................................... C–3

Static IP Address ........................................................................................................................ C–3

Point–to–Point Connections .......................................................................................................... C–4

Browsing to Your Board ...................................................................................................................... C–5

iv Altera Corporation

About this Manual

How to Find Information

This manual provides component details about the Nios® development
board, Stratix

The following table shows the reference manual’s revision history.

July 2005 Updated for the EP2S30 device.

October 2004 Updated the heat sink illustrations.

September 2004 First publication of Nios Development Board Reference

■ The Adobe Acrobat Find feature allows you to search the contents of

a PDF file. Click the binoculars toolbar icon to open the Find dialog
box.

■ Bookmarks serve as an additional table of contents.

■ Thumbnail icons, which provide miniature previews of each page,

provide a link to the pages.

■ Numerous links, shown in green text, allow you to jump to related

information.

™

II Edition.

Date Description

Manual, Stratix II Edition

Altera Corporation v
July 2005

How to Contact Altera

How to Contact
Altera

For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ altera.com/mysupport/

(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time)

Product literature www.altera.com www.altera.com

Altera literature services [e-mail] (1) [e-mail] (1)

Non-technical customer
service

FTP site ftp.altera.com ftp.altera.com

Note to table:

(1) You can also contact your local Altera sales office or sales representative.

[phone] [phone]

[phone] (1)
(7:00 a.m. to 5:00 p.m. Pacific Time)

(7:30 a.m. to 5:30 p.m. Pacific Time)

vi Altera Corporation

July 2005

About this Manual Typographic Conventions

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

c

w

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN

75: High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.

The warning indicates information that should be read prior to starting or
continuing the procedure or processes

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Altera Corporation vii
July 2005

Typographic Conventions

viii Altera Corporation

July 2005

Introduction

Features Overview

General Description

The Nios development board, Stratix II Edition, provides a hardware
platform for developing embedded systems based on Altera Stratix II
devices. The Nios development board, Stratix II Edition provides the
following features:

■ A Stratix II FPGA with more than 13,500 adaptive logic modules

(ALM) and 1.3 million bits of on-chip memory

■ 16 Mbytes of flash memory

■ 1Mbyte of static RAM

■ 16 Mbytes of SDRAM

■ On board logic for configuring the Stratix II device from flash

memory

■ On-board Ethernet MAC/PHY device

■ Two 5V-tolerant expansion/prototype headers each with access to 41

Stratix II user I/O pins

■ CompactFlash

■ Mictor connector for hardware and software debug

■ Two RS-232 DB9 serial ports

■ Four push-button switches connected to Stratix II user I/O pins

■ Eight LEDs connected to Stratix II user I/O pins

■ Dual 7-segment LED display

■ JTAG connectors to Altera

■ 50 MHz oscillator and zero-skew clock distribution circuitry

■ Power-on reset circuitry

The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to use the features of the Nios development
board. Software designers can use the pre-programmed Nios II processor
design on the board to begin prototyping software immediately.

TM

connector for Type I CompactFlash cards

®

devices via Altera download cables

This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board.

f Refer to the Nios II Development Kit, Getting Started User Guide for

instructions on setting up the Nios development board and installing
Nios II development tools.

Altera Corporation 1–1
July 2005

General Description

Figure 1–1 shows a block diagram of the Nios development board.

Figure 1–1. Nios Development Board, Stratix II Edition Block Diagram

1 Early shipments of the Nios development board, Stratix II

edition use an EP2S60F672C5ES device. This is a fully tested
engineering sample (ES) device. However, it has a known issue
affecting the M-RAM blocks. The issue can be worked around
easily, but some consideration is required when migrating
designs based on this device to a non-ES device. There is a label
near the FPGA; if the letters “ES” appear on the label, the device
is an engineering sample.

f For details, refer to the Stratix II FPGA Family Errata Sheet and the

documented example designs included in the Nios II Development Kit.

1–2 Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition July 2005

Introduction

Factory­Programmed
Reference
Design

When power is applied to the board, on-board logic configures the
Stratix II FPGA using hardware configuration data stored in flash
memory. When the device is configured, the Nios II processor design in
the FPGA wakes up and begins executing boot code from flash memory.

The board is factory-programmed with a default reference design. This
reference design is a web server that delivers web pages via the Ethernet
port. For further information on the default reference design, see

Appendix C, Connecting to the Board via Ethernet.

In the course of development, you may overwrite or erase the flash
memory space containing the default reference design. Altera provides
the flash image for the default reference design so you can return the
board to its default state. See Appendix B, Restoring the Factory

Configuration for more information.

Altera Corporation 1–3
July 2005 Nios Development Board Reference Manual, Stratix II Edition

Factory-Programmed Reference Design

1–4 Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition July 2005

Board Components

Component List

Figure 2–1. Nios Development Board

This section introduces all the important components on the Nios
development board (see Figure 2–1). A complete set of schematics, a
physical layout database, and GERBER files for the development board
are installed in the Nios II development kit documents directory.

See Figure 2–1 and Table 2–1 on page 2–6 for locations and brief
descriptions of all features of the board.

Altera Corporation 2–5
July 2005

Component List

Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 1 of 2)

Board Designation Name Description

Featured Device

U60 Stratix II FPGA EP2S60F672C5 or EP2S30F672C5 device with mounted

heat sink

User Interface

SW0 – SW3 Push-button

switches

D0 – D7 Individual LEDs Eight individual LEDs driven by the FPGA

U8, U9 Seven-segment

LEDs

Memory

U35, U36 SRAM memory Two SRAM chips combined to form 1 Mbyte of fast, static

U5 Flash memory 16 Mbytes of nonvolatile memory for use by both the FPGA

U57 SDRAM memory 16 Mbytes of SDRAM

Connectors & Interfaces

U4, RJ1 Ethernet

MAC/PHY

J19, J27 Serial connectors Two serial connectors with 5 V-tolerant buffers. Supports all

PROTO1 (J11, J12, J13) Expansion

prototype
connector

PROTO2 (J15, J16, J17) Expansion

prototype
connector

CON3 CompactFlash

connector

J25 Mictor connector Mictor connector for debugging Nios II systems using a First

J24 JTAG connector Connects to the FPGA allowing hardware configuration from

J5 JTAG connector Connects to the configuration controller

Configuration & Reset

U3 Configuration

controller

Four momentary contact switches for user input to the FPGA

Two seven-segment LEDs to display numeric output from the
FPGA

RAM

and the configuration controller

10/100 Ethernet MAC/PHY chip connected to an RJ-45
Ethernet connector

RS-232 signals.

Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.

Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.

CompactFlash connector for memory expansion

Silicon Solutions (FS2) debug probe.

Quartus II software and software debug from the Nios II IDE.

Altera EPM7128AE device used to configure the FPGA from
flash memory

2–6 Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition July 2005

Board Components

Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 2 of 2)

Board Designation Name Description

SW8 CPU Reset button Push-button switch to reboot the Nios II processor configured

in the FPGA

SW9 Factory Config

button

SW10 Reset, Config Push-button switch to reset the board

LED0 – LED3 Configuration

status LEDs

Clock Circuitry

Y2 Oscillator 50 MHz clock signal driven to FPGA

J4 External clock

input

Power Supply

J26 DC power jack 17 V DC unregulated power source

D34 Bridge rectifier Power rectifier allows for center-negative or center-positive

Push-button switch to reconfigure the FPGA with the factory­programmed reference design

LEDs that display the current configuration status of the
FPGA

Connector to FPGA clock pin

power supplies

The sections that follow describe each component in detail.

Stratix II Device (U60)

U60 is a Stratix II FPGA in a 672-pin FineLine BGA® package. Early
shipments of the Nios Development Board, Stratix II Edition included an
EP2S60F672C5 device. Some early boards used engineering sample parts,
indicated by “ES” after the part number. Later shipments of the board use
an EP2S30F672C5 device. Table 2–2 lists the device features.

Table 2–2. Stratix II Device Features (Part 1 of 2)

Feature EP2S30 EP2S60

ALMs 13,552 24,176

Adaptive look-up tables (ALUTs) 27,104 48,352

Equivalent LEs 33,880 60,440

M512 RAM blocks 202 329

M4K RAM blocks 144 255

M-RAM blocks 1 2

Total RAM bits 1,369,728 2,544,192

DSP blocks 16 36

Altera Corporation 2–7
July 2005 Nios Development Board Reference Manual, Stratix II Edition

Stratix II Device (U60)

Table 2–2. Stratix II Device Features (Part 2 of 2)

Feature EP2S30 EP2S60

18-bit x 18-bit multipliers 64 144

Enhanced PLLS 2 4

Fast PLLs 4 8

User I/O pins 500 492

The development board provides two separate methods for configuring
the Stratix II device:

1. Using the Quartus II software running on a host computer, a
designer configures the device directly via an Altera® download

cable connected to the Stratix II JTAG header (J24).

2. When power is applied to the board, a configuration controller
device (U3) attempts to configure the Stratix II device with
hardware configuration data stored in flash memory. For more
information on the configuration controller, see “Configuration

Controller Device (U3)” on page 2–25.

f For Stratix II-related documentation including Stratix II pinout data refer

to the Altera Stratix II literature page at www.altera.com/ literature/lit­stx2.html.

Early shipments of the board had a heat sink mounted on the Stratix II
FPGA. Boards shipped later than May 2005 do not include the heat sink,
because thermal management is unnecessary for the majority of FPGA
designs for this board. A heat sink maintains the FPGA within its
specified thermal operating range, independent of the resource
utilization, clock frequency, and operating conditions of the FPGA. The
heat sink used on early shipments of the board is produced by Intricast
Inc., part number CS1995V01. See www.intricast.com for details.

f Refer to Altera's AN185: Thermal Management Using Heat Sinks for

information on using heat sinks with Altera devices.

2–8 Altera Corporation
Nios Development Board Reference Manual, Stratix II Edition July 2005

Board Components

Push-Button
Switches (SW0 ­SW3)

Individual LEDs (D0 - D7)

SW0 – SW3 are momentary-contact push-button switches and are used to
provide stimulus to designs in the Stratix II device. See Figure 2–2. Each
switch is connected to a Stratix II general-purpose I/O pin with a pull-up
resistor as shown in Tab le 2– 3. Each Stratix II device pin will see a logic 0
when its corresponding switch is pressed.

Table 2–3. Push Button Switches Pin Out
Tab le

Button

SW0 W24

SW1 W23

SW2 Y24

SW3 Y23

This Nios development board provides eight individual LEDs connected
to the Stratix II device. See Figure 2–2. D0 – D7 are connected to general
purpose I/O pins on the Stratix II device as shown in Ta bl e 2 –4 . When the
Stratix II pin drives logic 1, the corresponding LED turns on.

Table 2–4. LED Pin Out Table

LED Stratix II Pin

D0 AD26

D1 AD25

D2 AC25

D3 AC24

D4 AB24

D5 AB23

D6 AB26

D7 AB25

Stratix II Pin

Altera Corporation 2–9
July 2005 Nios Development Board Reference Manual, Stratix II Edition