Altera NCO MegaCore Function User Manual
NCO IP Core
User Guide
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TOC-2
Contents
About the NCO IP Core...................................................................................... 1-1
NCO IP Core Getting Started............................................................................. 2-1
Altera DSP IP Core Features...................................................................................................................... 1-1
NCO IP Core Features................................................................................................................................ 1-2
DSP IP Core Device Family Support.........................................................................................................1-2
NCO IP Core MegaCore Verification.......................................................................................................1-3
NCO IP Core Release Information............................................................................................................1-3
NCO IP Core Performance and Resource Utilization............................................................................1-4
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
NCO IP Core OpenCore Plus Timeout Behavior....................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-5
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-8
DSP Builder Design Flow............................................................................................................................2-9
NCO IP Core Functional Description................................................................ 3-1
NCO IP Core Architectures....................................................................................................................... 3-2
Large ROM Architecture................................................................................................................ 3-2
Small ROM Architecture................................................................................................................ 3-2
CORDIC Architecture.....................................................................................................................3-3
Multiplier-Based Architecture....................................................................................................... 3-4
Multichannel NCOs.....................................................................................................................................3-5
Frequency Hopping.....................................................................................................................................3-5
Phase Dithering............................................................................................................................................3-6
Frequency Modulation................................................................................................................................3-7
Phase Modulation........................................................................................................................................3-7
NCO IP Core Parameters........................................................................................................................... 3-7
Architecture Parameters................................................................................................................. 3-7
Frequency Parameters.....................................................................................................................3-8
Optional Ports Parameters..............................................................................................................3-9
NCO IP Core Interfaces and Signals.........................................................................................................3-9
Avalon-ST Interfaces in DSP IP Cores..........................................................................................3-9
NCO IP Core Signals.....................................................................................................................3-10
NCO IP Core Timing Diagrams..................................................................................................3-11
NCO Multichannel Design Example...................................................................4-1
NCO Design Example Specification..........................................................................................................4-2
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TOC-3
Opening the NCO Multichannel Design Example..................................................................................4-4
Document Revision History................................................................................5-1
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2014.12.15
Constellation
Mapper
IF Signal
NCO
Q
I
FIR
Filter
FIR
Filter
cos(wt)
sin(wt)
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About the NCO IP Core
1
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The Altera® NCO IP core generates numerically controlled oscillators (NCOs) customized for Altera
devices. A numerically controlled oscillator (NCO) synthesizes a discrete-time, discrete-valued
representation of a sinusoidal waveform.
Typically, you can use NCOs in communication systems as quadrature carrier generators in I-Q mixers,
in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways.
Figure 1-1: Simple Modulator
You can also use NCOs in all-digital phase-locked-loops (PLLs) for carrier synchronization in communi‐
cations receivers, or as standalone frequency shift keying (FSK) or phase shift keying (PSK) modulators.
In these applications, the phase or the frequency of the output waveform varies directly according to an
input data stream.
You can implement ROM-based, CORDIC-based, and multiplier-based NCO architectures,. The wizard
also includes time and frequency domain graphs that dynamically display the functionality of the NCO,
based on your parameter settings.
To decide which NCO implementation to use, consider the spectral purity, frequency resolution,
performance, throughput, and required device resources. Also, consider the trade-offs between some or
all of these parameters.
Altera DSP IP Core Features
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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NCO IP Core Features
• Avalon® Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
NCO IP Core Features
• 32-bit precision for angle and magnitude
• Source interface compatible with the Avalon Interface Specification
• Multiple NCO architectures:
• Multiplier-based implementation using DSP blocks or logic elements (LEs), (single cycle and multicycle)
• Parallel or serial CORDIC-based implementation
• ROM-based implementation using embedded array blocks (EABs), embedded system blocks
(ESBs), or external ROM
• Single or dual outputs (sine/cosine)
• Variable width frequency modulation input
• Variable width phase modulation input
• User-defined frequency resolution, angular precision, and magnitude precision
• Frequency hopping
• Multichannel capability
• Simulation files and architecture-specific testbenches for VHDL, Verilog HDL and MATLAB
• Dual-output oscillator and quaternary frequency shift keying (QFSK) modulator example designs
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DSP IP Core Device Family Support
Altera offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: DSP IP Core Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final
Cyclone® IV Final
Cyclone V Final
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NCO Compiler
Wizard
Bit
Accurate
Model
Output
File
Verilog HDL
Output
File
VHDL
Output
File
Synthesis
Structure
Output
File
Perl
Script
Parameter
Sweep
Compare
Results
Testbench
All Languages
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Device Family Support
MAX® 10 FPGA Final
Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Other device families No support
NCO IP Core MegaCore Verification
Figure 1-2: Regression Flow
NCO IP Core MegaCore Verification
1-3
NCO IP Core Release Information
Table 1-2: NCO IP Core Release Information
Version 14.1
Release Date December 2014
Ordering Code IP-NCO
Product ID(s) 0014
Vendor ID(s) 6AF7
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Item Description
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NCO IP Core Performance and Resource Utilization
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous
version. The Altera IP Release Notes lists any exceptions.
Related Information
• Altera IP Release Notes
• Errata for NCO IP core in the Knowledge Base
NCO IP Core Performance and Resource Utilization
Table 1-3: NCO IP Core Performance
Typical performance using the Quartus II software with the Arria V (5AGXFB3H4F40C4), Cyclone V
(5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices
Device Parameters ALM
DSP
Blocks
Arria V Cordic 838 0 1 -- 1,879 8 340
Memory Registers
M10K M20K Primary Secondary
(MHz)
f
MAX
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Arria V Large Rom 56 0 12 -- 149 0 350
Arria V Multiplier
92 2 2 -- 244 2 310
Based
Arria V Small ROM 132 0 6 -- 300 0 350
CycloneVCordic 838 0 1 -- 1,881 6 260
CycloneVLarge Rom 56 0 12 -- 149 0 275
CycloneVMultiplier
92 2 2 -- 244 2 275
Based
CycloneVSmall ROM 120 0 6 -- 300 0 275
Stratix V Cordic 838 0 -- 1 1,881 6 644
Stratix V Large Rom 56 0 -- 5 149 0 700
Stratix V Multiplier
92 2 -- 2 245 1 500
Based
Stratix V Small ROM 126 0 -- 3 300 0 700
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acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
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NCO IP Core Getting Started
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1.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note:
The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2-2
NCO IP Core OpenCore Plus Timeout Behavior
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
NCO IP Core OpenCore Plus Timeout Behavior
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the
time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus
II software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCore
Plus evaluation program. After you activate the feature, do not delete these files..
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When the evaluation time expires, the output of NCO IP core goes low.
Related Information
• AN 320: OpenCore Plus Evaluation of Megafunctions
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
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Search for installed IP cores
Double-click to customize, right-click for
detailed information
Show IP only for target device
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Specifying IP Core Parameters and Options
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no
project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, and view links to documentation.
• Click Search for Partner IP, to access partner IP information on the Altera website.
Figure 2-2: Quartus II IP Catalog
2-3
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Specifying IP Core Parameters and Options
You can quickly configure a custom IP variation in the parameter editor. Use the following steps to
specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters
and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.
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Specifying IP Core Parameters and Options
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1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Optionally select preset parameter values if provided for your IP core. Presets specify initial
parameter values for specific applications.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
7. To generate an HDL instantiation template that you can copy and paste into your text editor, click
Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If
you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in
Project to add the file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
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