Altera MAX V CPLD Development Board User Manual

MAX V CPLD Development Board Reference Manual

MAX V CPLD Development Board

Reference Manual

101 Innovation Drive
San Jose, CA 95134

www.altera.com

MNL-01061-1.0

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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective
holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance
with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera
customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
services.

MAX V CPLD Development Board Reference Manual January 2011 Altera Corporation

Contents

Chapter 1. Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: MAX V CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

CPLD Configuration over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

CPLD Configuration using External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

PC Speaker Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

DC Motor Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Off-Chip EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

2

I

C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

January 2011 Altera Corporation MAX V CPLD Development Board Reference Manual

iv Contents

MAX V CPLD Development Board Reference Manual January 2011 Altera Corporation

Introduction

This document describes the hardware features of the MAX® V CPLD development
board, including the detailed pin-out and component reference information required
to create custom CPLD designs that interface with all components of the board.

General Description

The MAX V CPLD development board provides a hardware platform for developing
and prototyping low-cost, low-power CPLD designs, as well as to demonstrate the
features of the MAX V CPLD device.

To facilitate the development of MAX V CPLD designs, the board provides connectors
to interface to external functions or devices.

f For more information on the MAX V CPLD device family, refer to the MAX V Device

Handbook.

1. Overview

Board Component Blocks

The board features the following major component blocks:

■ MAX V CPLD 5M570ZF256C5N in a 256-pin FineLine BGA (FBGA) package

■ 570 logic elements (LEs)

■ 440 equivalent macrocells

■ 8,192-bits user flash memory (UFM)

■ 4 global clocks

■ 159 user I/Os

■ 1.8-V core power

■ MAX II EPM240M100C4N CPLD in the 100-pin Micro FBGA (MBGA) package

■ On-Board configuration circuitry

■ Embedded USB-Blaster

■ On-Board connectors

■ Type-B USB connector (as power source and communication port)

■ Two general purpose I/O (GPIO) 2×20-pin 0.1-inch expansion headers

■ One 4-pin PC speaker header

TM

for use with the Quartus® II Programmer

■ Two 2×3-pin DC motor headers

■ On-Board clocking circuitry

■ 10-MHz single-ended external oscillator

January 2011 Altera Corporation MAX V CPLD Development Board Reference Manual

1–2 Chapter 1: Overview

DC Motor
Header 1

EPM240M100

Embedded

USB-Blaster

USB

2.0

x1

x9

x2

JTAG Chain

GPIO

Header 2

EP5M570ZF256N

SPI x4

User LEDs

Push-Button

Switches

x2

x36

I2C x2

10 MHz Oscillator

GPIO

Header 1

x36

PC Speaker

Header

Capacitor

Sense

Push-Button

Switch

x8

x9

DC Motor
Header 2

EEPROM

EEPROM

Development Board Block Diagram

■ General user I/O

■ LEDs and display

■ Two CPLD user LEDs

■ One USB status LED

■ One power status LED

■ Push-Button switches

■ Two user-defined push-button switches

■ One capacitor sense push-button switch

■ Mechanical

■ 4.1” × 3.1” board

Development Board Block Diagram

Figure 1–1 shows the block diagram of the MAX V CPLD development board.

Figure 1–1. MAX V CPLD Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge
precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

MAX V CPLD Development Board Reference Manual January 2011 Altera Corporation

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demonstration

2. Board Components

This chapter introduces the major components on the MAX V CPLD development
board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief
description of all component features of the board.

development board reside in the MAX V CPLD development kit documents directory.

software, refer to the MAX V CPLD Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: MAX V CPLD” on page 2–3

■ “Configuration, Status, and Setup Elements” on page 2–5

■ “Clock Circuitry” on page 2–7

■ “Connectors” on page 2–8

■ “General User Input/Output” on page 2–13

■ “Off-Chip EEPROM” on page 2–14

■ “Power Supply” on page 2–16

■ “Statement of China-RoHS Compliance” on page 2–16

January 2011 Altera Corporation MAX V CPLD Development Board Reference Manual

2–2 Chapter 2: Board Components

MAX V

CPLD

(U5)

10-MHz Single-Ended

External Oscillator

(J1)

User

LEDs

(D7, D8)

GPIO Headers

(J6, J7)

USB Type-B

Connector (J4)

Motor Control

Header 1

(J5)

Power LED

(D1)

User

Push-Button

Switches (S1, S2)

MAX II CPLD
EPM240M100C4N
(For embedded
USB-Blaster) (U4)

Motor Control

Header 2

(J10)

Speaker

Header

(J9)

Footprint for

I

2

C EEPROM

(U6)

Footprint for
SPI EEPROM
(U8)

Powe r
Regulator
(U7)

USB LED

(D3)

Capacitor

Sense Button

(CPB1)

VAR_VCCIO
Voltage Output
Selection Jumper
(U7)

Board Overview

Board Overview

This section provides an overview of the MAX V CPLD development board,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.

Figure 2–1. Overview of the MAX V CPLD Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. MAX V CPLD Development Board Components (Part 1 of 2)

Board Reference Type Description

Featured Device

U5 CPLD MAX V 5M570ZF256C5N, 256-pin FBGA.

Configuration, Status, and Setup Elements

Connects the USB cable to the computer to enable embedded

J4 USB Type-B connector

USB-Blaster JTAG. The connector also supplies power to the board
through a USB cable when the cable is connected to a PC USB slot at
the other end.

MAX V CPLD Development Board Reference Manual January 2011 Altera Corporation