ALTERA MAX V Service Manual

MAX V Device Handbook

101 Innovation Drive San Jose, CA 95134

www.altera.com

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, Q UARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service ma rks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsi bility or liability arising out of the appli cation or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are a dvised to obtain the latest version of devi ce specifica tions before relying on any published information and before placing orders for products or servi ces.

MAX V Device Handbook May 2011 Altera Corporation

Section I. MAX V Device Core

Chapter 1. MAX V Device Family Overview

Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Integrated Software Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. MAX V Architecture

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

LUT Chain and Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

addnsub Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

LE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Dynamic Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Carry-Select Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

LE RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

User Flash Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

UFM Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Program, Erase, and Busy Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Auto-Increment Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

UFM Block to Logic Array Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Core Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

Fast I/O Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

I/O Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

I/O Standards and Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

PCI Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

LVDS and RSDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Output Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Programmable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Slew-Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

Programmable Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

Bus-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

May 2011 Altera Corporation MAX V Device Handbook

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MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Chapter 3. DC and Switching Characteristics for MAX V Devices

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Programming/Erasure Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Bus Hold Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Timing Model and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Preliminary and Final Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

Internal Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

External Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

External Timing I/O Delay Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23

Maximum Input and Output Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26

LVDS and RSDS Output Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

JTAG Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30

Section II. System Integration in MAX V Devices

Chapter 4. Hot Socketing and Power-On Reset in MAX V Devices

MAX V Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Devices Can Be Driven Before Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

I/O Pins Remain Tri-Stated During Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Signal Pins Do Not Drive the V

AC and DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Hot-Socketing Feature Implementation in MAX V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Chapter 5. Using MAX V Devices in Multi-Voltage Systems

I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

MultiVolt I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5.0-V Device Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Recommended Operating Conditions for 5.0-V Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

Chapter 6. JTAG and In-System Programmability in MAX V Devices

IEEE Std. 1149.1 Boundary-Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

JTAG Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

Parallel Flash Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

IEEE 1532 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

Jam Standard Test and Programming Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

CCIO

or V

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

CCINT

MAX V Device Handbook May 2011 Altera Corporation

Contents v

Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

User Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

In-System Programming Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Real-Time ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Programming with External Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Chapter 7. User Flash Memory in MAX V Devices

UFM Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

Memory Organization Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

Using and Accessing UFM Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

UFM Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

UFM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

UFM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

UFM Program/Erase Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

Instantiating the Oscillator without the UFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

UFM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

Read/Stream Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

Programming and Reading the UFM with JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

Jam Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

Jam Players . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

Software Support for UFM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

Inter-Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

Byte Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16

Page Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Acknowledge Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20

ALTUFM_I2C Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22

Instantiating the I

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–23

Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25

ALTUFM SPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35

Instantiating SPI Using Quartus II ALTUFM_SPI Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . 7–35

Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36

ALTUFM Parallel Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37

Instantiating Parallel Interface Using Quartus II ALTUFM_PARALLEL Megafunction . . . . . . 7–37

None (Altera Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38

Instantiating None Using Quartus II ALTUFM_NONE Megafunction . . . . . . . . . . . . . . . . . . . . 7–38

Creating Memory Content File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39

Memory Initialization for the ALTUFM_PARALLEL Megafunction . . . . . . . . . . . . . . . . . . . . . . 7–39

Memory Initialization for the ALTUFM_SPI Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39

Memory Initialization for the ALTUFM_I2C Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40

Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43

C Interface Using the Quartus II ALTUFM_I2C Megafunction . . . . . . . . . . . 7–23

May 2011 Altera Corporation MAX V Device Handbook

vi Contents

Chapter 8. JTAG Boundary-Scan Testing in MAX V Devices

IEEE Std. 1149.1 BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

IEEE Std. 1149.1 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

Boundary-Scan Cells of a MAX V Device I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4

JTAG Pins and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5

IEEE Std. 1149.1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6

SAMPLE/PRELOAD Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8

EXTEST Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

BYPASS Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

IDCODE Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

USERCODE Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

CLAMP Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

HIGHZ Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

I/O Voltage Support in the JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

Boundary-Scan Test for Programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14

Disabling IEEE Std. 1149.1 BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

MAX V Device Handbook May 2011 Altera Corporation

Section I. MAX V Device Core

This section provides a complete overview of all features relating to the MAX®V device family.

This section includes the following chapters:

■ Chapter 1, MAX V Device Family Overview

■ Chapter 2, MAX V Architecture

■ Chapter 3, DC and Switching Characteristics for MAX V Devices

May 2011 Altera Corporation MAX V Device Handbook

I–2 Section I: MAX V Device Core

MAX V Device Handbook May 2011 Altera Corporation

MV51001-1.2

1. MAX V Device Family Overview

The MAX®V family of low cost and low power CPLDs offer more density and I/Os per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements (LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog IC interface.

MAX V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX V CPLDs can help you meet your low power design requirement.

This chapter contains the following sections:

■ “Feature Summary” on page 1–1

■ “Integrated Software Platform” on page 1–3

■ “Device Pin-Outs” on page 1–3

■ “Ordering Information” on page 1–4

Feature Summary

The following list summarizes the MAX V device family features:

■ Low-cost, low-power, and non-volatile CPLD architecture

■ Instant-on (0.5 ms or less) configuration time

■ Standby current as low as 25 µA and fast power-down/reset operation

■ Fast propagation delay and clock-to-output times

■ Internal oscillator

■ Emulated RSDS output support with a data rate of up to 200 Mbps

■ Emulated LVDS output support with a data rate of up to 304 Mbps

■ Four global clocks with two clocks available per logic array block (LAB)

■ User flash memory block up to 8 Kbits for non-volatile storage with up to 1000

read/write cycles

■ Single 1.8-V external supply for device core

■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

■ Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the righ t to make changes to any products and services a t any time without n otice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera cus tomers are advised to obtain the latest version of device specifications before relying on any published information and befo re placing orders for products or services.

MAX V Device Handbook May 2011

1–2 Chapter 1: MAX V Device Family Overview

Feature Summary

■ I/Os are fully compliant with the PCI-SIG

PCI Local Bus Specification, revision

2.2 for 3.3-V operation

■ Hot-socket compliant

■ Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990

Ta bl e 1 –1 lists the MAX V family features.

Table 1–1. MAX V Family Features

Feature 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z

LEs 40 80 160 240 570 1,270 2,210

Typical Equivalent Macrocells 32 64 128 192 440 980 1,700

User Flash Memory Size (bits) 8,192 8,192 8,192 8,192 8,192 8,192 8,192

Global Clocks 4444444

Internal Oscillator 1 1 1 1 1 1 1

Maximum User I/O pins 54 79 79 114 159 271 271

(ns) (1) 7.5 7.5 7.5 7.5 9.0 6.2 7.0

PD1

(MHz) (2) 152 152 152 152 152 304 304

CNT

(ns) 2.3 2.3 2.3 2.3 2.2 1.2 1.2

(ns) 6.5 6.5 6.5 6.5 6.7 4.6 4.6

Notes to Table 1–1:

(1) t

represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic

PD1

implemented in a single LUT and LAB that is adjacent to the output pin.

(2) The maximum global clock frequency, f

than this number.

, is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster

CNT

MAX V devices accept 1.8 V on their

VCCINT

pins. The 1.8-V V

external supply

CCINT

powers the device core directly. MAX V devices operate internally at 1.8 V. The supported MultiVolt I/O interface voltage levels (V

) are 1.2 V, 1.5 V, 1.8 V, 2.5 V,

CCIO

and 3.3 V.

MAX V devices are available in two speed grades: –4 and –5, with –4 being the fastest. For commercial applications, speed grades –C4 and –C5 are available. For industrial and automotive applications, speed grade –I5 and –A5 are available, respectively. These speed grades represent the overall relative performance, not any specific timing parameter.

f For propagation delay timing numbers within each speed grade and density, refer to

the DC and Switching Characteristics for MAX V Devices chapter.

MAX V devices are available in space-saving FineLine BGA (FBGA), Micro FineLine BGA (MBGA), plastic enhanced quad flat pack (EQFP), and thin quad flat pack (TQFP) packages (refer to Table 1–2 and Ta bl e 1 – 3). MAX V devices support vertical migration within the same package (for example, you can migrate between the 5M570Z, 5M1270Z, and 5M2210Z devices in the 256-pin FineLine BGA package). Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must lay out for the largest planned density in a package to provide

MAX V Device Handbook May 2011 Altera Corporation

Chapter 1: MAX V Device Family Overview 1–3

Integrated Software Platform

the necessary power pins for migration. For I/O pin migration across densities, cross reference the available I/O pins using the device pin-outs for all planned densities of

a given package type to identify which I/O pins can be migrated. The Quartus

II software can automatically cross-reference and place all pins for you when given a device migration list.

Table 1–2. MAX V Packages and User I/O Pins (Note 1)

Device

5M40Z 30 54 — — — — — —

5M80Z 30 54 52 79 — — — —

5M160Z — 54 52 79 79 — — —

5M240Z — — 52 79 79 114 — —

5M570Z — — — 74 74 114 159 —

5M1270Z — — — — — 114 211 271

5M2210Z — — — — — — 203 271

Note to Table 1–2:

(1) Device packages under the same arrow sign have vertical migration capability.

Table 1–3. MAX V Package Sizes

Package

Pitch (mm) 0.5 0.4 0.5 0.5 0.5 0.5 1 1

Area (mm

Length × width (mm × mm)

) 20.25 81 25 256 36 484 289 361

64-Pin

MBGA

64-Pin

MBGA

4.5 × 4.5 9 × 9 5 × 5 16 × 16 6 × 6 22 × 22 17 × 17 19 × 19

64-Pin

EQFP

64-Pin

EQFP

68-Pin

MBGA

68-Pin

MBGA

100-Pin

TQFP

100-Pin

TQFP

100-Pin

MBGA

100-Pin

MBGA

144-Pin

TQFP

144-Pin

TQFP

256-Pin

FBGA

256-Pin

FBGA

324-Pin

FBGA

324-Pin

FBGA

Integrated Software Platform

The Quartus II software provides an integrated environment for HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, and programming of MAX V devices.

f For more information about the Quartus II software features, refer to the Quartus II

Handbook.

You can debug your MAX V designs using In-System Sources and Probes Editor in the Quartus II software. This feature allows you to easily control any internal signal and provides you with a completely dynamic debugging environment.

f For more information about the In-System Sources and Probes Editor, refer to the

Design Debugging Using In-System Sources and Probes chapter of the Quartus II

Handbook.

Device Pin-Outs

f For more information, refer to the MAX V Device Pin-Out Files page.

May 2011 Altera Corporation MAX V Device Handbook

1–4 Chapter 1: MAX V Device Family Overview

Package Type

T: Thin quad flat pack (TQFP) F: FineLine BGA (FBGA) M: Micro FineLine BGA (MBGA) E: Plastic Enhanced Quad Flat Pack (EQFP)

Speed Grade

Family Signature

5M: MAX V

Operating Temperature

Pin Count

Device Type

40Z: 40 Logic Elements 80Z: 80 Logic Elements 160Z: 160 Logic Elements 240Z: 240 Logic Elements 570Z: 570 Logic Elements 1270Z: 1,270 Logic Elements 2210Z: 2,210 Logic Elements

Optional Suffix

4 or 5, with 4 being the fastest

Number of pins for a particular package

C: Commercial temperature (T

= 0° C to 85° C)

I: Industrial temperature (T

= -40° C to 100° C)

A: Automotive temperature (TJ = -40° C to 125° C)

5M 40Z E 64 C 4 N

Indicates specific device options or shipment method

N: Lead-free packaging

Ordering Information

Figure 1–1 shows the ordering codes for MAX V devices.

Figure 1–1. MAX V Device Packaging Ordering Information

Document Revision History

Ta bl e 1 –4 lists the revision history for this chapter.

Table 1–4. Document Revision History

Date Version Changes

May 2011 1.2

January 2011 1.1 Updated “Feature Summary” section.

December 2010 1.0 Initial release.

MAX V Device Handbook May 2011 Altera Corporation

■ Updated Figure 1–1.

■ Updated Ta ble 1– 3.

MV51002-1.0

2. MAX V Architecture

This chapter describes the architecture of the MAX® V device and contains the following sections:

■ “Functional Description” on page 2–1

■ “Logic Array Blocks” on page 2–4

■ “Logic Elements” on page 2–8

■ “MultiTrack Interconnect” on page 2–14

■ “Global Signals” on page 2–19

■ “User Flash Memory Block” on page 2–21

■ “Internal Oscillator” on page 2–22

■ “Core Voltage” on page 2–25

■ “I/O Structure” on page 2–26

Functional Description

MAX V devices contain a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs).

Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of logic that provides efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures.

The I/O elements (IOEs) located after the LAB rows and columns around the periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single-ended standards, such as 33-MHz, 32-bit PCI™, and LVTTL.

MAX V devices provide a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device. You can also use the global clock lines for control signals such as clear, preset, or output enable.

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or li ab ility aris ing out of th e app lic atio n or us e of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook December 2010

2–2 Chapter 2: MAX V Architecture

Logic Array BLock (LAB)

MultiTrack Interconnect

MultiTrack

Interconnect

Logic

Element

Logic

Element

IOE

IOE IOE

Logic

Element

Logic

Element

IOE

Logic

Element

Logic

Element

IOE IOE

Logic

Element

Logic

Element

Logic

Element

Logic

Element

IOE IOE

Logic

Element

Logic

Element

Functional Description

Figure 2–1 shows a functional block diagram of the MAX V device.

Figur e 2–1. Device Block Diagram

Each MAX V device contains a flash memory block within its floorplan. This block is located on the left side of the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. On the 5M240Z (T144 package), 5M570Z, 5M1270Z, and 5M2210Z devices, the flash memory block is located on the bottom-left area of the device. The majority of this flash memory storage is partitioned as the dedicated configuration flash memory (CFM) block. The CFM block provides the non-volatile storage for all of the SRAM configuration information. The CFM automatically downloads and configures the logic and I/O at power-up, providing instant-on operation.

f For more information about configuration upon power-up, refer to the Hot Socketing

and Power-On Reset for MAX V Devices chapter.

A portion of the flash memory within the MAX V device is partitioned into a small block for user data. This user flash memory (UFM) block provides 8,192 bits of general-purpose user storage. The UFM provides programmable port connections to the logic array for reading and writing. There are three LAB rows adjacent to this block, with column numbers varying by device.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–3

Functional Description

Table 2–1 lists the number of LAB rows and columns in each device, as well as the

number of LAB rows and columns adjacent to the flash memory area. The long LAB rows are full LAB rows that extend from one side of row I/O blocks to the other. The short LAB rows are adjacent to the UFM block; their length is shown as width in LAB columns.

Table 2–1 . Device Resources for MAX V Devi ces

Device UFM Bl ocks LAB Column s

Tot al L ABs

Long LAB Rows Short LAB Rows (Width) (1)

5M40Z 1 6 4 — 24

5M80Z 1 6 4 — 24

5M160Z 1 6 4 — 24

5M240Z (2) 164 — 24

5M240Z (3) 1124 3 (3) 57

5M570Z 1 12 4 3 (3) 57

5M1270Z (4) 1167 3 (5) 127

5M1270Z (5) 12010 3 (7) 221

5M2210Z 1 20 10 3 (7) 221

Notes to Tab le 2 –1 :

(1) The width is the number of LAB columns in length. (2) Not applicable to T144 package of the 5M240Z device. (3) Only applicable to T144 package of the 5M240Z device. (4) Not applicable to F324 package of the 5M1270Z device. (5) Only applicable to F324 package of the 5M1270Z device.

LAB Rows

December 2010 Altera Corporation MAX V Device Handbook

2–4 Chapter 2: MAX V Architecture

Logic Array Blocks

Figure 2–2 shows a floorplan of a MAX V device.

Figur e 2–2. Device Floorplan for MAX V Devices (Note 1)

I/O Blocks

Logic Array

Blocks

2 GCLK

Inputs

I/O Blocks

UFM Block

CFM Block

Logic Arra Blocks

2 GCLK Inputs

Note to Figure 2–2:

(1) The device shown is a 5M570Z device. 5M1270Z and 5M2210Z devices have a similar floorplan with more LABs. For 5M40Z, 5M80Z, 5M160Z,

and 5M240Z devices, the CFM and UFM blocks are located on the left side of the device.

Logic Array Blocks

Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, a look-up table (LUT) chain, and register chain connection lines. There are 26 possible unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE outputs in the same LAB. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the LUT output from one LE to the

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–5

Logic Array Blocks

adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE’s register to the adjacent LE’s register within an LAB. The Quartus® II software places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–3 shows the MAX V LAB.

Figur e 2–3. LAB Str ucture for MAX V Devices

Row Interconnect

Column Interconnect

Fast I/O connection to IOE (1)

DirectLink interconnect from adjacent LAB or IOE

LE0

LE1

LE2

LE3

LE4

LE5

Fast I/O connection to IOE (1)

DirectLink interconnect from adjacent LAB or IOE

DirectLink interconnect to adjacent LAB or IOE

Note to Figure 2–3:

(1) Only from LABs adjacent to IOEs.

Logic Element

LE6

LE7

LE8

LE9

DirectLink interconnect to adjacent LAB or IOE

Local InterconnectLAB

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2–6 Chapter 2: MAX V Architecture

LAB

DirectLink interconnect to right

DirectLink interconnect from right LAB or IOE output

DirectLink interconnect from

left LAB or IOE output

Local

Interconnect

DirectLink

interconnect

to left

LE0

LE1

LE2

LE3

LE4

LE6

LE7

LE8

LE9

LE5

Logic Element

Logic Array Blocks

LAB Interconnects

Column and row interconnects and LE outputs within the same LAB drive the LAB local interconnect. Adjacent LABs, from the left and right, can also drive an LAB’s local interconnect through the DirectLink connection. The DirectLink connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink interconnects. Figure 2–4 shows the DirectLink connection.

Figur e 2–4. DirectLink Connection

MAX V Device Handbook December 2010 Altera Corporation

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, a synchronous clear, an asynchronous preset/load, a synchronous load, and add/subtract control signals, providing a maximum of 10 control signals at a time. Synchronous load and clear signals are generally used when implementing counters but they can also be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked. For example, any LE in a particular LAB using the

labclk1

of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable signal turns off the LAB-wide clock.

Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. By default, the Quartus II software uses a achieve preset. If you disable the to power-up high using the Quartus II software, the preset is then achieved using the asynchronous load signal with asynchronous load data input tied high.

signal also uses

labclkena1

NOT

. If the LAB uses both the rising and falling edges

NOT

gate push-back technique to

gate push-back option or assign a given register

Chapter 2: MAX V Architecture 2–7

labclkena1

labclk2labclk1

labclkena2

asyncload

or labpre

syncload

Dedicated LAB Column Clocks

Local Interconnect

labclr1

labclr2

synclr

addnsub

Logic Array Blocks

With the LAB-wide and subtractor. This signal saves LE resources and improves performance for logic functions such as correlators and signed multipliers that alternate between addition and subtraction depending on data.

The LAB column clocks interconnect generate the LAB-wide control signals. The MultiTrack interconnect structure drives the LAB local interconnect for non-global control signal generation. The MultiTrack interconnect’s inherent low skew allows clock and control signal distribution in addition to data signals. Figure 2–5 shows the LAB control signal generation circuit.

Figur e 2–5. LAB-Wide Control Signals

addnsub

[3..0]

control signal, a single LE can implement a one-bit adder

, driven by the global clock network, and LAB local

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Logic Elements

The smallest unit of logic in the MAX V architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry-select capability. A single LE also supports dynamic single-bit addition or subtraction mode that is selected by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and DirectLink interconnects as shown in Figure 2–6.

Figur e 2–6. LE for MAX V Devices

addnsub

data1

data2 data3

data4

labclr1 labclr2

labpre/aload

Chip-Wide

Reset (DEV_CLRn)

labclk1 labclk2

LAB Carry-In

Carry-In1

Carry-In0

Asynchronous

Clear/Preset/

Load Logic

Clock and

Clock Enable

Select

Look-Up

Ta ble (LUT)

Carry

Chain

previous LE

LAB-wide

Synchronous

Load

Synchronous

Load and

Clear Logic

LAB-wide

Clear

Packed Register Select

PRN/ALD

ADATA

ENA

CLRN

Programmable Register

LUT chain routing to next LE

Row, column,

and DirectLink routing

Row, column, and DirectLink routing

Local routing

labclkena1 labclkena2

Carry-Out0

Carry-Out1

LAB Carry-Out

You can configure each LE’s programmable register for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general purpose I/O (GPIO) pins, or any LE can drive the register’s clock and clear control signals. Either GPIO pins or LEs can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the

data3

inpu t of the LE. For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs.

Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive either a column or row and DirectLink routing connections while one output drives the local interconnect resources. This configuration allows the LUT to drive one output while the register drives another output. This register packing feature

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Chapter 2: MAX V Architecture 2–9

Logic Elements

improves device utilization because the device can use the register and the LUT for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This mode provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output.

LUT Chain and Register Chain

In addition to the three general routing outputs, the LEs within a LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows a LAB to use LUTs for a single combinational function and the registers for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. For more information about LUT chain and register chain connections, refer to “MultiTrack Interconnect” on page 2–14.

addnsub Signal

The LE’s dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal A + B or A – B. The LUT computes addition; subtraction is computed by adding the two’s complement of the intended subtractor. The LAB-wide signal converts to two’s complement by inverting the B bits within the LAB and setting carry-in to 1, which adds one to the LSB. The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions.

addnsub

. The

addnsub

signal automatically sets the carry-in to 1. The

signal sets the LAB to perform either

LE Operating Modes

The MAX V LE can operate in one of the following modes:

■ “Normal Mode”

■ “Dynamic Arithmetic Mode”

Each mode uses LE resources differently. In each mode, eight available inputs to the LE, the four data inputs from the LAB local interconnect, from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connection are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The

addnsub

The Quartus II software, along with parameterized functions such as the library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.

control signal is allowed in arithmetic mode.

carry-in0

and

carry-in1

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2–10 Chapter 2: MAX V Architecture

data1

4-Input

LUT

data2 data3

cin (from cout of previous LE)

data4

addnsub (LAB Wide)

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

aload

(LAB Wide)

ALD/PRE

CLRN

ENA

ADATA

sclear

(LAB Wide)

sload

(LAB Wide)

connection

LUT chain connection

Row, column, and DirectLink routing

Local routing

(1)

Logic Elements

Normal Mode

The normal mode is suitable for general logic applications and combinational functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT as shown in Figure 2–7. The Quartus II Compiler automatically selects the carry-in or the Each LE can use LUT chain connections to drive its combinational output directly to the next LE in the LAB. Asynchronous load data for the register comes from the input of the LE. LEs in normal mode support packed registers.

Figur e 2–7. LE in Normal Mode

data3

signal as one of the inputs to the LUT.

data3

Note to Figure 2–7:

(1) This signal is only allowed in normal mode if the LE is after an adder/subtractor chain.

Dynamic Arithmetic Mode

The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. A LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry-select circuitry. As shown in Figure 2–8, the LAB carry-in signal selects either the

carry-in1

sum is generated as a combinational or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums:

data1 + data2 + carry-in0

chain. The selected chain’s logic level in turn determines which parallel

data1 + data2 + carry-in1

MAX V Device Handbook December 2010 Altera Corporation

carry-in0

Chapter 2: MAX V Architecture 2–11

Logic Elements

The other two LUTs use the carry-out signals: one for a carry of 1 and the other for a carry of 0. The signal acts as the carry-select for the carry-select for the registered and unregistered versions of the LUT output.

The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other L ABs. The acts as an adder or subtractor.

Figur e 2–8. LE in Dynamic Ar ithmetic Mode

LAB Carry-In

Carry-In0 Carry-In1

addnsub

(LAB Wide)

(1)

data1

carry-out1

(LAB Wide)

connection

and

data2

signals to generate two possible

carry-in0

carry-out0

output and

carry-in1

acts as the

output. LEs in arithmetic mode can drive out

addnsub

sload

LAB-wide signal controls whether the LE

sclear

(LAB Wide)

aload

(LAB Wide)

data1 data2 data3

LUT

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

Carry-Out1Carry-Out0

Note to Figure 2–8:

(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.

Carry-Select Chain

The carry-select chain provides a very fast carry-select function between LEs in dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 0 and carry-in of 1 in parallel. The signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB.

ALD/PRE

ADATA

ENA

CLRN

carry-in0

and

Row, column, an direct link routing

Local routing

LUT chain connection

carry-in1

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2–12 Chapter 2: MAX V Architecture

LE3

LE2

LE1

LE0

A1 B1

A2 B2

A3 B3

A4 B4

Sum1

Sum2

Sum3

Sum4

LE9

LE8

LE7

LE6

A7 B7

A8 B8

A9 B9

A10 B10

Sum7

LE5

A6 B6

Sum6

LE4

A5 B5

Sum5

Sum8

Sum9

Sum10

LAB Carry-In

LAB Carry-Out

LUT

data1

LAB Carry-In

data2

Carry-In0

Carry-In1

Carry-Out0 Carry-Out1

Sum

To top of adjacent LAB

Logic Elements

The speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. Because the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delays between LAB carry-in generation (

LE5

and

LE10

) are now part of the critical path. This feature allows the MAX V architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width.

Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full adder. One

portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain,

carry-in1

, selects the carry-out to carry forward to the carry-in signal of the

carry-in0

next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects.

Figur e 2–9. Carry-Select Chain

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Chapter 2: MAX V Architecture 2–13

Logic Elements

The Quartus II software automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II software creates carry chains longer than 10 LEs by linking adjacent LABs within the same row together automatically. A carry chain can extend horizontally up to one full LAB row, but does not extend between LAB rows.

Clear and Preset Logic Control

LAB-wide signals control the logic for the register’s clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. MAX V devices support simultaneous preset/asynchronous load and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal.

In addition to the clear and preset ports, MAX V devices provide a chip-wide reset pin (

DEV_CLRn

the Quartus II software controls this pin. This chip-wide reset overrides all other control signals and uses its own dedicated routing resources without using any of the four global resources. Driving this signal low before or during power-up prevents user mode from releasing clears within the design. This allows you to control when clear is released on a device that has just been powered-up. If not set for its chip-wide reset function, the

) that resets all registers in the device. An option set before compilation in

DEV_CLRn

pin is a regular I/O pin.

By default, all registers in MAX V devices are set to power-up low. However, this power-up state can be set to high on individual registers during design entry using the Quartus II software.

LE RAM

The Quartus II memory compiler can configure the unused LEs as LE RAM.

MAX V devices support the following memory types:

■ FIFO synchronous R/W

■ FIFO asynchronous R/W

■ 1 port SRAM

■ 2 port SRAM

■ 3 port SRAM

■ shift registers

f For more information about memory, refer to the Internal Memory (RAM and ROM)

User Guide.

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2–14 Chapter 2: MAX V Architecture

Chapter 2: MAX V Architecture 2–15

MultiTrack Interconnect

Figur e 2–10. R4 Int erconnect Co nnections

Adjacent LAB can drive onto another LAB’s R4 Interconnect

R4 Interconnect

Driving Left

Neighbor

Notes to Figure 2–10:

(1) C4 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row.

LAB

Primary LAB (2)

C4 Column Interconnects (1)

LAB

Neighbor

R4 Interconnect Driving Right

The column interconnect operates similarly to the row interconnect. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs and row and column IOEs. These column resources include:

■ LUT chain interconnects within an LAB

■ Register chain interconnects within an LAB

■ C4 interconnects traversing a distance of four LABs in an up and down direction

MAX V devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinational output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from

LE 1

LE 10

in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–11 shows the LUT chain and register chain interconnects.

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2–16 Chapter 2: MAX V Architecture

LE0

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LUT Chain Routing to

Adjacent LE

Local

Interconnect

Local Interconnect Routing Among LEs in the LAB

MultiTrac k Int erconnect

Figur e 2–11. LUT Cha in and Register Cha in Interconnects

The C4 interconnects span four LABs up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–12 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by column and row IOEs. For LAB interconnection, a primary LAB or its vertical LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.

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Chapter 2: MAX V Architecture 2–17

C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows

Adjacent LAB can drive onto neighboring LAB's C4 interconnect

C4 Interconnect Driving Up

C4 Interconnect Driving Down

LAB

Row Interconnect

Local

Interconnect

MultiTrack Interconnect

Figur e 2–12. C4 Int erconnect Co nnections (Note 1)

Note to Figure 2–12:

(1) Each C4 interconnect can drive either up or down four rows.

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2–18 Chapter 2: MAX V Architecture

MultiTrac k Int erconnect

The UFM block communicates with the logic array similar to LAB-to-LAB interfaces. The UFM block connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. This block also has DirectLink interconnects for fast connections to and from a neighboring LAB. For more information about the UFM interface to the logic array, refer too “User Flash Memory

Block” on page 2–21.

Table 2–2 lists the MAX V device routing scheme.

Table 2–2. Routing Scheme for MAX V Devices

Destination

Source

LUT

Chai n

Local

(1)

DirectLink

(1)

R4 (1) C4 (1) LE

UFM

Block

Column

IOE

Row

IOE

Fast I/O

(1)

LUT Chain — — — — — — v ———— Register Chain — — — — — — v ————

Local Interconnect

DirectLink Interconnect

——— — ——vv vv—

——v — — ——— ———

R4 Interconnect — — v — vv—— ——— C4 Interconnect — — v — vv—— ——— LE vvv v vv—— vvv UFM Block — — vv vv—— ——— Column IOE — — — — — v —— ——— Row I OE — — — vvv—— ———

Note to Tab l e 2 –2 :

(1) These categories are interconnects.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–19

Global Signals

Each MAX V device has four dual-purpose dedicated clock pins (

GCLK[3..0]

, two pins on the left side and two pins on the right side) that drive the global clock network for clocking, as shown in Figure 2–13. These four pins can also be used as GPIOs if they are not used to drive the global clock network.

The four global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device including LEs, LAB local interconnect, IOEs, and the UFM block. The global clock lines can also be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, or protocol control signals such as

TRDY

and

IRDY

for the PCI I/O standard. Internal logic can drive the global clock network for internally-generated global clocks and control signals.

Figure 2–13 shows the various sources that drive the global clock network.

Figur e 2–13. Global Clock Gen eration

GCLK0 GCLK1 GCLK2 GCLK3

Logic Array(1)

Note to Figure 2–13:

(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.

Global Clock

Network

The global clock network drives to individual LAB column signals, LAB column clocks

[3..0]

, that span an entire LAB column from the top to the bottom of the device. Unused global clocks or control signals in an LAB column are turned off at the LAB column clock buffers shown in Figure 2–14. The LAB column clocks

[3..0]

are multiplexed down to two LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. For more information, refer to “LAB Control Signals” on page 2–6.

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UFM Block (2)

CFM Block

I/O Block Region

LAB Column clock[3..0]

LAB Column

clock[3..0]

4 4 4 4 4 4 4 4

Global Signals

Figur e 2–14. Global Clock Network (Note 1)

Notes to Figure 2–14:

(1) LAB column clocks in I/O block regions provide high fan-out output enable signals. (2) LAB column clocks drive to the UFM block.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–21

OSC 4

Program

Erase

Control

UFM Sector 1

UFM Sector 0

Address

PROGRAM

ERASE

OSC_ENA

RTP_BUSY

BUSY

OSC

Data Register

UFM Block

DRDin

DRDout

ARCLK

ARSHFT

ARDin

DRCLK

DRSHFT

16 16

User Flash Memory Block

MAX V devices feature a single UFM block, which can be used like a serial EEPROM for storing non-volatile information up to 8,192 bits. The UFM block connects to the logic array through the MultiTrack interconnect, allowing any LE to interface to the UFM block. Figure 2–15 shows the UFM block and interface signals. The logic array is used to create customer interface or protocol logic to interface the UFM block data outside of the device. The UFM block offers the following features:

■ Non-volatile storage up to 16-bit wide and 8,192 total bits

■ Two sectors for partitioned sector erase

■ Built-in internal oscillator that optionally drives logic array

■ Program, erase, and busy signals

■ Auto-increment addressing

■ Serial interface to logic array with programmable interface

Figur e 2–15. UFM Block and Inter face Signal s

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User Flash Memory Block

UFM Storage

Each device stores up to 8,192 bits of data in the UFM block. Table 2–3 lists the data size, sector, and address sizes for the UFM block.

Table 2–3. UFM Array Size

Device Total Bits Sectors Address Bits Data Width

5M40Z 8,192 2 (4,096 bits per sector) 9 16

5M80Z 8,192 2 (4,096 bits per sector) 9 16

5M160Z 8,192 2 (4,096 bits per sector) 9 16

5M240Z 8,192 2 (4,096 bits per sector) 9 16

5M570Z 8,192 2 (4,096 bits per sector) 9 16

5M1270Z 8,192 2 (4,096 bits per sector) 9 16

5M2210Z 8,192 2 (4,096 bits per sector) 9 16

There are 512 locations with 9-bit addressing ranging from address space is data width is up to 16 bits of data. The Quartus II software automatically creates logic to accommodate smaller read or program data widths. Erasure of the UFM involves individual sector erasing (that is, one erase of sector 0 and one erase of sector 1 is required to erase the entire UFM block). Because sector erase is required before a program or write operation, having two sectors enables a sector size of data to be left untouched while the other sector is erased and programmed with new data.

Internal Oscillator

As shown in Figure 2–15, the dedicated circuitry within the UFM block contains an oscillator. The dedicated circuitry uses this oscillator internally for its read and program operations. This oscillator's divide by 4 output can drive out of the UFM block as a logic interface clock source or for general-purpose logic clocking. The typical frequency of operation is not programmable.

The UFM internal oscillator can be instantiated using the MegaWizard™ Plug-In Manager. You can also use the MAX II/MAX V Oscillator megafunction to instantiate the UFM oscillator without using the UFM memory block.

OSC

000h

1FFh

. The sector 0

000h

0FFh

and the sector 1 address space is from

100h

1FFh

output signal frequency ranges from 3.9 to 5.3 MHz, and its exact

. The

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Chapter 2: MAX V Architecture 2–23

User Flash Memory Block

Program, Erase, and Busy Signals

The UFM block’s dedicated circuitry automatically generates the necessary internal program and erase algorithm after the asserted. The indicating the UFM internal program or erase operation has completed. The UFM block also supports JTAG as the interface for programming and reading.

f For more information about programming and erasing the UFM block, refer to the

User Flash Memory in MAX V Devices chapter.

PROGRAM

ERASE

signal must be asserted until the busy signal deasserts,

PROGRAM

ERASE

input signals have been

Auto-Increment Addressing

The UFM block supports standard read or stream read operations. The stream read is supported with an auto-increment address feature. Deasserting the while clocking the consecutive locations from the UFM array.

ARCLK

signal increments the address register value to read

ARSHIFT

signal

Serial Interface

The UFM block supports a serial interface with serial address and data signals. The internal shift registers within the UFM block for address and data are 9 bits and 16 bits wide, respectively. The Quartus II software automatically generates interface logic in LEs for a parallel address and data interface to the UFM block. Other standard protocol interfaces such as SPI are also automatically generated in LE logic by the Quartus II software.

f For more information about the UFM interface signals and the Quartus II LE-based

alternate interfaces, refer to the User Flash Memory in MAX V Devices chapter.

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User Flash Memory Block

UFM Block to Logic Array Interface

The UFM block is a small partition of the flash memory that contains the CFM block, as shown in Figure 2–1 and Figure 2–2. The UFM block for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices is located on the left side of the device adjacent to the left most LAB column. The UFM blocks for the 5M570Z, 5M1270Z, and 5M2210Z devices are located at the bottom left of the device. The UFM input and output signals interface to all types of interconnects (R4 interconnect, C4 interconnect, and DirectLink interconnect to/from adjacent LAB rows). The UFM signals can also be driven from global clocks, 5M160Z, and 5M240Z devices are shown in Figure 2–16. The interface regions for 5M570Z, 5M1270Z, and 5M2210Z devices are shown in Figure 2–17.

Figur e 2–16. 5M40Z, 5M80Z, 5M160Z, and 5M240Z UFM Block LAB Row Interface (Note 1), (2)

GCLK[3..0]

CFM Block

UFM Block

. The interface regions for the 5M40Z, 5M80Z,

LAB

PROGRAM

ERASE

OSC_ENA

RTP_BUSY

DRDin

DRCLK

DRSHFT

ARin

ARCLK

ARSHFT

DRDout

OSC

BUSY

LAB

Notes to Figure 2–16:

(1) The UFM block inputs and outputs can drive to and from all types of interconnects, not only DirectLink interconnects

from adjacent row LABs.

(2) Not applicable to the T144 package of the 5M240Z device.

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Chapter 2: MAX V Architecture 2–25

MAX V Device

1.8-V on

VCCINT Pins

1.8-V Core Voltage

Core Voltage

Figur e 2–17. 5M240Z, 5M570Z, 5M1270Z, and 5M2210Z UFM Bloc k LAB Row Interface (Note 1)

CFM Block

RTP_BUSY

BUSY

OSC

DRDout

DRDin

DRDCLK

DRDSHFT

ARDin

PROGRAM

ERASE

OSC_ENA

ARCLK

ARSHFT

UFM Block

LAB

Core Voltage

LAB

Note to Figure 2–17:

(1) Only applicable to the T144 package of the 5M240Z device.

The MAX V architecture supports a 1.8-V core voltage on the V use a 1.8-V VCC external supply to power the

VCCINT

pins.

Figur e 2–18. Core Voltage Fe ature in MAX V Devices

supply. You must

CCINT

December 2010 Altera Corporation MAX V Device Handbook

2–26 Chapter 2: MAX V Architecture

I/O Structure

IOEs support many features, including:

■ LVTTL, LVCMOS, LVDS, and RSDS I/O standards

■ 3.3-V, 32-bit, 33-MHz PCI compliance

■ JTAG boundary-scan test (BST) support

■ Programmable drive strength control

■ Weak pull-up resistors during power-up and in system programming

■ Slew-rate control

■ Tri-state buffers with individual output enable control

■ Bus-hold circuitry

■ Programmable pull-up resistors in user mode

■ Unique output enable per pin

■ Open-drain outputs

■ Schmitt trigger inputs

■ Fast I/O connection

■ Programmable input delay

MAX V device IOEs contain a bidirectional I/O buffer. Figure 2–19 shows the MAX V IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s bidirectional I/O buffers. The Quartus II software automatically attempts to place registers in the adjacent LAB with fast I/O connection to achieve the fastest possible clock-to-output and registered output enable timing. When the fast input registers option is enabled, the Quartus II software automatically routes the register to guarantee zero hold time. You can set timing assignments in the Quartus II software to achieve desired I/O timing.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–27

Data_in

Optional Schmitt Trigger Input

Drive Strength Control

Open-Drain Output

Slew Control

Fast_out

Data_out OE

Optional PCI Clamp (1)

Programmable Pull-Up (2)

CCIOVCCIO

I/O Pin

Optional Bus-Hold Circuit

DEV_OE

Programmable Input Delay

I/O Structure

Fast I/O Connection

A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O block provides faster output delays for clock-to-output and tPD propagation delays. This connection exists for data output signals, not output enable signals or input signals. Figure 2–20, Figure 2–21, and Figure 2–22 illustrate the fast I/O connection.

Figur e 2–19. IOE St ructure for MAX V Devices

Notes to Figure 2–19:

(1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices. (2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed.

December 2010 Altera Corporation MAX V Device Handbook

2–28 Chapter 2: MAX V Architecture

R4 Interconnects

C4 Interconnects

I/O Block Local

Interconnect

data_in[6..0]

data_out

[6..0]

fast_out

[6..0]

Row I/O Block Contains up to

Seven IOEs

Direct Link

Interconnect

to Adjacent LAB

Direct Link

Interconnect

from Adjacent LAB

LAB Column clock [3..0]

LAB Local Interconnect

LAB

Row

I/O Block

I/O Structure

I/O Blocks

The IOEs are located in I/O blocks around the periphery of the MAX V device. There are up to seven IOEs per row I/O block and up to four IOEs per column I/O block. Each column or row I/O block interfaces with its adjacent LAB and MultiTrack interconnect to distribute signals throughout the device. The row I/O blocks drive row, column, or DirectLink interconnects. The column I/O blocks drive column interconnects.

1 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices have a maximum of five IOEs per row

I/O block.

Figure 2–20 shows how a row I/O block connects to the logic array.

Figur e 2–20. Row I/O Block Connection to the Interconnect (Note 1)

MAX V Device Handbook December 2010 Altera Corporation

Note to Figure 2–20:

(1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and

one data_in input.

Chapter 2: MAX V Architecture 2–29

I/O Structure

Figure 2–21 shows how a column I/O block connects to the logic array.

Figur e 2–21. Colu mn I/O Block Connection to t he Interconnect (Note 1)

Column I/O

Column I/O Block

Block Contains Up To 4 IOEs

I/O Block

Local Interconnect

LAB Local Interconnect

data_out

[3..0]

R4 Interconnects

C4 Interconnects

[3..0]

LAB LAB LAB

fast_out

[3..0]

Fast I/O

Interconnect

Path

LAB Local Interconnect

LAB Column

Clock [3..0]

data_in [3..0]

LAB Local Interconnect

C4 Interconnects

Note to Figure 2–21:

(1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and

one data_in input.

I/O Standards and Banks

Table 2–4 lists the I/O standards supported by MAX V devices.

Table 2–4. MAX V I/O Standards (Part 1 of 2)

I/O Standard Type

Output Supply Voltage (V

(V)

3.3-V LVTTL/LVCMOS Single-ended 3.3

2.5-V LVTTL/LVCMOS Single-ended 2.5

1.8-V LVTTL/LVCMOS Single-ended 1.8

1.5-V LVCMOS Single-ended 1.5

1.2-V LVCMOS Single-ended 1.2

December 2010 Altera Corporation MAX V Device Handbook

CCIO

)

2–30 Chapter 2: MAX V Architecture

All I/O Banks Support

3.3-V LVTTL/LVCMOS,

2.5-V LVTTL/LVCMOS,

1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS,

1.2-V LVD S (4) RSDS (5)

LVCMOS (3),

I/O Bank 2

I/O Bank 1

I/O Structure

Table 2–4. MAX V I/O Standards (Part 2 of 2)

I/O Standard Type

Output Supply Voltage (V

(V)

CCIO

)

3.3-V PCI (1) Single-ended 3.3

LVD S (2) Differential 2.5

RSDS (3) Differential 2.5

Notes to Tab le 2 –4 :

(1) The 3.3-V PCI compliant I/O is supported in Bank 3 of the 5M1270Z and 5M2210Z devices. (2) MAX V devices only support emulated LVDS output using a three resistor network (LVDS_E_3R). (3) MAX V devices only support emulated RSDS output using a three resistor network (RSDS_E_3R).

The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices support two I/O banks, as shown in Figure 2–22. Each of these banks support all the LVTTL, LVCMOS, LVDS, and RSDS standards shown in Table 2–4. PCI compliant I/O is not supported in these devices and banks.

Figur e 2–22. I/O Banks for 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z Devices (Note 1), (2)

Notes to Figure 2–22:

(1) Figure 2–22 is a top view of the silicon die. (2) Figure 2–22 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations. (3) This I/O standard is not supported in Bank 1. (4) Emulated LVDS output using a three resistor network (LVDS_E_3R). (5) Emulated RSDS output using a three resistor network (RSDS_E_3R).

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–31

I/O Bank 2

I/O Bank 3

I/O Bank 4

I/O Bank 1

Also Supports the 3.3-V PCI I/O Standard

All I/O Banks Support

3.3-V LVTTL/LVCMOS,

2.5-V LVTTL/LVCMOS,

1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS,

1.2-V LVCMOS (3), LVD S (4), RSDS(5)

I/O Structure

The 5M1270Z and 5M2210Z devices support four I/O banks, as shown in Figure 2–23. Each of these banks support all of the LVTTL, LVCMOS, LVDS, and RSDS standards shown in Table 2–4. PCI compliant I/O is supported in Bank 3. Bank 3 supports the PCI clamping diode on inputs and PCI drive compliance on outputs. You must use Bank 3 for designs requiring PCI compliant I/O pins. The Quartus II software automatically places I/O pins in this bank if assigned with the PCI I/O standard.

Figur e 2–23. I/O Banks for 5M1270Z and 5M2210Z Devices (Note 1), (2)

Notes to Figure 2–23:

(1) Figure 2–23 is a top view of the silicon die. (2) Figure 2–23 is a graphical representation only. Refer to the pin list and t he Quartus II software for exact pin locations . (3) This I/O standard is not supported in Bank 1. (4) Emulated LVDS output using a three resistor network (LVDS_E_3R). (5) Emulated RSDS output using a three resistor network (RSDS_E_3R).

Each I/O bank has dedicated V

pins that determine the voltage standard support

CCIO

in that bank. A single device can support 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a different standard. Each I/O bank can support multiple standards with the same V V

is 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. V

CCIO

December 2010 Altera Corporation MAX V Device Handbook

both the input and output buffers in MAX V devices.

The JTAG pins for MAX V devices are dedicated pins that cannot be used as regular I/O pins. The pins

TMS, TDI, TDO

Table 2–4 on page 2–29 except for PCI and 1.2-V LVCMOS. These pins reside in Bank 1

for all MAX V devices and their I/O standard support is controlled by the V setting for Bank 1.

, and

for input and output pins. For example, when

CCIO

powers

CCIO

TCK

support all the I/O standards shown in

CCI O

2–32 Chapter 2: MAX V Architecture

I/O Structure

PCI Compliance

The MAX V 5M1270Z and 5M2210Z devices are compliant with PCI applications as well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2. These devices are also large enough to support PCI intellectual property (IP) cores.

Table 2–5 shows the MAX V device speed grades that meet the PCI timing

specifications.

Table 2–5 . 3.3-V PCI Elect rical Specifications and PCI Timing Support f or MAX V Devices

Device 33-MHz PCI

5M1270Z All Speed Grades

5M2210Z All Speed Grades

LVDS and RSDS Channels

The MAX V device supports emulated LVDS and RSDS outputs on both row and column I/O banks. You can configure the rows and columns as emulated LVDS or RSDS output buffers that use two single-ended output buffers with three external resistor networks.

Table 2–6. LVDS and RSDS Channels supported in MAX V Devices (Note 1)

Device 64 MBGA 64 EQFP 68 MBGA 100 TQFP 100 MBGA 144 TQFP 256 FBGA 324 FBGA

5M40Z 10 eTx 20 eTx — — — — — —

5M80Z 10 eTx 20 eTx 20 eTx 33 eTx — — — —

5M160Z — 20 eTx 20 eTx 33 eTx 33 eTx — — —

5M240Z — — 20 eTx 33 eTx 33 eTx 49 eTx — —

5M570Z — — — 28 eTx 28 eTx 49 eTx 75 eTx —

5M1270Z — — — — — 42 eTx 90 eTx 115 eTx

5M2210Z — — — — — — 83 eTx 115 eTx

Note to Tab l e 2 –6 :

(1) eTx = emulated LVDS output buffers (LVDS_E_3R) or emulated RSDS output buffers (RSDS_E_3R).

Schmitt Trigger

The input buffer for each MAX V device I/O pin has an optional Schmitt trigger setting for the 3.3-V and 2.5-V standards. The Schmitt trigger allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt triggers provide hysteresis on the input buffer, preventing slow-rising noisy input signals from ringing or oscillating on the input signal driven into the logic array. This provides system noise tolerance on MAX V inputs, but adds a small, nominal input delay.

The JTAG input pins (

TMS, TCK

, and

TDI

) have Schmitt trigger buffers that are always

enabled.

1 The

TCK

input is susceptible to high pulse glitches when the input signal fall time is

greater than 200 ns for all I/O standards.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–33

I/O Structure

Output Enable Signals

Each MAX V IOE output buffer supports output enable signals for tri-state control. The output enable signal can originate from the MultiTrack interconnect. The MultiTrack interconnect routes output enable signals and allows for a unique output enable for each output or bidirectional pin.

GCLK[3..0]

global signals or from the

MAX V devices also provide a chip-wide output enable pin ( output enable for every output pin in the design. An option set before compilation in the Quartus II software controls this pin. This chip-wide output enable uses its own routing resources and does not use any of the four global resources. If this option is turned on, all outputs on the chip operate normally when the pin is deasserted, all outputs are tri-stated. If this option is turned off, the pin is disabled when the device operates in user mode and is available as a user I/O pin.

Programmable Drive Strength

The output buffer for each MAX V device I/O pin has two levels of programmable drive strength control for each of the LVTTL and LVCMOS I/O standards. Programmable drive strength provides system noise reduction control for high performance I/O designs. Although a separate slew-rate control feature exists, using the lower drive strength setting provides signal slew-rate control to reduce system noise and signal overshoot without the large delay adder associated with the slew-rate control feature. Table 2–7 lists the possible settings for the I/O standards with drive strength control. The Quartus II software uses the maximum current strength as the default setting. The PCI I/O standard is always set at 20 mA with no alternate setting.

Table 2–7. Programmable Driv e Strength (Note 1)

DEV_OE

) to control the

is asserted. When

DEV_OE

I/O Standard IOH/IOL Current Strength Setting (mA)

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS 3

Note to Tab l e 2 –7 :

(1) The IOH current strength numbers shown are for a condition of a V

minimum is specified by the I/O standard. The IOL current strength numbers shown are for a condition of a V

= VOL maximum, where the VOL maximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS,

OUT

the IOH condition is V

= 1.7 V and the IOL condition is V

OUT

= VOH minimum, where the VOH

OUT

= 0.7 V.

1 The programmable drive strength feature can be used simultaneously with the

slew-rate control feature.

December 2010 Altera Corporation MAX V Device Handbook

2–34 Chapter 2: MAX V Architecture

I/O Structure

Slew-Rate Control

The output buffer for each MAX V device I/O pin has a programmable output slew-rate control that can be configured for low noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal output delay to rising and falling edges. The lower the voltage standard (for example, 1.8-V LVTTL) the larger the output delay when slow slew is enabled. Each I/O pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. If no slew-rate control is specified, the Quartus II software defaults to a fast slew rate.

1 The slew-rate control feature can be used simultaneously with the programmable

drive strength feature.

Open-Drain Output

MAX V devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane.

Programmable Ground Pins

Each unused I/O pin on MAX V devices can be used as an additional ground pin. This programmable ground feature does not require the use of the associated LEs in the device. In the Quartus II software, unused pins can be set as programmable GND on a global default basis or they can be individually assigned. Unused pins also have the option of being set as tri-stated input pins.

Bus-Hold

Each MAX V device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Because the bushold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated.

The bus-hold circuitry also pulls un-driven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output will drive no higher than V device cannot use the programmable pull-up option.

The bus-hold circuitry is only active after the device has fully initialized. The bus-hold circuit captures the value on the pin present at the moment user mode is entered.

to prevent overdriving signals. If the bus-hold feature is enabled, the

CCIO

MAX V Device Handbook December 2010 Altera Corporation

Chapter 2: MAX V Architecture 2–35

I/O Structure

Programmable Pull-Up Resistor

Each MAX V device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor holds the output to the V

level of the output pin’s bank.

CCIO

1 The programmable pull-up resistor feature should not be used at the same time as the

bus-hold feature on a given I/O pin.

1 The programmable pull-up resistor is active during power-up, ISP, and if the device is

unprogrammed.

Programmable Input Delay

The MAX V IOE includes a programmable input delay that is activated to ensure zero hold times. A path where a pin directly drives a register, with minimal routing between the two, may require the delay to ensure zero hold time. However, a path where a pin drives a register through long routing or through combinational logic may not require the delay to achieve a zero hold time. The Quartus II software uses this delay to ensure zero hold times when needed.

MultiVolt I/O Interface

The MAX V architecture supports the MultiVolt I/O interface feature, which allows MAX V devices in all packages to interface with systems of different supply voltages. The devices have one set of sets for input buffers and I/O output driver buffers (V number of I/O banks available in the devices where each set of I/O bank. The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices each have two I/O banks while the 5M1270Z and 5M2210Z devices each have four I/O banks.

Connect

VCCIO

pins to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (that is, when power supply, the output levels are compatible with 1.5-V systems). When are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with

3.3-V or 5.0-V systems. Table 2–8 summarizes MAX V MultiVolt I/O support.

Table 2–8 . Mu lti Vol t I/O Support in MAX V Devi ces (Part 1 of 2) (Note 1)

VCCIO (V)

1.2

1.5

1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

v —————v —————

— vvvv— vv————

Input Sig nal Output Signal

VCC

pins for internal operation (V

), and up to four

CCINT

), depending on the

CCI O

VCCIO

pins powers one

VCCIO

pins are connected to a 1.5-V

VCCIO

pins

1.8

2.5

December 2010 Altera Corporation MAX V Device Handbook

— vvvv— v (2) v (2) v ——— ———vv— v (3) v (3) v (3) v ——

2–36 Chapter 2: MAX V Architecture

Document Revision History

Table 2–8 . Mu lti Vol t I/O Support in MAX V Devi ces (Part 2 of 2) (Note 1)

VCCIO (V)

Input Sig nal Output Signal

1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

3.3

Notes to Tab le 2 –8 :

(1) To drive inputs higher than V

the device, enable the I/O clamp diode to prevent VI from rising above 4.0 V. Use an external diode if the I/O pin does not support the clamp

diode. (2) When V (3) When V (4) When V (5) MAX V devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on the 5M1270Z and 5M 2210Z devices.

Use an external clamp diode if the internal clamp diode is not available. (6) When V (7) When V

with internal I/O clamp diode (available onl y on 5M1270Z and 5M2210Z devices) and external resistor is required. Use an external clamp diode

if the internal clamp diode is not available.

———v (4) vv (5) v (6) v (6) v (6) v (6) vv (7)

but less than 4.0 V including the overshoot, disable the I/O clamp diode. However, to drive 5.0-V signals to

CCIO

= 1.8 V, a MAX V device can drive a 1.2-V or 1.5-V device with 1.8-V tolerant inputs.

CCIO

= 2.5 V, a MAX V device can drive a 1.2-V, 1.5-V, or 1.8-V device with 2.5-V tolerant inputs.

CCIO

= 3.3 V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected.

CCIO

= 3.3 V, a MAX V device can drive a 1.2-V, 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.

CCIO

= 3.3 V, a MAX V device can drive a device with 5.0-V TTL inputs but not 5.0-V CMOS inputs. For 5.0-V CMOS, open-drain setting

CCIO

Document Revision History

Table 2–9 lists the revision history for this chapter.

Table 2–9. Document Revision History

Date Version Changes

December 2010 1.0 Initia l release.

MAX V Device Handbook December 2010 Altera Corporation

May 2011 MV51003-1.2

MV51003-1.2

This chapter covers the electrical and switching characteristics for MAX®V devices. Electrical characteristics include operating conditions and power consumptions. This chapter also describes the timing model and specifications.

You must consider the recommended DC and switching conditions described in this chapter to maintain the highest possible performance and reliability of the MAX V devices.

This chapter contains the following sections:

■ “Operating Conditions” on page 3–1

■ “Power Consumption” on page 3–10

■ “Timing Model and Specifications” on page 3–10

Operating Conditions

3. DC and Switching Characteristics for MAX V Devices

Ta bl e 3 –1 through Table 3–15 on page 3–9 list information about absolute maximum

ratings, recommended operating conditions, DC electrical characteristics, and other specifications for MAX V devices.

Absolute Maximum Ratings

Ta bl e 3 –1 lists the absolute maximum ratings for the MAX V device family.

Table 3–1. Absolute Maximum Ratings for MAX V Devices (Note 1), (2)

Symbol Parameter Conditions Minimum Maximum Unit

CCINT

CCIO

OUT

STG

AMB

Notes to Table 3–1:

(1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in Tab le 3 –1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum

ratings for extended periods of time may have adverse affects on the device.

(3) For more information about “under bias” conditions, refer to Table 3–2.

Internal supply voltage With respect to ground –0.5 2.4 V

I/O supply voltage — –0.5 4.6 V

DC input voltage — –0.5 4.6 V

DC output current, per pin — –25 25 mA

Storage temperature No bias –65 150 °C

Ambient temperature Under bias (3) –65 135 °C

Junction temperature

TQFP and BGA packages under bias

— 135 °C

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

MAX V Device Handbook May 2011

3–2 Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Recommended Operating Conditions

Ta bl e 3 –2 lists recommended operating conditions for the MAX V device family.

Table 3–2. Recommended Operating Conditions for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

1.8-V supply voltage for internal logic and

(1)

CCINT

in-system programming (ISP)

Supply voltage for I/O buffers, 3.3-V operation

Supply voltage for I/O buffers, 2.5-V operation

CCIO

(1)

Supply voltage for I/O buffers, 1.8-V operation

Supply voltage for I/O buffers, 1.5-V operation

Supply voltage for I/O buffers, 1.2-V operation

Notes to Table 3–2:

(1) MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended

operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends that you read back the UFM contents and verify it against the intended write data).

(2) The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods

shorter than 20 ns.

(3) During transitions, the inputs may overshoot to the voltages shown below based on the input duty cycle. The DC case is equivalent to 100%

duty cycle. For more information about 5.0-V tolerance, refer to the Using MAX V Devices in Multi-Voltage Systems chapter. V

4.0 V 100% (DC)

4.1 V 90%

4.2 V 50%

4.3 V 30%

4.4 V 17%

4.5 V 10% (4) All pins, including the clock, I/O, and JTAG pins, may be driven before V (5) For the extended temperature range of 100 to 125°C, MAX V UFM programming (erase/write) is only supported using the JTAG interface. UFM

programming using the logic array interface is not guaranteed in this range.

Input voltage (2), (3), (4) –0.5 4.0 V

Output voltage — 0 V

Operating junction temperature

Max. Duty Cycle

MAX V devices 1.71 1.89 V

— 3.00 3.60 V

— 2.375 2.625 V

— 1.71 1.89 V

— 1.425 1.575 V

— 1.14 1.26 V

CCIO

Commercial range 0 85 °C

Industrial range –40 100 °C

Extended range (5) –40 125 °C

CCINT

and V

are powered.

CCIO

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–3

Operating Conditions

Programming/Erasure Specifications

Ta bl e 3 –3 lists the programming/erasure specifications for the MAX V device family.

Table 3–3. Programming/Erasure Specifications for MAX V Devices

Parameter Block Minimum Typical Maximum Unit

Erase and reprogram cycles

Note to Table 3–3:

(1) This value applies to the commercial grade devices. For the industrial grade devices, the value is 100 cycles.

UFM — — 1000 (1) Cycles

Configuration flash memory (CFM) — — 100 Cycles

DC Electrical Characteristics

Ta bl e 3 –4 lists DC electrical characteristics for the MAX V device family.

Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 1 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

CCSTANDBY

SCHMITT

CCPOWERUP

PULLUP

Input pin leakage current VI = V

Tri-stated I/O pin leakage current

supply current

CCINT

(standby) (3)

Hysteresis for Schmitt

(8)

trigger input (9)

supply current

CCINT

during power-up (10)

Value of I/O pin pull-up resistor during user mode and ISP

5M40Z, 5M80Z, 5M160Z, and 5M240Z (Commercial grade)

(4), (5)

5M240Z (Commercial grade)

(6)

5M40Z, 5M80Z, 5M160Z, and 5M240Z (Industrial grade)

(5), (7)

5M240Z (Industrial grade) (6) — 27 152 µA

5M570Z (Commercial grade)

(4)

5M570Z (Industrial grade) (7) — 27 152 µA

5M1270Z and 5M2210Z — 2 — mA

MAX V devices — — 40 mA

max to 0 V (2) –10 — 10 µA

CCIO

= V

max to 0 V (2) –10 — 10 µA

CCIO

—2590µA

—2796µA

— 25 139 µA

—2796µA

= 3.3 V — 400 — mV

CCIO

= 2.5 V — 190 — mV

CCIO

= 3.3 V (11) 5—25k

CCIO

= 2.5 V (11) 10 — 40 k

CCIO

= 1.8 V (11) 25 — 60 k

CCIO

= 1.5 V (11) 45 — 95 k

CCIO

= 1.2 V (11) 80 — 130 k

CCIO

May 2011 Altera Corporation MAX V Device Handbook

3–4 Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 2 of 2)

Symbol Parameter Conditions Minimum Typical Maximum Unit

I/O pin pull-up resistor

PULLUP

current when I/O is

— — — 300 µA

unprogrammed

Input capacitance for user I/O pin

———8pF

Input capacitance for

GCLK

dual-purpose GCLK/user

———8pF

I/O pin

Notes to Table 3–4:

(1) Typical values are for TA = 25°C, V (2) This value is specified for normal device operation. The value may vary during power-up. This applies to all V

and 1.2 V).

= ground, no load, and no toggling inputs.

(3) V

(4) Commercial temperature ranges from 0°C to 85°C with the maximum current at 85°C. (5) Not applicable to the T144 package of the 5M240Z device. (6) Only applicable to the T144 package of the 5M240Z device. (7) Industrial temperature ranges from –40°C to 100°C with the maximum current at 100°C. (8) This value applies to commercial and industrial range devices. For extended temperature range devices, the V

for V

= 3.3 V and 120 mV for V

CCIO

TCK

(9) The

input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards. (10) This is a peak current value with a maximum duration of t (11) Pin pull-up resistance values will lower if an external source drives the pin higher than V

= 1.8 V and V

CCINT

= 2.5 V.

CCIO

= 1.2, 1.5, 1.8, 2.5, or 3.3 V.

CCIO

time.

CONFIG

CCIO

settings (3.3, 2.5, 1.8, 1.5,

CCIO

typical value is 300 mV

SCHMITT

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Voltage (V)

Typical I

Output Current (mA)

3.3-V VCCIO

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

(Minimum Drive Strength)

MAX V Output Drive I

Characteristics

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3. 5

Voltage (V)

Typical I

Output Current (mA)

3.3-V VCCIO

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

(Minimum Drive Strength)

MAX V Output Drive I

Characteristics

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Voltage (V)

Typical I

Output Current (mA)

3.3-V VCCIO

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

(Maximum Drive Strength)

MAX V Output Drive I

Characteristics

1.2-V VCCIO (2)

MAX V Output Drive IOH Characteristics

(Maximum Drive Strength)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Voltage (V)

Typical I

Output Current (mA)

3.3-V VCCIO

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

1.2-V VCCIO (2)

Operating Conditions

Output Drive Characteristics

Figure 3–1 shows the typical drive strength characteristics of MAX V devices.

Figure 3–1. Output Drive Characteristics of MAX V Devices (Note 1)

Notes to Figure 3–1:

(1) The DC output current per pin is subject to the absolute maximum rating of Table 3–1 on page 3–1. (2) 1.2-V V

CCIO

I/O Standard Specifications

Table 3–5. 3.3-V LVTTL Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

Note to Table 3–5:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

May 2011 Altera Corporation MAX V Device Handbook

is only applicable to the maximum drive strength.

Ta bl e 3 –5 through Table 3–13 on page 3–8 list the I/O standard specifications for the

MAX V device family.

I/O supply voltage — 3.0 3.6 V

High-level input voltage — 1.7 4.0 V

Low-level input voltage — –0.5 0.8 V

High-level output voltage IOH = –4 mA (1) 2.4 — V

Low-level output voltage IOL = 4 mA (1) —0.45V

3–6 Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–6. 3.3-V LVCMOS Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

Note to Table 3–6:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

I/O supply voltage — 3.0 3.6 V

High-level input voltage — 1.7 4.0 V

Low-level input voltage — –0.5 0.8 V

= 3.0,

High-level output voltage

Low-level output voltage

CCIO

IOH = –0.1 mA (1)

= 3.0,

CCIO

IOL = 0.1 mA (1)

– 0.2 — V

CCIO

—0.2V

Table 3–7. 2.5-V I/O Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

I/O supply voltage — 2.375 2.625 V

High-level input voltage — 1.7 4.0 V

Low-level input voltage — –0.5 0.7 V

IOH = –0.1 mA (1) 2.1 — V

High-level output voltage

IOH = –1 mA (1) 2.0 — V

IOH = –2 mA (1) 1.7 — V

IOL = 0.1 mA (1) —0.2V

Low-level output voltage

IOL = 1 mA (1) —0.4V

IOL = 2 mA (1) —0.7V

Note to Table 3–7:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

Table 3–8. 1.8-V I/O Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

Notes to Table 3–8:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

(2) This maximum V

in Table 3–2 on page 3–2.

MAX V Device Handbook May 2011 Altera Corporation

I/O supply voltage — 1.71 1.89 V

High-level input voltage — 0.65 × V

CCIO

Low-level input voltage — –0.3 0.35 × V

High-level output voltage IOH = –2 mA (1) V

– 0.45 — V

CCIO

2.25 (2) V

CCIO

Low-level output voltage IOL = 2 mA (1) —0.45V

reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–7

Operating Conditions

Table 3–9. 1.5-V I/O Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

Notes to Table 3–9:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

(2) This maximum V

in Table 3–2 on page 3–2.

I/O supply voltage — 1.425 1.575 V

High-level input voltage — 0.65 × V

CCIO

Low-level input voltage — –0.3 0.35 × V

High-level output voltage IOH = –2 mA (1) 0.75 × V

CCIO

Low-level output voltage IOL = 2 mA (1) —0.25 × V

reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter

+ 0.3 (2) V

CCIO

—V

CCIO

Table 3–10. 1.2-V I/O Specifications for MAX V Devices

Symbol Parameter Conditions Minimum Maximum Unit

CCIO

Note to Table 3–10:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

I/O supply voltage — 1.14 1.26 V

High-level input voltage — 0.8 × V

CCIO

Low-level input voltage — –0.3 0.25 × V

High-level output voltage IOH = –2 mA (1) 0.75 × V

CCIO

Low-level output voltage IOL = 2 mA (1) —0.25×V

+0.3 V

CCIO

—V

CCIO

Table 3–11. 3.3-V PCI Specifications for MAX V Devices (Note 1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

CCIO

Note to Table 3–11:

(1) 3.3-V PCI I/O standard is only supported in Bank 3 of the 5M1270Z and 5M2210Z devices.

I/O supply voltage — 3.0 3.3 3.6 V

High-level input voltage — 0.5 × V

CCIO

Low-level input voltage — –0.5 — 0.3 × V

High-level output voltage IOH = –500 µA 0.9 × V

CCIO

Low-level output voltage IOL = 1.5 mA — — 0.1 × V

—V

+ 0.5 V

CCIO

——V

CCIO

Table 3–12. LVDS Specifications for MAX V Devices (Note 1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

CCIO

Note to Table 3–12:

(1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R).

I/O supply voltage — 2.375 2.5 2.625 V

Differential output voltage swing — 247 — 600 mV

Output offset voltage — 1.125 1.25 1.375 V

May 2011 Altera Corporation MAX V Device Handbook

3–8 Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–13. RSDS Specifications for MAX V Devices (Note 1)

Symbol Parameter Conditions Minimum Typical Maximum Unit

CCIO

Note to Table 3–13:

(1) Supports emulated RSDS output using a three-resistor network (RSDS_E_3R).

I/O supply voltage — 2.375 2.5 2.625 V

Differential output voltage swing — 247 — 600 mV

Output offset voltage — 1.125 1.25 1.375 V

Bus Hold Specifications

Ta bl e 3 –1 4 lists the bus hold specifications for the MAX V device family.

Table 3–14. Bus Hold Specifications for MAX V Devices

Level

CCIO

Parameter Conditions

Low sustaining current

High sustaining current

Low overdrive current

High overdrive current

> VIL (maximum) 10 — 20 — 30 — 50 — 70 — µA

< VIH (minimum) –10 — –20 — –30 — –50 — –70 — µA

0 V < V

< V

CCIO

Unit1.2 V 1.5 V 1.8 V 2.5 V 3.3 V

Min Max Min Max Min Max Min Max Min Max

—130—160—200—300—500µA

— –130 — –160 — –200 — –300 — –500 µA

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–9

Operating Conditions

Power-Up Timing

Ta bl e 3 –1 5 lists the power-up timing characteristics for the MAX V device family.

Table 3–15. Power-Up Timing for MAX V Devices

Symbol Parameter Device Temperature Range Min Typ Max Unit

5M40Z

5M80Z

5M160Z

5M240Z (2)

The amount of time from

CONFIG

when minimum V

reached until the device

CCINT

5M240Z (3)

enters user mode (1)

5M570Z

5M1270Z (4)

5M1270Z (5)

5M2210Z

Notes to Table 3–15:

(1) For more information about power-on reset (POR) trigger voltage, refer to the Hot Socketing and Power-On Reset in MAX V Devices chapter. (2) Not applicable to the T144 package of the 5M240Z device. (3) Only applicable to the T144 package of the 5M240Z device. (4) Not applicable to the F324 package of the 5M1270Z device. (5) Only applicable to the F324 package of the 5M1270Z device.

Commercial and industrial — — 200 µs

Extended — — 300 µs

Commercial and industrial — — 200 µs

Extended — — 300 µs

Commercial and industrial — — 200 µs

Extended — — 300 µs

Commercial and industrial — — 200 µs

Extended — — 300 µs

Commercial and industrial — — 300 µs

Extended — — 400 µs

Commercial and industrial — — 300 µs

Extended — — 400 µs

Commercial and industrial — — 300 µs

Extended — — 400 µs

Commercial and industrial — — 450 µs

Extended — — 500 µs

Commercial and industrial — — 450 µs

Extended — — 500 µs

May 2011 Altera Corporation MAX V Device Handbook

3–10 Chapter 3: DC and Switching Characteristics for MAX V Devices

I/O Pin

I/O Input Delay

INPUT

Global Input Delay

Output

Delay

LOCAL

GLOB

Logic Element

I/O Pin

FASTIO

Output Routing

Delay

User

Flash

Memory

From Adjacent LE

To Adjacent LE

Input Routing

Delay

LUT

LUT Delay

Delay

PRE

CLR

Data-In/LUT Chain

Data-Out

IODR

Output and Output Enable

Data Delay

IOE

COMB

Combinational Path Delay

Power Consumption

You can use the Altera® PowerPlay Early Power Estimator and PowerPlay Power Analyzer to estimate the device power.

f For more information about these power analysis tools, refer to the PowerPlay Early

Power Estimator for Altera CPLDs User Guide and the PowerPlay Power Analysis chapter

in volume 3 of the Quartus II Handbook.

Timing Model and Specifications

MAX V devices timing can be analyzed with the Altera Quartus®II software, a variety of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 3–2.

MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation.

Figure 3–2. Timing Model for MAX V Devices

You can derive the timing characteristics of any signal path from the timing model and parameters of a particular device. You can calculate external timing parameters, which represent pin-to-pin timing delays, as the sum of the internal parameters.

f For more information, refer to AN629: Understanding Timing in Altera CPLDs.

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–11

Timing Model and Specifications

Preliminary and Final Timing

This section describes the performance, internal, external, and UFM timing specifications. All specifications are representative of the worst-case supply voltage and junction temperature conditions.

Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 3–16 lists the status of the MAX V device timing models.

Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible.

Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under the worst-case voltage and junction temperature conditions.

Table 3–16. Timing Model Status for MAX V Devices

Device Final

5M40Z v

5M80Z v 5M160Z v 5M240Z v 5M570Z v

5M1270Z v 5M2210Z v

Performance

Ta bl e 3 –1 7 lists the MAX V device performance for some common designs. All

performance values were obtained with the Quartus II software compilation of megafunctions.

Table 3–17. Device Performance for MAX V Devices (Part 1 of 2)

Resource

Used

Design Size and

Function

16-bit counter (1) — 16 0 184.1 118.3 247.5 201.1 MHz

64-bit counter (1) — 64 0 83.2 80.5 154.8 125.8 MHz

16-to-1 multiplexer — 11 0 17.4 20.4 8.0 9.3 ns

32-to-1 multiplexer — 24 0 12.5 25.3 9.0 11.4 ns

XOR

16-bit

16-bit decoder with single address line

function — 5 0 9.0 16.1 6.6 8.2 ns

Resources Used

Mode LEs

— 5 0 9.2 16.1 6.6 8.2 ns

UFM

Blocks

Performance

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

May 2011 Altera Corporation MAX V Device Handbook

3–12 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)

Performance

Resource

Used

Design Size and

Function

Resources Used

Mode LEs

UFM

Blocks

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5 C4 C5, I5

512 × 16 None 3 1 10.0 10.0 10.0 10.0 MHz

512 × 16 SPI (2) 37 1 9.7 9.7 8.0 8.0 MHz

UFM

512 × 8

512 × 16 I

Notes to Table 3–17:

(1) This design is a binary loadable up counter. (2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used. (3) This design is configured for read-only operation. Read and write ability increases the number of LEs used. (4) This design is asynchronous. (5) The I

C megafunction is verified in hardware up to 100-kHz serial clock line rate.

Parallel

(3)

C (3) 142 1 100 (5) 100 (5) 100 (5) 100 (5) kHz

73 1 (4) (4) (4) (4) MHz

Unit

Internal Timing Parameters

Internal timing parameters are specified on a speed grade basis independent of device density. Table 3–18 through Table 3–25 on page 3–19 list the MAX V device internal timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and MultiTrack interconnects.

f For more information about each internal timing microparameters symbol, refer to

AN629: Understanding Timing in Altera CPLDs.

Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

Symbol Parameter

LUT

COMB

CLR

PRE

LE combinational look-up table (LUT) delay

Combinational path delay — 243 — 309 — 192 — 236 ps

LE register clear delay 401 — 545 — 309 — 381 — ps

LE register preset delay 401 — 545 — 309 — 381 — ps

LE register setup time before clock

LE register hold time after clock

LE register clock-to-output delay

C4 C5, I5 C4 C5, I5

Min Max Min Max Min Max Min Max

— 1,215 — 2,247 — 742 — 914 ps

260 — 321 — 271 — 333 — ps

0 —0 —0 —0 —ps

— 380 — 494 — 305 — 376 ps

5M1270Z/ 5M2210Z

Unit

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–13

Timing Model and Specifications

Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 2 of 2)

Symbol Parameter

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Min Max Min Max Min Max Min Max

CLKHL

Minimum clock high or low time

253 — 339 — 216 — 266 — ps

Table 3–19. IOE Internal Timing Microparameters for MAX V Devices

Symbol Parameter

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Min Max Min Max Min Max Min Max

FASTIO

Data output delay from adjacent LE to I/O block

I/O input pad and buffer delay

— 170 — 428 — 207 — 254 ps

— 907 — 986 — 920 — 1,132 ps

I/O input pad and buffer

(1)

GLOB

delay used as global

— 2,261 — 3,322 — 1,974 — 2,430 ps

signal pin

IOE

(2)

(3)

(4)

Notes to Table 3–19:

(1) Delay numbers for t

(2) For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–34 on page 3–24

(3) For more information about t

(4) For more information about t

Internally generated output enable delay

Input routing delay — 318 — 509 — 291 — 358 ps

Output delay buffer and pad delay

Output buffer disable delay

Output buffer enable delay

differ for each device density and speed grade. The delay numbers for t

device target.

and Table 3–35 on page 3–25.

page 3–15 and Table 3–23 on page 3–15.

page 3–14 and Table 3–21 on page 3–14.

GLOB

delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–22 on

delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–20 on

— 530 — 1,410 — 374 — 460 ps

— 1,319 — 1,543 — 1,383 — 1,702 ps

— 1,045 — 1,276 — 982 — 1,209 ps

— 1,160 — 1,353 — 1,303 — 1,604 ps

, shown in Table 3–19, are based on a 5M240Z

GLOB

May 2011 Altera Corporation MAX V Device Handbook

3–14 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Ta bl e 3 –2 0 through Ta b le 3 – 23 list the adder delays for tZX and tXZ microparameters

when using an I/O standard other than 3.3-V LVTTL with 16 mA drive strength.

Table 3–20. tZX IOE Microparameter Adders for Fast Slew Rate for MAX V Devices

Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA —0 —0 —0 —0 ps

8 mA — 72 — 74 — 101 — 125 ps

8 mA —0 —0 —0 —0 ps

4 mA — 72 — 74 — 101 — 125 ps

14 mA — 126 — 127 — 155 — 191 ps

7 mA — 196 — 197 — 545 — 671 ps

6 mA — 608 — 610 — 721 — 888 ps

3 mA — 681 — 685 — 2012 — 2477 ps

4 mA — 1162 — 1157 — 1590 — 1957 ps

2 mA — 1245 — 1244 — 3269 — 4024 ps

1.2-V LVCMOS 3 mA — 1889 — 1856 — 2860 — 3520 ps

3.3-V PCI 20 mA — 72 — 74 — –18 — –22 ps

LVDS — — 126 — 127 — 155 — 191 ps

RSDS — — 126 — 127 — 155 — 191 ps

Table 3–21. tZX IOE Microparameter Adders for Slow Slew Rate for MAX V Devices

Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA — 5,951 — 6,063 — 6,012 — 5,743 ps

8 mA — 6,534 — 6,662 — 8,785 — 8,516 ps

8 mA — 5,951 — 6,063 — 6,012 — 5,743 ps

4 mA — 6,534 — 6,662 — 8,785 — 8,516 ps

14 mA — 9,110 — 9,237 — 10,072 — 9,803 ps

7 mA — 9,830 — 9,977 — 12,945 — 12,676 ps

6 mA — 21,800 — 21,787 — 21,185 — 20,916 ps

3 mA — 23,020 — 23,037 — 24,597 — 24,328 ps

4 mA — 39,120 — 39,067 — 34,517 — 34,248 ps

2 mA — 40,670 — 40,617 — 39,717 — 39,448 ps

1.2-V LVCMOS 3 mA — 69,505 — 70,461 — 55,800 — 55,531 ps

3.3-V PCI 20 mA — 6,534 — 6,662 — 35 — 44 ps

Unit

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–15

Timing Model and Specifications

Table 3–22. tXZ IOE Microparameter Adders for Fast Slew Rate for MAX V Devices

Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA—0—0—0—0 ps

8 mA — –69 — –69 — –74 — –91 ps

8 mA—0—0—0—0 ps

4 mA — –69 — –69 — –74 — –91 ps

14 mA — –7 — –10 — –46 — –56 ps

7 mA — –66 — –69 — –82 — –101 ps

6 mA — 45 — 37 — –7 — –8 ps

3 mA — 34 — 25 — 119 — 147 ps

4 mA — 166 — 155 — 339 — 418 ps

2 mA — 190 — 179 — 464 — 571 ps

1.2-V LVCMOS 3 mA — 300 — 283 — 817 — 1,006 ps

3.3-V PCI 20 mA — –69 — –69 — 80 — 99 ps

LVDS — — –7 — –10 — –46 — –56 ps

RSDS — — –7 — –10 — –46 — –56 ps

Table 3–23. tXZ IOE Microparameter Adders for Slow Slew Rate for MAX V Devices

Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA — 171 — 174 — 73 — –132 ps

8 mA — 112 — 116 — 758 — 553 ps

8 mA — 171 — 174 — 73 — –132 ps

4 mA — 112 — 116 — 758 — 553 ps

14 mA — 213 — 213 — 32 — –173 ps

7 mA — 166 — 166 — 714 — 509 ps

6 mA — 441 — 438 — 96 — –109 ps

3 mA — 496 — 494 — 963 — 758 ps

4 mA — 765 — 755 — 238 — 33 ps

2 mA — 903 — 897 — 1,319 — 1,114 ps

1.2-V LVCMOS 3 mA — 1,159 — 1,130 — 400 — 195 ps

3.3-V PCI 20 mA — 112 — 116 — 303 — 373 ps

Unit

May 2011 Altera Corporation MAX V Device Handbook

3–16 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

1 The default slew rate setting for MAX V devices in the Quartus II design software is

“fast”.

Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2)

Symbol Parameter

ACLK

Address register clock period

Address register shift

ASU

signal setup to address register clock

Address register shift

signal hold to address register clock

Address register data in

ADS

setup to address register clock

Address register data in

ADH

hold from address register clock

DCLK

Data register clock period 100 — 100 — 100 — 100 — ns

Data register shift signal

DSS

setup to data register clock

Data register shift signal

DSH

hold from data register clock

Data register data in

DDS

setup to data register clock

DDH

Data register data in hold from data register clock

Program signal to data clock hold time

Maximum delay between

program rising edge to

busy

UFM

signal rising

edge

Minimum delay allowed

from UFM going low to program

busy

signal going low

PPMX

Maximum length of pulse during a program

signal

busy

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5 C4 C5, I5

Min Max Min Max Min Max Min Max

100 — 100 — 100 — 100 — ns

20—20—20—20—ns

60—60—60—60—ns

20—20—20—20—ns

0—0—0—0—ns

— 960 — 960 — 960 — 960 ns

20—20—20—20—ns

— 100 — 100 — 100 — 100 µs

Unit

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–17

Timing Model and Specifications

Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)

Symbol Parameter

Minimum

to address clock hold

erase

time

Maximum delay between

erase

the the UFM

rising edge to

busy

rising edge

Minimum delay allowed

EPMX

from the UFM signal going low to

erase

signal going low

Maximum length of pulse during an erase

Delay from data register

DCO

clock to data register output

Delay from

signal reaching UFM to rising clock of

OSC_ENA

leaving the UFM

Maximum read access time

Maximum delay between

OSCS

OSC_ENA

the to the

rising edge

erase/program

signal rising edge

Minimum delay allowed from the

OSCH

erase/program

going low to

OSC_ENA

signal going low

signal

busy

OSC

signal

busy

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5 C4 C5, I5

Min Max Min Max Min Max Min Max

0—0—0—0 —ns

— 960 — 960 — 960 — 960 ns

20—20—20—20—ns

— 500 — 500 — 500 — 500 ms

—5—5—5—5ns

180 — 180 — 180 — 180 — ns

—65—65—65—65ns

250 — 250 — 250 — 250 — ns

Unit

May 2011 Altera Corporation MAX V Device Handbook

3–18 Chapter 3: DC and Switching Characteristics for MAX V Devices

ADS

ASU

ACLK

ADH

DDS

DCLK

DSS

DSH

DDH

PPMX

OSCS

OSCH

ARShft

ARClk

ARDin

DRShft

DRClk

DRDin

DRDout

Program

Erase

Busy

16 Data Bits

9 Address Bits

OSC_ENA

Timing Model and Specifications

Figure 3–3 through Figure 3–5 show the read, program, and erase waveforms for

UFM block timing parameters listed in Table 3–24.

Figure 3–3. UFM Read Waveform

ARShft

ARClk

ASU

ARDin

DRShft

ADS

DRClk

DRDin

DRDout

OSC_ENA

Program

Erase

Busy

Figure 3–4. UFM Program Waveform

ACLK

9 Address Bits

ADH

DCO

16 Data Bits

DSS

DCLK

DSH

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–19

ARShft

ARClk

ARDin

DRShft

DRClk

DRDin

DRDout

Program

Erase

Busy

9 Address Bits

ASU

ACLK

ADH

ADS

EPMX

OSCS

OSCH

OSC_ENA

Timing Model and Specifications

Figure 3–5. UFM Erase Waveform

Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

Routing

C4 C5, I5 C4 C5, I5

Min Max Min Max Min Max Min Max

LOCAL

— 860 — 1,973 — 561 — 690 ps

— 655 — 1,479 — 445 — 548 ps

— 1,143 — 2,947 — 731 — 899 ps

External Timing Parameters

External timing parameters are specified by device density and speed grade. All external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different drive strengths, use the I/O standard input and output delay adders in Table 3–32 on page 3–23 through Table 3–36 on page 3–25.

f For more information about each external timing parameters symbol, refer to

AN629: Understanding Timing in Altera CPLDs.

5M1270Z/ 5M2210Z

Unit

May 2011 Altera Corporation MAX V Device Handbook

3–20 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Ta bl e 3 –2 6 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,

and 5M240Z devices.

Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices

(Note 1), (2)

Symbol Parameter Condition

Unit

Min Max Min Max

C4 C5, I5

PD1

PD2

CNT

Notes to Table 3–26:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

(2) Not applicable to the T144 package of the 5M240Z device.

Worst case pin-to-pin delay through one LUT 10 pF — 7.9 — 14.0 ns

Best case pin-to-pin delay through one LUT 10 pF — 5.8 — 8.5 ns

Global clock setup time — 2.4 — 4.6 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 6.6 2.0 8.6 ns

Global clock high time — 253 — 339 — ps

Global clock low time — 253 — 339 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 5.4 — 8.4 — ns

— — 184.1 — 118.3 MHz

Ta bl e 3 –2 7 lists the external I/O timing parameters for the T144 package of the

5M240Z device.

Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2)

C4 C5, I5

Symbol Parameter Condition

Unit

Min Max Min Max

PD1

PD2

CNT

Notes to Table 3–27:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

(2) Only applicable to the T144 package of the 5M240Z device.

Worst case pin-to-pin delay through one LUT 10 pF — 9.5 — 17.7 ns

Best case pin-to-pin delay through one LUT 10 pF — 5.7 — 8.5 ns

Global clock setup time — 2.2 — 4.4 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 6.7 2.0 8.7 ns

Global clock high time — 253 — 339 — ps

Global clock low time — 253 — 339 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 5.4 — 8.4 — ns

— — 184.1 — 118.3 MHz

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–21

Timing Model and Specifications

Ta bl e 3 –2 8 lists the external I/O timing parameters for the 5M570Z device.

Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device (Note 1)

Symbol Parameter Condition

Unit

Min Max Min Max

C4 C5, I5

PD1

PD2

CNT

Note to Table 3–28:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

Worst case pin-to-pin delay through one LUT 10 pF — 9.5 — 17.7 ns

Best case pin-to-pin delay through one LUT 10 pF — 5.7 — 8.5 ns

Global clock setup time — 2.2 — 4.4 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 6.7 2.0 8.7 ns

Global clock high time — 253 — 339 — ps

Global clock low time — 253 — 339 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 5.4 — 8.4 — ns

— — 184.1 — 118.3 MHz

Ta bl e 3 –2 9 lists the external I/O timing parameters for the 5M1270Z device.

Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)

Symbol Parameter Condition

Unit

Min Max Min Max

C4 C5, I5

PD1

PD2

CNT

Notes to Table 3–29:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

(2) Not applicable to the F324 package of the 5M1270Z device.

Worst case pin-to-pin delay through one LUT 10 pF — 8.1 — 10.0 ns

Best case pin-to-pin delay through one LUT 10 pF — 4.8 — 5.9 ns

Global clock setup time — 1.5 — 1.9 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 5.9 2.0 7.3 ns

Global clock high time — 216 — 266 — ps

Global clock low time — 216 — 266 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 4.0 — 5.0 — ns

— — 247.5 — 201.1 MHz

May 2011 Altera Corporation MAX V Device Handbook

3–22 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Ta bl e 3 –3 0 lists the external I/O timing parameters for the F324 package of the

5M1270Z device.

Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)

Symbol Parameter Condition

Unit

Min Max Min Max

C4 C5, I5

PD1

PD2

CNT

Notes to Table 3–30:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

(2) Only applicable to the F324 package of the 5M1270Z device.

Worst case pin-to-pin delay through one LUT 10 pF — 9.1 — 11.2 ns

Best case pin-to-pin delay through one LUT 10 pF — 4.8 — 5.9 ns

Global clock setup time — 1.5 — 1.9 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 6.0 2.0 7.4 ns

Global clock high time — 216 — 266 — ps

Global clock low time — 216 — 266 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 4.0 — 5.0 — ns

— — 247.5 — 201.1 MHz

Ta bl e 3 –3 1 lists the external I/O timing parameters for the 5M2210Z device.

Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1)

Symbol Parameter Condition

Unit

Min Max Min Max

C4 C5, I5

PD1

PD2

CNT

Note to Table 3–31:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

Worst case pin-to-pin delay through one LUT 10 pF — 9.1 — 11.2 ns

Best case pin-to-pin delay through one LUT 10 pF — 4.8 — 5.9 ns

Global clock setup time — 1.5 — 1.9 — ns

Global clock hold time — 0 — 0 — ns

Global clock to output delay 10 pF 2.0 6.0 2.0 7.4 ns

Global clock high time — 216 — 266 — ps

Global clock low time — 216 — 266 — ps

Minimum global clock period for 16-bit counter

Maximum global clock frequency for 16-bit counter

clock input pin maximum frequency.

— 4.0 — 5.0 — ns

— — 247.5 — 201.1 MHz

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–23

Timing Model and Specifications

External Timing I/O Delay Adders

The I/O delay timing parameters for the I/O standard input and output adders and the input delays are specified by speed grade, independent of device density.

Ta bl e 3 –3 2 through Table 3–36 on page 3–25 list the adder delays associated with I/O

pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the input delay adder to the external t

page 3–20 through Table 3–31. If you select an I/O standard other than 3.3-V LVTTL

with 16 mA drive strength and fast slew rate, add the output delay adder to the external t

and tPD listed in Table 3–26 on page 3–20 through Ta bl e 3 –3 1 .

Table 3–32. External Timing Input Delay Adders for MAX V Devices

timing parameters listed in Table 3–26 on

I/O Standard

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

Without Schmitt Trigger

With Schmitt Trigger

Without Schmitt Trigger

With Schmitt Trigger

Without Schmitt Trigger

With Schmitt Trigger

Without Schmitt Trigger

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Min Max Min Max Min Max Min Max

—0—0—0—0ps

— 387 — 442 — 480 — 591 ps

—0—0—0—0ps

— 387 — 442 — 480 — 591 ps

— 42 — 42 — 246 — 303 ps

— 429 — 483 — 787 — 968 ps

— 378 — 368 — 695 — 855 ps

— 681 — 658 — 1,334 — 1,642 ps

— 1,055 — 1,010 — 2,324 — 2,860 ps

—0—0—0—0ps

Table 3–33. External Timing Input Delay t

I/O Standard

Adders for GCLK Pins for MAX V Devices (Part 1 of 2)

GLOB

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5 C4 C5, I5

Unit

Min Max Min Max Min Max Min Max

Without Schmitt

3.3-V LVTTL

Trigger

With Schmitt Trigger

May 2011 Altera Corporation MAX V Device Handbook

—0—0—0—0ps

— 387 — 442 — 400 — 493 ps

3–24 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–33. External Timing Input Delay t

I/O Standard

Min Max Min Max Min Max Min Max

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

Without Schmitt Trigger

With Schmitt Trigger

Without Schmitt Trigger

With Schmitt Trigger

Without Schmitt Trigger

—0—0—0—0ps

— 387 — 442 — 400 — 493 ps

— 242 — 242 — 287 — 353 ps

— 429 — 483 — 550 — 677 ps

— 378 — 368 — 459 — 565 ps

— 681 — 658 — 1,111 — 1,368 ps

— 1,055 — 1,010 — 2,067 — 2,544 ps

—0—0—7—9ps

Adders for GCLK Pins for MAX V Devices (Part 2 of 2)

GLOB

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5 C4 C5, I5

Unit

Table 3–34. External Timing Output Delay and tOD Adders for Fast Slew Rate for MAX V Devices

I/O Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA—0—0—0—0ps

8 mA — 39 — 58 — 84 — 104 ps

8 mA—0—0—0—0ps

4 mA — 39 — 58 — 84 — 104 ps

14 mA — 122 — 129 — 158 — 195 ps

7 mA — 196 — 188 — 251 — 309 ps

6 mA — 624 — 624 — 738 — 909 ps

3 mA — 686 — 694 — 850 — 1,046 ps

4 mA — 1,188 — 1,184 — 1,376 — 1,694 ps

2 mA — 1,279 — 1,280 — 1,517 — 1,867 ps

1.2-V LVCMOS 3 mA — 1,911 — 1,883 — 2,206 — 2,715 ps

3.3-V PCI 20 mA — 39 — 58 — 4 — 5 ps

LVDS — — 122 — 129 — 158 — 195 ps

RSDS — — 122 — 129 — 158 — 195 ps

Unit

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–25

Timing Model and Specifications

Table 3–35. External Timing Output Delay and tOD Adders for Slow Slew Rate for MAX V Devices

I/O Standard

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Min Max Min Max Min Max Min Max

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

16 mA — 5,913 — 6,043 — 6,612 — 6,293 ps

8 mA — 6,488 — 6,645 — 7,313 — 6,994 ps

8 mA — 5,913 — 6,043 — 6,612 — 6,293 ps

4 mA — 6,488 — 6,645 — 7,313 — 6,994 ps

14 mA — 9,088 — 9,222 — 10,021 — 9,702 ps

7 mA — 9,808 — 9,962 — 10,881 — 10,562 ps

6 mA — 21,758 — 21,782 — 21,134 — 20,815 ps

3 mA — 23,028 — 23,032 — 22,399 — 22,080 ps

4 mA — 39,068 — 39,032 — 34,499 — 34,180 ps

2 mA — 40,578 — 40,542 — 36,281 — 35,962 ps

1.2-V LVCMOS 3 mA — 69,332 — 70,257 — 55,796 — 55,477 ps

3.3-V PCI 20 mA — 6,488 — 6,645 — 339 — 418 ps

Table 3–36. IOE Programmable Delays for MAX V Devices

Parameter

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

C4 C5, I5 C4 C5, I5

5M1270Z/ 5M2210Z

Unit

Input Delay from Pin to Internal Cells = 1

Input Delay from Pin to Internal Cells = 0

Min Max Min Max Min Max Min Max

— 1,858 — 2,214 — 1,592 — 1,960 ps

— 569 — 616 — 115 — 142 ps

May 2011 Altera Corporation MAX V Device Handbook

3–26 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Maximum Input and Output Clock Rates

Ta bl e 3 –3 7 and Table 3–38 list the maximum input and output clock rates for standard

I/O pins in MAX V devices.

Table 3–37. Maximum Input Clock Rate for I/Os for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

I/O Standard

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL

2.5-V LVCMOS

1.8-V LVTTL Without Schmitt Trigger 200 MHz

1.8-V LVCMOS Without Schmitt Trigger 200 MHz

1.5-V LVCMOS Without Schmitt Trigger 150 MHz

1.2-V LVCMOS Without Schmitt Trigger 120 MHz

3.3-V PCI Without Schmitt Trigger 304 MHz

Without Schmitt Trigger 304 MHz

With Schmitt Trigger 304 MHz

Without Schmitt Trigger 304 MHz

With Schmitt Trigger 304 MHz

Without Schmitt Trigger 304 MHz

With Schmitt Trigger 304 MHz

Without Schmitt Trigger 304 MHz

With Schmitt Trigger 304 MHz

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

C4, C5, I5

Unit

Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

I/O Standard

3.3-V LVTTL 304 MHz

3.3-V LVCMOS 304 MHz

2.5-V LVTTL 304 MHz

2.5-V LVCMOS 304 MHz

1.8-V LVTTL 200 MHz

1.8-V LVCMOS 200 MHz

1.5-V LVCMOS 150 MHz

1.2-V LVCMOS 120 MHz

3.3-V PCI 304 MHz

LVDS 304 MHz

RSDS 200 MHz

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

C4, C5, I5

Unit

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–27

Timing Model and Specifications

LVDS and RSDS Output Timing Specifications

Ta bl e 3 –3 9 lists the emulated LVDS output timing specifications for MAX V devices.

Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

Parameter Mode

Min Max

10 — 304 Mbps

9 — 304 Mbps

8 — 304 Mbps

7 — 304 Mbps

Data rate (1), (2)

6 — 304 Mbps

5 — 304 Mbps

4 — 304 Mbps

3 — 304 Mbps

2 — 304 Mbps

1 — 304 Mbps

—4555%

DUTY

Total jitter (3) ——0.2UI

——450ps

RISE

——450ps

FALL

Notes to Table 3–39:

(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R

I/O buffer or 2x (F

the Quartus II timing analysis of the complete design. (2) For the input clock pin to achieve 304 Mbps, use I/O standard with V (3) This specification is based on external clean clock source.

of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through

MAX

of 2.5 V and above.

CCIO

5M2210Z

Unit

C4, C5, I5

May 2011 Altera Corporation MAX V Device Handbook

3–28 Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Ta bl e 3 –4 0 lists the emulated RSDS output timing specifications for MAX V devices.

Table 3–40. Emulated RSDS Output Timing Specifications for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

Parameter Mode

Unit

C4, C5, I5

Min Max

10 — 200 Mbps

9 — 200 Mbps

8 — 200 Mbps

7 — 200 Mbps

Data rate (1)

6 — 200 Mbps

5 — 200 Mbps

4 — 200 Mbps

3 — 200 Mbps

2 — 200 Mbps

1 — 200 Mbps

—4555%

DUTY

Total jitter (2) ——0.2UI

——450ps

RISE

——450ps

FALL

Notes to Table 3–40:

(1) For the input clock pin to achieve 200 Mbps, use I/O standard with V (2) This specification is based on external clean clock source.

of 1.8 V and above.

CCIO

MAX V Device Handbook May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices 3–29

TDI

TMS

TDO

TCK

Signal

to be

Captured

Signal

to be

Driven

JCP

JCH

JCL

JPSU

JPH

JPCO

JPXZ

JPZX

JSSU

JSH

JSZX

JSCO

JSXZ

Timing Model and Specifications

JTAG Timing Specifications

Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device

family.

Figure 3–6. JTAG Timing Waveform for MAX V Devices

Ta bl e 3 –4 1 lists the JTAG timing parameters and values for the MAX V device family.

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)

Symbol Parameter Min Max Unit

TCK

JCP

JCH

JCL

JPSU

JPH

JPCO

JPZX

JPXZ

JSSU

JSH

JSCO

JSZX

(1)

clock period for V

TCK

clock period for V

TCK

clock period for V

TCK

clock period for V

TCK

clock high time 20 — ns

TCK

clock low time 20 — ns

JTAG port setup time (2) 8—ns

JTAG port hold time 10 — ns

JTAG port clock to output (2) —15ns

JTAG port high impedance to valid output (2) —15ns

JTAG port valid output to high impedance (2) —15ns

Capture register setup time 8 — ns

Capture register hold time 10 — ns

Update register clock to output — 25 ns

Update register high impedance to valid output — 25 ns

= 3.3 V 55.5 — ns

CCIO1

= 2.5 V 62.5 — ns

CCIO1

= 1.8 V 100 — ns

CCIO1

= 1.5 V 143 — ns

CCIO1

May 2011 Altera Corporation MAX V Device Handbook

3–30 Chapter 3: DC and Switching Characteristics for MAX V Devices

Document Revision History

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)

Symbol Parameter Min Max Unit

JSXZ

Notes to Table 3–41:

(1) Minimum clock period specified for 10 pF load on the (2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and

1.5-V LVCMOS operation, the t

Update register valid output to high impedance — 25 ns

TDO

minimum is 6 ns and t

JPSU

pin. Larger loads on

, t

JPZX

, and t

JPCO

TDO

degrades the maximum

are maximum values at 35 ns.

JPXZ

TCK

frequency.

Document Revision History

Ta bl e 3 –4 2 lists the revision history for this chapter.

Table 3–42. Document Revision History

Date Version Changes

May 2011 1.2 Updated Tabl e 3–2, Table 3–15, Table 3–16, and Table 3–33.

January 2011 1.1 Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.

December 2010 1.0 Initial release.

MAX V Device Handbook May 2011 Altera Corporation

Section II. System Integration in MAX V

Devices

This section provides information about system integration in MAX®V devices.

This section includes the following chapters:

■ Chapter 4, Hot Socketing and Power-On Reset in MAX V Devices

■ Chapter 5, Using MAX V Devices in Multi-Voltage Systems

■ Chapter 6, JTAG and In-System Programmability in MAX V Devices

■ Chapter 7, User Flash Memory in MAX V Devices

■ Chapter 8, JTAG Boundary-Scan Testing in MAX V Devices

May 2011 Altera Corporation MAX V Device Handbook

II–2 Section II: System Integration in MAX V Devices

MAX V Device Handbook May 2011 Altera Corporation

December 2010 MV51004-1.0

MV51004-1.0

4. Hot Socketing and Power-On Reset in MAX V Devices

This chapter provides information about hot-socketing specifications, power-on reset (POR) requirements, and their implementation in MAX

MAX V devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support. You can insert or remove a MAX V device in a system during system operation without causing undesirable effects to the running system bus. The hot-socketing feature removes some of the difficulty when using MAX V devices on PCBs that contain a mixture of 3.3-, 2.5-, 1.8-, and 1.5-V devices.

The MAX V hot-socketing feature provides the following:

■ Board or device insertion and removal

■ Support for any power-up sequence

■ Non-intrusive I/O buffers to system buses during hot insertion

This chapter contains the following sections:

■ “MAX V Hot-Socketing Specifications” on page 4–1

■ “Hot-Socketing Feature Implementation in MAX V Devices” on page 4–3

■ “Power-On Reset Circuitry” on page 4–5

MAX V Hot-Socketing Specifications

MAX V devices offer the hot-socketing feature without the need for external components or special design requirements. The advantages of hot-socketing support in MAX V devices includes the following:



V devices.

■ The device can be driven before and during power up or power down without

damaging the device.

■ I/O pins remain tri-stated during power up. The device does not drive out before

or during power up, thereby affecting other operating buses.

■ Signal pins do not drive the V

to the device I/O pins do not power the device V using internal paths. This is true if the V

CCIO

or V

power supplies. External input signals

CCINT

CCIO

and V

or V

power supplies are held at

CCIO

power supplies

CCINT

GND.

1 Altera uses GND as a reference for the hot-socketing and I/O buffers circuitry

designs. To ensure device reliability and compliance to the hot-socketing specifications, you must connect GND between boards before connecting the V and V

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRI A, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTU S and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

MAX V Device Handbook December 2010

power supplies.

CCIO

CCINT

4–2 Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices

MAX V Hot-Socketing Specifications

Devices Can Be Driven Before Power Up

You can drive signals into the I/O pins and or during power up or power down without damaging the device. To simplify the system-level design, MAX V devices support any power-up or power-down sequence (V

CCIO1

, V

CCIO2

, V

CCIO3

, V

CCIO4

, and V

CCINT

I/O Pins Remain Tri-Stated During Power Up

A device that does not support hot socketing may interrupt system operation or cause contention by driving out before or during power up. In a hot-socketing situation, the MAX V device’s output buffers are turned off during system power up. MAX V devices do not drive out until the device attains proper operating conditions and is fully configured. For more information about turn-on voltages, refer to “Power-On

Reset Circuitry” on page 4–5.

Signal Pins Do Not Drive the V

CCIO

or V

CCINT

MAX V devices do not have a current path from the I/O pins or the V

CCIO

or V

power supplies before or during power up. A MAX V device may

CCINT

be inserted into (or removed from) a system board that is powered up without damaging or interfering with system-board operation. When hot socketing, MAX V devices may have a minimal effect on the signal integrity of the backplane.

AC and DC Specifications

GCLK[3..0]

pins of MAX V devices before

Power Supplies

GCLK[3..0]

pins to

You can power up or power down the V

CCIO

and V

power supplies in any

CCINT

sequence. During hot socketing, the I/O pin capacitance is less than 8 pF. MAX V devices meet the following hot-socketing specifications:

■ DC specification: | I

■ AC specification: | I

1 MAX V devices are immune to latch-up when hot socketing. If the

| < 300 A.

IOPIN

| < 8 mA for 10 ns or less.

IOPIN

TCK

JTAG input pin is driven high during hot socketing, the current on that pin might exceed the specifications listed above.

is the current for any user I/O pin on the device. The AC specification applies

IOPIN

when the device is being powered up or powered down. This specification takes into account the pin capacitance but not the board trace and external loading capacitance. You must consider additional capacitance for trace, connector, and loading separately. The peak current duration due to power-up transients is 10 ns or less.

The DC specification applies when all V

supplies to the device are stable in the

powered-up or powered-down conditions.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices 4–3

Output Enable

CCIO

Hot Socket

Voltage

Tolerance

Control

Power On

Reset

Monitor

Weak

Pull-Up

Resistor

PAD

Input Buffer to Logic Array

Hot-Socketing Feature Implementation in MAX V Devices

The hot-socketing feature tri-states the output buffer during the power-up event (either the V

CCINT

or V circuitry generates an internal the threshold voltage during power up or power down. The the output buffer to ensure that no DC current leaks through the pin (except for weak pull-up leaking). When V relatively low even after the POR signal is released and device configuration is complete.

power supplies) or power-down event. The hot-socketing

CCIO

HOTSCKT

ramps up very slowly during power up, VCC may still be

signal when either V

or V

CCINT

HOTSCKT

is below

CCIO

signal cuts off

1 Ensure that V

is within the recommended operating range even though SRAM

CCINT

download has completed.

Figure 4–1 shows the circuitry for each I/O and clock pin.

Figure 4–1. Hot-Socketing Circuitry for MAX V Devices

The POR circuit monitors the V

CCINT

and V

voltage levels and keeps the I/O pins

CCIO

tri-stated until the device has completed its flash memory configuration of the SRAM logic. The weak pull-up resistor (R) from the I/O pin to V

is enabled during

CCIO

download to keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V before V

and/or V

CCIO

are powered,

CCINT

and it prevents the I/O pins from driving out when the device is not fully powered or operational. The hot-socketing circuitry prevents the I/O pins from internally powering V powered.

CCIO

and V

when driven by external signals before the device is

CCINT

f For more information about the 5.0-V tolerance, refer to the Using MAX V Devices in

Multi-Voltage Systems chapter.

December 2010 Altera Corporation MAX V Device Handbook

4–4 Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices

n - well

Hot-Socketing Feature Implementation in MAX V Devices

Figure 4–2 shows a transistor-level cross section of the MAX V device I/O buffers.

This design ensures that the output buffers do not drive when V before V

or if the I/O pad voltage is higher than V

CCINT

sudden voltage spikes during hot insertion. The V

PA D

. This also applies for

CCIO

leakage current charges the

is powered

CCIO

3.3-V tolerant circuit capacitance.

Figure 4–2. Transistor-Level I/O Buffers for MAX V Devices

VPAD

IOE Signal

p - well

The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge (ESD) protection. There are two cases to consider for ESD voltage strikes—positive voltage zap and negative voltage zap.

A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/ P-Substrate junction of the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turn on to discharge ESD current from I/O pin to GND. The dashed line in Figure 4–3 shows the ESD current discharge path during a positive ESD zap.

Figure 4–3. ESD Protection During Positive Voltage Zap

IOE Signal or the

Larger of VCCIO or VPAD

VCCIO

The Larger of

VCCIO or VPAD

p - substrate

Ensures 3.3-V Tolerance and Hot-Socket Protection

Source

Gate

PMOS

Drain

I/O

Drain

Gate

NMOS

Source

GND

P-Substrate

I/O

N+

GND

MAX V Device Handbook December 2010 Altera Corporation

Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices 4–5

I/O

Gate

Drain

PMOS

NMOS

Source

GND

N+

P-Substrate

Power-On Reset Circuitry

When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V is the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current path is from GND to the I/O pin, as shown in Figure 4–4.

Figure 4–4. ESD Protection During Negative Voltage Zap

Power-On Reset Circuitry

MAX V devices have POR circuits to monitor the V during power up. The POR circuit monitors these voltages, triggering download from the non-volatile configuration flash memory block to the SRAM logic, maintaining the tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this process. When the MAX V device enters user mode, the POR circuit releases the I/O pins to user functionality. The POR circuit of the MAX V device does not monitor the

voltage level after the device enters into user mode.

CCINT

Power-Up Characteristics

When power is applied to a MAX V device, the POR circuit monitors V begins SRAM download at 1.55 V for MAX V devices. From this voltage reference, the SRAM download and entry into user mode takes 200 to 450 µs maximum, depending on your device density. This period of time is specified as t timing section of the DC and Switching Characteristics for MAX V Devices chapter.

Entry into user mode is gated by whether all the V sufficient operating voltage. If V device enters user mode within the t than t banks are powered.

after V

CONFIG

, the device does not enter user mode until 2 µs after all V

CCINT

and V

CCIO

specifications. If V

CONFIG

are powered simultaneously, the

and V

CCINT

CONFIG

banks are powered with

CCIO

voltage levels

CCIO

in the power-up

is powered more

CCIO

CCINT

and

CCIO

December 2010 Altera Corporation MAX V Device Handbook

4–6 Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices

Document Revision History

For MAX V devices, the POR circuitry does not monitor the V levels after the device enters user mode. If there is a V during user mode, the functionality of the device is not guaranteed and you must power down V

up again. After V

CCIO

to 250 mV for a minimum of 10 µs before powering V

CCINT

rises from 250 mV back to approximately 1.55 V, the

CCINT

SRAM download restarts and the device begins to operate after the t passed.

Figure 4–5 shows the voltages for POR of MAX V devices during power up into user

mode and from user mode to power down or brown out.

1 All V

CCINT

and V

power supplies of all banks must be powered on before entering

CCIO

user mode.

Figure 4–5. Power-Up Characteristics for MAX V Devices (Note 1), (2)

MAX V Device

Approximate Voltage for SRAM Download Start

3.3 V

1.8 V

1.55 V

1.4 V

CCINT

must be powered down

CCINT

to 250 mV if the

dips below this level

and V

CCINT

voltage sag below 1.4 V

CCINT

CONFIG

VCCINT

voltage

CCIO

and

CCINT

time has

minimum 10

250 mV

Tri-State

CONFIG

User Mode

Operation

Notes to Figure 4–5:

(1) Time scale is relative. (2) For this figure,

banks are powered.

CCIO

all the V

banks are powered up simultaneously with the V

CCIO

1 After SRAM configuration, all registers in the device are cleared and released into

user function before the I/O tri-states are released. To release clears after the tri-states are released, use the configuration time, use the

DEV_CLRn

DEV_OE

pin option. To hold the tri-states beyond the power-up

Document Revision History

Ta bl e 4 –1 lists the revision history for this chapter.

Table 4–1. Document Revision History

Date Version Changes

December 2010 1.0 Initial release.

µs

Tri-State

profile shown. If this is not the case, t

CCINT

pin option.

CONFIG

User Mode

Operation

stretches out until all

CONFIG

MAX V Device Handbook December 2010 Altera Corporation

December 2010 MV51005-1.0

MV51005-1.0

5. Using MAX V Devices in Multi-Voltage Systems

This chapter describes how to implement Altera® devices in multi-voltage systems without damaging the device or the system.

Technological advancements in deep submicron processes have lowered the supply voltage levels of semiconductor devices, creating a design environment where devices on a system board may potentially use many different supply voltages such as 5.0, 3.3,

2.5, 1.8, 1.5, and 1.2 V, which can ultimately lead to voltage conflicts.

To accommodate interfacing with a variety of devices on system boards, MAX devices have MultiVolt I/O interfaces that allow devices in a mixed-voltage design environment to communicate directly with MAX V devices. The MultiVolt interface separates the power supply voltage (V

) from the output voltage (V

CCINT

CCIO

allowing MAX V devices to interface with other devices using a different voltage level on the same PCB. The 1.8-V input directly powers the core of the MAX V devices.

f For more information about hot socketing and power-on reset (POR), refer to the Hot

Socketing and Power-On Reset in MAX V Devices chapter.

I/O Standards

This chapter contains the following sections:

■ “I/O Standards” on page 5–1

■ “MultiVolt I/O Operation” on page 5–3

■ “5.0-V Device Compatibility” on page 5–3

■ “Recommended Operating Conditions for 5.0-V Compatibility” on page 5–7

■ “Power-Up Sequencing” on page 5–8

The I/O buffer of MAX V devices is programmable and supports a wide range of I/O voltage standards. You can program each I/O bank in a MAX V device to comply with a different I/O standard. You can configure all I/O banks with the following standards:

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

■ 1.5-V LVCMOS

■ 1.2-V LVCMOS

■ Emulated LVDS output (LVDS_E_3R)

■ Emulated RSDS output (RSDS_E_3R)

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRI A, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTU S and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

MAX V Device Handbook December 2010

5–2 Chapter 5: Using MAX V Devices in Multi-Voltage Systems

I/O Standards

The Schmitt trigger input option is supported by the 3.3-V and 2.5-V I/O standards. The I/O Bank 3 also includes the 3.3-V PCI I/O standard interface capability on the 5M1270Z and 5M2210Z devices. Figure 5–1 shows the I/O standards supported by MAX V devices.

Figure 5–1. I/O Standards Supported by MAX V Devices (Note 1), (2), (3), (4), (5)

I/O Bank 2

I/O Bank 3 also supports the 3.3-V PCI I/O Standard

All I/O Banks Support

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

I/O Bank 1

■ 1.5-V LVCMOS

■ 1.2-V LVCMOS

■ Emulated LVDS output

(LVDS_E_3R)

■ Emulated RSDS output

(RSDS_E_3R)

I/O Bank 3

Individual Power Bus

I/O Bank 4

Notes to Figure 5–1:

(1) Figure 5–1 is a top view of the silicon die. (2) Figure 5–1 is a graphical representation only. For the exact pin locations, refer to the pin list and the Quartus (3) 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices only have two I/O banks. (4) The 3.3-V PCI I/O standard is only supported in 5M1270Z and 5M2210Z devices. (5) The Schmitt trigger input option for 3.3-V and 2.5-V I/O standards is supported for all I/O pins.

II software.

MAX V Device Handbook December 2010 Altera Corporation

Chapter 5: Using MAX V Devices in Multi-Voltage Systems 5–3

MultiVolt I/O Operation

MAX V devices allow the device core and I/O blocks to be powered-up with separate supply voltages. The

VCCINT

supply power to the device I/O buffers. The for MAX V devices. All the capability must be supplied from the same voltage level (for example, 5.0, 3.3, 2.5, 1.8,

1.5, or 1.2 V). Figure 5–2 shows how to implement a multiple-voltage system for MAX V devices.

Figure 5–2. Implementing a Multi-Voltage System with a MAX V Device (Note 1), (2)

pins supply power to the device core and the

VCCINT

pins are powered-up with 1.8 V

VCCIO

pins for a given I/O bank that have MultiVolt

1.8-V

Power Supply

CCINT

VCCIO

pins

5.0-V

Device

Notes to Figure 5–2:

(1) MAX V devices can drive a 5.0-V transistor-to-transistor logic (TTL) input when V

CMOS, you must have an open-drain setting with an internal I/O clamp diode and external resistor.

(2) MAX V devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on

5M1270Z and 5M2210Z devices.

5.0-V Device Compatibility

A MAX V device can drive a 5.0-V TTL device by connecting the MAX V device to 3.3 V. This is possible because the output high voltage (V

3.3-V interface meets the minimum high-level voltage of 2.4 V of a 5.0-V TTL device.

A MAX V device may not correctly interoperate with a 5.0-V CMOS device if the output of the MAX V device is connected directly to the input of the 5.0-V CMOS device. If the MAX V device‘s V still conducts if the pin is driving high, preventing an external pull-up resistor from pulling the signal to 5.0 V. To make MAX V device outputs compatible with 5.0-V CMOS devices, configure the output pins as open-drain pins with the I/O clamp diode enabled and use an external pull-up resistor.

CCIO

MAX V Device

is greater than V

OUT

CCIO

3.3-, 2.5-, 1.8-,

1.5-, 1.2-V Device

= 3.3 V. To drive a 5.0-V

CCIO

VCCIO pins of the

, the PMOS pull-up transistor

CCIO

) of a

December 2010 Altera Corporation MAX V Device Handbook

5–4 Chapter 5: Using MAX V Devices in Multi-Voltage Systems

5.0-V Device Compatibility

Figure 5–3 shows MAX V device compatibility with 5.0-V CMOS devices.

Figure 5–3. MAX V Device Compatibility with 5.0-V CMOS Devices

CCIO

5.0 V ± 0.5 V

EXT

3.3 V

CCIO

(1)

CCIO

Model as R

INT

Open Drain

VSS

OUT

5.0-V CMOS

Device

Note to Figure 5–3:

(1) This diode is only active after power-up. MAX V devices require an external diode if driven by 5.0 V before

power-up.

The open-drain pin never drives high, only low or tri-state. When the open-drain pin is active, it drives low. When the open-drain pin is inactive, the pin is tri-stated and the trace pulls up to 5.0 V by the external resistor. The purpose of enabling the I/O clamp diode is to protect the MAX V device’s I/O pins. The 3.3-V V

supplied to

CCIO

the I/O clamp diodes causes the voltage at point A to clamp at 4.0 V, which meets the MAX V device’s reliability limits when the trace voltage exceeds 4.0 V. The device operates successfully because a 5.0-V input is within its input specification.

1 The I/O clamp diode is only supported in the 5M1270Z and 5M2210Z devices’ I/O

Bank 3. You must have an external protection diode for the other I/O banks in the 5M1270Z and 5M2210Z devices and all the I/O pins in the 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices.

The pull-up resistor value must be small enough for a sufficient signal rise time, but large enough so that it does not violate the I

(output low) specification of the

MAX V devices.

The maximum MAX V device I

depends on the programmable drive strength of the

I/O output. Table 5–1 lists the programmable drive strength settings that are available for the 3.3-V LVTTL/LVCMOS I/O standard for MAX V devices. The Quartus II software uses the maximum current strength as the default setting. The PCI I/O standard is always set to 20 mA with no alternate setting.

Table 5–1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength (Part 1 of 2)

I/O Standard I

3.3-V LVTTL

MAX V Device Handbook December 2010 Altera Corporation

Current Strength Setting (mA)

OH/IOL

Chapter 5: Using MAX V Devices in Multi-Voltage Systems 5–5

EXT

5.5 V 0.45 V– 16 mA

---------------------------------------- - 315.6 ==

5.0-V Device Compatibility

Table 5–1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength (Part 2 of 2)

I/O Standard I

3.3-V LVCMOS

To compute the required value of R

, first calculate the model of the open-drain

EXT

transistors on the MAX V device. You can model this output resistor (R dividing V

by IOL (R

= VOL/IOL). Table 5–2 lists the maximum VOL for the 3.3-V

EXT

Current Strength Setting (mA)

OH/IOL

EXT

) by

LVTTL/LVCMOS I/O standard for MAX V devices.

f For more information about I/O standard specifications, refer to the DC and Switching

Characteristics for MAX V Devices chapter.

Table 5–2. 3.3-V LVTTL/LVCMOS Maximum VOL

I/O Standard Voltage (V)

3.3-V LVTTL 0.45

3.3-V LVCMOS 0.20

Select R compute the required pull-up resistor value of R R

EXT

with a 16 mA drive strength, given that the maximum power supply (V you can calculate the value of R

so that the MAX V device’s IOL specification is not violated. You can

EXT

by using the equation:

EXT

=(VCC/IOL)–R

. For example, if an I/O pin is configured as a 3.3-V LVTTL

INT

as follows:

EXT

) is 5.5 V,

Equation 5–1.

This resistor value computation assumes worst-case conditions. You can adjust the R

value according to the device configuration drive strength. Additionally, if your

EXT

system does not see a wide variation in voltage-supply levels, you can adjust these calculations accordingly.

Because MAX V devices are 3.3-V, 32-bit, 66-MHz PCI compliant, the input circuitry accepts a maximum high-level input voltage (V with a 5.0-V device, you must connect a resistor (R

) of 4.0 V. To drive a MAX V device

) between the MAX V device and

the 5.0-V device.

December 2010 Altera Corporation MAX V Device Handbook

5–6 Chapter 5: Using MAX V Devices in Multi-Voltage Systems

5.0 V ± 0.5 V

Model as R

5.0-V Device

MAX V Device

CCIO

3.3 V

PCI Clamp

(1)

5.0-V Device Compatibility

Figure 5–4 shows how to drive a MAX V PCI-compliant device with a 5.0-V device.

Figure 5–4. Driving a MAX V PCI-Compliant Device with a 5.0-V Device

Note to Figure 5–4:

(1) This diode is only active after power-up. MAX V devices require an external diode if driven by 5.0 V before

power-up.

If V

for the MAX V devices is 3.3 V and you enabled the I/O clamp diode, the

CCIO

voltage at point B in Figure 5–4 is 4.0 V, which meets the MAX V devices reliability limits when the trace voltage exceeds 4.0 V. To limit large current draw from the 5.0-V device, R does not violate the high-level output current (I

must be small enough for a fast signal rise time and large enough so that it

) specifications of the devices

driving the trace.

To compute the required value of R transistors on the 5.0-V device. You can model this output resistor (R

5.0-V device supply voltage (V

, first calculate the model of the pull-up

) by IOH: R1=VCC/IOH.

) by dividing the

Figure 5–5 shows an example of typical output drive characteristics of a 5.0 V device.

Figure 5–5. Output Drive Characteristics of a 5.0-V Device

150

135

120

Typical Output Current (mA)

VO Output Voltage (V)

CCINT

CCIO

= 5.0 V

321

MAX V Device Handbook December 2010 Altera Corporation

Chapter 5: Using MAX V Devices in Multi-Voltage Systems 5–7

5.5 V 3.7 V–8 mA 30 – 8mA

------------------------------------------------------------------------------------ 194 ==

Recommended Operating Conditions for 5.0-V Compatibility

As shown in Figure 5–5, R1= 5.0 V/135 mA.

The values usually shown in the data sheets reflect typical operating conditions. Subtract 20% from the data sheet value for guard band. When you subtract the 20% from the previous example, the R

Select R

so that the MAX V device’s IOH specification is not violated. For example, if

the above device has a maximum I V

IN=VCCIO

) is 5.5 V, calculate value of R2 as follows:

+ 0.7 V = 3.7 V. Given that the maximum supply load of a 5.0-V device

value is 30.

of 8 mA, given the I/O clamp diode,

Equation 5–2.

This analysis assumes worst-case conditions. If your system does not see a wide variation in voltage-supply levels, you can adjust these calculations accordingly.

Because 5.0-V device tolerance in MAX V devices requires the use of the I/O clamp, and this clamp is activated only after power-up, 5.0-V signals may not be driven into the device until it is configured. The I/O clamp diode is only supported in the 5M1270Z and 5M2210Z devices’ I/O Bank 3. You must have an external protection diode for the other I/O banks for the 5M1270Z and 5M2210Z devices and all the I/O pins in the 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices.

Recommended Operating Conditions for 5.0-V Compatibility

As mentioned earlier, a 5.0-V tolerance can be supported with the I/O clamp diode enabled with external series/pull-up resistance. To guarantee long term reliability of the device’s I/O buffer, there are restrictions on the signal duty cycle that drive the MAX V I/O, which is based on the maximum clamp current. Ta bl e 5 – 3 lists the maximum signal duty cycle for the 3.3-V V capability.

Table 5–3. Maximum Signal Duty Cycle

(V) (1) ICH (mA) (2) Max Duty Cycle (%)

4.0 5.00 100

4.1 11.67 90

4.2 18.33 50

4.3 25.00 30

4.4 31.67 17

4.5 38.33 10

4.6 45.00 5

Notes to Table 5–3:

(1) VIN is the voltage at the package pin. (2) The I

is calculated with a 3.3-V V

. A higher V

CCIO

given a PCI clamp current-handling

CCIO

value will have a lower ICH value with the same VIN.

CCIO

December 2010 Altera Corporation MAX V Device Handbook

5–8 Chapter 5: Using MAX V Devices in Multi-Voltage Systems

Power-Up Sequencing

1 For signals with a duty cycle greater than 30% on MAX V input pins, Altera

recommends using a V signals with a duty cycle less than 30%, the V

voltage of 3.0 V to guarantee long-term I/O reliability. For

CCIO

voltage can be 3.3 V.

CCIO

Power-Up Sequencing

MAX V devices are designed to operate in multi-voltage environments where it may be difficult to control power sequencing. Therefore, MAX V devices are designed to tolerate any possible power-up sequence. Either V

CCINT

or V power to the device and 3.3-, 2.5-, 1.8-, 1.5-, or 1.2-V input signals can drive the devices without special precautions before V can operate with a V

When V

CCIO

and V

device, a delay between V

voltage level that is higher than the V

CCIO

are supplied from different power sources to a MAX V

CCINT

CCIO

and V

may occur. Normal operation does not

CCINT

or V

CCIO

occur until both power supplies are in their recommended operating range. When

is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. If

CCINT

connected to V

CCIO

and V Thus, any transition on JTAG state, leading to incorrect operation when V

is not powered-up, the JTAG signals are left floating.

CCIO

TCK

can cause the state machine to transition to an unknown

is finally powered-up. To

CCIO

disable the JTAG state during the power-up sequence, pull

TCK

inadvertent rising edge does not occur on

can initially supply

CCIO

is applied. MAX V devices

level.

CCINT

TMS

and

TCK

are

TCK

low to ensure that an

Document Revision History

Ta bl e 5 –4 lists the revision history for this chapter.

Table 5–4. Document Revision History

Date Version Changes

December 2010 1.0 Initial release.

MAX V Device Handbook December 2010 Altera Corporation

May 2011 MV51006-1.1

MV51006-1.1

6. JTAG and In-System Programmability in MAX V Devices

This chapter describes the IEEE Standard 1149.1 JTAG BST circuitry that is supported

in MAX

V devices and how you can enable concurrent in-system programming of multiple devices in a minimum time with the IEEE Standard 1532 in-system programmability (ISP). This chapter also describes the programming sequence, types

of programming with the Quartus

II software or external hardware, and design

security.

This chapter includes the following sections:

■ “IEEE Std. 1149.1 Boundary-Scan Support” on page 6–1

■ “In-System Programmability” on page 6–5

IEEE Std. 1149.1 Boundary-Scan Support

All MAX V devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-2001 specification. You can only perform JTAG boundary-scan testing after you have fully powered the V amount of configuration time (t MAX V devices can use the JTAG port with either the Quartus II software or hardware with Programmer Object File (.pof), Jam Language (STAPL) Format File (.jam), or Jam Byte Code Files (.jbc).

JTAG pins support 1.5-V, 1.8-V, 2.5-V, and 3.3-V I/O standards. The V where it is located determines the supported voltage level and standard. The dedicated JTAG pins reside in Bank 1 of all MAX V devices.

) have passed. For in-system programming,

CONFIG

CCINT

and all V

™

Standard Test and Programming

banks and a certain

CCIO

of the bank

Ta bl e 6 –1 lists the JTAG instructions supported in MAX V devices.

Table 6–1. JTAG Instructions for MAX V Devices (Part 1 of 2)

JTAG Instruction Instruction Code Description

Allows you to capture and examine a snapshot of signals at the

SAMPLE/PRELOAD 00 0000 0101

device pins if the device is operating in normal mode. Permits an initial data pattern to be an output at the device pins.

Allows you to test the external circuitry and board-level

EXTEST

(1)

00 0000 1111

interconnects by forcing a test pattern at the output pins and capturing test results at the input pins.

BYPASS 11 1111 1111

Places the 1-bit bypass register between the which allows the boundary-scan test (BST) data to pass synchronously through target devices to adjacent devices during

TDI

and

TDO

pins,

normal device operation.

Selects the 32-bit

TDO

USERCODE 00 0000 0111

and

TDO

pins, allowing you to shift the

pin serially. If you do not specify the

software, the 32-bit

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

USERCODE

in the Quartus II

TDI

MAX V Device Handbook May 2011

6–2 Chapter 6: JTAG and In-System Programmability in MAX V Devices

IEEE Std. 1149.1 Boundary-Scan Support

Table 6–1. JTAG Instructions for MAX V Devices (Part 2 of 2)

JTAG Instruction Instruction Code Description

IDCODE 00 0000 0110

Selects the pins, allowing you to shift the

IDCODE

TDI

and

TDO

serially.

HIGHZ

(1)

00 0000 1011

Places the 1-bit bypass register between the which allows the BST data to pass synchronously through target devices to adjacent devices if the device is operating in normal mode

TDI

and

TDO

pins,

and tri-stating all the I/O pins.

Places the 1-bit bypass register between the

TDI

and

TDO

pins,

which allows the BST data to pass synchronously through target

CLAMP

(1)

00 0000 1010

devices to adjacent devices during normal device operation and holding I/O pins to a state defined by the data in the boundary-scan register.

USER0 00 0000 1100

Allows you to define the scan chain between the the MAX V logic array. Use this instruction for custom logic and

TDI

and

TDO

pins in

JTAG interfaces.

USER1 00 0000 1110

Allows you to define the scan chain between the the MAX V logic array. Use this instruction for custom logic and

TDI

and

TDO

pins in

JTAG interfaces.

For the instruction codes of the IEEE 1532

IEEE 1532 instructions

instructions, refer to the

IEEE 1532 BSDL Files

IEEE 1532 in-system concurrent (ISC) instructions used if

programming a MAX V device through the JTAG port. page of the Altera website.

Note to Table 6–1:

(1)

HIGHZ, CLAMP

, and

EXTEST

instructions do not disable weak pull-up resistors or bus hold features.

w You must not issue unsupported JTAG instructions to the MAX V device because this

may put the device into an unknown state, requiring a power cycle to recover device operation.

MAX V Device Handbook May 2011 Altera Corporation

Chapter 6: JTAG and In-System Programmability in MAX V Devices 6–3

IEEE Std. 1149.1 Boundary-Scan Support

The MAX V device instruction register length is 10 bits and the

USERCODE

length is 32 bits. Table 6–2 and Ta bl e 6 –3 list the boundary-scan register length and

IDCODE

device

information for MAX V devices.

Table 6–2. Boundary-Scan Register Length for MAX V Devices

Device Boundary-Scan Register Length

5M40Z 240

5M80Z 240

5M160Z 240

5M240Z (1) 240

5M240Z (2) 480

5M570Z 480

5M1270Z (3) 636

5M1270Z (4) 816

5M2210Z 816

Notes to Table 6–2:

(1) Not applicable to T144 package of the 5M240Z device. (2) Only applicable to T144 package of the 5M240Z device. (3) Not applicable to F324 package of the 5M1270Z device. (4) Only applicable to F324 package of the 5M1270Z device.

Table 6–3. 32-Bit IDCODE for MAX V Devices

Device

Version

(4 Bits)

5M40Z

5M80Z

5M160Z

5M240Z (3)

5M240Z (4)

5M570Z

5M1270Z (5)

5M1270Z (6)

5M2210Z

Notes to Table 6–2:

(1) The MSB is on the left.

IDCODE

(2) The LSB for

(3) Not applicable to T144 package of the 5M240Z device. (4) Only applicable to T144 package of the 5M240Z device. (5) Not applicable to F324 package of the 5M1270Z device. (6) Only applicable to F324 package of the 5M1270Z device.

is always 1.

0000 0010 0000 1010 0101 000 0110 1110

0000 0010 0000 1010 0110 000 0110 1110

0000 0010 0000 1010 0011 000 0110 1110

0000 0010 0000 1010 0100 000 0110 1110

Binary IDCODE (32 Bits) (1)

Part Number

Manufacturer

Identity (11 Bits)

LSB

HEX IDCODE

(1 Bit) (2)

1 0x020A50DD

1 0x020A60DD

1 0x020A30DD

1 0x020A40DD

f For JTAG direct current (DC) characteristics, refer to the DC and Switching

Characteristics for MAX V Devices chapter.

May 2011 Altera Corporation MAX V Device Handbook

6–4 Chapter 6: JTAG and In-System Programmability in MAX V Devices

IEEE Std. 1149.1 Boundary-Scan Support

f For more information about JTAG BST, refer to the JTAG Boundary-Scan Testing for

MAX V Devices chapter.

JTAG Block

If you issue either the controller, the MAX V JTAG block feature allows you to access the JTAG TAP controller and state signals. The boundary-scan chain ( (BSCs) of MAX V devices. Each JTAG chain into the logic array.

USER0

USER1

instruction to the JTAG test access port (TAP)

USER0

and

USER1

instructions bring the JTAG

TDI

) through the user logic instead of the boundary-scan cells

USER

instruction allows for one unique user-defined

Parallel Flash Loader

MAX V devices have the ability to interface JTAG to non-JTAG devices and are suitable to use with the general flash memory devices that require programming during the in-circuit test. You can use the flash memory devices for FPGA configuration or be part of the system memory. In many cases, you can use the MAX V device as a bridge device that controls configuration between FPGA and flash devices. Unlike ISP-capable CPLDs, bulk flash devices do not have JTAG TAP pins or connections. For small flash devices, it is common to use the serial JTAG scan chain of a connected device to program the non-JTAG flash device but this is slow, inefficient, and impractical for large parallel flash devices. Using the MAX V JTAG block as a parallel flash loader (PFL) with the Quartus II software to program and verify flash contents provides a fast and cost-effective means of in-circuit programming during testing.

f For more information about PFL, refer to the Parallel Flash Loader Megafunction User

Guide.

MAX V Device Handbook May 2011 Altera Corporation

Chapter 6: JTAG and In-System Programmability in MAX V Devices 6–5

PFL

Configuration

Logic

Flash

Memory Device

MAX V Device

DQ[7..0]

RY/BY

A[20..0]

OE WE

DQ[7..0]

RY/BY

A[20..0] OE WE CE

TDI TMS TCK

TDI_U

TDO_U

TMS_U

TCK_U

SHIFT_U

CLKDR_U

UPDATE_U

RUNIDLE_U

USER1_U

TDO

Altera FPGA

CONF_DONE nSTATUS nCE

DCLK

DATA0 nCONFIG

(1), (2)

In-System Programmability

Figure 6–1 shows how you can use the MAX V JTAG block as a PFL.

Figure 6–1. PFL for MAX V Devices

Notes to Figure 6–1:

(1) This block is implemented in logic elements (LEs). (2) This function is supported in the Quartus II software.

In-System Programmability

You can program MAX V devices in-system through the industry standard 4-pin IEEE Std. 1149.1 interface. ISP offers quick and efficient iterations during design development and debugging cycles. The flash-based SRAM configuration elements configure the logic, circuitry, and interconnects in the MAX V architecture. Each time the device is powered up, the configuration data is loaded into the SRAM elements. The process of loading the SRAM data is called configuration. The on-chip configuration flash memory (CFM) block stores the configuration data of the SRAM element. The CFM block stores the configuration pattern of your design in a reprogrammable flash array. During ISP, the MAX V JTAG and ISP circuitry programs the design pattern into the non-volatile flash array of the CFM block.

The MAX V JTAG and ISP controller internally generate the high programming voltages required to program the CFM cells, allowing in-system programming with any of the recommended operating external voltage supplies. You can configure the ISP anytime after you have fully powered V

CCINT

and all V has completed the configuration power-up time. By default, during in-system programming, the I/O pins are tri-stated and weakly pulled-up to V eliminate board conflicts. The in-system programming clamp and real-time ISP feature allow user control of the I/O state or behavior during ISP.

For more information, refer to “In-System Programming Clamp” on page 6–7 and

“Real-Time ISP” on page 6–8.

These devices also offer an programming is interrupted. This prevents all I/O pins from driving until the bit is programmed.

May 2011 Altera Corporation MAX V Device Handbook

ISP_DONE

bit that provides safe operation if in-system

ISP_DONE

bit, which is the last bit programmed,

banks, and the device

CCIO

banks to

CCIO

6–6 Chapter 6: JTAG and In-System Programmability in MAX V Devices

In-System Programmability

IEEE 1532 Support

The JTAG circuitry and ISP instruction set in MAX V devices are compliant to the IEEE-1532-2002 programming specification. This provides industry-standard hardware and software for in-system programming among multiple vendor programmable logic devices (PLDs) in a JTAG chain.

f For more information about MAX V 1532 Boundary-Scan Description Language

(.bsd) files, refer to the IEEE 1532 BSDL Files page of the Altera website.

Jam Standard Test and Programming Language

You can use the Jam STAPL to program MAX V devices with in-circuit testers, PCs, or embedded processors. The Jam byte code is also supported for MAX V devices. These software programming protocols provide a compact embedded solution for programming MAX V devices.

f For more information, refer to AN 425: Using Command-Line Jam STAPL Solution for

Device Programming.

Programming Sequence

During in-system programming, 1532 instructions, addresses, and data are shifted into the MAX V device through the output pin and compared with the expected data.

To program a pattern into the device, follow these steps:

1. Enter ISP—The enter ISP stage ensures that the I/O pins transition smoothly from

user mode to ISP mode.

2. Check ID—The silicon ID is checked before any Program or Verify process. The

time required to read this silicon ID is relatively small compared to the overall programming time.

3. Sector Erase—Erasing the device in-system involves shifting in the instruction to

erase the device and applying an erase pulse or pulses. The erase pulse is automatically generated internally by waiting in the run, test, or idle state for the specified erase pulse time of 500 ms for the CFM block and 500 ms for each sector of the user flash memory (UFM) block.

4. Program—Programming the device in-system involves shifting in the address,

data, and program instruction and generating the program pulse to program the flash cells. The program pulse is automatically generated internally by waiting in the run/test/idle state for the specified program pulse time of 75 µs. This process is repeated for each address in the CFM and UFM blocks.

TDI

input pin. Data is shifted out through the

TDO

5. Verify—Verifying a MAX V device in-system involves shifting in addresses,

applying the verify instruction to generate the read pulse, and shifting out the data for comparison. This process is repeated for each CFM and UFM address.

6. Exit ISP—An exit ISP stage ensures that the I/O pins transition smoothly from ISP

mode to user mode.

MAX V Device Handbook May 2011 Altera Corporation

ALTERA MAX V Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Section I. MAX V Device Core

1. MAX V Device Family Overview

Feature Summary

Integrated Software Platform

Device Pin-Outs

Ordering Information

Document Revision History

2. MAX V Architecture

Functional Description

Logic Array Blocks

LAB Interconnects

LAB Control Signals

Logic Elements

LUT Chain and Register Chain

addnsub Signal

LE Operating Modes

Normal Mode

Dynamic Arithmetic Mode

Carry-Select Chain

Clear and Preset Logic Control

LE RAM

Global Signals

User Flash Memory Block

UFM Storage

Internal Oscillator

Program, Erase, and Busy Signals

Auto-Increment Addressing

Serial Interface

UFM Block to Logic Array Interface

Core Voltage

I/O Structure

Fast I/O Connection

I/O Blocks

I/O Standards and Banks

PCI Compliance

LVDS and RSDS Channels

Schmitt Trigger

Output Enable Signals

Programmable Drive Strength

Slew-Rate Control

Open-Drain Output

Programmable Ground Pins

Bus-Hold

Programmable Pull-Up Resistor

Programmable Input Delay

MultiVolt I/O Interface

Document Revision History

Operating Conditions

3. DC and Switching Characteristics for MAX V Devices

Absolute Maximum Ratings

Recommended Operating Conditions

Programming/Erasure Specifications

DC Electrical Characteristics

Output Drive Characteristics

I/O Standard Specifications

Bus Hold Specifications

Power-Up Timing

Power Consumption

Timing Model and Specifications

Preliminary and Final Timing

Performance

Internal Timing Parameters

External Timing Parameters

External Timing I/O Delay Adders

Maximum Input and Output Clock Rates

LVDS and RSDS Output Timing Specifications

JTAG Timing Specifications

Document Revision History

4. Hot Socketing and Power-On Reset in MAX V Devices

MAX V Hot-Socketing Specifications

Devices Can Be Driven Before Power Up

I/O Pins Remain Tri-Stated During Power Up

AC and DC Specifications

Hot-Socketing Feature Implementation in MAX V Devices

Power-On Reset Circuitry