ALTERA MAX 7000A Service Manual

MAX 7000A

Includes

®

August 2000, ver. 3.1 Data Sheet

High-performance 3.3-V EEPROM-based programmable logic

Features...

■

devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)

3.3-V in-system programmability (ISP) through the built-in

■

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with

■

IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language

■

(STAPL) JESD-71
Enhanced ISP features

■

– Enhanced ISP algorithm for faster programming (excluding

EPM7128A and EPM7256A devices)

– ISP_Done bit to ensure complete programming (excluding

EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices

■

High-density PLDs ranging from 600 to 10,000 usable gates

■

4.5-ns pin-to-pin logic delays with counter frequencies of up to

■

227.3 MHz

MAX 7000AE

Programmable Logic

Device Family

f

For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the

Data Sheet

or the

MAX 7000B Programmable Logic Device Family Data Sheet

MAX 7000 Programmable Logic Device Family

Table 1. MAX 7000A Device Features

Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE

Usable gates 600 1,250 2,500 5,000 10,000

Macrocells 32 64 128 256 512

Logic array blocks 2 4 8 16 32

Maximum user I/O
pins

(ns) 4.5 4.5 5.0 5.5 7.5

t

PD

tSU (ns) 2.9 2.8 3.3 3.9 5.6

t

(ns) 2.5 2.5 2.5 2.5 3.0

FSU

t

(ns) 3.0 3.1 3.4 3.5 4.7

CO1

f

(MHz) 227.3 222.2 192.3 172.4 116.3

CNT

Altera Corporation 1

A-DS-M7000A-03.1

36 68 100 164 212

.

MAX 7000A Programmable Logic Device Family Data Sheet

MultiVoltTM I/O interface enables device core to run at 3.3 V, while

...and More
Features

■

I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack

■

(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space­saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
Supports hot-socketing in MAX 7000AE devices

■

Programmable interconnect array (PIA) continuous routing structure

■

for fast, predictable performance
Peripheral component interconnect (PCI)-compatible

■

Bus-friendly architecture, including programmable slew-rate control

■

Open-drain output option

■

Programmable macrocell registers with individual clear, preset,

■

clock, and clock enable controls
Programmable power-up states for macrocell registers in

■

MAX 7000AE devices
Programmable power-saving mode for 50% or greater power

■

reduction in each macrocell
Configurable expander product-term distribution, allowing up to

■

32 product terms per macrocell
Programmable security bit for protection of proprietary designs

■

6 to 10 pin- or logic-driven output enable signals

■

Two global clock signals with optional inversion

■

Enhanced interconnect resources for improved routability

■

Fast input setup times provided by a dedicated path from I/O pin to

■

macrocell registers
Programmable output slew-rate control

■

Programmable ground pins

■

Software design support and automatic place-and-route provided by

■

Altera’s development systems for Windows-based PCs and Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations
Additional design entry and simulation support provided by EDIF

■

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit

■

(MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel
port download cable, ByteBlasterMVTM parallel port download cable,
and MasterBlasterTM serial/universal serial bus (USB)
communications cable, as well as programming hardware from
third-party manufacturers and any JamTM STAPL File (
Byte-Code File (

.jbc

), or Serial Vector Format File- (
in-circuit tester (the ByteBlaster cable is obsolete and is replaced by
the ByteBlasterMV cable)

.jam

.svf

) capable

), Jam

2 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

General Description

MAX 7000A (including MAX 7000AE) devices are high-density, high­performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM­based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,

-6, -7 and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG)

PCI Local Bus Specification, Revision 2.2

. See Table 2.

Table 2. MAX 7000A Speed Grades

Device Speed Grade

-4 -5 -6 -7 -10 -12

EPM7032AE

EPM7064AE

EPM7128A

EPM7128AE

EPM7256A

EPM7256AE

EPM7512AE

Note:

(1) Altera does not recommend using EPM7128A or EPM7256A devices for new

designs. Use EPM7128AE or EPM7256AE devices for these designs instead.

vvv
vvv

(1)

vvvv

vvv

(1)

vvv

vvv

vvv

The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See Table 3 and Table 4.

Altera Corporation 3

MAX 7000A Programmable Logic Device Family Data Sheet

Table 3. MAX 7000A Maximum User I/O Pins

Device 44-Pin

PLCC

44-Pin

TQFP

49-Pin

Ultra

FineLine

BGA

EPM7032AE 36 36

EPM7064AE 36 36 41 68 68

EPM7128A

EPM7128AE 68 84 84

EPM7256A

EPM7256AE 84 84

EPM7512AE

(5)

(5)

Table 4. MAX 7000A Maximum User I/O Pins

Device 144-Pin

TQFP

169-Pin

Ultra

FineLine

BGA

(3)

EPM7032AE

EPM7064AE

EPM7128A

EPM7128AE 100 100 100

EPM7256A

EPM7256AE 120 164 164

EPM7512AE 120 176 212 212

Notes to tables:

(1) Contact Altera for up-to-date information on available device package options.
(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or

boundary-scan testing, four I/O pins become JTAG pins.

(3) All Ultra FineLine BGA packages are footprint-compatible via the SameFrame

feature. Therefore, designers can design a board to support a variety of devices,
providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-

Outs” on page 14 for more details.

(4) All FineLine BGA packages are footprint-compatible via the SameFrame

Therefore, designers can design a board to support a variety of devices, providing
a flexible migration path across densities and pin counts. Device migration is fully
supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for
more details.

(5) Altera does not recommend using EPM7128A or EPM7256A devices for new

designs. Use EPM7128AE or EPM7256AE devices for these designs instead.

(5)

(5)

100 100

120 164 164

(3)

208-Pin

PQFP

Notes (1), (2)

84-Pin

PLCC

68 84 84

100-Pin

TQFP

84

Notes (1), (2)

256-Pin

BGA

FineLine

TM

100-Pin

FineLine

BGA

(4)

256-Pin

BGA

(4)

TM

feature.

4 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.

MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable­register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high­speed parallel expander product terms, providing up to 32 product terms
per macrocell.

MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are

2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.

AND

/fixed-OR array and a configurable

MAX 7000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX-workstation-based EDA tools. The
software runs on Windows-based PCs, as well as Sun SPARCstation,
HP 9000 Series 700/800, and IBM RISC System/6000 workstations.

f

Altera Corporation 5

For more information on development tools, see the

Programmable Logic Development System & Software Data Sheet
Quartus Programmable Logic Development System & Software Data Sheet

MAX+PLUS II

and the

.

MAX 7000A Programmable Logic Device Family Data Sheet

Functional Description

The MAX 7000A architecture includes the following elements:

■

Logic array blocks (LABs)

■

Macrocells

■

Expander product terms (shareable and parallel)

■

Programmable interconnect array

■

I/O control blocks

The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.

Figure 1. MAX 7000A Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 or 10 Output Enables

2 to 16 I/O

I/O

Control

Block

2 to 16

2 to 16

(1)

LAB A

Macrocells

1 to 16

36 36

16

6 or 10 Output Enables

LAB B

2 to 16

Macrocells

17 to 32

16

2 to 16

Control

I/O

Block

(1)

2 to 16 I/O

PIA

2 to 16

16

2 to 16

Macrocells

49 to 64

LAB D

2 to 16

2 to 16

I/O

Control

Block

6

2 to 16 I/O

6

2 to 16 I/O

I/O

Control

Block

6

LAB C

2 to 16

2 to 16

6

Macrocells

33 to 48

2 to 16

36 36

16

2 to 16

Note:

(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.

EPM7512AE devices have 10 output enables.

6 Altera Corporation

Logic Array Blocks

The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in

Figure 1. Multiple LABs are linked together via the PIA, a global bus that

is fed by all dedicated input pins, I/O pins, and macrocells.

Each LAB is fed by the following signals:

■

■

■

Macrocells

MAX 7000A macrocells can be individually configured for either
sequential or combinatorial logic operation. The macrocells consist of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows a MAX 7000A macrocell.

Figure 2. MAX 7000A Macrocell

LAB Local Array

MAX 7000A Programmable Logic Device Family Data Sheet

36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times

Global

Global

Clear

Product-

Te r m
Select
Matrix

Parallel Logic
Expanders
(from other
macrocells)

Clear

Select

Clocks

2

VCC

Clock/
Enable
Select

Fast Input
Select

D/T Q

ENA

PRN

CLRN

Programmable
Register

Register

Bypass

From
I/O pin

To I/O
Control
Block

To PIA

36 Signals

from PIA

16 Expander

Product Terms

Shared Logic
Expanders

Altera Corporation 7

MAX 7000A Programmable Logic Device Family Data Sheet

Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.

Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:

■ Shareable expanders, which are inverted product terms that are fed

back into the logic array

■ Parallel expanders, which are product terms borrowed from adjacent

macrocells

The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.

Each programmable register can be clocked in three different modes:

■ Global clock signal. This mode achieves the fastest clock-to-output

performance.

■ Global clock signal enabled by an active-high clock enable. A clock

enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.

■ Array clock implemented with a product term. In this mode, the

flipflop can be clocked by signals from buried macrocells or I/O pins.

Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the global clock pins, GCLK1 or GCLK2.

8 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry.

All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.

Expander Product Terms

Although most logic functions can be implemented with the five product
terms available in each macrocell, more complex logic functions require
additional product terms. Another macrocell can be used to supply the
required logic resources. However, the MAX 7000A architecture also
offers both shareable and parallel expander product terms that provide
additional product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest possible
logic resources to obtain the fastest possible speed.

Shareable Expanders

Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (t
shareable expanders are used. Figure 3 shows how shareable expanders
can feed multiple macrocells.

Altera Corporation 9

) is incurred when

SEXP

MAX 7000A Programmable Logic Device Family Data Sheet

Figure 3. MAX 7000A Shareable Expanders

Shareable expanders can be shared by any or all macrocells in an LAB.

Macrocell
Product-Term
Logic

Product-Term Select Matrix

Macrocell
Product-Term
Logic

36 Signals
from PIA

16 Shared
Expanders

Parallel Expanders

Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.

The compiler can allocate up to three sets of up to five parallel expanders
to the macrocells that require additional product terms. Each set of five
parallel expanders incurs a small, incremental timing delay (t
example, if a macrocell requires 14 product terms, the Compiler uses the
five dedicated product terms within the macrocell and allocates two sets
of parallel expanders; the first set includes five product terms, and the
second set includes four product terms, increasing the total delay by 2 ×

t

.

PEXP

PEXP

). For

10 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower­numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowest-numbered macrocell
can only lend parallel expanders, and the highest-numbered macrocell
can only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.

Figure 4. MAX 7000A Parallel Expanders

Unused product terms in a macrocell can be allocated to a neighboring macrocell.

From

Previous

Macrocell

Preset

36 Signals

from PIA

16 Shared
Expanders

Product-

Te r m
Select
Matrix

Product-

Te r m
Select
Matrix

Macrocell
Product­Term Logic

Clock
Clear

Preset

Macrocell
Product­Term Logic

Clock
Clear

To Next

Macrocell

Altera Corporation 11

MAX 7000A Programmable Logic Device Family Data Sheet

Programmable Interconnect Array

Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input AND gate,
which selects a PIA signal to drive into the LAB.

Figure 5. MAX 7000A PIA Routing

To LAB

PIA Signals

While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000A PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.

I/O Control Blocks

The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.

12 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Figure 6. I/O Control Block of MAX 7000A Devices

6 or 10 Global
Output Enable Signals

(1)

PIA

OE Select Multiplexer

To Other I/O Pins

From
Macrocell

Fast Input to
Macrocell
Register

To PIA

VCC

GND

Open-Drain Output
Slew-Rate Control

Note:

(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable

signals. EPM7512AE devices have 10 output enable signals.

When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.

The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.

Altera Corporation 13

MAX 7000A Programmable Logic Device Family Data Sheet

SameFrame Pin-Outs

MAX 7000A devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball­count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EPM7128AE device in a 100-pin
FineLine BGA package to an EPM7512AE device in a 256-pin
FineLine BGA package.

The Altera design software provides support to design PCBs with
SameFrame pin-out devices. Devices can be defined for present and
future use. The software generates pin-outs describing how to lay out a
board to take advantage of this migration (see Figure 7).

Figure 7. SameFrame Pin-Out Example

Printed Circuit Board

Designed for 256-Pin FineLine BGA Package

100-Pin

FineLine

BGA

100-Pin FineLine BGA Package

(Reduced I/O Count or

Logic Requirements)

14 Altera Corporation

256-Pin FineLine BGA Package

(Increased I/O Count or

Logic Requirements)

256-Pin

FineLine

BGA

MAX 7000A Programmable Logic Device Family Data Sheet

In-System
Programma­bility (ISP)

MAX 7000A devices can be programmed in-system via an industry­standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient
iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 kΩ.

MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only.

ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 7000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the Altera BitBlaster serial download cable, ByteBlaster parallel port
download cable, ByteBlasterMV parallel port download cable, and
MasterBlaster serial/USB communications cable. Programming the
devices after they are placed on the board eliminates lead damage on
high-pin-count packages (e.g., QFP packages) due to device handling.
MAX 7000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.

In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. A constant algorithm uses a pre­defined (non-adaptive) programming sequence that does not take
advantage of adaptive algorithm programming time improvements.
Some in-circuit testers cannot program using an adaptive algorithm.
Therefore, a constant algorithm must be used. MAX 7000AE devices can
be programmed with either an adaptive or constant (non-adaptive)
algorithm. EPM7128A and EPM7256A device can only be programmed
with an adaptive algorithm; users programming these two devices on
platforms that cannot use an adaptive algorithm should use EPM7128AE
and EPM7256AE devices.

The Jam programming and test language can be used to program
MAX 7000A devices with in-circuit testers, PCs, or embedded processors.

Altera Corporation 15

MAX 7000A Programmable Logic Device Family Data Sheet

f

Programming with External Hardware

f

f

IEEE Std.

1149.1 (JTAG)
Boundary-Scan
Support

For more information on using the Jam STAPL language, see Application

Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor)

and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded

Processor).

MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checks to ensure adequate
electrical contact between the adapter and the device.

For more information, see the Altera Programming Hardware Data Sheet.

The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.

Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices.

For more information, see Programming Hardware Manufacturers.

MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.

1149.1. Table 5 describes the JTAG instructions supported by MAX 7000A
devices. The pin-out tables starting on page 52 of this data sheet show the
location of the JTAG control pins for each device. If the JTAG interface is
not required, the JTAG pins are available as user I/O pins.

16 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Table 5. MAX 7000A JTAG Instructions

JTAG Instruction Description

SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins

EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing test results at the input pins

BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST

data to pass synchronously through a selected device to adjacent devices during normal
device operation

IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the

IDCODE to be serially shifted out of TDO

USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,

allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is
available for MAX 7000AE devices only

UESCODE These instructions select the user electronic signature (UESCODE) and allow the

UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.

ISP Instructions These instructions are used when programming MAX 7000A devices via the JTAG ports

with the BitBlaster, ByteBlaster, ByteBlasterMV, or MasterBlaster download cable, or
using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test
equipment.

Altera Corporation 17

MAX 7000A Programmable Logic Device Family Data Sheet

The instruction register length of MAX 7000A devices is 10 bits. The user
electronic signature (UES) register length in MAX 7000A devices is 16 bits.
The MAX 7000AE USERCODE register length is 32 bits. Tables 6 and 7
show the boundary-scan register length and device IDCODE information
for MAX 7000A devices.

Table 6. MAX 7000A Boundary-Scan Register Length

Device Boundary-Scan Register Length

EPM7032AE 96

EPM7064AE 192

EPM7128A 288

EPM7128AE 288

EPM7256A 480

EPM7256AE 480

EPM7512AE 624

Table 7. 32-Bit MAX 7000A Device IDCODE Note (1)

Device IDCODE (32 Bits)

f

Version

(4 Bits)

EPM7032AE 0001 0111 0000 0011 0010 00001101110 1

EPM7064AE 0001 0111 0000 0110 0100 00001101110 1

EPM7128A 0000 0111 0001 0010 1000 00001101110 1

EPM7128AE 0001 0111 0001 0010 1000 00001101110 1

EPM7256A 0000 0111 0010 0101 0110 00001101110 1

EPM7256AE 0001 0111 0010 0101 0110 00001101110 1

EPM7512AE 0001 0111 0101 0001 0010 00001101110 1

Notes:

(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.

Part Number (16 Bits) Manufacturer’s

Identity (11 Bits)

1 (1 Bit)

(2)

See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera

Devices) for more information on JTAG BST.

18 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Figure 8 shows timing information for the JTAG signals.

Figure 8. MAX 7000A JTAG Waveforms

TMS

TDI

t

JCP

t

JCL

t

JPSU

t

JPH

TCK

t

JCH

t

JPXZ

TDO

Signal

to Be

Captured

Signal

to Be

Driven

t

JPZX

t

JSZX

t

JSSU

t

JPCO

t

JSH

t

JSCO

t

JSXZ

Table 8 shows the JTAG timing parameters and values for MAX 7000A

devices.

Table 8. JTAG Timing Parameters & Values for MAX 7000A Devices Note (1)

Symbol Parameter Min Max Unit

t

JCP

t

JCH

t

JCL

t

JPSU

t

JPH

t

JPCO

t

JPZX

t

JPXZ

t

JSSU

t

JSH

t

JSCO

t

JSZX

t

JSXZ

TCK clock period 100 ns

TCK clock high time 50 ns

TCK clock low time 50 ns

JTAG port setup time 20 ns

JTAG port hold time 45 ns

JTAG port clock to output 25 ns

JTAG port high impedance to valid output 25 ns

JTAG port valid output to high impedance 25 ns

Capture register setup time 20 ns

Capture register hold time 45 ns

Update register clock to output 25 ns

Update register high impedance to valid output 25 ns

Update register valid output to high impedance 25 ns

Note:

(1) Timing parameters shown in this table apply for all specified VCCIO levels.

Altera Corporation 19

MAX 7000A Programmable Logic Device Family Data Sheet

Programmable Speed/Power Control

Output
Configuration

MAX 7000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.

The designer can program each individual macrocell in a MAX 7000A
device for either high-speed (i.e., with the Turbo Bit option turned on) or
low-power operation (i.e., with the Turbo Bit option turned off). As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (t

tEN, t

MAX 7000A device outputs can be programmed to meet a variety of
system-level requirements.

SEXP

, t

ACL

, and t

parameters.

CPPW

) for the t

LPA

LAD

, t

LAC

, tIC,

MultiVolt I/O Interface

The MAX 7000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000A devices to connect to systems with
differing supply voltages. MAX 7000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).

The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with

2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with V
incur a slightly greater timing delay of t
always be driven by 2.5-V, 3.3-V, or 5.0-V signals.

Table 9 describes the MAX 7000A MultiVolt I/O support.

Table 9. MAX 7000A MultiVolt I/O Support

V

Voltage Input Signal (V) Output Signal (V)

CCIO

2.5 3.3 5.0 2.5 3.3 5.0

2.5

3.3

20 Altera Corporation

vvvv
vvv vv

OD2

levels lower than 3.0 V

CCIO

instead of t

. Inputs can

OD1

MAX 7000A Programmable Logic Device Family Data Sheet

Open-Drain Output Option

MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-OR plane.

Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V

3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the trace will be pulled up to 5.0 V by the resistor. The open­drain pin will only drive low or tri-state; it will never drive high. The rise
time is dependent on the value of the pull-up resistor and load
impedance. The IOL current specification should be considered when
selecting a pull-up resistor.

IH

of

Programmable Ground Pins

Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.

Slew-Rate Control

The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the
rising and falling edges of the output signal.

Altera Corporation 21

MAX 7000A Programmable Logic Device Family Data Sheet

CC

Power Sequencing & Hot-Socketing

Design Security

Generic Testing

Because MAX 7000A devices can be used in a mixed-voltage
environment, they have been designed specifically to tolerate any possible
power-up sequence. The V

CCIO

and V

power planes can be powered

CCINT

in any order.

Signals can be driven into MAX 7000AE devices before and during power­up without damaging the device. Additionally, MAX 7000AE devices do
not drive out during power-up. Once operating conditions are reached,
MAX 7000AE devices operate as specified by the user.

All MAX 7000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.

MAX 7000A devices are fully tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 9. Test patterns can be used and then
erased during early stages of the production flow.

Figure 9. MAX 7000A AC Test Conditions

Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground­current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V
outputs. Numbers without brackets are for

3.3-V outputs.

703 Ω

[521 Ω]

Device
Output

586 Ω

[481 Ω]

Device input
rise and fall
times < 2 ns

C1 (includes JIG
capacitance)

V

To Test
System

22 Altera Corporation

MAX 7000A Programmable Logic Device Family Data Sheet

Operating Conditions

Tables 10 through 13 provide information on absolute maximum ratings,

recommended operating conditions, operating conditions, and
capacitance for MAX 7000A devices.

Table 10. MAX 7000A Device Absolute Maximum Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

V

V

I

OUT

T

T

T

CC

I

STG

A

J

Supply voltage With respect to ground (2) –0.5 4.6 V

DC input voltage –2.0 5.75 V

DC output current, per pin –25 25 mA

Storage temperature No bias –65 150 ° C

Ambient temperature Under bias –65 135 ° C

Junction temperature BGA, FineLine BGA, PQFP, and

135 ° C

TQFP packages, under bias

Table 11. MAX 7000A Device Recommended Operating Conditions

Symbol Parameter Conditions Min Max Unit

V

CCINT

V

CCIO

V

CCISP

V

I

V

O

T

A

T

J

t

R

t

F

Supply voltage for internal logic

(3) 3.0 3.6 V

and input buffers

Supply voltage for output

(3) 3.0 3.6 V

drivers, 3.3-V operation

Supply voltage for output

(3) 2.3 2.7 V

drivers, 2.5-V operation

Supply voltage during in-

3.0 3.6 V

system programming

Input voltage (4) –0.5 5.75 V

Output voltage 0 V

CCIO

Ambient temperature For commercial use 0 70 ° C

For industrial use –40 85 ° C

Junction temperature For commercial use 0 90 ° C

For industrial use –40 105 ° C

Input rise time 40 ns

Input fall time 40 ns

V

Altera Corporation 23

MAX 7000A Programmable Logic Device Family Data Sheet

Table 12. MAX 7000A Device DC Operating Conditions Note (5)

Symbol Parameter Conditions Min Max Unit

V

V

V

V

I

I

I

OZ

R

High-level input voltage 1.7 5.75 V

IH

Low-level input voltage –0.5 0.8 V

IL

3.3-V high-level TTL output

OH

IOH = –8 mA DC, V

= 3.00 V (6) 2.4 V

CCIO

voltage

3.3-V high-level CMOS output
voltage

2.5-V high-level output voltage I

I

= –0.1 mA DC, V

OH

(6)

= –100 µA DC, V

OH

CCIO

CCIO

= 3.00 V

= 2.30 V

V

– 0.2 V

CCIO

2.1 V

(6)

I

3.3-V low-level TTL output

OL

= –1 mA DC, V

OH

= –2 mA DC, V

I

OH

IOL = 8 mA DC, V

= 2.30 V (6) 2.0 V

CCIO

= 2.30 V (6) 1.7 V

CCIO

= 3.00 V (7) 0.45 V

CCIO

voltage

3.3-V low-level CMOS output

I

= 0.1 mA DC, V

OL

= 3.00 V (7) 0.2 V

CCIO

voltage

2.5-V low-level output voltage I

= 100 µA DC, V

OL

I

= 1 mA DC, V

OL

= 2 mA DC, V

I

OL

Input leakage current VI = V

Tri-state output off-state

VO = V

or ground –10 10 µA

CCINT

or ground –10 10 µA

CCINT

= 2.30 V (7) 0.2 V

CCIO

= 2.30 V (7) 0.4 V

CCIO

= 2.30 V (7) 0.7 V

CCIO

current

Value of I/O pin pull-up resistor

ISP

during in-system programming
or during power-up

V

= 3.0 to 3.6 V (8) 20 50 kΩ

CCIO

= 2.3 to 2.7 V (8) 30 80 kΩ

V

CCIO

= 2.3 to 3.6 V (9) 20 74 kΩ

V

CCIO

Table 13. MAX 7000A Device Capacitance Note (10)

Symbol Parameter Conditions Min Max Unit

C

C

24 Altera Corporation

Input pin capacitance VIN = 0 V, f = 1.0 MHz 8 pF

IN

I/O pin capacitance V

I/O

= 0 V, f = 1.0 MHz 8 pF

OUT

MAX 7000A Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents

less than 100 mA and periods shorter than 20 ns.
(3) For EPM7128A and EPM7256A devices only, V
(4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before

and V

V

CCINT

(5) These values are specified under the recommended operating conditions shown in Table 11 on page 23.

are powered.

CCIO

(6) The parameter is measured with 50% of the outputs each sourcing the specified current. The I

to high-level TTL or CMOS output current.
(7) The parameter is measured with 50% of the outputs each sinking the specified current. The I

low-level TTL or CMOS output current.

must rise monotonically.

CC

parameter refers

OH

parameter refers to

OL

(8) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.
(9) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed

devices during power-up.
(10) Capacitance is measured at 25 °C and is sample-tested only. The

OE1 pin (high-voltage pin during programming)

has a maximum capacitance of 20 pF.

Altera Corporation 25