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June 2003, ver. 6.6 Data Sheet

MAX 7000

Programmable Logic

Device Family

Features...

■ High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX

■ 5.0-V in-system programmability (ISP) through the built-in

architectu re

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

■ Built-in JTAG boundary-scan test (BST) circuitry in MAX

7000S

devices with 128 or more macrocells

■ Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see Tables 1 and 2)

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

■ PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devi ces, see th e MAX 7000 A Programma ble Logi c Device F amily

Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.

Table 1. MAX 7000 Device Features

Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E

Usable gates

Macrocells 32 64 96 128 160 192 256 Logic array

blocks Maximum

user I/O pins

(ns) 6 6 7. 5 7.5 10 12 12

(ns)5566777

(ns)2.5 2.533333

FSU

(ns)444.54.5566

CO1

(MHz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9

CNT

600 1,250 1,800 2,500 3,200 3,750 5,000

2468101216

36 68 76 100 104 124 164

Altera Corporation 1

DS-MAX7000-6.6

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 2.MAX 7000S Device Features

Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

Usable gates 600 1,250 2,500 3,200 3,75 0 5,000 Macrocells 32 64 128 160 192 256 Logic array

blocks Maximum

user I/O pins

(ns)55667.57.5

(ns) 2.9 2.9 3.4 3.4 4.1 3.9

(ns) 2.5 2.5 2.5 2.5 3 3

FSU

(ns) 3.2 3.2 4 3.9 4.7 4.7

CO1

(MHz) 175.4 175.4 147.1 149.3 125.0 128.2

CNT

2 4 8 10 12 16

36 68 100 104 124 164

...and More Features

■ Open-drain output option in MAX 7000S devices

■ Programmable macrocell flipflops with individual clear, preset,

clock, and clock enable controls

■ Programmable power-saving mode for a reduction o f over 50% in

each macrocell

■ Configurable expander product-term distribution, allowing up to

32 product terms per macrocell

■ 44 to 208 pins avail ab le in pla stic J-lead chip carr ier (P L CC), ceramic

pin-grid array (PGA), plastic quad flat pack (PQFP), p ower q uad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

■ Programmable security bit for protection of proprietary designs

■ 3.3-V or 5.0-V operation

– MultiVolt

I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (M ultiVolt I/O ope ration is not avai lable in 44-pin packages)

– Pin compatible with low-voltage MAX 7000A and MAX 7000B

devices

■ Enhanc ed features availabl e in MAX 7000E and MAX 7000 S devices

– Six pin- or logic-driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Fast input setup times provided by a dedicated path from I/O

pin to macrocell registers

– Programmable output slew-rate control

■ Software design s upport and au tomatic plac e-and-ro ute provided by

Altera’s development system for Windows-based PC s and Sun SPARCstation, and HP 9000 Series 700/800 workstations

2 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

■ Additional design entry and simula tion support pr ovide d by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfa ces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBes t

■ Programming support

– Altera’s Master Programming Unit (MPU) and programming

hardware from third-party manufacturers program all MAX 7000 devices

–The BitBlaster

parallel port download cable, and MasterBlaster

serial download cable, By te Bl as terMVTM

serial/universal serial bus (USB) download cable program MAX 7000S devices

General Description

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,

-7, and -10 spe ed g ra d es as we l l as MAX7000 and MAX7000E devices in

-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.

Table 3.MAX 7000 Speed Grades

Device Speed Grade

-5 -6 -7 -10P -10 -12P -12 -15 -15T -20

EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S

vvv v

vv v vvv

vvvvv

vvvv vvvvvv

vv v v

vv vv v

vv v v

vv v

vvv v

Altera Corporation 3

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E de v ices —have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmabl e slew rate.

In-system programmable MAX 7000 devices—called MAX7000S devices—include the EPM7032S, EPM7064S, EPM7 12 8S , EPM7160S, EPM7192S, and EPM7256S devices. MAX7000S devices have the enhanced fea tures of MAX7000E device s as well as JTAG BST circu itry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.

Table 4. MAX 7000 Device Features

Feature EPM7032

EPM7064 EPM7096

ISP via JTAG interface JTAG BST circuitry Open-drain output option Fast input registers Six global output enables Two global clocks Slew-rate control MultiVolt interface (2) Programmable register Parallel expanders Shared expanders Power - saving mode Security bit PCI-compliant devices avai lable

Notes:

(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. (2) The Mul t iVolt I/O interf ace is not available in 44-pin packages.

vvv vvv vvv vvv vvv vvv vvv

All

MAX 7000E

Devices

All

MAX 7000S

Devices

v v(1)

v vv vv vv vv

4 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide ran ge of packages, includin g P LCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5.

Table 5. MAX 7000 Maximum User I/O Pins Note (1)

Device 44-

PLCC

EPM7032 36 36 36 EPM7032S 36 36 EPM7064 36 36 52 68 68 EPM7064S 36 36 68 68 EPM7096 52 64 76 EPM7128E 68 84 100 EPM7128S 68 84 84 (2) 100 EPM7160E 64 84 104 EPM7160S 64 84 (2) 104 EPM7192E 124 124 EPM7192S 124 EPM7256E 132 (2) 164 164 EPM7256S 164 (2) 164

Notes:

(1) When the JTAG inte r face in M AX 7000S devices is used for ei the r b ound ary-scan testing or for ISP, four I/O pins

become JTAG pins.

(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see

the Operating Requirements for Altera Devices Data Sheet.

44Pin

PQFP

44Pin

TQFP

68Pin

PLCC

84Pin

PLCC

100-

PQFP

100-

TQFP

160-

PQFP

160-

PGA

192-

PGA

208-

PQFP

208-

RQFP

MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independe nt c omb inat orial and se qu ent ial l ogic func tions . T he devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programme d and erased up to 100 times.

Altera Corporation 5

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

MAX 700 0 d evices contain fro m 32 to 256 ma cr ocells th at are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with ind epend ently prog rammabl e clock, clock enable, cle ar, an d preset functions. To bu ild compl ex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expand er product terms to provide up to 32 product terms per macrocell.

The MAX 7000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switc hing. The output drive rs of all M AX 7000 devices (except 44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing MAX 7000 devices to be used in mixed-voltage systems.

The MAX 7000 family is supported byAltera deve lopment systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Descr ipt i on Langu age (AHDL)— and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX-workst ation-based EDA tools . The software run s on Windows-based PC s, as well a s Sun SPARCsta tion, and H P 9000 Series 700/800 workstations.

Functional Description

6 Altera Corporation

For more information on development tools, see the MAX+PLUS II

Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet.

The MAX 7000 architecture includes the following elements:

■ Logic array blo cks

■ Macrocells

■ Expander product terms (shareable and parallel)

■ Programmable interconnect arra y

■ I/O control blocks

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure1 shows the ar chite cture of EPM7032 , EPM7064, and EPM7096 devic es .

Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram

INPUT/GLCK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2

LAB A LAB B

8 to 16 I/O pins

I/O

Control

Block

I/O

Control

Block

8 to 16

LAB C

Macrocells

1 to 16

Macrocells

33 to 48

8 to 16

LAB D

8 to 16

I/O

Control

Block

I/O

Control

Block

8 to 16 I/O pins

PIA

8 to 16

Macrocells

17 to 32

Macrocells

49 to 64

Altera Corporation 7

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure2 shows the architecture of MAX 7000E and MAX 7000S devices.

Figure 2. MAX 7000E & MAX 7000S Device Block Diagram

INPUT/GCLK1

NPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 Output Enables

Macrocells

17 to 32

Macrocells

49 to 64

LAB B

LAB D

6 to16

I/O

Control

Block

I/O

Control

Block

6 to 16 I/O Pin

LAB A

6 to16

6 to 16 I/O Pins

I/O

Control

Block

I/O

Control

Block

6 to16

LAB C

Macrocells

1 to 16

Macrocells

33 to 48

36 36

6 to16

36 36

6 to16

PIA

6 to16

Logic Array Blocks

The MAX 7000 device architecture is based on the linking of highperformance, flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macr ocell array s, as shown in Figures 1 and 2. Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and macrocells.

8 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

(

)

Each LAB is fed by the following signals:

■ 36 signals from the PIA that are used for general logic inputs

■ Global controls that are used for secondary register functions

■ Direct input paths from I/O pins to the registers that are used

for fast setup times for MAX 7000E and MAX 7000S devices

Macrocells

The MAX 7000 macrocell can be individual ly configur ed for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. The macrocell of EPM7032, EPM7064, and EPM7096 devic es i s s hown in Figure 3.

Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell

Logic Arra

Product

elect

atri

rallel Logic

Expanders

from other

macrocells

Global

Clear

Select

Global Clocks

VCC

Clock/

Enable

Select

Fast Input Select

PRN

D/T Q

ENA

CLRN

Programmable Register

Bypass

From I/O pin

To I/O Control Block

to PIA

36 Signals

rom PIA

16 Expander

Product

hared Logic

Expanders

Altera Corporation 9

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure4 shows a MAX 7000E and MAX 7000 S device macrocell.

Figure 4. MAX 7000E & MAX 7000S Device Macrocell

Logic Array

Product-

Term Select Matrix

Parallel Logic Expanders (from other macrocells)

Global

Clear

Clear Select

Global Clocks

VCC

Clock/

Enable

Select

Fast Input Select

PRN

D/T Q

ENA

CLRN

Programmable Register

Bypass

from I/O pin

to I/O Control Block

36 Signals

from PIA

16 Expander

Product T erms

Shared Logic Expanders

to PIA

Combinatorial logic is implemented in the logic array, which provides five product terms per macroce ll. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the ma crocell’s register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources:

■ Sharea ble expanders, which a re inverted product ter ms that are fed

back into the logic array

■ Parallel expanders, which are product terms borrowed from adjacent

macrocells

The Altera developm en t sys te m aut omatically optimizes pro du ct-term allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with prog rammable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization.

10 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

Each programmable regist er can be clock ed in th ree differe nt mo des:

■ By a global clock signal. This mode achieves th e fastest clock-to -

output performance.

■ By a glo b al clock signal and enabled by an act iv e-high cl ock

enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock.

■ By an array clock implemented with a product term. In this

mode, the flipflop can be clocked by signals from buried macrocells or I/O pins.

In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 70 00E a n d M A X 7000S devices, two glob al cl ock signals ar e available. As show n in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2.

Each register also suppor ts asynchr onous prese t and clear functions. As shown in Figures 3 and 4, the product -term select matrix al locates product terms to control these operations. Although the product-term-driven preset and clear of the register are active high, active-low control c an be obta ined by inve rting t he signal within t he logic array. In addition, each regist er c l ea r function can be individually driven by the active-low dedica te d global clea r pin (GCLRn). Upon power-up, each register in the device will be set to a low state.

All MAX 7000E and MAX 70 00S I/O pins h ave a f a st input path to a macrocell registe r . T his ded ica te d pat h a llows a s ig nal to by pas s t he PIA and combinatorial logic and be driven t o an input D flipflop w ith an extremely fast (2.5 ns) input setup time.

Expander Product Terms

Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources; however, the MAX 7000 architecture also allows both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.

Altera Corporation 11

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Shareable Expanders

Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (t shareable expanders are used. Figure 5 shows how shareable exp anders can feed multiple macrocells.

Figure 5. Shareable Expanders

Shareable expanders can be shared by any or all macrocells in an LAB.

) is incurred when

SEXP

Product-Term Select Matrix

Macrocell Product-Ter Logic

36 Signals from PIA

16 Shared Expanders

Parallel Expanders

Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product te rms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB.

12 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

From

The compile r can allocate up t o three sets of up to f iv e parallel expa nd ers automatically to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (t

). For example, if a macrocell requires 14 product terms, the

PEXP

Compiler use s the five dedicated pr oduct terms within the macroce ll a nd allocates two se ts of parallel expande rs; the first set includ e s fiv e p rodu ct terms and th e secon d set includ es fo ur product terms , inc reasing the to tal delay by 2 × t

PEXP

Two groups of 8 macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 6 shows how parallel ex pa nd er s ca n be borrowed from a neighboring macrocell.

Figure 6. Parallel Expanders

Unused product terms in a macrocell can be allocated to a neighboring macrocell.

Macrocell

Preset

36 Signals

from PIA

16 Shared

Expanders

Product-

Term

Select

Matrix

Product-

Term Select Matrix

Clock Clear

Preset

Clock Clear

To Next

Macrocell

Macrocell ProductTerm Logic

Altera Corporation 13

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Programmable Int er co nnec t A rray

Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000 dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available thro ugh out t he e ntire device. Only the sig nals required by eac h LAB are actually routed from the PIA into the LAB. Figure 7 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB.

Figure 7. PIA Ro ut ing

PIA

Signals

To LAB

While the routing dela ys of cha nne l-b ased r outi ng sche me s in ma sk ed or FPGAs are cumulativ e, vari able, and path-d epen dent, the MAX 7000 PI A has a fixed delay. The PIA thus eliminates skew between signals and makes timing performance easy to predict.

I/O Control Blocks

The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or V control block for the MAX 7000 family. The I/O control block of EPM7032, EPM7064, and EP M7096 device s has two global outp ut enable signal s that are driven by t wo dedicate d active-low ou tput ena ble pins ( OE1 and OE2). The I/O control block of MAX 7000E and MAX 7000S devices has six global output enab le signa ls that are d riven by the true or complemen t of two output enable sig na ls, a s ubse t of t he I /O pin s, o r a sub set of the I /O macrocells.

14 Altera Corporation

. Figure 8 shows the I/O

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Figure 8. I/O Control Block of MAX 7000 Devices

PM7032, EPM7064 & EPM7096 Devices

VCC

OE1 OE2

GND

rom Macrocell

To PIA

AX 7000E & MAX 7000S Devices

Six Global Output Enable Signals

PIA

VCC

To Other I/O Pins

From Macrocell

Fast Input to Macrocell Register

To PIA

GND

Open-Drain Output (1) Slew-Rate Control

Note:

(1) The open- d r ain o utput option is available only in MAX 7000S d ev i ces.

Altera Corporation 15

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-sta te buffer cont r ol is con ne cted to V enabled.

The MAX 7000 architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic.

, the output is

In-System Programmability (ISP)

MAX 7000S devices are in-system programmable via an industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 7000S architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-syst em programming wit h only a sing le 5.0 V power supply. Du ring in-system pr ogramming, the I /O pins are tri- stated and pulled-up to eliminate boa rd conflicts. The pull-up value is nomi nally 50 k¾.

ISP simplifies the man ufacturing flow by allowi ng devices to be mou nted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 7000S devices can be programmed by downloading the information via in-circuit teste rs (ICT), embedde d processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlast erMV cable, which can program and configure

2.5-V, 3 .3-V, and 5.0-V devi ces.) Prog ramming the devices after they are placed on the board eliminates lead damage on high-p in-cou nt pa ck ages (e.g., QFP packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem.

In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support a n adaptive alg or ithm, Altera o ff ers d evic es te sted with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code.

The Jam used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor.

16 Altera Corporation

Standard Test and Programming Lang uage (STAPL) can be

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

For more information on using the Jam language, see Application Note 88

(Using the Jam Language for ISP & ICR via an Embedded Processor).

The ISP circuitr y in MAX 7000S devices is compa tible wit h IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.

Programming Seque nce

During in-system programming, instructions, addresses, and data are shifted into the MAX 7000S device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data.

Programming a pattern into the device requires the following six ISP stages. A stand-alon e verification of a programmed pa ttern invo lves only stages 1, 2, 5, and 6.

1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1ms.

2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time.

3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms.

4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address.

5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address.

6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1ms.

Altera Corporation 17

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

-- -

Cycle

---

Programming Times

The time required to implement each of the six programming stages can be broken into the following two elements:

■ A pulse time to erase, program, or read the EEPROM cells.

■ A shifting time based on the test clock (TCK) frequency and the

number of TCK cycles to shift instructions, address, and data into the device.

By combining the pulse and shift times for each of the programming stages, the prog ram or v erify t ime ca n be d er ived as a fu nct ion of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fix ed and total var iable tim es are unique for a si ngle d evice.

Programming a Single MAX 7000S Device

The time required to program a single MAX 7000S device in-system can be calculated from the following formula:

Cycle

PTC

PROGtPPULSE

--------- --------------- -----

TCK

where: t

PROG

PPULSE

= Programming time = Sum of the fixed times to erase, program, and

verify the EEPROM cells

Cycle f

TCK

=Number of TCK cycles to program a device

PTCK

= TCK frequency

The ISP tim es for a stand-alone veri fica tion of a single M AX 7000S device can be calculated from the following formula:

VTCK

VERtVPULSE

where: t

VER

VPULSE

Cycle

18 Altera Corporation

---------- --------------- ----

TCK

=Verify time = Sum of the fixed times to verify the EEPROM cells

=Number of TCK cycles to verify a device

VTCK

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

The programming times described in Tables 6 through 8 are ass o ciated with the worst-case method using the enhanced ISP algorithm.

Table 6.MAX 7000S t

PULSE

& Cycle

TCK

Values

Device Programming Stand-Alone Verification

(s) Cycle

PPULSE

EPM7032S 4.02 342,000 0.03 200,000 EPM7064S 4.50 504,000 0.03 308,000 EPM7128S 5.11 832,000 0.03 528,000 EPM7160S 5.35 1,001,000 0.03 640,000 EPM7192S 5.71 1,192,000 0.03 764,000 EPM7256S 6.43 1,603,000 0.03 1,024,000

PTCK

(s) Cycle

VPULSE

VTCK

Tables 7 and 8 show the in-system programming and stand alone

verification times for several common test clock frequencies.

Table 7. MAX 7000S In-Sy stem Programming Times for Different Test Clock Frequencies

Device f

TCK

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kH z 50 kHz

EPM7032S 4.06 4.09 4.19 4.36 4.71 5.73 7.44 10.86 s EPM7064S 4.55 4.60 4.76 5.01 5.51 7.02 9.54 14.58 s EPM7128S 5.19 5.27 5.52 5.94 6.77 9.27 13.43 21.75 s EPM7160S 5.45 5.55 5.85 6.35 7.35 10.35 15.36 25.37 s EPM7192S 5.83 5.95 6.30 6.90 8.09 11.67 17.63 29.55 s EPM7256S 6.59 6.75 7.23 8.03 9.64 14.45 22.46 38.49 s

Units

Table 8.MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies

Device f

TCK

Units

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

EPM7032S 0.05 0.07 0.13 0.23 0.43 1.03 2.03 4.03 s EPM7064S 0.06 0.09 0.18 0.34 0.64 1.57 3.11 6.19 s EPM7128S 0.08 0.14 0.29 0.56 1.09 2.67 5.31 10.59 s EPM7160S 0.09 0.16 0.35 0.67 1.31 3.23 6.43 12.83 s EPM7192S 0.11 0.18 0.41 0.79 1.56 3.85 7.67 15.31 s EPM7256S 0.13 0.24 0.54 1.06 2.08 5.15 10.27 20.51 s

Altera Corporation 19

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Programmable Speed/Power Control

Output Configuration

MAX 7000 devices offer a power-saving mode that supports low-power operatio n across user-define d signal paths or the ent ire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic app lications requir e only a small fr action of all ga tes to operat e at maximum frequency.

The designer can program each individual macrocell in a MAX 7000

device for either high-speed (i.e., with the Turbo Bit

option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths ca n operate at re duced power . Macrocells t hat run at low power incur a nominal timing delay adder (t

, and t

SEXP

, t

ACL

, and t

parameters.

CPPW

) for the t

LPA

LAD

, t

, tIC,

LAC

MAX 7000 device outputs can be programmed to meet a variety of system-level requ ir eme nts.

MultiVolt I/O Interface

MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O interface feature, which allo ws MAX 7000 devices to interfac e with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I /O output drivers (VCCIO).

The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V V are therefore compatible with both 3.3-V and 5.0-V inputs.

level, input voltage thre shold s are at TTL levels, and

CCINT

The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power supply, depending on th e output require ments. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When V

is connected to a 3.3-V supply, the output high is

CCIO

3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V timing delay of t

levels lower than 4.75 V incur a nominally greater

CCIO

instead of t

OD2

OD1

Open-Drain Output Option (MAX 7000S Devic es Only )

MAX 7000S devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane.

20 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input vol tages. When

is 3.3 V, setting the open drain option will turn off the output

CCIO

pull-up transistor, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. When

is 5.0 V, setting the output drain option is not necessary

CCIO

because the pull-up transistor will already turn off when the pin exceeds appr oximately 3.8 V, allowing the external pull-up r esistor to pull the output high enough to meet 5.0-V CMOS input voltages.

Slew-Rate Control

The output buffer for each MAX 7000E and MAX 7000S I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew r ate provid es high-sp eed transit ions for high-performance sy stems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces s ystem noise, b ut adds a nominal de lay of 4 to 5 ns. In MAX 7000E devices, when the Turbo Bit is turned off, the slew rate is set for low noise performance. For MAX 7000S devices, each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis.

Programming wi th External Hardware

Altera Corporation 21

MAX 7000 devices can be programmed on Windows- based PCs with the Altera Logic Programmer card, the Master Pro gramming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the dev ice.

For more information, see the Altera Programming Hardware Data

Sheet.

The Altera development system can use text- or waveform-format test vectors created with the Text Editor or Waveform Editor to test the programmed device. For added de sign verification, designers can perform functional te sting to compare the functional beha vior of a MAX 7000 device with the results of simulation. Moreover, Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices.

For more information, see the Programming Hardware Manufacturers.

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

IEEE Std.

1149.1 (JTAG) Boundary-Scan Support

MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.

1149.1-1990. Table 9 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not requir ed, the JTAG pins are available as us er I/O pins.

Table 9. MAX 7000 JTAG Inst ructions

JTAG Instruction Dev ice s Description

SAMPLE/PRELOAD EPM7128S

EPM7160S EPM7192S EPM7256S

EXTEST EPM7128S

EPM7160S EPM7192S EPM7256S

BYPASS EPM7032S

EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

IDCODE EPM7032S

EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

ISP Instructions EPM7032S

EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

Allows a snapshot of signals at the device pins to be captured and examined during normal dev ic e operation, and permits an initial data pattern output at the device pins.

Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the out put pins and c apt uring test results at the input pins.

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation.

Selects the IDCODE registe r and plac es it be tween TDI and TDO, allowing the IDCODE to be serially shifted out of TDO.

These instructions are used whe n programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte -Co de f ile (.jbc), or Ser ial Vect or F ormat file (.svf) via an embedded proc es s or or te st equipment.

22 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

The instruction r egist er len gt h of MAX 7000S d evices is 10 bits . Tables 10 and 11 show the boundary-scan register length and device IDCODE information for MAX 7000S devices.

Table 10. MAX 7000S Boundary-Scan R egister Length

Device Boundary-Scan Register Length

EPM7032S 1 (1) EPM7064S 1 (1) EPM7128S 288 EPM7160S 312 EPM7192S 360 EPM7256S 480

Note:

(1) This device does not support JTAG boundary-scan testing. Selecting either the

EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register.

Table 11.32-Bit MAX 7000 Device IDCODE Note (1)

Device IDCODE (32 Bits)

Version (4 Bits)

EPM7032S 0000 0111 0000 0011 0010 00001101110 1 EPM7064S 0000 0111 0000 0110 0100 00001101110 1 EPM7128S 0000 0111 0001 0010 1000 00001101110 1 EPM7160S 0000 0111 0001 0110 0000 00001101110 1 EPM7192S 0000 0111 0001 1001 0010 00001101110 1 EPM7256S 0000 0111 0010 0101 0110 00001101110 1

Notes:

(1) The most significant bit (MSB) is on the left. (2) The least si gnificant bi t (L SB) for all JTAG IDCODEs is 1.

Altera Corporation 23

Part Number (16 Bi t s) Manufacturer’s

Identity (11 Bits)

1 (1 Bit)

(2)

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure9 shows the timing requirements for the JTAG signals.

Figure 9. MAX 7000 JTAG Waveforms

TMS

TDI

JCP

JCH

JCL

TCK

JPSU

JPH

JPXZ

TDO

Signal

to Be

Captured

Signal

to Be

Driven

JPZX

JSZX

JSSU

JPCO

JSH

JSCO

JSXZ

Table12 shows the JTAG timing parameters and values for MAX 7000S

devices.

Table 12. JTAG Timing Parameters & Values for MA X 7000S Devices

Symbol Parameter Min Max Unit

t t t t t t t t t t t t t

TCK clock period 100 ns

JCP

TCK clock high time 50 ns

JCH

TCK clock low time 50 ns

JCL

JTAG port setup time 20 ns

JPSU

JTAG port hold time 45 ns

JPH

JTAG port clock to output 25 ns

JPCO

JTAG port high impedance t o val id out put 25 ns

JPZX

JTAG port valid output to high im pedance 25 ns

JPXZ

Capture register setup time 20 ns

JSSU

Capture register hold time 45 ns

JSH

Update register clock to output 25 ns

JSCO

Update register high impedance to valid output 25 ns

JSZX

Update register valid output to high impedance 25 ns

JSXZ

For more information, see Application Note 39 (IEEE 1149.1 (JTAG)

Boundary-Scan Testing in Altera Devices).

24 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

VCC

Design Security

Generic Testing

All MAX 7000 devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the devi ce cannot be copied or retrieved. This feature provides a high level of design security because programmed data wit hin EEPROM cells is invisible . The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed.

Each MAX 7000 device is functionally tested. Complete testing of each programmable EEPROM bit a nd a ll in te rnal logi c e lements e nsur es 1 00 % programming yield . AC test measurements are taken under conditions equivalent to those sh own in Figure 10. Test patt erns c an be u sed an d the n erased during early stages of the production flow.

Figure 10 . MAX 7000 AC Test Conditions

Power supply transients can affect AC measurements. Simultaneous transitions of m ulti pl e out put s sh ould be avoided for accurate measurement. Threshold tes ts must not be performed under AC condit ions. Large-ampli tude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance be tween the device grou nd pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V devices and outputs. Numbers without brackets are for 3.3-V devices and outputs.

464 Ω

[703 Ω]

Device Output

250

[8.06 ]

KΩ

Device input rise and fall times < 3 ns

To Test System

Ω

C1 (includes JIG capacitance)

QFP Carrier & Development Socket

MAX 7000 and MAX 7000E de vices in QFP package s with 100 or more pins are shipped in special plastic carriers to protect the QFP leads. The carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology makes it possible to prog ram, tes t, erase, a nd reprogra m a device without exposing the leads to mechanical stress.

For detailed information and carrier dimensions, refer to the QFP Carrier

& Development Socket Data Sheet.

1 MAX 7000S devices are not shipped in carriers.

Altera Corporation 25

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Operating Conditions

Tables 13 through 18 provide information about absolute maximum

ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V MAX 7000 devices.

Table 13. MAX 7000 5.0-V Device Absolute Maxi mum Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

V I T T T

OUT

Supply voltage With respect to ground (2) –2.0 7.0 V

DC input voltage –2.0 7.0 V

DC output current, per pin –25 25 mA Storage temperature N o bias –65 150 ° C

STG

Ambient temperature Under bias –65 135 ° C

AMB

Junction temperature C eramic packages, under bias 150 ° C

PQFP and RQFP packages, under bias 135 ° C

Table 14. MAX 7000 5.0-V Device Recommended Op erating Conditions

Symbol Parameter Conditions Min Max Unit

V V V T

Supply voltage for internal logic and

CCINT

input buffers Supply voltage for output drivers,

CCIO

5.0-V operation Supply voltage for output drivers,

3.3-V operation Supply voltage during ISP (7) 4.75 5.25 V

CCISP

Input voltage –0.5 (8) V

Output voltage 0V

Ambient temperature For commercial use 0 70 ° C

Junction temperature For commercial use 0 90 ° C

Input rise time 40 ns Input fall time 40 ns

(3), (4), (5) 4.75

(4.50)

(3), (4) 4.75

(4.50)

(3), (4), (6) 3.00

(3.00)

For industrial use –40 85 ° C

For industrial use –40 105 ° C

5.25

(5.50)

5.25

(5.50)

3.60

(3.60)

CCINT

CCIO

+ 0.5 V

26 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 15.MAX 7000 5.0-V Device DC Operating Conditions Note (9)

Symbol Parameter Conditions Min Max Unit

V V V

High-level input voltage 2.0 V

Low-level input voltage –0.5 (8) 0.8 V

5.0-V high-level TTL output voltage IOH = –4 mA DC, V

3.3-V high-level TTL output voltage I

3.3-V high-level CMOS output voltage

5.0-V low-level TTL output voltage IOL = 12 mA DC, V

3.3-V low-level TTL output voltage I

3.3-V low-level CMOS output voltage

Leakage current of dedicated input

= –4 mA DC, V

= –0.1 mA DC, V

= 12 mA DC, V

= 0.1 mA DC, V

VI = –0.5 to 5.5 V (11) –10 10 µA

= 4.75 V (10) 2.4 V

CCIO

= 3.00 V (10) 2.4 V

CCIO

= 3.0 V (10) V

CCIO

= 4.75 V (11) 0.45 V

CCIO

= 3.00 V (11) 0.45 V

CCIO

= 3.0 V(11) 0.2 V

CCIO

– 0.2 V

CCIO

pins I/O pin tri-state output off-state

VI = –0.5 to 5.5 V (11), (12) –40 40 µA

current

CCINT

+ 0.5 V

Table 16.MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices Note (13)

Symbol Parameter Conditions Min Max Unit

C C

Input pin capacitance VIN = 0 V, f = 1.0 MHz 12 pF

I/O pin capacitance V

I/O

= 0 V, f = 1.0 MHz 12 pF

OUT

Table 17.MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices No te (13)

Symbol Parameter Conditions Min Max Unit

C C

Input pin capacitance VIN = 0 V, f = 1.0 MHz 15 pF

I/O pin capacitance V

I/O

= 0 V, f = 1.0 MHz 15 pF

OUT

Table 18.MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Note (13)

Symbol Parameter Conditions Min Max Unit

C C

Altera Corporation 27

Dedicated input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF

I/O pin capacitance V

I/O

= 0 V, f = 1.0 MHz 10 pF

OUT

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

T O C

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimu m DC input volta ge on I/O pins is –0 . 5 V a n d on 4 dedicated input pins is –0 . 3 V. D ur ing transit ions, the

inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than

20 ns. (3) Numbers in parentheses are for industrial-te mperatur e-ra nge devices. (4) V (5) The POR time for all 7000S devices does not exceed 300 µs. The sufficient V

(6) 3.3-V I/O operation is n ot avail able for 44-pin packages. (7) The V (8) During in-system pro gr a mming, the minimum DC input voltage is –0.3 V.

must rise monotonically.

device is fully initialized within the POR time after V

parameter applies only t o MA X 7000S devices.

CCISP

voltage level for POR is 4.5 V. The

reaches the sufficient POR voltage level.

CCINT

(9) The se values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26. (10) The parameter is measured with 50% of the outputs each sourcing the specified current. The I

to high-level TTL or CMOS output current. (11) The parameter is measured with 50% of the outputs each sinking the specified current. The I

low-level T T L, PCI, or CM OS output current.

parameter refers

parameter refers to

(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically

–60 µA. (13) Capacitan c e is measured at 25° C and is sample-tested only. The

OE1 pin has a maximum capacitance of 20 pF.

Figure 11 shows the typical output drive characteristics of MAX 7000

devices.

Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices

150

120

ypical

utput

urrent (mA)

Timing Model

Typical

= 5.0 V

CCIO

Room T emperature

12345

Output Current (mA)

VO Output Voltage (V)

MAX 7000 de vice timi ng ca n be an aly zed wi th the Alt era so ftwa re, with a variety of popula r industry-standard EDA simulators and timing

150

120

12345

= 3.3 V

CCIO

Room T emperature

3.3

VO Output Voltage (V)

analyzers, or with the timing model shown in Figure 12. MAX 7000 devices have fixed internal delays that enable the designer to determine the worst-case ti ming of any design . The Alt era sof tware provid es timin g simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation.

28 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Figure 12 . MAX 7000 Timing Model

Internal Output

Enable Delay

(1)

IOE

Input

Delay

PIA

Delay

PIA

Global Control

Delay

GLOB

Logic Array

Delay

LAD

Control Delay

LAC

Shared

Expander Delay

SEXP

Notes:

(1) Only available in M A X 7000E and MAX 7000S devi ces. (2) Not available in 44-pin d evices.

The timing characteristics of any signal path can be derived from the timing model and parameters of a particular dev ice . Ex te rn al timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 13 shows the internal timing relationship of internal and external delay parameters.

Parallel

Expander Delay

PEXP

Input Delay

Fast

FIN

(1)

Delay

PRE

CLR

COMB

FSU

Output

Delay

OD1

OD2

OD3

ZX2

ZX3

(2)

(2) (1)

I/O

Delay

For more infomration, see Application Note 94 (Understanding MAX 7000

Timing).

Altera Corporation 29

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure 13. Swi t ch i ng W aveforms

tR & tF < 3 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. A ll timing characteristics are measured at 1.5 V.

Input Pin

I/O Pin

PIA Delay

Shared Expander

Parallel Expander

Delay

Logic Array

Input

Delay

Logic Array

Output

Output Pin

Global

Clock Pin

Global Clock

at Register

Data or Enable

(Logic Array Output)

Combinatorial Mode

Global Clock Mode

tSUt

GLOB

PIA

SEXP

, t

LAC

LAD

PEXP

COMB

Array Clock Mode

, t

CLR

PRE

PIA

Input or I/O Pin

Clock into PIA

Clock into

Logic Array

Clock at

Data from

Logic Array

to Logic Array

to Pin

ACH

PIA

ACL

PIA

30 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Tables 19 through 26 show the MAX 7000 and MAX 7000E AC

operating conditions.

Table 19.MAX 7000 & MAX 7000E External Timing Parameters Note (1)

Symbol Parameter Conditions -6 Speed Grade -7 Speed Grade Unit

Min Max Min Max

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 6.0 7.5 ns I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns Global clock setup time 5.0 6.0 ns Global clock hold time 0.0 0.0 ns Global clock setup time of fast input (2) 2.5 3.0 ns Global clock hold time of fast input (2) 0.5 0.5 ns Global clock to output delay C1 = 35 pF 4.0 4.5 ns Global clock high time 2.5 3.0 ns Global clock low time 2.5 3.0 ns Array clock setup time 2.5 3.0 ns Array clock hold time 2.0 2.0 ns Array clock to output delay C 1 = 35 pF 6.5 7.5 ns Array clock high time 3.0 3.0 ns Array clock low time 3.0 3.0 ns Minimum pulse width for clear and

(3) 3.0 3.0 ns

preset Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns Minimum global clock period 6.6 8.0 ns Maximum internal global clock

(5) 151.5 125.0 MHz

frequency Minimum array clock period 6.6 8.0 ns Maximum internal array clock

(5) 151.5 125.0 MHz

frequency Maximum clock frequency (6) 200 166.7 MHz

Altera Corporation 31

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 20. MAX 7000 & MAX 7000E Inter nal Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade -6 Speed Grade -7 Unit

Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Input pad and buffer delay 0.4 0.5 ns I/O input pad and buffer delay 0.4 0.5 ns Fast input delay (2) 0.8 1.0 ns Shared expander delay 3.5 4.0 ns Parallel expander delay 0.8 0.8 ns Logic array delay 2.0 3.0 ns Logic control array delay 2.0 3.0 ns Internal output enable delay (2) 2.0 ns Output buffer and pad delay

Slow slew rate = off, V

CCIO

Output buffer and pad delay Slow slew rate = off, V

CCIO

Output buffer and pad delay

= 5.0 V

= 3.3 V

C1 = 35 pF 2.0 2.0 ns

C1 = 35 pF (7) 2.5 2.5 ns

C1 = 35 pF (2) 7.0 7.0 ns

Slow slew rate = on,

= 5.0 V or 3.3 V

CCIO

Output buffer enable delay Slow slew rate = off, V

CCIO

Output buffer enable delay Slow slew rate = off, V

CCIO

Output buffer enable delay

= 5.0 V

= 3.3 V

C1 = 35 pF 4.0 4.0 ns

C1 = 35 pF (7) 4.5 4.5 ns

C1 = 35 pF (2) 9.0 9.0 ns

Slow slew rate = on

= 5.0 V or 3.3 V

CCIO

Output buffer disable delay C1 = 5 pF 4.0 4.0 ns Register setup time 3.0 3.0 ns Register hold time 1.5 2.0 ns Register setup time of fast input (2) 2.5 3.0 ns Register hold time of fast input (2) 0.5 0.5 ns Register delay 0.8 1.0 ns Combinatorial delay 0.8 1.0 ns Array clock delay 2.5 3.0 ns Register enable time 2.0 3.0 ns Global control delay 0.8 1.0 ns Register preset time 2.0 2.0 ns Register clear time 2.0 2.0 ns PIA delay 0.8 1.0 ns Low-power adder (8) 10.0 10.0 ns

32 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 21.MAX 7000 & MAX 7000E External Timing Parameters Note (1)

Symbol Paramet er Conditi ons Speed G rade Unit

MAX 7000E (-10P) MAX 7000 (-10)

MAX 7000E (-10)

Min Max Min Max

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 10.0 10.0 ns I/O input to non-registered output C1 = 35 pF 10.0 10.0 ns Global clock setup time 7.0 8.0 ns Global clock hold time 0.0 0.0 ns Global clock setup time of fast input (2) 3.0 3.0 ns Global clock hold time of fast input (2) 0.5 0.5 ns Global clock to output delay C1 = 35 pF 5.0 5 ns Global clock high time 4.0 4.0 ns Global clock low time 4.0 4.0 ns Array clock setup time 2.0 3.0 ns Array clock hold time 3.0 3.0 ns Array clock to output delay C1 = 35 pF 10.0 10.0 ns Array clock high time 4.0 4.0 ns Array clock low time 4.0 4.0 ns Minimum pulse width for clear and

(3) 4.0 4.0 ns

preset Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns Minimum global clock period 10.0 10.0 ns Maximum internal global clock

(5) 100.0 100.0 MHz

frequency Minimum array clock period 10.0 10.0 ns Maximum internal array clock

(5) 100.0 100.0 MHz

frequency Maximum clock frequency (6) 125.0 125.0 MHz

Altera Corporation 33

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 22. MAX 7000 & MAX 7000E Inter nal Timing Parameters Note (1)

Symbol Parameter Conditio ns Speed Grade Unit

MAX 7000E ( -10P ) MAX 7000 (-10)

MAX 7000E (-10)

Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

34 Altera Corporation

Input pad and buffer delay 0.5 1.0 ns I/O input pad and buffer delay 0.5 1.0 ns Fast input delay (2) 1.0 1 .0 ns Shared expander delay 5.0 5.0 ns Parallel expander delay 0.8 0.8 ns Logic array delay 5.0 5.0 ns Logic control array delay 5.0 5.0 ns Internal output enable delay (2) 2.0 2.0 ns Output buffer and pad delay

C1 = 35 pF 1.5 2.0 ns Slow slew rate = off V

= 5.0 V

CCIO

Output buffer and pad delay

C1 = 35 pF (7) 2.0 2.5 ns Slow slew rate = off V

= 3.3 V

CCIO

Output buffer and pad delay

C1 = 35 pF (2) 5.5 6.0 ns Slow slew rate = on V

= 5.0 V or 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF 5.0 5.0 ns Slow slew rate = off V

= 5.0 V

CCIO

Output buffer enable delay

C1 = 35 pF (7) 5.5 5.5 ns Slow slew rate = off V

= 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF (2) 9.0 9.0 ns Slow slew rate = on V

= 5.0 V or 3.3 V

CCIO

Output buffer disable delay C1 = 5 pF 5.0 5.0 ns Register setup time 2.0 3.0 ns Register hold time 3.0 3 .0 ns Register setup time of fast input (2) 3.0 3.0 ns Register hold time of fast input (2) 0.5 0.5 ns Register delay 2.0 1.0 ns Combinatorial delay 2.0 1.0 ns Array clock delay 5.0 5.0 ns Register enable time 5.0 5.0 ns Global control delay 1.0 1.0 ns Register preset time 3.0 3.0 ns Register clear time 3.0 3.0 ns PIA delay 1.0 1.0 ns Low-power adder (8) 11.0 11.0 ns

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 23.MAX 7000 & MAX 7000E External Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

MAX 7000E ( -12 P) MAX 7000 (-12)

MAX 7000E (-12)

Min Max Min Max

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 12.0 12.0 ns I/O input to non-registered output C1 = 35 pF 12.0 12.0 ns Global clock setup time 7.0 10.0 ns Global clock hold time 0.0 0.0 ns Global clock setup time of fast input (2) 3.0 3.0 ns Global clock hold time of fast input (2) 0.0 0.0 ns Global clock to output delay C1 = 35 pF 6.0 6.0 ns Global clock high time 4.0 4.0 ns Global clock low time 4.0 4.0 ns Array clock setup time 3.0 4.0 ns Array clock hold time 4.0 4.0 ns Array clock to output delay C1 = 35 pF 12.0 12.0 ns Array clock high time 5.0 5.0 ns Array clock low time 5.0 5.0 ns Minimum pulse width for clear and

(3) 5.0 5.0 ns

preset Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns Minimum global clock period 11.0 11.0 ns Maximum internal global clock

(5) 90.9 90.9 MHz

frequency Minimum array clock period 11.0 11.0 ns Maximum internal array clock

(5) 90.9 90.9 MHz

frequency Maximum clock frequency (6) 125.0 125.0 MHz

Altera Corporation 35

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 24.MAX 7000 & MAX 7000E Internal Timi ng Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

MAX 7000E (-12P) MAX 7000 (-12)

MAX 7000E (-12)

Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

36 Altera Corporation

Input pad and buffer delay 1.0 2.0 ns I/O input pad and buffer delay 1.0 2.0 ns Fast input delay (2) 1.0 1.0 ns Shared expander delay 7.0 7.0 ns Parallel expander delay 1 .0 1.0 ns Logic array delay 7.0 5.0 ns Logic control array delay 5.0 5.0 ns Internal output enable delay (2) 2.0 2.0 ns Output buffer and pad delay

C1 = 35 pF 1.0 3.0 ns

Slow slew rate = off

= 5.0 V

CCIO

Output buffer and pad delay

C1 = 35 pF (7) 2.0 4.0 ns

Slow slew rate = off

= 3.3 V

CCIO

Output buffer and pad delay

C1 = 35 pF (2) 5.0 7.0 ns

Slow slew rate = on

= 5.0 V or 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF 6.0 6.0 ns

Slow slew rate = off

= 5.0 V

CCIO

Output buffer enable delay

C1 = 35 pF (7) 7.0 7.0 ns

Slow slew rate = off

= 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF (2) 10.0 10.0 ns

Slow slew rate = on

= 5.0 V or 3.3 V

CCIO

Output buffer disable delay C1 = 5 pF 6.0 6.0 ns Register setup time 1.0 4.0 ns Register hold time 6.0 4.0 ns Register setup time of fast input (2) 4.0 2.0 ns Register hold time of fast input (2) 0.0 2.0 ns Register delay 2.0 1.0 ns Combinatorial delay 2.0 1.0 ns Array clock delay 5.0 5.0 ns Register enable time 7.0 5.0 ns Global control delay 2.0 0.0 ns Register preset time 4.0 3.0 ns Register clear time 4.0 3.0 ns PIA delay 1.0 1.0 ns Low-power adder (8) 12.0 12.0 ns

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 25. MAX 7000 & MAX 7000E External Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-15 -15T -20

Min Max Min Max Min Max

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 15.0 15.0 20.0 ns I/O input to non-registered

C1 = 35 pF 15.0 15.0 20.0 ns

output Global clock setup time 11.0 11.0 12.0 ns Global clock hold time 0.0 0.0 0.0 ns Global clock setup time of fast

(2) 3.0 – 5.0 ns

input Global clock hold time of fast

(2) 0.0 – 0.0 ns

input Global clock to output delay C1 = 35 pF 8.0 8.0 12.0 ns Global clock high time 5.0 6.0 6.0 ns Global clock low time 5.0 6.0 6.0 ns Array clock setup time 4.0 4.0 5.0 ns Array clock hold time 4.0 4.0 5.0 ns Array clock to output delay C1 = 35 pF 15.0 15.0 20.0 ns Array clock high time 6.0 6.5 8.0 ns Array clock low time 6.0 6.5 8.0 ns Minimum pulse width for clear

(3) 6.0 6.5 8.0 ns

and preset Output data hold time after

C1 = 35 pF (4) 1.0 1.0 1.0 ns

clock Minimum global clock period 13.0 13.0 16.0 n s Maximum internal global clock

(5) 76.9 76.9 62.5 MHz

frequency Minimum array clock period 13.0 13.0 16 .0 ns Maximum internal array clock

(5) 76.9 76.9 62.5 MHz

frequency Maximum clock frequency (6) 100 83.3 83.3 MHz

Altera Corporation 37

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 26.MAX 7000 & MAX 7000E Internal Timi ng Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-15 -15T -20

Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Input pad and buffer delay 2.0 2.0 3.0 ns I/O input pad and buffer delay 2.0 2.0 3.0 ns Fast input delay (2) 2.0 – 4.0 ns Shared expander delay 8.0 10.0 9.0 ns Parallel expander delay 1.0 1.0 2.0 ns Logic array delay 6.0 6.0 8.0 ns Logic control array delay 6.0 6.0 8.0 ns Internal output enable delay (2) 3.0 – 4.0 ns Output buffer and pad delay

C1 = 35 pF 4.0 4.0 5.0 ns

Slow slew rate = off

= 5.0 V

CCIO

Output buffer and pad delay

C1 = 35 pF (7) 5.0 – 6.0 ns

Slow slew rate = off

= 3.3 V

CCIO

Output buffer and pad delay

C1 = 35 pF (2) 8.0 – 9.0 ns

Slow slew rate = on

= 5.0 V or 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF 6.0 6.0 10.0 ns Slow slew rate = off V

= 5.0 V

CCIO

Output buffer enable delay

C1 = 35 pF (7) 7.0 – 11.0 ns Slow slew rate = off V

= 3.3 V

CCIO

Output buffer enable delay

C1 = 35 pF (2) 10.0 – 14.0 ns Slow slew rate = on V

= 5.0 V or 3.3 V

CCIO

Output buffer disable delay C1 = 5 pF 6.0 6.0 10.0 ns Register setup time 4.0 4.0 4.0 ns Register hold time 4.0 4.0 5.0 ns Register setup time of fast input (2) 2.0 – 4.0 ns Register hold time of fast input (2) 2.0 – 3.0 ns Register delay 1.0 1.0 1.0 ns Combinatorial delay 1.0 1.0 1.0 ns Array clock delay 6.0 6.0 8.0 ns Register enable time 6.0 6.0 8.0 ns Global control delay 1.0 1.0 3.0 ns Register preset time 4.0 4.0 4.0 ns Register clear time 4.0 4.0 4.0 ns PIA delay 2.0 2.0 3.0 ns Low-power adder (8) 13.0 15.0 15.0 ns

38 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14 . See Figure 1 3 for more

information on switching waveforms. (2) This parameter applies to MAX 7000E devices only. (3) This minimum pulse width for preset and clear applies for both global clear and array controls. The t

must be added to this minimum width if the clear or reset signal incorporates the t

path.

parameter into the signal

LAD

parameter

LPA

(4) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

parameter applies for both global and array clocking. (5) These parameter s ar e measured with a 16-bit loa d ab le, en abled, up/down counter programmed int o eac h L AB . (6) The f (7) Operati ng con d iti o ns : V (8) The t

running in the low-power mode.

values repr esent the highest fr eq uency for pi pelined data.

MAX

parameter must be added to the t

LPA

= 3.3 V ± 10% for commercial and industrial use.

CCIO

LAD

, t

LAC

, tIC, tEN, t

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

Tables 27 and 28 show the EPM7032S AC operating conditions.

Table 27.EPM7032S External Timing Parameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns I/O input to non-registered

C1 = 35 pF 5.0 6.0 7.5 10.0 ns

output Global clock setup time 2.9 4.0 5.0 7.0 ns Global clock hold time 0.0 0.0 0.0 0.0 ns Global clock setup time of fast

2.5 2.5 2.5 3.0 ns

input Global clock hold time of fast

0.0 0.0 0.0 0.5 ns

input Global clock to output delay C1 = 35 pF 3.2 3.5 4.3 5.0 ns Global clock high time 2.0 2.5 3.0 4.0 ns Global clock low time 2.0 2.5 3.0 4.0 ns Array clock setup time 0.7 0.9 1.1 2.0 ns Array clock hold time 1.8 2.1 2.7 3.0 ns Array clock to output delay C1 = 35 pF 5.4 6.6 8.2 10.0 ns Array clock high time 2.5 2.5 3.0 4.0 ns Array clock low time 2.5 2.5 3.0 4.0 ns Minimum pulse width for clear

(2) 2.5 2.5 3.0 4.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns

clock Minimum global clock period 5.7 7.0 8.6 10.0 ns Maximum internal global clock

(4) 17 5.4 142.9 11 6.3 100.0 MHz

frequency Minimum array clock period 5.7 7.0 8.6 10.0 ns

Altera Corporation 39

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 27.EPM7032S External Timing Parameters (Part 2 of 2) Note (1)

Symbol Parameter Con di tions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

ACNT

MAX

Maximum internal array clock

(4) 175.4 142.9 116.3 100.0 M Hz

frequency Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz

Table 28. EPM 7032S Internal Timing Parameters Note (1)

Symbol Parameter Conditio ns Speed Grad e Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

Input pad and buffer delay 0.2 0.2 0.3 0.5 ns I/O input pad and buffer delay 0.2 0.2 0.3 0.5 ns Fast input delay 2.2 2.1 2.5 1.0 ns Shared expander delay 3.1 3.8 4.6 5.0 ns Parallel expander delay 0.9 1.1 1.4 0.8 ns Logic array delay 2.6 3.3 4.0 5.0 ns Logic control array delay 2.5 3.3 4.0 5.0 ns Internal output enable delay 0.7 0.8 1.0 2.0 ns Output buffer and pad delay C1 = 35 pF 0.2 0.3 0.4 1.5 ns Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 0.9 2.0 ns Output buffer and pad delay C1 = 35 pF 5.2 5.3 5.4 5.5 ns Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns Register setup time 0.8 1.0 1.3 2.0 ns Register hold time 1.7 2.0 2.5 3.0 ns Register setup time of fast

1.9 1.8 1.7 3.0 ns

input Register hold time of fast

0.6 0.7 0.8 0.5 ns

input Register delay 1.2 1.6 1.9 2.0 ns Combinatorial delay 0.9 1.1 1.4 2.0 ns Array clock delay 2.7 3.4 4.2 5.0 ns Register enable time 2.6 3.3 4.0 5.0 ns Global control delay 1.6 1.4 1.7 1.0 ns Register preset time 2.0 2 .4 3.0 3.0 ns Register clear time 2.0 2.4 3.0 3.0 ns

40 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 28. EPM7032S Int ernal Timing Parameters Note (1)

Symbol Paramet er Conditio ns Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

PIA

LPA

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14 . See Figure 1 3 for more

(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t

(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

(4) These parameter s ar e measured with a 16-bit loa d ab le, en abled, up/down counter programmed int o eac h L AB . (5) The f (6) Operati ng con d iti o ns : V (7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, E PM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,

(8) The t

PIA delay (7) 1.1 1.1 1.4 1.0 ns Low-power adder (8) 12.0 10.0 10.0 11.0 ns

information on switching waveforms.

parameter must be added to this minimum width if the clear or reset signal incorporates the t path.

parameter into the signal

LAD

LPA

parameter applies for both global and array clocking.

values repr esent the highest fr eq uency for pi pelined data.

MAX

= 3.3 V ± 10% for commercial and industrial use.

CCIO

these values are spec i fied for a PIA fan-out of one LA B (16 macrocells). For eac h add it ional LAB fan-out in thes e devices, add an addition al 0. 1 n s to th e PI A ti mi ng v alu e.

parameter must be added to the t

LPA

running in the low-power mode.

LAD

, t

LAC

, tIC, tEN, t

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

Tables 29 and 30 show the EPM7064S AC operating conditions.

Table 29.EPM7064S External Timing Parameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

PD1

PD2

FSU

CO1

ASU

Altera Corporation 41

Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns I/O input to non-registered

output Global clock setup time 2.9 3.6 6.0 7.0 ns Global clock hold time 0.0 0.0 0.0 0.0 ns Global clock setup time of fast

input Global clock hold time of fast

input Global clock to output delay C1 = 35 pF 3.2 4.0 4.5 5.0 ns Global clock high time 2.0 2.5 3.0 4.0 ns Global clock low time 2.0 2.5 3.0 4.0 ns Array clock setup time 0.7 0.9 3.0 2.0 ns Array clock hold time 1.8 2.1 2.0 3.0 ns

C1 = 35 pF 5.0 6.0 7.5 10.0 ns

2.5 2.5 3.0 3.0 ns

0.0 0.0 0.5 0.5 ns

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 29.EPM7064S External Timing Parameters (Part 2 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Array clock to output delay C1 = 35 pF 5.4 6.7 7.5 10.0 ns Array clock high time 2.5 2.5 3.0 4.0 ns Array clock low time 2.5 2.5 3.0 4.0 ns Minimum pulse width for clear

(2) 2.5 2.5 3.0 4.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns

clock Minimum global clock period 5.7 7.1 8.0 10.0 ns Maximum internal global clock

(4) 175.4 140.8 125.0 100.0 MHz

frequency Minimum array clock period 5.7 7.1 8.0 10.0 ns Maximum internal array clock

(4) 175.4 140.8 125.0 100.0 MHz

frequency Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz

Table 30. EPM7064S Int ernal Timing Parameters (Part 1 of 2) Note (1)

Symbol P ara me ter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

42 Altera Corporation

Input pad and buffer delay 0.2 0.2 0.5 0.5 ns I/O input pad and buffer delay 0.2 0.2 0.5 0.5 ns Fast input delay 2.2 2.6 1.0 1.0 ns Shared expander delay 3.1 3.8 4.0 5.0 ns Parallel expander delay 0.9 1.1 0.8 0.8 ns Logic array delay 2.6 3.2 3.0 5.0 ns Logic control array delay 2.5 3.2 3.0 5.0 ns Internal output enable delay 0.7 0.8 2.0 2.0 ns Output buffer and pad delay C1 = 35 pF 0.2 0.3 2.0 1.5 ns Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 2.5 2.0 ns Output buffer and pad delay C1 = 35 pF 5.2 5.3 7.0 5.5 ns Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns Register setup time 0.8 1.0 3.0 2.0 ns Register hold time 1.7 2.0 2.0 3.0 ns

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 30.EPM7064S Internal Timing Parameters (Part 2 of 2) Note (1)

Symbol Parame t er Conditio ns Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more

(2) This minimum pulse width for p reset and cl ear applies fo r both global cle ar and arra y controls. The t

(3) This par a meter is a guideline that is s ample-teste d only and is ba s ed o n extensive de v ic e c haracteri za t ion. This

(4) These paramete rs are measu r ed with a 16-bit loadable, enab le d , up/ d own counter program med into each LAB. (5) The f (6) Operating conditions: V (7) For EPM7064S-5, E PM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, an d EPM7256S-7 devices,

(8) The t

Register delay 1.2 1.6 1.0 2.0 ns Combinatorial delay 0.9 1.0 1.0 2.0 ns Array clock delay 2.7 3.3 3.0 5.0 ns Register enable time 2.6 3.2 3.0 5.0 ns Global control delay 1.6 1.9 1.0 1.0 ns Register preset time 2.0 2.4 2.0 3.0 ns Register clear time 2.0 2.4 2.0 3.0 ns PIA delay (7) 1.1 1 .3 1.0 1.0 ns Low-power adder (8) 12.0 11.0 10.0 11.0 ns

1.9 1 .8 3.0 3.0 ns

0.6 0 .7 0.5 0.5 ns

information on switching waveforms.

parameter must be added to this minimum width if the clear or reset signal incorporates the t path.

parameter into the signal

LAD

LPA

parameter applies for both global and array clocking.

values repres en t th e highest frequency for pipeline d data.

MAX

= 3.3 V ± 10% for commercial and industrial use.

CCIO

these values ar e specified for a PIA fan-out of on e L A B (16 macrocells). For ea c h add itional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value.

parameter must be added to the t

LPA

running in th e low-power mod e.

LAD

, t

, tIC, tEN, t

LAC

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

Altera Corporation 43

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Tables 31 and 32 show the EPM7128S AC operating conditions.

Table 31.EPM7128S Exter na l Timi ng Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

MinMaxMinMaxMinMaxMinMax

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns I/O input to non-registered

C1 = 35 pF 6.0 7.5 10.0 15.0 ns

output Global clock setup time 3.4 6.0 7.0 11.0 ns Global clock hold time 0.0 0.0 0.0 0.0 ns Global clock setup time of fast

2.5 3.0 3.0 3.0 ns

input Global clock hold time of fast

0.0 0.5 0.5 0.0 ns

input Global clock to output delay C1 = 35 pF 4.0 4.5 5.0 8.0 ns Global clock high time 3.0 3.0 4.0 5.0 ns Global clock low time 3.0 3.0 4.0 5.0 ns Array clock setup time 0.9 3.0 2.0 4.0 ns Array clock hold time 1.8 2.0 5.0 4.0 ns Array clock to output delay C1 = 35 pF 6.5 7.5 10.0 15.0 ns Array clock high time 3.0 3.0 4.0 6.0 ns Array clock low time 3.0 3.0 4.0 6.0 ns Minimum pulse width for clear

(2) 3.0 3.0 4.0 6.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns

clock Minimum global clock period 6.8 8.0 10.0 13.0 ns Maximum internal global clock

(4) 147.1 125.0 100.0 76.9 MHz

frequency Minimum array clock period 6.8 8.0 10.0 13.0 ns Maximum internal array clock

(4) 147.1 125.0 100.0 76.9 MHz

frequency Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz

44 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 32. EPM 7128S Internal Timing Parameters Note (1)

Symbol Parame t er Conditio ns Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Input pad and buffer delay 0.2 0.5 0.5 2.0 ns I/O input pad and buffer delay 0.2 0.5 0.5 2.0 ns Fast input delay 2.6 1.0 1.0 2.0 ns Shared expander delay 3.7 4.0 5.0 8.0 ns Parallel expander delay 1.1 0.8 0.8 1.0 ns Logic array delay 3.0 3.0 5.0 6.0 ns Logic control array delay 3.0 3.0 5.0 6.0 ns Internal output enable delay 0.7 2.0 2.0 3.0 ns Output buffer and pad delay C1 = 35 pF 0.4 2.0 1.5 4.0 ns Output buffer and pad delay C1 = 35 pF (6) 0.9 2.5 2.0 5.0 ns Output buffer and pad delay C1 = 35 pF 5.4 7.0 5.5 8.0 ns Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns Register setup time 1.0 3.0 2.0 4.0 ns Register hold time 1.7 2.0 5.0 4.0 ns Register setup time of fast

1.9 3.0 3.0 2.0 ns

input Register hold time of fast

0.6 0.5 0.5 1.0 ns

input Register delay 1.4 1.0 2.0 1.0 ns Combinatorial delay 1.0 1.0 2.0 1.0 ns Array clock delay 3.1 3.0 5.0 6.0 ns Register enable time 3.0 3.0 5.0 6.0 ns Global control delay 2.0 1.0 1.0 1.0 ns Register preset time 2.4 2.0 3.0 4.0 ns Register clear time 2.4 2.0 3.0 4.0 ns PIA delay (7) 1.4 1 .0 1.0 2.0 ns Low-power adder (8) 11.0 10.0 11.0 13.0 ns

Altera Corporation 45

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14 . See Figure 1 3 for more

information on switching waveforms.

(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t

must be added to this minimum width if the clear or reset signal incorporates the t path.

parameter into the signal

LAD

parameter

LPA

(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

parameter applies for both global and array clocking.

values repr esent the highest fr eq uency for pi pelined data.

MAX

= 3.3 V ± 10% for commercial and industrial use.

CCIO

these values are spec i fied for a PIA fan-out of one LA B (16 macrocells). For eac h add it ional LAB fan-out in thes e devices, add an addition al 0. 1 n s to th e PI A ti mi ng v alu e.

(8) The t

parameter must be added to the t

LPA

running in the low-power mode.

LAD

, t

LAC

, tIC, tEN, t

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

Tables 33 and 34 show the EPM7160S AC operating conditions.

Table 33.EPM7160S External Timing Parameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

MinMaxMinMaxMinMaxMinMax

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns I/O input to non-registered

C1 = 35 pF 6.0 7.5 10.0 15.0 ns

output Global clock setup time 3.4 4.2 7.0 11.0 ns Global clock hold time 0.0 0.0 0.0 0.0 ns Global clock setup time of fast

2.5 3.0 3.0 3.0 ns

input Global clock hold time of fast

0.0 0.0 0.5 0.0 ns

input Global clock to output delay C1 = 35 pF 3.9 4.8 5 8 ns Global clock high time 3.0 3.0 4.0 5.0 ns Global clock low time 3.0 3.0 4.0 5.0 ns Array clock setup time 0.9 1.1 2.0 4.0 ns Array clock hold time 1.7 2.1 3.0 4.0 ns Array clock to output delay C1 = 35 pF 6.4 7.9 10.0 15.0 ns Array clock high time 3.0 3.0 4.0 6.0 ns Array clock low time 3.0 3.0 4.0 6.0 ns Minimum pulse width for clear

(2) 2.5 3.0 4.0 6.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns

clock Minimum global clock period 6.7 8.2 10.0 13.0 ns Maximum internal global clock

(4) 149.3 122.0 100.0 76.9 MHz

frequency

46 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 33.EPM7160S External Timing Parameters (Part 2 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

ACNT

MAX

Minimum array clock period 6.7 8.2 10.0 13.0 ns Maximum internal array clock

(4) 149.3 122.0 100.0 76.9 MHz

frequency Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz

Table 34.EPM7160S Internal Timing Parameters (Part 1 of 2) Note (1)

Symbol Parame t er Conditio ns Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

Input pad and buffer delay 0.2 0.3 0.5 2.0 ns I/O input pad and buffer delay 0.2 0.3 0.5 2.0 ns Fast input delay 2.6 3.2 1.0 2.0 ns Shared expander delay 3.6 4.3 5.0 8.0 ns Parallel expander delay 1.0 1.3 0.8 1.0 ns Logic array delay 2.8 3.4 5.0 6.0 ns Logic control array delay 2.8 3.4 5.0 6.0 ns Internal output enable delay 0.7 0.9 2.0 3.0 ns Output buffer and pad delay C1 = 35 pF 0.4 0.5 1.5 4.0 ns Output buffer and pad delay C1 = 35 pF (6) 0.9 1.0 2.0 5.0 ns Output buffer and pad delay C1 = 35 pF 5.4 5.5 5.5 8.0 ns Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns Register setup time 1.0 1.2 2.0 4.0 ns Register hold time 1.6 2.0 3.0 4.0 ns Register setup time of fast

1.9 2.2 3.0 2.0 ns

input Register hold time of fast

0.6 0.8 0.5 1.0 ns

input Register delay 1.3 1.6 2.0 1.0 ns Combinatorial delay 1.0 1.3 2.0 1.0 ns Array clock delay 2.9 3.5 5.0 6.0 ns Register enable time 2.8 3.4 5.0 6.0 ns Global control delay 2.0 2.4 1.0 1.0 ns Register preset time 2.4 3.0 3.0 4.0 ns

Altera Corporation 47

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 34. EPM7160S Int ernal Timing Parameters (Part 2 of 2) Note (1)

Symbol P ara me ter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

CLR

PIA

LPA

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14 . See Figure 1 3 for more

(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t

(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

(8) The t

information on switching waveforms.

parameter must be added to this minimum width if the clear or reset signal incorporates the t path.

parameter into the signal

LAD

LPA

parameter applies for both global and array clocking.

values repr esent the highest fr eq uency for pi pelined data.

MAX

= 3.3 V ± 10% for commercial and industrial use.

CCIO

these values are spec i fied for a PIA fan-out of one LA B (16 macrocells). For eac h add it ional LAB fan-out in thes e devices, add an addition al 0. 1 n s to th e PI A ti mi ng v alu e.

parameter must be added to the t

LPA

running in the low-power mode.

LAD

, t

LAC

, tIC, tEN, t

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

Tables 35 and 36 show the EPM7192S AC operating conditions.

Table 35.EPM7192S External Timing Parameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

PD1

PD2

FSU

CO1

ASU

48 Altera Corporation

Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns I/O input to non-registered

output Global clock setup time 4.1 7.0 11.0 ns Global clock hold time 0.0 0.0 0.0 ns Global clock setup time of fast

input Global clock hold time of fast

input Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns Global clock high time 3.0 4.0 5.0 ns Global clock low time 3.0 4.0 5.0 ns Array clock setup time 1.0 2.0 4.0 ns

C1 = 35 pF 7.5 10.0 15.0 ns

3.0 3.0 3.0 ns

0.0 0.5 0.0 ns

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Table 35.EPM7192S External Timing Parameters (Part 2 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

MinMaxMinMaxMinMax

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Array clock hold time 1.8 3.0 4.0 ns Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns Array clock high time 3.0 4.0 6.0 ns Array clock low time 3.0 4.0 6.0 ns Minimum pulse width for clear

(2) 3.0 4.0 6.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 ns

clock Minimum global clock period 8.0 10.0 13.0 ns Maximum internal global clock

(4) 125.0 100.0 76.9 MHz

frequency Minimum array clock period 8.0 10.0 13.0 ns Maximum internal array clock

(4) 125.0 100.0 76.9 MHz

frequency Maximum clock frequency (5) 166.7 125.0 100.0 M Hz

Table 36.EPM7192S Internal Timing Parameters (Part 1 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

Altera Corporation 49

Input pad and buffer delay 0.3 0.5 2.0 ns I/O input pad and buffer delay 0.3 0.5 2.0 ns Fast input delay 3.2 1.0 2.0 ns Shared expander delay 4.2 5.0 8.0 ns Parallel expander delay 1.2 0.8 1.0 ns Logic array delay 3.1 5.0 6.0 ns Logic control array delay 3.1 5.0 6.0 ns Internal output enable delay 0.9 2.0 3.0 ns Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns Output buffer and pad delay C1 = 35 pF 5.5 5.5 7.0 ns Output buffer enable delay C1 = 35 pF 4.0 5 .0 6.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns Output buffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns Register setup time 1.1 2.0 4.0 n s

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 36. EPM7192S Int ernal Timing Parameters (Part 2 of 2) Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14 . See Figure 1 3 for more

(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t

(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

(8) The t

2.3 3.0 2.0 ns

input Register hold time of fast

0.7 0.5 1.0 ns

input Register delay 1.4 2.0 1.0 ns Combinatorial delay 1.2 2.0 1.0 ns Array clock delay 3.2 5.0 6.0 ns Register enable time 3.1 5.0 6.0 ns Global control delay 2.5 1.0 1.0 ns Register preset time 2.7 3.0 4.0 ns Register clear time 2.7 3.0 4.0 ns PIA delay (7) 2.4 1.0 2.0 ns Low-power adder (8) 10.0 11.0 13.0 ns

information on switching waveforms.

parameter must be added to this minimum width if the clear or reset signal incorporates the t path.

parameter into the signal

LAD

LPA

parameter applies for both global and array clocking.

values repr esent the highest fr eq uency for pi pelined data.

MAX

= 3.3 V ± 10% for commercial and industrial use.

CCIO

these values are spec i fied for a PIA fan-out of one LA B (16 macrocells). For eac h add it ional LAB fan-out in thes e devices, add an addition al 0. 1 n s to th e PI A ti mi ng v alu e.

parameter must be added to the t

LPA

running in the low-power mode.

LAD

, t

LAC

, tIC, tEN, t

SEXP

, t

ACL

, and t

parameters for macrocells

CPPW

50 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Tables 37 and 38 show the EPM7256S AC oper ati ng condit ions .

Table 37. EPM7256S Exte rnal Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

MinMaxMinMaxMinMax

PD1

PD2

FSU

CO1

ASU

ACO1

ACH

ACL

CPPW

ODH

CNT

ACNT

MAX

Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns I/O input to non-registered

C1 = 35 pF 7.5 10.0 15.0 ns

output Global clock setup time 3.9 7.0 11.0 ns Global clock hold time 0.0 0.0 0.0 ns Global clock setup time of fast

3.0 3.0 3.0 ns

input Global clock hold time of fast

0.0 0.5 0.0 ns

input Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns Global clock high time 3.0 4.0 5.0 ns Global clock low time 3.0 4.0 5.0 ns Array clock setup time 0.8 2.0 4.0 ns Array clock hold time 1.9 3.0 4.0 ns Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns Array clock high time 3.0 4.0 6.0 ns Array clock low time 3.0 4.0 6.0 ns Minimum pulse width for clear

(2) 3.0 4.0 6.0 ns

and preset Output data hold time after

C1 = 35 pF (3) 1.0 1.0 1.0 ns

clock Minimum global clock period 7.8 10.0 13.0 ns Maximum internal global clock

(4) 128.2 100.0 76.9 MHz

frequency Minimum array clock period 7.8 10.0 13.0 ns Maximum internal array clock

(4) 128.2 100.0 76.9 MHz

frequency Maximum clock frequency (5) 166.7 125.0 100.0 M Hz

Altera Corporation 51

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 38. EPM7256S Int ernal Timing Parameters Note (1)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

FIN

SEXP

PEXP

LAD

LAC

IOE

OD1

OD2

OD3

ZX1

ZX2

ZX3

FSU

COMB

GLOB

PRE

CLR

PIA

LPA

Input pad and buffer delay 0.3 0.5 2.0 ns I/O input pad and buffer delay 0.3 0.5 2.0 ns Fast input delay 3.4 1.0 2.0 ns Shared expander delay 3.9 5.0 8.0 ns Parallel expander delay 1.1 0.8 1.0 ns Logic array delay 2.6 5.0 6.0 ns Logic control array delay 2.6 5.0 6.0 ns Internal output enable delay 0.8 2.0 3.0 ns Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns Output buffer and pad delay C1 = 35 pF 5.5 5.5 8.0 ns Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns Output buffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns Register setup time 1.1 2.0 4.0 ns Register hold time 1.6 3.0 4.0 ns Register setup time of fast

2.4 3.0 2.0 ns

input Register hold time of fast

0.6 0.5 1.0 ns

input Register delay 1.1 2.0 1.0 ns Combinatorial delay 1.1 2.0 1.0 ns Array clock delay 2.9 5.0 6.0 ns Register enable time 2.6 5.0 6.0 ns Global control delay 2.8 1.0 1.0 ns Register preset time 2.7 3.0 4.0 ns Register clear time 2.7 3.0 4.0 ns PIA delay (7) 3.0 1.0 2.0 ns Low-power adder (8) 10.0 11.0 13.0 ns

52 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Notes to tables:

(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more

information on switching waveforms.

(2) This minimum pulse width for p reset and cl ear applies fo r both global cle ar and arra y controls. The t

must be added to this minimum width if the clear or reset signal incorporates the t path.

(3) This par a meter is a guideline that is s ample-teste d only and is ba s ed o n extensive de v ic e c haracteri za t ion. This

parameter applies for both global and array clocking.

(4) These paramete rs are measu r ed with a 16-bit loadable, enab le d , up/ d own counter program med into each LAB. (5) The f (6) Operating conditions: V (7) For EPM7064S-5, E PM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, an d EPM7256S-7 devices,

these values ar e specified for a PIA fan-out of on e L A B (16 macrocells). For ea c h add itional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value.

(8) The t

running in th e low-power mod e.

values repres en t th e highest frequency for pipeline d data.

MAX

parameter must be added to the t

LPA

= 3.3 V ± 10% for commercial and industrial use.

CCIO

, t

LAD

, tIC, tEN, t

LAC

SEXP

, t

, and t

ACL

parameter into the signal

LAD

parameters for macrocells

CPPW

parameter

LPA

Power Consumption

Supply power (P) versus frequency (f

in MHz) for MAX 7000 dev ices

MAX

is calculated with the following equation:

P = P

INT

= I

× VCC + P

INT

+ P

The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in

Application Note 74 (Evaluating Power for Altera Devices).

The I

value, which depends on the switching frequency and the

CCINT

application logic, is calculated with the following equation:

CCINT

A × MC

+ B × (MC

TON

DEV

– MC

) + C × MC

TON

USED

× f

MAX

× tog

The parameters in this equation are shown below:

= Number of ma crocells with the Turbo Bit op tion turned on,

TON

as reported in the MAX+PLUS II Report File (.rpt)

MC MC

= Number of macrocells in the device

DEV

= Total number of macrocells in the design, as reported

USED

in the MAX+PLUS II Report File (.rpt)

MAX

tog

= Highest clock frequency to the device = Average ratio of logic cells toggling at each clock

(typicall y 0.125)

A, B, C = Constants, shown in Table 39

Altera Corporation 53

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 39. MAX 7000 I

Equation Constants

Device A B C

EPM7032 1.87 0.52 0.144 EPM7064 1.63 0.74 0.144 EPM7096 1.63 0.74 0.144 EPM7128E 1.17 0.54 0.096 EPM7160E 1.17 0.54 0.096 EPM7192E 1.17 0.54 0.096 EPM7256E 1.17 0.54 0.096 EPM7032S 0.93 0.40 0.040 EPM7064S 0.93 0.40 0.040 EPM7128S 0.93 0.40 0.040 EPM7160S 0.93 0.40 0.040 EPM7192S 0.93 0.40 0.040 EPM7256S 0.93 0.40 0.040

This calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual I

values should be verifie d during

operation because this measurement is sensitive to the actual pattern in the device and the en vironmen tal operating conditions.

54 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

Figure 14 shows typical supply current versus frequency for

MAX 7000 devices.

Figure 14 . ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2)

EPM7032

Typical I

Active (mA)

EPM7096

Typical I

Active (mA)

VCC = 5.0 V

180

Room T emperature

140

100

VCC = 5.0 V

Room T emperature

60.2 MHz

Low Power

Frequency (MHz)

55.5 MHz

Low Power

151.5 MHz

High Speed

200100 150

125 MHz

High Speed

EPM7064

Typical I

Active (mA)

300

Room T emperature

200

100

= 5.0 V

High Speed

60.2 MHz

Low Power

Frequency (MHz)

151.5 MHz

200100 150

Frequency (MHz)

Altera Corporation 55

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)

EPM7128E

Typical I

Active (mA)

500

VCC = 5.0 V Room T emperature

400

300

200

100

125 MHz

High Speed

55.5 MHz

Low Power

EPM7160E

Typical I

Active (mA)

500

VCC = 5.0 V Room T emperature

400

300

200

100

100 MHz

High Speed

47.6 MHz

Low Power

EPM7192E

Typical I

Active (mA)

500

VCC = 5.0 V Room T emperature

400

300

200

100

25 50 100 125

50 100

Frequency (MHz)

43.5 MHz

Low Power

Frequency (MHz)

150 200

High Speed

90.9 MHz

EPM7256E

Typical I

Active (mA)

750

VCC = 5.0 V Room T emperature

600

450

300

150

50 100

150 200

Frequency (MHz)

90.9 MHz

High Speed

43.4 MHz

Low Power

25 50 100

Frequency (MHz)

125

56 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

EPM7032S

EPM7064S

T A

Figure 15 shows typical supply current versus frequency for MAX 7000S

devices.

Figure 15 . ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2)

ypical I

ctive (mA)

PM7128S

ypical I

ctive (mA)

280

240

200

160

VCC = 5.0 V Room T emperature

58.8 MHz

Low Power

50 100

Frequency (MHz)

VCC = 5.0 V Room T emperature

56.2 MHz

Low Power

50 100

Frequency (MHz)

142.9 MHz

High Speed

150

147.1 MHz

High Speed

150

200

Typical I Active (mA)

EPM7160S

Typical I

Active (mA)

VCC = 5.0 V

120

Room T emperature

100

56.5 MHz

Low Power

50 100

High Speed

150

175.4 MHz

200

Frequency (MHz)

VCC = 5.0 V Room T emperature

300

240

180

120

56.5 MHz

Low Power

50 100

149.3 MHz

High Speed

150

200

Frequency (MHz)

Altera Corporation 57

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2)

EPM7192S

EPM7256S

Typical I

Active (mA)

Device Pin-Outs

300

240

180

120

400

200

100

VCC = 5.0 V Room T emperature

56.2 MHz

Low Power

50 75

Frequency (MHz)

= 5.0 V

Room T emperature

55.6 MHz

Low Power

50 75

Frequency (MHz)

High Speed

100

125.0 MHz

125

Typical I

Active (mA)

See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information.

High Speed

100

128.2 MHz

125

58 Altera Corporation

Figures 16 through 22 show the package pin-out diagrams for MAX 7000

)

devices.

Figure 16 . 44-Pin Package Pin-Out Diagram

Package outlines not drawn to scale.

I/O

VCC

INPUT/OE2/(GCLK2) (1)INPUT/GCLRn

INPUT/OE1

INPUT//GCLK1

GND

I/O

Pin 1

(2) I/O/(TDI)

I/O I/O

GND

I/O I/O

(2) I/O/(TMS)

I/O

VCC

I/O I/O

Pin 12 Pin 23

I/O

EPM7032

I/O

VCC

GND

44-Pin PQFP

Pin 34

I/O

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

INPUT/OE2/(GCLK2) (1)

I/O

VCC

INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

6 5 4 3 2 1 44 43 42 41 40

I/O I/O/(TDO) (2) I/O I/O VCC I/O I/O I/O/(TCK) (2) I/O GND I/O

(2) I/O/(TDI)

GND

(2) I/O/(TMS)

VCC

7 8

I/O

10 11

I/O

13 14

I/O

15 16

I/O

18 19 20 21 22 23 24 25 26 27 28

I/O

EPM7032 EPM7032S EPM7064 EPM7064S

I/O

VCC

GND

39 38 37 36 35 34 33 32 31 30 29

I/O

44-Pin PLCC

I/O I/O/(TDO) (2 I/O I/O VCC I/O I/O I/O/(TCK) (2) I/O GND I/O

I/O

VCC

INPUT/OE2/(GCLK2) (1)

INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

Pin 1

(2) I/O/(TDI)

I/O I/O

GND

I/O I/O

(2) I/O/(TMS)

I/O

VCC

I/O I/O

Pin 12 Pin 23

I/O

EPM7032 EPM7032S EPM7064 EPM7064S

I/O

VCC

GND

I/O

Pin 34

I/O I/O/(TDO) (2) I/O I/O VCC I/O I/O I/O/(TCK) (2) I/O GND I/O

I/O

44-Pin TQFP

Notes:

(1) The pin functions shown in pare nth esi s ar e on ly avail ab le in M AX 7000E and MAX 7000S dev ices. (2) JTAG ports are availa ble in M AX 7000S devices only.

Altera Corporation 59

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure 17. 68-Pin Package Pin-Out Diagram

Package outlines not drawn to scale.

I/O

987654321

I/O

VCCIO

(2) I/O/(TDI)

I/O

GND

I/O

VCCIO

GND

19 20

I/O

21 22

I/O

2728293031323334353637383940414243

I/O

(2) I/O/(TMS)

Notes:

(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX

7000S devices.

(2) JTAG ports are av ail abl e in M A X 7000S devices only.

I/O

GND

I/O

VCCINT

EPM7064 EPM7096

I/O

VCCIO

68-Pin PLCC

INPUT/OE2/(GCLK2) (1)INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

68676665646362

I/O

GND

VCCINT

I/O

VCCIO

I/O

GND

I/O/(TDO) (2)

I/O

VCCIO

I/O

I/O/(TCK) (2)

I/O

GND

I/O

VCCIO

60 Altera Corporation

Figure 18 . 84-Pin Package Pin-Out Diagram

Package outline not drawn to scale.

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

(2)

(3)

VCCIO

I/O/(TDI)

GND

I/O/(TMS)

VCCIO

GND

(1)

I/O

GND

I/O

VCCINT

I/O

VCCIO

INPUT/OE2/(GCLK2)

EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S

I/O

(1)

GND

I/O

987654321

I/O

12 13 14

I/O

18 19

I/O

22 23 24

I/O

26 27

I/O

333435363738394041424344454647484950515253

I/O

INPUT/GLCRn

VCCINT

(1)

VCCIO

INPUT/OE1

INPUT/GCLK1

848382818079787776

I/O

GND

I/O

(1)

GND

I/O

GND

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

I/O

VCCIO

I/O/(TDO) I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/(TCK) I/O I/O GND I/O I/O I/O I/O I/O

(3)

84-Pin PLCC

Notes:

(1) Pins 6, 39, 46, and 79 are no-con n ect (N. C. ) pins on EPM7096, EPM7160E, and EPM7160S devices. (2) The pin functions shown in pare nth esi s ar e on ly avail ab le in M AX 7000E and MAX 7000S dev ices. (3) JTAG ports are availa ble in M AX 7000S devices only.

Altera Corporation 61

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure 19. 100-Pin Package Pin-Out Diagram

Package outline not drawn to scale.

Pin 1

Pin 81

Pin 1

Pin 7

EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E

Pin 31

Pin 51

100-Pin PQFP

Figure 20. 160-Pin Package Pin-Out Diagram

Package outline not drawn to scale.

R P N M L K J H G F E D C B A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

EPM7192E

Bottom

View

160-Pin PGA 160-Pin PQFP

Pin 1

Pin 41

Pin 26

EPM7064S EPM7128S EPM7160S

Pin 51

100-Pin TQFP

Pin 12

EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E

Pin 81

62 Altera Corporation

Figure 21. 192-Pin Package Pin-O ut Diagram

Package outline not drawn to scale.

U T R P N M L K J H G F E D C B A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Figure 22. 208-Pin Package Pin-O ut Diagram

Package outline not drawn to scale.

Pin 1 Pin 15

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

EPM7256E

Bottom

View

192-Pin PGA

EPM7256E EPM7256S

Pin 53

Pin 10

208-Pin PQFP/RQFP

Altera Corporation 63

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Revision History

The information contained in the MAX 7000 Programmable Logic Devic e Family Data Sheet version 6.6 supersedes information published in previous versions. The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.6:

Version 6.6

The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.6:

■ Added Tables 6 through 8.

Version 6.5

The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5:

■ Updated text on page 16.

Version 6.4

The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.4:

■ Added Note (5) on page28.

Version 6.3

The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.3:

■ Updated the “Open-Drain Output Opt io n (MA X 70 00 S Devices

Only)” section on page 20.

64 Altera Corporation

Notes:

Altera Corporation 65

e s a

g o

1 S ( h

(

MAX 7000 Programmabl e Log ic Dev ice Fam ily Data Sheet

01 Innovation Drive

an Jose, CA 95134

408) 544-7000 ttp://www.altera.com

pplications Hotline:

800) 800-EPLD

ustomer Marketi ng:

408) 544-7104

iterature Services:

it_req@altera.com

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, th stylized Altera logo, specific device designations, and all other words and logos that are identified a trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Alter Corporation in the U.S. and other countries. All other product or service names are the property of the respectiv e holders. Alte ra products are p rotected under numerous U.S. an d foreign paten ts and pendin applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products t current specifications in accordance with Alter a's standar d warr anty, but rese rv es the rig ht to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any inf ormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

66 Altera Corporation

ALTERA MAX 7000 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual