ALTERA MAX7000 DATA SHEET

®

MAX 7000

Programmable Logic

Device Family

December 2002, ver. 6.5 Data Sheet

Features...

■ High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX

■ 5.0-V in-system programmability (ISP) through the built-in

®

architectu re

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

■ Built-in JTAG boundary-scan test (BST) circuitry in MAX

7000S

devices with 128 or more macrocells

■ Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see Tables 1 and 2)

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

■ PCI-compliant devices available

f

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devi ces, see th e MAX 7000 A Programma ble Logi c Device F amily

Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.

Table 1. MAX 7000 Device Features

Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E

Usable
gates

Macrocells 32 64 96 128 160 192 256
Logic array

blocks
Maximum

user I/O pins

(ns) 6 6 7. 5 7.5 10 12 12

t

PD

(ns)5566777

t

SU

t

(ns)2.5 2.533333

FSU

t

(ns)444.54.5566

CO1

f

(MHz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9

CNT

600 1,250 1,800 2,500 3,200 3,750 5,000

2468101216

36 68 76 100 104 124 164

Altera Corporation 1

DS-MAX7000-6.5

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Table 2.MAX 7000S Device Features

Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

Usable gates 600 1,250 2,500 3,200 3,750 5,000
Macrocells 32 64 128 160 192 256
Logic array

blocks
Maximum

user I/O pins

(ns)55667.57.5

t

PD

t

(ns) 2.9 2.9 3.4 3.4 4.1 3.9

SU

(ns) 2.5 2.5 2.5 2.5 3 3

t

FSU

t

(ns) 3.2 3.2 4 3.9 4.7 4.7

CO1

f

(MHz) 175.4 175.4 147.1 149.3 125.0 128.2

CNT

2 4 8 10 12 16

36 68 100 104 124 164

...and More Features

■ Open-drain output option in MAX 7000S devices

■ Programmable macrocell flipflops with individual clear, preset,

clock, and clock enable controls

■ Programmable power-saving mode for a reduction o f over 50% in

each macrocell

■ Configurable expander product-term distribution, allowing up to

32 product terms per macrocell

■ 44 to 208 pins avail ab le in pla stic J-lead chip carr ier (P L CC), ceramic

pin-grid array (PGA), plastic quad flat pack (PQFP), p ower q uad flat
pack (RQFP), and 1.0-mm th in quad flat pack (TQFP) pack ages

■ Programmable security bit for protection of proprietary designs

■ 3.3-V or 5.0-V operation

– MultiVolt

TM

I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (M ultiVolt I/O ope ration is
not avai lable in 44 -pin packages)

– Pin compatible with low-voltage MAX 7000A and MAX 7000B

devices

■ Enhanc ed features availab le in MAX 7000 E and MAX 70 00S devices

– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O

pin to macrocell registers

– Programmable output slew-rate control

■ Software design s upport and au tomatic plac e-and-ro ute provided by

Altera’s devel opment system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations

2 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

■ Additional design entry and simula tion support pr ovide d by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfa ces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBes t

■ Programming support

– Altera’s Master Programming Unit (MPU) and programming

hardware from third-party manufacturers program all
MAX 7000 devices

TM

–The BitBlaster

parallel port download cable, and MasterBlaster

serial download cable, By te Bl as terMVTM

TM

serial/universal serial bus (USB) download cable program MAX
7000S devices

General Description

The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,

-7, and -10 spe ed g ra d es as we l l as MAX7000 and MAX7000E devices in

-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3
for available speed grades.

Table 3.MAX 7000 Speed Grades

Device Speed Grade

-5 -6 -7 -10P -10 -12P -12 -15 -15T -20

EPM7032
EPM7032S
EPM7064
EPM7064S
EPM7096
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S

vvv v

vvv v

vv v vvv

vvvvv

vvvv
vvvvvv

vv v v

vv vv v

vv v v

vv v

vv v

vvv v

vvv v

Altera Corporation 3

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

The MAX 7000E devices—including the EPM7128E, EPM7160E,
EPM7192E, and EPM7256E de v ices —have several enhanced feature s:
additional global clocking, additional output enable controls, enhanced
interconnect resources, fast input registe rs, and a pr ogrammable slew
rate.

In-system programmable MAX 7000 devices—called MAX7000S
devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S,
EPM7192S, and EPM7256S devices. MAX7000S devices have the
enhanced fea tures of MAX7000E device s as well as JTAG BST circu itry in
devices with 128 or more macrocells, ISP, and an open-drain output
option. See Table 4.

Table 4. MAX 7000 Device Features

Feature EPM7032

EPM7064
EPM7096

ISP via JTAG interface
JTAG BST circuitry
Open-drain output option
Fast input registers
Six global output enables
Two global clocks
Slew-rate control
MultiVolt interface (2)
Programmable register
Parallel expanders
Shared expanders
Power - saving mode
Security bit
PCI-compliant devices avai lable

Notes:

(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only.
(2) The Mul t iVolt I/O inter face is not av ailable in 44-p in packages.

vvv
vvv
vvv
vvv
vvv
vvv
vvv

All

MAX 7000E

Devices

All

MAX 7000S

Devices

v
v(1)

v
vv
vv
vv
vv

4 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide ran ge of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP package s. See Table 5.

Table 5. MAX 7000 Maximum User I/O Pins Note (1)

Device 44-

PLCC

EPM7032 36 36 36
EPM7032S 36 36
EPM7064 36 36 52 68 68
EPM7064S 36 36 68 68
EPM7096 52 64 76
EPM7128E 68 84 100
EPM7128S 68 84 84 (2) 100
EPM7160E 64 84 104
EPM7160S 64 84 (2) 104
EPM7192E 124 124
EPM7192S 124
EPM7256E 132 (2) 164 164
EPM7256S 164 (2) 164

Notes:

(1) When the JTAG inte r face in M AX 7000S devices is used for either boundary-scan t estin g o r for IS P, four I/O pins

become JTAG pins.

(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see

the Operating Requirements for Altera Devices Data Sheet.

Pin

44­Pin

PQFP

44­Pin

TQFP

68­Pin

PLCC

84­Pin

PLCC

100-

Pin

PQFP

100-

Pin

TQFP

160-

Pin

PQFP

160-

Pin

PGA

192-

Pin

PGA

208-

Pin

PQFP

208-

Pin

RQFP

MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independe nt c omb inat orial and se qu ent ial l ogic func tions . T he
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.

Altera Corporation 5

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

MAX 700 0 d evices c ontain from 32 to 256 macrocell s that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with ind epend ently prog rammabl e clock, clock enable, cle ar, an d
preset functions. To bu ild compl ex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high­speed parallel expand er product terms to provide up to 32 product terms
per macrocell.

The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals are switc hing. The output drive rs of all M AX 7000 devices (except
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.

The MAX 7000 family is supported byAltera deve lopment systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Descr ipt i on Langu age (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry­standard PC- and UNIX-workst ation-based EDA tools . The software run s
on Windows-based PC s, as well a s Sun SPARCsta tion, and H P 9000 Series
700/800 workstations.

f

Functional Description

6 Altera Corporation

For more information on development tools, see the MAX+PLUS II

Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System & Software Data Sheet.

The MAX 7000 architecture includes the following elements:

■ Logic array blo cks

■ Macrocells

■ Expander product terms (shareable and parallel)

■ Programmable interconnect arra y

■ I/O control blocks

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

The MAX 7000 architecture includes four dedicated inputs that can
be used as general-purpose inputs or as high-speed, global control
signals (clock, clear, and two output enable signals) for each
macrocell and I/O pin. Figure1 shows the ar chite cture of EPM7032 ,
EPM7064, and EPM7096 devic es .

Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram

INPUT/GLCK1
INPUT/GCLRn
INPUT/OE1
INPUT/OE2

LAB A LAB B

8 to 16
I/O pins

8 to 16
I/O pins

I/O

Control

Block

I/O

Control

Block

8 to 16

8 to 16

LAB C

Macrocells

1 to 16

Macrocells

33 to 48

16

8 to 16

16

8 to 16

LAB D

8 to 16

8 to 16

I/O

Control

Block

I/O

Control

Block

8 to 16
I/O pins

8 to 16
I/O pins

36

36

PIA

36

36

16

8 to 16

16

8 to 16

Macrocells

17 to 32

Macrocells

49 to 64

Altera Corporation 7

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

I

s

s

Figure2 shows the architecture of MAX 7000E and MAX 7000S devices.

Figure 2. MAX 7000E & MAX 7000S Device Block Diagram

INPUT/GCLK1

NPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 Output Enables

6 Output Enables

Macrocells

17 to 32

Macrocells

49 to 64

LAB B

LAB D

6 to16

6 to16

6 to16

6 to16

I/O

Control

Block

I/O

Control

Block

6 to 16 I/O Pin

6

6 to 16 I/O Pin

6

LAB A

6 to16

6 to16

6 to 16 I/O Pins

6 to 16 I/O Pins

I/O

Control

Block

I/O

Control

Block

6

6 to16

6 to16

6

LAB C

Macrocells

1 to 16

Macrocells

33 to 48

36 36

16

6 to16

36 36

16

6 to16

PIA

16

6 to16

16

6 to16

Logic Array Blocks

The MAX 7000 device architecture is based on the linking of high­performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macr ocell array s, as shown in Figures 1 and 2.
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.

8 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

-

er

S

M

x

f

er

y

a

(

)

S

Each LAB is fed by the following signals:

■ 36 signals from the PIA that are used for general logic inputs

■ Global controls that are used for secondary register functions

■ Direct input paths from I/O pins to the registers that are used

for fast setup times for MAX 7000E and MAX 7000S devices

Macrocells

The MAX 7000 macrocell ca n be individu ally configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devic es i s s hown in Figure 3.

Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell

Logic Arra

Product

elect

atri

rallel Logic

Expanders

from other

macrocells

Global

Clear

Clear

Select

Global
Clocks

2

VCC

Clock/

Enable

Select

Fast Input
Select

PRN

D/T Q

ENA

CLRN

Programmable
Register

Register

Bypass

From
I/O pin

To I/O
Control
Block

to PIA

36 Signals

rom PIA

16 Expander

Product

hared Logic

Expanders

ms

Altera Corporation 9

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Figure4 shows a MAX 7000E and MAX 7000S device macrocell.

Figure 4. MAX 7000E & MAX 7000S Device Macrocell

Logic Array

Product-

Term
Select
Matrix

Parallel Logic
Expanders
(from other
macrocells)

Global

Clear

Clear
Select

Global
Clocks

2

VCC

Clock/

Enable

Select

Fast Input
Select

PRN

D/T Q

ENA

CLRN

Programmable
Register

Register

Bypass

from
I/O pin

to I/O
Control
Block

36 Signals

from PIA

16 Expander

Product T erms

Shared Logic
Expanders

to PIA

Combinatorial logic is implemented in the logic array, which provides
five product terms per macroce ll. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the ma crocell’s register clear, preset, cl ock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:

■ Sharea ble expanders, which are inverted product terms that are fed

back into the logic array

■ Parallel expanders, which are product terms borrowed from adjacent

macrocells

The Altera developm en t sys te m aut omatically optimizes pro du ct-term
allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with prog rammable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.

10 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Fam ily Data Sheet

Each programmable regist er can be clock ed in th ree differe nt mo des:

■ By a global clock signal. This mode achieves th e fastest clock-to -

output performance.

■ By a glo b al clock signal and ena b led by an active-high clock

enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.

■ By an array clock implemented with a product term. In this

mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.

In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin, GCLK1, as shown in Figure 1.
In MAX 70 00E a n d M A X 7000S devices, two glob al cl ock signals ar e
available. As show n in Figure 2, these global clock signals can be the
true or the complement of either of the global clock pins, GCLK1 or
GCLK2.

Each register also suppor ts asynchr onous prese t and clear functions.
As shown in Figures 3 and 4, the product -term select matrix al locates
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control c an be obta ined by inve rting t he signal within t he
logic array. In addition, each regist er c l ea r function can be
individually driven by the active-low dedica te d global clea r pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.

All MAX 7000E and MAX 70 00S I/O pins h ave a f a st input path to a
macrocell registe r . T his ded ica te d pat h a llows a s ig nal to by pas s t he
PIA and combinatorial logic and be driven t o an input D flipflop w ith
an extremely fast (2.5 ns) input setup time.

Expander Product Terms

Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.

Altera Corporation 11

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

m

m

Shareable Expanders

Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (t
shareable expanders are used. Figure 5 shows how shareable exp an de r s
can feed multiple macrocells.

Figure 5. Shareable Expanders

Shareable expanders can be shared by any or all macrocells in an LAB.

) is incurred when

SEXP

Product-Term Select Matrix

Macrocell
Product-Ter
Logic

Macrocell
Product-Ter
Logic

36 Signals
from PIA

Parallel Expanders

16 Shared
Expanders

Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product te rms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.

12 Altera Corporation

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

From

The compile r can allocate up t o three sets of up to f iv e p ar al l el ex pa nd ers
automatically to the macrocells that require additional product terms.
Each set of five parallel expanders incurs a small, incremental timing
delay (t

). For example, if a macrocell requires 14 product terms, the

PEXP

Compiler use s the five dedicated pr oduct terms within the macroce ll a nd
allocates two se ts of parallel expande rs; the first set includ e s fiv e p rodu ct
terms and th e secon d set includ es fo ur product terms , inc reasing the to tal
delay by 2 × t

PEXP

.

Two groups of 8 macrocells within each LAB (e.g., macrocells
1 through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower­numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 6 shows how parallel ex pa nd er s ca n be
borrowed from a neighboring macrocell.

Figure 6. Parallel Expanders

Unused product terms in a macrocell can be allocated to a neighboring macrocell.

Previous

Macrocell

Preset

36 Signals

from PIA

16 Shared

Expanders

Product-

Term

Select

Matrix

Product-

Term
Select
Matrix

Clock
Clear

Preset

Clock
Clear

To Next

Macrocell

Macrocell
Product­Term Logic

Macrocell
Product­Term Logic

Altera Corporation 13

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Programmable Int er co nnec t A rray

Logic is routed between LABs via the programmable interconnect array
(PIA). This global bus is a programmable path that connects any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
I/O pins, and macrocell outputs feed the PIA, which makes the signals
available thro ugh out t he e ntire device. Only the sig nals required by eac h
LAB are actually routed from the PIA into the LAB. Figure 7 shows how
the PIA signals are routed into the LAB. An EEPROM cell controls one
input to a 2-input AND gate, which selects a PIA signal to drive into the
LAB.

Figure 7. PIA Ro ut ing

PIA

Signals

To LAB

While the routing dela ys of cha nne l-b ased r outi ng sche me s in ma sk ed or
FPGAs are cumulativ e, vari able, and path-d epen dent, the MAX 7000 PI A
has a fixed delay. The PIA thus eliminates skew between signals and
makes timing performance easy to predict.

I/O Control Blocks

The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
control block for the MAX 7000 family. The I/O control block of EPM7032,
EPM7064, and EP M7096 device s has two global outp ut enable signal s that
are driven by t wo dedicate d active-low ou tput ena ble pins ( OE1 and OE2).
The I/O control block of MAX 7000E and MAX 7000S devices has six
global output enab le signa ls that are d riven by the true or complemen t of
two output enable sig na ls, a s ubse t of t he I /O pin s, o r a sub set of the I /O
macrocells.

14 Altera Corporation

. Figure 8 shows the I/O

CC

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

E

M

F

Figure 8. I/O Control Block of MAX 7000 Devices

PM7032, EPM7064 & EPM7096 Devices

VCC

OE1
OE2

GND

rom Macrocell

AX 7000E & MAX 7000S Devices

To PIA

Six Global Output Enable Signals

PIA

VCC

To Other I/O Pins

From
Macrocell

Fast Input to
Macrocell
Register

To PIA

GND

Open-Drain Output (1)
Slew-Rate Control

Note:

(1) The open- d r ain o utput option is available only in MAX 700 0S d ev i c e s.

Altera Corporation 15

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-sta te buffer cont r ol is con ne cted to V
enabled.

The MAX 7000 architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.

, the output is

CC

In-System
Programma­bility (ISP)

MAX 7000S devices are in-system programmable via an
industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE
Std. 1149.1-1990). ISP allows quick, efficient iterations during design
development and debugging cycles. The MAX 7000S architecture
internally generates the high programming voltage required to program
EEPROM cells, allowing in-syst em programming wit h only a sing le 5.0 V
power supply. Du ring in-system pr ogramming, the I /O pins are tri- stated
and pulled-up to eliminate boa rd conflicts. The pull-up value is nomi nally
50 k¾.

ISP simplifies the man ufacturing flow by allowi ng devices to be mou nted
on a printed circuit board with standard in-circuit test equipment before
they are programmed. MAX 7000S devices can be programmed by
downloading the information via in-circuit teste rs (ICT), embedde d
processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster,
BitBlaster download cables. (The ByteBlaster cable is obsolete and is
replaced by the ByteBlast erMV cable, which can program and config ure

2.5-V, 3 .3-V, and 5.0-V dev ices.) Pr ogramming the dev ices afte r they are
placed on the board eliminates lead damage on high-p in-cou nt pa ck ages
(e.g., QFP packages) due to device handling and allows devices to be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.

In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support a n adaptive alg or ithm, Altera o ff ers d evic es te st ed w i th a
constant algorithm. Devices tested to the constant algorithm have an “F”
suffix in the ordering code.

TM

The Jam
used to program MAX 7000S devices with in-circuit testers, PCs, or
embedded processor.

16 Altera Corporation

Standard Test and Programming Lang uage (STAPL) can be

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

f

Programmable Speed/Power Control

Output Configuration

For more information on using the Jam language, see Application Note 88

(Using the Jam Language for ISP & ICR via an Embedded Processor).

The ISP circuitr y in MAX 7000S devices is compa tible wit h IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.

MAX 7000 devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic a pplications require only a s mall fraction of all gates to
operate at maximum frequency.

The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo Bit
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate a t reduced powe r. Macrocells tha t run at low
power incur a nominal timing delay adder (t

, and t

t

EN

MAX 7000 device outputs can be programmed to meet a variety of
system- level requ irements.

SEXP

, t

ACL

, and t

CPPW

parameters.

) for the t

LPA

TM

option turned on)

, t

LAC

, tIC,

LAD

MultiVolt I/O Inter fac e

MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O
interface feature, which allows MAX 7000 devices to interface with
systems that have differi ng suppl y voltages . The 5.0-V devices in all
packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).

The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V V
are therefore compatible with both 3.3-V and 5.0-V input s.

The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power
supply, depend ing on the outpu t requireme nts. When the VCCIO pins ar e
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When V

3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with V
timing delay o f t

Altera Corporation 17

level, input voltage t hresholds ar e at TTL level s, and

CCINT

is connected to a 3.3-V supply, the output high is

CCIO

levels lower than 4.75 V incur a nominally greater

CCIO

instead of t

OD2

OD1

.

MAX 7000 Programm ab le Logic D evi ce F ami ly Data Sheet

Open-Drain Output Option (MAX 7000S Devic es Only )

MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.

By using an external 5.0-V pull-up resistor, output pins on MAX 7000S
devices can be set to meet 5.0-V CMOS input voltages. When V

3.3 V, setting the open drain option will turn off the output pull-up
transistor, allowing the external pull-up resistor to pull the output high
enough to meet 5.0-V CMOS input volt ages. Whe n V
the output drain option is not ne cessary becau se the pull-up transistor wil l
already turn off when the pin exceeds approximately 3.8 V, allowing the
external pull-up resistor to pull the output high enough to meet 5.0-V
CMOS input voltages.

Slew-Rate Control

The output buffer for each MAX 7000E and MAX 7000S I/O pin has an
adjustable output slew rate that can be configured for low-noise or high­speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the
Turbo Bit is turne d off, the sle w rate is set for low noi se perf orm a nce . F or
MAX 7000S devices, each I/O pin has an individual EEPROM bit that
controls the slew rate, allowing designers to specify the slew rate on a
pin-by-pin basis.

is 5.0 V , setting

CCIO

CCIO

is

Programming with External Hardware

f

f

18 Altera Corporation

MAX 7000 devices can be programme d on Windows-based PCs wi th the
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs a continuity
check to ensure adequate electrical contact between the adapter and the
device.

For more information, see the Altera Programming Hardware Data Sheet.

The Altera development system can use text- or waveform-format test
vectors created with the Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers ca n
perform functional testing to compare the functional behavior of a
MAX 7000 device with the results of simulation. Moreover, Data I/O, BP
Microsystems, and other programming hardware manufacturers also
provide programming support for Altera devices.

For more information, see the Programming Hardware Manufacturers.

MAX 7000 Programmabl e Log i c Dev ic e Family Data Sheet

IEEE Std.

1149.1 (JTAG)
Boundary-Scan
Support

MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.

1149.1-1990. Table 6 describes the JTAG instructions supported by the
MAX 7000 family. The pin-ou t tables (see the Alter a web site
(http://www.altera.com) or the Altera Digital Library for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.

Table 6. MAX 7000 JTAG Instructions

JTAG Instruction Devices Description

SAMPLE/PRELOAD EPM7128S

EPM7160S
EPM7192S
EPM7256S

EXTEST EPM7128S

EPM7160S
EPM7192S
EPM7256S

BYPASS EPM7032S

EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S

IDCODE EPM7032S

EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S

ISP Instructions EPM7032S

EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S

Allows a snapshot of signals at the dev ic e pins to be capt ured and
examined during normal dev ic e operation, and permits an initial dat a
pattern output at the device pins.

Allows the external circuit ry and board-level interconnection s to be
tested by forcing a test pattern at the ou tpu t pin s and capturing test
results at the input pins.

Places the 1-bit bypass register bet w een th e TDI and TDO pins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices durin g norm al dev ic e operation.

Selects the IDCODE regist er and places it between TDI and TDO,
allowing the IDCODE to be ser ially shift ed out of TDO.

These instructions are us ed wh en programming MAX 7000S devices
via the JTAG ports with the Maste rBlas t er, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) v ia an em bedded processor or test
equipment.

Altera Corporation 19