ALTERA MAX 3000A Service Manual
MAX 3000A
®
Programmable Logic
Device Family
September 2000, ver. 1.1 Data Sheet
High-performance, low-cost CMOS EEPROM-based programmable
Features...
■
logic devices (PLDs) built on a Multiple Array MatriX (MAX®)
architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built-in
■
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with
■
IEEE Std. 1149.1-1990
Enhanced ISP features:
■
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in-system programming
High-density PLDs ranging from 600 to 5,000 usable gates
■
4.5-ns pin-to-pin logic delays with counter frequencies of up to
■
227.3 MHz
MultiVoltTM I/O interface enabling the device core to run at 3.3 V,
■
while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic
levels
Pin counts ranging from 44 to 208 in a variety of thin quad flat pack
■
(TQFP), plastic quad flat pack (PQFP), and plastic J-lead chip carrier
(PLCC) packages
■
Hot-socketing support
Programmable interconnect array (PIA) continuous routing structure
■
for fast, predictable performance
PCI compatible
■
Bus-friendly architecture including programmable slew-rate control
■
■
Open-drain output option
Table 1. MAX 3000A Device Features
Feature EPM3032A EPM3064A EPM3128A EPM3256A
Usable gates 600 1,250 2,500 5,000
Macrocells 32 64 128 256
Logic array blocks 2 4 8 16
Maximum user I/O
pins
(ns) 4.5 4.5 5.0 5.5
t
PD
tSU (ns) 2.9 2.8 3.3 3.9
t
(ns) 3.0 3.1 3.4 3.5
CO1
f
(MHz) 227.3 222.2 192.3 172.4
CNT
Altera Corporation 1
A-DS-M3000A-01.1
34 66 96 158
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable macrocell flipflops with individual clear, preset,
...and More Features
■
clock, and clock enable controls
■
Programmable power-saving mode for a power reduction of over
50% in each macrocell
■
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■
Programmable security bit for protection of proprietary designs
■
Enhanced architectural features, including:
– 6 pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Programmable output slew-rate control
■
Software design support and automatic place-and-route provided by
the Altera® MAX+PLUS® II development system for Windows-based
PCs and Sun SPARCstations, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third-party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■
Programming support with the Altera master programming unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from third-party manufacturers and
any in-circuit tester that supports JamTM Standard Test and
Programming Language (STAPL) Files (
Files (
.jbc
), or Serial Vector Format Files (
.jam
), Jam STAPL Byte-Code
.svf
)
General Description
2 Altera Corporation
MAX 3000A devices are low-cost, high-performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM-based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG)
Specification, Revision 2.2
. See Table 2.
PCI Local Bus
MAX 3000A Programmable Logic Device Family Data Sheet
Table 2. MAX 3000A Speed Grades
Device Speed Grade
-4 -5 -6 -7 -10
EPM3032A
EPM3064A
EPM3128A
EPM3256A
Note:
(1) Contact Altera for up-to-date information on the availability of this speed grade.
vvv
vvv
vvv
v (1)
vv
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH, and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See Table 3.
Table 3. MAX 3000A Maximum User I/O Pins
Device 44-Pin
PLCC
EPM3032A 34 34
EPM3064A 34 34 66
EPM3128A 80 96
EPM3256A 116 158
Notes:
(1) Contact Altera for up-to-date information on available device package options.
(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or
boundary-scan testing, four I/O pins become JTAG pins.
44-Pin
TQFP
Notes (1), (2)
100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
Altera Corporation 3
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A devices contain 32 to 256 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmableindependently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high-speed parallel expander
product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixed-voltage systems.
MAX 3000A devices are supported by the MAX+PLUS II development
system, an integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIXworkstation-based EDA tools. The MAX+PLUS II software runs on
Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series
700/800, and IBM RISC System/6000 workstations.
AND
/fixed-OR array and a configurable register with
f
Functional Description
4 Altera Corporation
For more information on development tools, see the
Programmable Logic Development System & Software Data Sheet
The MAX 3000A architecture includes the following elements:
■
Logic array blocks (LABs)
■
Macrocells
■
Expander product terms (shareable and parallel)
■
Programmable interconnect array (PIA)
■
I/O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 3000A devices.
MAX+PLUS II
.
Figure 1. MAX 3000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
MAX 3000A Programmable Logic Device Family Data Sheet
INPUT/GCLRn
6 to 16 I/O
6 to 16 I/O
6 Output Enables
6 to 16
I/O
Control
Block
6
6 to 16
I/O
Control
Block
6
LAB A
LAB C
Macrocells
1 to 16
Macrocells
33 to 48
36 36
16
6 to 16
36 36
16
6 to 16
16
6 to 16
PIA
16
6 to 16
Macrocells
17 to 32
Macrocells
49 to 64
6 Output Enables
LAB B
6 to 16
Control
LAB D
6 to 16
Control
I/O
Block
I/O
Block
6 to 16 I/O
6
6 to 16 I/O
6
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
36 signals from the PIA that are used for general logic inputs
■
Global controls that are used for secondary register functions
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product-term select matrix, and
programmable register. Figure 2 shows a MAX 3000A macrocell.
Altera Corporation 5
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 2. MAX 3000A Macrocell
LAB Local Array
Product-
Term
Select
Matrix
Parallel Logic
Expanders
(from other
macrocells)
Global
Clear
Clear
Select
Global
Clocks
2
VCC
Clock/
Enable
Select
D/T
ENA
PRN
CLRN
Programmable
Register
Register
Bypass
Q
to I/O
Control
Block
36 Signals
from PIA
16 Expander
Product T erms
Shared Logic
Expanders
to PIA
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR
gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
Shareable expanders, which are inverted product terms that are fed
■
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
■
macrocells
The MAX+PLUS II development system automatically optimizes
product-term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
6 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
■
Global clock signal mode, which achieves the fastest clock-to-output
performance.
■
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
Array clock implemented with a product term. In this mode, the
■
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 3000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the two global clock pins,
GCLK1
or
GCLK2
.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (
GCLRn
).
Expander Product Terms
Although most logic functions can be implemented with the five product
terms available in each macrocell, highly complex logic functions require
additional product terms. Another macrocell can be used to supply the
required logic resources. However, the MAX 3000A architecture also
offers both shareable and parallel expander product terms (“expanders”)
that provide additional product terms directly to any macrocell in the
same LAB. These expanders help ensure that logic is synthesized with the
fewest possible logic resources to obtain the fastest possible speed.
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (
shareable expanders are used. Figure 3 shows how shareable expanders
can feed multiple macrocells.
t
) is incurred when
SEXP
Altera Corporation 7
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 3. MAX 3000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
36 Signals
from PIA
16 Shared
Expanders
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
The MAX+PLUS II Compiler can automatically allocate up to three sets of
up to five parallel expanders to the macrocells that require additional
product terms. Each set of five parallel expanders incurs a small,
incremental timing delay (
product terms, the MAX+PLUS II Compiler uses the five dedicated
product terms within the macrocell and allocates two sets of parallel
expanders; the first set includes five product terms, and the second set
includes four product terms, increasing the total delay by 2 ×
t
). For example, if a macrocell requires 14
PEXP
t
PEXP
.
8 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowest-numbered macrocell
can only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.
Figure 4. MAX 3000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
from
Previous
Macrocell
Preset
36 Signals
from PIA
16 Shared
Expanders
Product-
Term
Select
Matrix
Product-
Term
Select
Matrix
Macrocell
ProductTerm Logic
Clock
Clear
Preset
Macrocell
ProductTerm Logic
Clock
Clear
to Next
Macrocell
Altera Corporation 9
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input
which selects a PIA signal to drive into the LAB.
Figure 5. MAX 3000A PIA Routing
AND
gate,
to LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 3000A PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 3000A devices. The I/O control block has
six global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
10 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 6. I/O Control Block of MAX 3000A Devices
PIA
6 Global
Output Enable Signals
OE Select Multiplexer
to Other I/O Pins
from
Macrocell
to PIA
VCC
GND
Open-Drain Output
Slew-Rate Control
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 3000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
Altera Corporation 11
MAX 3000A Programmable Logic Device Family Data Sheet
In-System
Programmability (ISP)
MAX 3000A devices can be programmed in-system via an industrystandard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system
programmability (ISP) offers quick, efficient iterations during design
development and debugging cycles. The MAX 3000A architecture
internally generates the high programming voltages required to program
its EEPROM cells, allowing in-system programming with only a single
3.3-V power supply. During in-system programming, the I/O pins are tristated and weakly pulled-up to eliminate board conflicts. The pull-up
value is nominally 50 kΩ.
MAX 3000A devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that ensures safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 3000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the MasterBlaster communications cable, the ByteBlasterMV parallel port
download cable, and the BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
high-pin-count packages (e.g., QFP packages) due to device handling.
MAX 3000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
The Jam STAPL can be used to program MAX 3000A devices with incircuit testers, PCs, or embedded processors.
f
Programming with External Hardware
f
12 Altera Corporation
For more information on using the Jam STAPL language, see Application
Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor)
and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded
Processor).
MAX 3000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, MPU, and the appropriate device adapter.
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the device.
For more information, see the Altera Programming Hardware Data Sheet.
MAX 3000A Programmable Logic Device Family Data Sheet
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Table 4. MAX 3000A JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
ISP Instructions These instructions are used when programming MAX 3000A devices via the JTAG ports
For more information, see Programming Hardware Manufacturers.
MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1-1990. Table 4 describes the JTAG instructions supported by
MAX 3000A devices. The pin-out tables starting on page 39 of this data
sheet show the location of the JTAG control pins for each device. If the
JTAG interface is not required, the JTAG pins are available as user I/O
pins.
normal device operation, and permits an initial data pattern output at the device pins
test pattern at the output pins and capturing test results at the input pins
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE to be serially shifted out of TDO
allowing the USERCODE value to be shifted out of TDO
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
The instruction register length of MAX 3000A devices is 10 bits. The
IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show
the boundary-scan register length and device IDCODE information for
MAX 3000A devices.
Altera Corporation 13
MAX 3000A Programmable Logic Device Family Data Sheet
Table 5. MAX 3000A Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPM3032A 96
EPM3064A 192
EPM3128A 288
EPM3256A 480
Table 6. 32-Bit MAX 3000A Device IDCODE Value Note (1)
Device IDCODE (32 bits)
f
Version
(4 Bits)
EPM3032A 0001 0111 0000 0011 0010 00001101110 1
EPM3064A 0001 0111 0000 0110 0100 00001101110 1
EPM3128A 0001 0111 0001 0010 1000 00001101110 1
EPM3256A 0001 0111 0010 0101 0110 00001101110 1
Notes:
(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
Part Number (16 Bits) Manufacturer’s
Identity (11 Bits)
1 (1 Bit)
(2)
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information on JTAG BST.
14 Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 7 shows the timing information for the JTAG signals.
Figure 7. MAX 3000A JTAG Waveforms
TMS
TDI
t
JCP
t
JCL
t
JPSU
t
JPH
TCK
t
JCH
t
JPZX
t
JPCO
t
JPXZ
TDO
t
JSH
t
JSCO
t
JSXZ
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
Table 7 shows the JTAG timing parameters and values for MAX 3000A
devices.
Altera Corporation 15
MAX 3000A Programmable Logic Device Family Data Sheet
Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices
Symbol Parameter Min Max Unit
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK clock period 100 ns
TCK clock high time 50 ns
TCK clock low time 50 ns
JTAG port setup time 20 ns
JTAG port hold time 45 ns
JTAG port clock to output 25 ns
JTAG port high impedance to valid output 25 ns
JTAG port valid output to high impedance 25 ns
Capture register setup time 20 ns
Capture register hold time 45 ns
Update register clock to output 25 ns
Update register high impedance to valid output 25 ns
Update register valid output to high impedance 25 ns
Programmable Speed/Power Control
Output
Configuration
MAX 3000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 3000A
device for either high-speed or low-power operation. As a result, speedcritical paths in the design can run at high speed, while the remaining
paths can operate at reduced power. Macrocells that run at low power
incur a nominal timing delay adder (t
t
CPPW
and t
parameters.
SEXP
) for the t
LPA
LAD
, t
LAC
, tIC, t
ACL
, tEN,
MAX 3000A device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 3000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 3000A devices to connect to systems with
differing supply voltages. MAX 3000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
16 Altera Corporation
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