Altera MAX 10 Power User Manual
MAX 10 Power Management User Guide
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TOC-2
Contents
MAX 10 Power Management Overview..............................................................1-1
MAX 10 Power Management Features and Architecture.................................. 2-1
Power Supply Device Options....................................................................................................................2-1
Single-Supply Device.......................................................................................................................2-1
Dual-Supply Device.........................................................................................................................2-1
Comparison of the MAX 10 Power Supply Device Options......................................................2-2
Power Supply Design.......................................................................................................................2-3
Power-On Reset Circuitry.......................................................................................................................... 2-4
Power Supplies Monitored and Not Monitored by the POR Circuitry................................... 2-4
Instant-On Support......................................................................................................................... 2-6
Power Management Controller Scheme...................................................................................................2-6
Power Management Controller Architecture.............................................................................. 2-6
Hot Socketing............................................................................................................................................... 2-8
Hot-Socketing Specifications......................................................................................................... 2-8
Hot-Socketing Feature Implementation.......................................................................................2-9
Power Management Controller Reference Design.............................................3-1
Clock Control Block.................................................................................................................................... 3-2
I/O Buffer......................................................................................................................................................3-2
Internal Oscillator........................................................................................................................................3-2
Power Management Controller................................................................................................................. 3-3
Entering State....................................................................................................................................3-3
Sleep State..........................................................................................................................................3-3
Exiting State......................................................................................................................................3-3
Awake State.......................................................................................................................................3-3
Entering or Exiting Sleep Mode.................................................................................................................3-4
Entering Sleep Mode........................................................................................................................3-4
Exiting Sleep Mode..........................................................................................................................3-4
Timing Parameters.......................................................................................................................... 3-5
Hardware Implementation and Current Measurement.........................................................................3-5
Additional Information for MAX 10 Power Management User Guide ...........A-1
Document Revision History for MAX 10 Power Management User Guide...................................... A-1
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2015.02.09
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MAX 10 Power Management Overview
1
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MAX® 10 devices offer the following power supply device options:
• Single-supply device—requires 1 external power supply of 3.0 V or 3.3 V whilst offering maximum
convenience and board simplicity.
• Dual-supply device—requires 2 external power supplies of 1.2 V and 2.5 V whilst offering the most
features, highest performance, and when coupled with high-efficiency Enpirion® PowerSoCs, the
lowest power solution.
Related Information
MAX 10 Power Management Features and Architecture on page 2-1
Provides information about power management features and architecture
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
MAX 10 Power Management Features and
VCC_ONE/VCCA
Voltage
Regulator
3.3 V/3.0 V
1.2 V
Max 10 Single-Supply Device
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MAX 10 power optimization features are as follows:
• Single-supply or dual-supply device options
• Power-on reset (POR) circuitry
• Power management controller scheme
• Hot socketing
Power Supply Device Options
This section covers the single-supply and dual-supply device options supported in MAX 10 devices.
Single-Supply Device
MAX 10 single-supply devices only need either a 3.0- or 3.3-V external power supply. The external power
supply serves as an input to the MAX 10 device VCC_ONE and VCCA power pins. This external power supply
is then regulated by an internal voltage regulator in the MAX 10 single-supply device to 1.2 V. The 1.2-V
voltage level is required by core logic operation.
Architecture
2
Figure 2-1: MAX 10 Single-Supply Device
Dual-Supply Device
MAX 10 dual-supply devices require 1.2 V and 2.5 V for the device core logics and periphery operations.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
MAX 10
Dual-Supply Device
(1.2 V)
VCCA, VCCA_ADC
(2.5 V)
2-2
Comparison of the MAX 10 Power Supply Device Options
Figure 2-2: MAX 10 Dual-Supply Device
Comparison of the MAX 10 Power Supply Device Options
Table 2-1: Comparison of the MAX 10 Power Supply Device Options
Characteristics Single-Supply Device Dual-Supply Device
Voltage regulator count
Core and I/O performance Low High
(1)
1 2
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For MAX 10 single-supply devices, only one power supply is required—3.0 V or 3.3 V to power the core
of the FPGA. The same power supply can be used to power the I/O if the same 3.0 V or 3.3 V voltage is
required. If different I/O voltage is used, then additional voltage regulators will be needed.
For MAX 10 dual-supply devices, two power supplies are required to supply power to the device core,
periphery, phase-locked loop (PLL), and analog-to-digital converters (ADC) blocks—1.2 V and 2.5 V.
Depending on the I/O standard voltage requirement, you may use two or more voltage regulators.
As the power rails for the FPGA core are supplied externally in the MAX 10 dual-supply devices, the
design can be optimized for power by using high efficiency switching power supplies on the board. The
power savings will be equal to the increased efficiency of the regulators used compared to the internal
linear regulators of the MAX 10 single-supply devices. If linear regulators are used to power the MAX 10
dual-supply devices, the power consumption of the MAX 10 dual-supply devices will be approximately
equal to the MAX 10 single-supply devices.
The device performance of the single-supply device is lower than that of the dual-supply device. For the
performance difference in terms of LVDS, pseudo-LVDS, digital signal processing (DSP), and internal
memory performance, refer to the MAX 10 FPGA device datasheet.
Related Information
MAX 10 FPGA Device Datasheet
Provides details about the MAX 10 performance difference in terms of LVDS, pseudo-LVDS, DSP, and
internal memory performance.
(1)
Altera Corporation
This shows the number of power supplies required by the core and periphery of the MAX 10 devices. You
may need additional voltage regulators to supply power to the VCCIO if the VCCIO does not have the same
voltage level as the core and periphery supply.
MAX 10 Power Management Features and Architecture
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Power Supply Design
Designing a power tree for a MAX 10 single- or dual-supply device will vary depending on the static and
dynamic power, as well as I/O and other feature utilization, for each specific use case.
Altera® Enpirion portfolio of power management solutions, combined with comprehensive design tools,
enable optimized MAX 10 device power supply design. The Enpirion portfolio includes power
management solutions that are compatible with all MAX 10 variants.
The MAX 10 FPGA Device Family Pin Connection Guidelines provides a more detailed recommendation
about how to group inputs in order to power a MAX 10 device. The PowerPlay Early Power Estimators
(EPE) tool for MAX 10 devices provides input rail power requirements and specific device recommenda‐
tions based on each specific MAX 10 use case.
Individual input rail voltage and current requirements are summarized on the Report tab while input rail
groupings and specific power supply recommendations can be found on the Main and Enpirion tabs,
respectively.
Power Supply Design
2-3
Warning: MAX 10 single-supply devices have maximum power consumption of V
following table. Running a design that goes beyond the maximum power consumption of
V
CC_ONE
of the MAX 10 single-supply device may cause functional issue on the device.
Therefore, ensure that your device does not exceed the maximum power consumption of
V
CC_ONE
when you analyze the power consumption of your design using the PowerPlay EPE
spreadsheet.
Table 2-2: Maximum Power Consumption of V
Device Maximum Power Consumption (W)
10M02S 0.778
10M04S 1.362
10M08S 1.362
10M16S 2.270
10M25S 2.943
10M40S 5.267
10M50S 5.267
Related Information
for MAX 10 Single-Supply Devices
CC_ONE
CC_ONE
, as listed in the
• Enpirion Power Management Solutions
Provides more information about Altera's Power Management IC and PowerSoC solutions designed
for powering FPGAs.
• MAX 10 FPGA Device Family Pin Connection Guidelines
Provides a more detailed recommendation about how to group inputs in order to power a MAX 10
device.
MAX 10 Power Management Features and Architecture
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2-4
Power-On Reset Circuitry
Power-On Reset Circuitry
The POR circuitry keeps the MAX 10 device in the reset state until the POR monitored power supply
outputs are within the recommended operating range of the maximum power supply ramp time, t
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.
RAMP
If the ramp time, t
, is not met, the MAX 10 device I/O pins and programming registers remain tri-
RAMP
stated, during which device configuration could fail.
The MAX 10 device POR circuit monitors the following power rails during power up regardless of the
power supply device options:
• V
• V
• V
The POR circuitry also ensures V
or regulated V
CC
of banks 1B and 8
CCIO
CCA
CC_ONE
(2)
level of I/O banks 1B and 8
CCIO
(2)
that contain configuration pins reach
an acceptable level before configuration is triggered.
Power Supplies Monitored and Not Monitored by the POR Circuitry
Table 2-3: Power Supplies Monitored and Not Monitored by the POR Circuitry
Power Supply Device Options Power Supplies Monitored Power Supplies Not Monitored
Single-supply device
Dual-supply device
• Regulated V
• V
CCA
CCIO
CC
CCA
CCIO
(3)
(3)
• V
• V
• V
• V
CC_ONE
• V
• V
• V
CCD_PLL
CCA_ADC
CCINT
—
The MAX 10 POR circuitry uses an individual POR-detecting circuitry to monitor each of the configura‐
tion-related power supplies independently. The main POR circuitry is gated by the outputs of all the
individual POR detectors. The main POR circuitry waits for all individual POR circuitries to release the
POR signal before allowing the control block to start programming the device. The main POR is released
after the last ramp-up power reaches the POR trip level followed by a POR delay.
By default, Quartus® II assigns POR delay time to standard POR delay. For some of the applications that
need fast wake-up to begin operation, you can enable fast POR delay time on the Quartus II programmer
user interface.
(2)
V
CCIO
(3)
For banks 1B and 8 for all MAX 10 devices and banks 1 and 8 for the 10M02 device.
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of banks 1 and 8 for the 10M02 device.
MAX 10 Power Management Features and Architecture
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