Altera MAX 10 JTAG User Manual
MAX 10 JTAG Boundary-Scan Testing
User Guide
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UG-M10JTAG
2015.05.04
101 Innovation Drive
San Jose, CA 95134
www.altera.com
TOC-2
Contents
Overview.............................................................................................................. 1-1
JTAG BST Architecture.......................................................................................2-1
JTAG BST Operation Control............................................................................ 3-1
JTAG Pins..................................................................................................................................................... 2-1
JTAG Circuitry Functional Model............................................................................................................ 2-1
JTAG Boundary-Scan Register...................................................................................................................2-2
Boundary-Scan Cells in MAX 10 I/O Pin.....................................................................................2-3
JTAG IDCODE ........................................................................................................................................... 3-1
JTAG Secure Mode......................................................................................................................................3-2
JTAG Private instruction............................................................................................................................3-2
JTAG Instructions........................................................................................................................................3-2
I/O Voltage Support in the JTAG Chain............................................................ 4-1
Enabling and Disabling JTAG BST Circuitry.....................................................5-1
Guidelines for JTAG BST....................................................................................6-1
Boundary-Scan Description Language Support.................................................7-1
Additional Information for MAX 10 JTAG Boundary-Scan Testing User
Guide ..............................................................................................................A-1
Document Revision History for MAX 10 JTAG Boundary-Scan Testing User Guide.....................A-1
Altera Corporation
2015.05.04
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Overview
1
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MAX® 10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing (BST).
When you perform BST, you can test pin connections without using physical test probes and capture
functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals
onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs.
Captured data is serially shifted out and externally compared to expected results.
Note: You can perform BST on MAX 10 devices before, after, and during configuration.
Related Information
• MAX 10 FPGA Configuration User Guide
Provides more information about JTAG in-system programming.
• JTAG BST Architecture on page 2-1
• JTAG Boundary-Scan Register on page 2-2
• JTAG BST Operation Control on page 3-1
• I/O Voltage Support in the JTAG Chain on page 4-1
• Enabling and Disabling JTAG BST Circuitry on page 5-1
• Guidelines for JTAG BST on page 6-1
• Boundary-Scan Description Language Support on page 7-1
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
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2015.05.04
www.altera.com
101 Innovation Drive, San Jose, CA 95134
JTAG BST Architecture
2
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MAX 10 JTAG interface uses four pins, TDI, TDO, TMS, and TCK.
JTAG Pins
Table 2-1: JTAG Pin Descriptions
Pin Function Description
TDI Serial input pin for:
• instructions
• test data
• programming data
TDO Serial output pin for:
• instructions
• test data
• programming data
TMS Input pin that provides the control
signal to determine the transitions of
the TAP controller state machine.
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• TDI is sampled on the rising edge of TCK
• TDI pins have internal weak pull-up resistors.
• TDO is sampled on the falling edge of TCK
• The pin is tri-stated if data is not being
shifted out of the device.
• TMS is sampled on the rising edge of TCK
• TMS pins have internal weak pull-up resistors.
TCK The clock input to the BST circuitry. —
All the JTAG pins are powered by the V
1B. In JTAG mode, the I/O pins support the LVTTL/
CCIO
LVCMOS 3.3-1.5V standards.
JTAG Circuitry Functional Model
The JTAG BST circuitry requires the following registers:
• Instruction register—determines which action to perform and which data register to access.
• Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and
TDO pins.
• Boundary-scan register—shift register composed of all the BSCs of the device.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
a
UPDATEIR
CLOCKIR
SHIFTIR
UPDATEDR
CLOCKDR
SHIFTDR
TDI
Instruction Register
Bypass Register
Boundary-Scan Register
Instruction Decode
TMS
TCK
TAP
Controller
ISP Registers
TDO
Data Registers
Device ID Register
2-2
JTAG Boundary-Scan Register
Figure 2-1: JTAG Circuitry Functional Model
• Test access port (TAP) controller—controls the JTAG BST.
• TMS and TCK pins—operate the TAP controller.
• TDI and TDO pins—provide the serial path for the data registers.
• The TDI pin also provides data to the instruction register to generate the control logic for the data
registers.
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JTAG Boundary-Scan Register
You can use the boundary-scan register to test external pin connections or to capture internal data. The
boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin as an
output. The boundary-scan register consists of 3-bit peripheral elements that are associated with MAX 10
I/O pins.
JTAG BST Architecture
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