Altera MAX 10 JTAG User Manual

MAX 10 JTAG Boundary-Scan Testing

User Guide

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Overview

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MAX® 10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing (BST). When you perform BST, you can test pin connections without using physical test probes and capture

functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs. Captured data is serially shifted out and externally compared to expected results.

Note: You can perform BST on MAX 10 devices before, after, and during configuration.

Related Information

• MAX 10 FPGA Configuration User Guide

Provides more information about JTAG in-system programming.

• JTAG BST Architecture on page 2-1

• JTAG Boundary-Scan Register on page 2-2

• JTAG BST Operation Control on page 3-1

• I/O Voltage Support in the JTAG Chain on page 4-1

• Enabling and Disabling JTAG BST Circuitry on page 5-1

• Guidelines for JTAG BST on page 6-1

• Boundary-Scan Description Language Support on page 7-1

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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JTAG BST Architecture

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MAX 10 JTAG interface uses four pins, TDI, TDO, TMS, and TCK.

JTAG Pins

Table 2-1: JTAG Pin Descriptions

Pin Function Description

TDI Serial input pin for:

• instructions

• test data

• programming data

TDO Serial output pin for:

• instructions

• test data

• programming data

TMS Input pin that provides the control

signal to determine the transitions of the TAP controller state machine.

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• TDI is sampled on the rising edge of TCK

• TDI pins have internal weak pull-up resistors.

• TDO is sampled on the falling edge of TCK

• The pin is tri-stated if data is not being shifted out of the device.

• TMS is sampled on the rising edge of TCK

• TMS pins have internal weak pull-up resistors.

TCK The clock input to the BST circuitry. —

All the JTAG pins are powered by the V

1B. In JTAG mode, the I/O pins support the LVTTL/

CCIO

LVCMOS 3.3-1.5V standards.

JTAG Circuitry Functional Model

The JTAG BST circuitry requires the following registers:

• Instruction register—determines which action to perform and which data register to access.

• Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and

TDO pins.

• Boundary-scan register—shift register composed of all the BSCs of the device.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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UPDATEIR

CLOCKIR

SHIFTIR

UPDATEDR

CLOCKDR

SHIFTDR

TDI

Instruction Register

Bypass Register

Boundary-Scan Register

Instruction Decode

TMS

TCK

TAP

Controller

ISP Registers

TDO

Data Registers

Device ID Register

2-2

JTAG Boundary-Scan Register

Figure 2-1: JTAG Circuitry Functional Model

• Test access port (TAP) controller—controls the JTAG BST.

• TMS and TCK pins—operate the TAP controller.

• TDI and TDO pins—provide the serial path for the data registers.

• The TDI pin also provides data to the instruction register to generate the control logic for the data registers.

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JTAG Boundary-Scan Register

You can use the boundary-scan register to test external pin connections or to capture internal data. The boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with MAX 10 I/O pins.

JTAG BST Architecture

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0 1

OUTPUT

OE

INPUTINPUT

OUTPUT

OE

From or

to Device

I/O Cell Circuitry or Logic Array

0 1

PIN_OUT

INJ

OEJ

OUTJ

VCC

SDO

SHIFT

SDI

CLOCK HIGHZ MODE

PIN_OE

PIN_IN

Output

Buffer

Capture

Registers

Update

Registers

Global

Signals

UPDATE

D Q

D Q D Q

D Q

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Boundary-Scan Cells in MAX 10 I/O Pin

The MAX 10 3-bit BSC contains the following registers:

• Capture registers—connect to internal device data through OUTJ, OEJ, and PIN_IN signals.

• Update registers—connect to external data through PIN_OUT and PIN_OE signals.

Figure 2-2: User I/O BSC with JTAG BST Circuitry for MAX 10 Devices

The TAP controller generates the global control signals internally for the JTAG BST registers, shift,

clock, and update. The instruction register generates the MODE signal.

The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.

Boundary-Scan Cells in MAX 10 I/O Pin

2-3

JTAG BST Architecture

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2-4

Boundary-Scan Cells in MAX 10 I/O Pin

Table 2-2: BSC Capture and Update Register for MAX 10 Devices

Captures Drives

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Pin Type

Output Capture Register

OE Capture

Register

Input Capture Register

Output Update

Register

OE Update

Register

Input Update

Register

User I/O OUTJ OEJ PIN_IN PIN_OUT PIN_OE INJ

Note: All VCC and GND pin types do not have BSCs.

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JTAG BST Architecture

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JTAG BST Operation Control

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JTAG IDCODE

The IDCODE is unique for each MAX 10 device. Use this code to identify the devices in a JTAG chain.

Table 3-1: IDCODE Information for MAX 10 Devices

Supply Option Device

10M02 0000 0011 0001 1000 0001 000 0110 1110 1 10M04 0000 0011 0001 1000 1010 000 0110 1110 1

10M08 0000 0011 0001 1000 0010 000 0110 1110 1 Singlesupply

10M16 0000 0011 0001 1000 0011 000 0110 1110 1

10M25 0000 0011 0001 1000 0100 000 0110 1110 1

10M40 0000 0011 0001 1000 1101 000 0110 1110 1

10M50 0000 0011 0001 1000 0101 000 0110 1110 1

Version (4

Bits)

Part Number (16 Bits) Manufacturer Identity

Device

LSB (1 Bit)

(11 Bits)

10M02 0000 0011 0001 0000 0001 000 0110 1110 1

10M04 0000 0011 0001 0000 1010 000 0110 1110 1

10M08 0000 0011 0001 0000 0010 000 0110 1110 1 Dualsupply

10M16 0000 0011 0001 0000 0011 000 0110 1110 1

10M25 0000 0011 0001 0000 0100 000 0110 1110 1

10M40 0000 0011 0001 0000 1101 000 0110 1110 1

10M50 0000 0011 0001 0000 0101 000 0110 1110 1

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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3-2

JTAG Secure Mode

In JTAG secure mode, the device only allow SAMPLE/PRELOAD, BYPASS, EXTEST, and IDCODE JTAG instructions.

Related Information

MAX 10 FPGA Configuration User Guide

Provides more information about the JTAG Secure Mode.

JTAG Private instruction

Caution: Never invoke the following instruction codes. These instructions can damage the device and

render it unusable:

• 10 0100 0000

• 10 0011 0000

• 10 1110 0000

• 10 0011 0001

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JTAG Instructions

Instruction Name Instruction

Binary

SAMPLE/PRELOAD 00 0000 0101

EXTEST

BYPASS 11 1111 1111

USERCODE 00 0000 0111

IDCODE 00 0000 0110

(1)

00 0000 1111

Description

• Permits an initial data pattern to be an output at the device pins.

• Allows you to capture and examine a snapshot of signals at the device pins if the device is operating in normal mode.

• Forces test pattern at the output pins and capture the test results at the input pins.

• Allows you to test the external circuitry and board-level intercon‐ nects.

• Places the 1-bit bypass register between the TDI and TDO pins.

• Allows the BST data to pass synchronously through target devices to adjacent devices during normal device operation.

• Places the 1-bit bypass register between the TDI and TDO pins.

• Allows you to shift the USERCODE register out of the TDO pin serially.

• Selects the IDCODE register and places it between the TDI and TDO pins.

• Allows you to shift the IDCODE register out of the TDO pin serially.

(1)

HIGHZ, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features.

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JTAG BST Operation Control

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JTAG Instructions

3-3

Instruction Name Instruction

Binary

(1)

HIGHZ

(1)

CLAMP

USER0 00 0000 1100

USER1 00 0000 1110

00 0000 1011

00 0000 1010

Description

• Places the 1-bit bypass register between the TDI and TDO pins. The 1-bit bypass register tri-states all the I/O pins.

• Allow the BST data to pass synchronously through target devices to adjacent devices if device is operating in normal mode.

• Places the 1-bit bypass register between the TDI and TDO pins. The 1-bit bypass register holds I/O pins to a state defined by the data in the boundary-scan register.

• Allow the BST data to pass synchronously through target devices to adjacent devices if device is operating in normal mode.

• Allows you to define the scan chain between the TDI and TDO pins in the MAX 10 logic array.

• Use this instruction for custom logic and JTAG interfaces.

• Allows you to define the scan chain between the TDI and TDO pins in the MAX 10 logic array.

• Use this instruction for custom logic and JTAG interfaces.

JTAG BST Operation Control

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2.5-V

V

CCIO

1.8-V

V

CCIO

1.8-V

V

CCIO

TDI

TDO

Tester

Shift TDO to Level

Accepted by Tester

if Necessary

Must be 5.0-V

Tolerant

Must be 3.3-V

Tolerant

Must be 2.5-V

Tolerant

1.5-V V

CCIO

Must be 1.8-V

Tolerant

Level

Shifter

3.3-V V

CCIO

5.0-V

V

CCIO

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I/O Voltage Support in the JTAG Chain

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A JTAG chain can contain several Altera and non-Altera devices. The TDO pin of a device drives out at the voltage level according to the V

can interface with each other although the devices may have different V For example, a device with 3.3-V V

can drive to a device with 5.0-V V

CCIO

minimum VIH on transistor-to-transistor logic (TTL)-level input for the 5.0-V V MAX 10 devices can support 1.5-, 1.8-, 2.5-, or 3.3-V input levels, depending on the V

of the device. The devices

CCIO

levels.

CCIO

because 3.3 V meets the

CCIO

device.

CCIO

Bank 1B. To interface the TDI and TDO lines of the JTAG pins of devices that have different V

CCIO

level shifter between the devices. If possible, construct the JTAG chain where device with a higher V level drives to a device with an equal or lower V

level. In this setup, you only require a level shifter for

CCIO

shifting the TDO level to a level JTAG tester accept.

Figure 4-1: JTAG Chain of Mixed Voltages and Level Shifters

voltage of I/O

levels, insert a

CCIO

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trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Enabling and Disabling JTAG BST Circuitry

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The JTAG BST circuitry in MAX 10 devices is automatically enabled after the power-up. To ensure that you do not inadvertently enable the JTAG BST circuitry when it is not required, disable the

circuitry permanently with pin connections as listed in the following table.

Table 5-1: Pin Connections to Permanently Disable the JTAG BST Circuitry in MAX 10 Devices

JTAG Pins Connection to Disable

TMS V TCK GND TDI V TDO Leave open

supply of Bank 1B

CCIO

supply of Bank 1B

CCIO

You must enable this circuitry only if you use the BST or ISP features.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Guidelines for JTAG BST

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Consider the following guidelines when you perform BST with the device:

• If the “10...” pattern does not shift out of the instruction register through the TDO pin during the first clock cycle of the SHIFT_IR state, the TAP controller did not reach the proper state. To solve this problem, try one of the following procedures:

• Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP

controller to the SHIFT_IR state, return TAP controller to the RESET state and send the 01100 code to the TMS pin.

• Check the connections to the VCC, GND, JTAG, and dedicated configuration pins on the device.

• Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data in the OUTJ update register is driven out. The state must be known and correct to avoid contention with other devices in the system.

• To perform testing before configuration, hold the nCONGFIG pin low.

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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Boundary-Scan Description Language Support

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The BSDL—a subset of VHDL—provides a syntax that allows you to describe the features of an IEEE Std.

1149.1 BST-capable device that can be tested. Test software development systems then use the BSDL files for test generation, analysis, failure diagnostics, and in-system programming.

Related Information

IEEE 1149.1 BSDL Files

Provides more information about BSC group definitions.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Additional Information for MAX 10 JTAG

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Boundary-Scan Testing User Guide

2015.05.04

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Document Revision History for MAX 10 JTAG Boundary-Scan Testing User Guide

Date Version Changes

May 2015 2015.05.04 Added note on about performing the boundary-scan testing in

September 2014 2014.09.22 Initial release.

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'Overview'.

A

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Altera MAX 10 JTAG User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Overview

JTAG BST Architecture

JTAG Pins

JTAG Circuitry Functional Model

JTAG Boundary-Scan Register

Boundary-Scan Cells in MAX 10 I/O Pin

JTAG BST Operation Control

JTAG IDCODE

JTAG Secure Mode

JTAG Private instruction

JTAG Instructions

I/O Voltage Support in the JTAG Chain

Enabling and Disabling JTAG BST Circuitry

Guidelines for JTAG BST

Boundary-Scan Description Language Support

Document Revision History for MAX 10 JTAG Boundary-Scan Testing User Guide