Altera MAX 10 Embedded Multipliers User Manual

MAX 10 Embedded Multipliers User

Guide

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TOC-2

Embedded Multiplier Block Overview

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The embedded multiplier is configured as either one 18 x 18 multiplier or two 9 x 9 multipliers. For multiplications greater than 18 x 18, the Quartus® II software cascades multiple embedded multiplier blocks together. There are no restrictions on the data width of the multiplier but the greater the data width, the slower the multiplication process.

Figure 1-1: Embedded Multipliers Arranged in Columns with Adjacent LABS

Table 1-1: Number of Embedded Multipliers in the MAX 10 Devices

10M02 16 32 16 10M04 20 40 20 10M08 24 48 24 10M16 45 90 45

(1)

These columns show the number of 9 x 9 or 18 x 18 multipliers for each device. The total number of multipliers for each device is not the sum of all the multipliers.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Device Embedded

Multipliers

9 x 9 Multipliers

(1)

18 x 18 Multipliers

(1)

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Embedded Multiplier Block Overview

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Device Embedded

9 x 9 Multipliers

(1)

18 x 18 Multipliers

Multipliers

10M25 55 110 55 10M40 125 250 125 10M50 144 288 144

You can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The LUTs contain partial results from multiplying input data with coefficients implementing variable depth and width high-performance soft multipliers for low-cost, high-volume DSP applications. The availability of soft multipliers increases the number of available multipliers in the device.

Table 1-2: Number of Multipliers in the MAX 10 Devices

Device Embedded

Multipliers

Soft Multipliers

(16 x 16)

(2)

Total Multipliers

10M02 16 12 28 10M04 20 21 41 10M08 24 42 66 10M16 45 61 106 10M25 55 75 130

(1)

(3)

10M40 125 140 265 10M50 144 182 326

(1)

These columns show the number of 9 x 9 or 18 x 18 multipliers for each device. The total number of multipliers for each device is not the sum of all the multipliers.

(2)

Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.

(3)

The total number of multipliers may vary, depending on the multiplier mode you use.

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Embedded Multipliers Features and

CLRN

D Q ENA

Data A

Data B

aclr

clock

ena

signa signb

CLRN

D Q ENA

CLRN

D Q ENA

Data Out

Embedded Multiplier Block

Output

Register

Input

Register

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Each embedded multiplier consists of three elements. Depending on the application needs, you can use an embedded multiplier block in one of two operational modes.

Embedded Multipliers Architecture

Each embedded multiplier consists of the following elements:

• Multiplier stage

• Input and output registers

• Input and output interfaces

Figure 2-1: Multiplier Block Architecture

Architecture

2

Input Register

Depending on the operational mode of the multiplier, you can send each multiplier input signal into either one of the following:

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Multiplier Stage

• An input register

• The multiplier in 9- or 18-bit sections Each multiplier input signal can be sent through a register independently of other input signals. For

example, you can send the multiplier Data A signal through a register and send the Data B signal directly to the multiplier.

The following control signals are available to each input register in the embedded multiplier:

• Clock

• Clock enable

• Asynchronous clear All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and

asynchronous clear signals.

Multiplier Stage

The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18 multipliers and other multipliers in between these configurations. Depending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel.

Each multiplier operand is a unique signed or unsigned number. Two signals, signa and signb, control an input of a multiplier and determine if the value is signed or unsigned. If the signa signal is high, the

Data A operand is a signed number. If the signa signal is low, the Data A operand is an unsigned

number.

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The following table lists the sign of the multiplication results for the various operand sign representations. The results of the multiplication are signed if any one of the operands is a signed value.

signa Value Logic Level signb Value Logic Level

Unsigned Low Unsigned Low Unsigned Unsigned Low Signed High Signed

Signed High Unsigned Low Signed Signed High Signed High Signed

You can dynamically change the signa and signb signals to modify the sign representation of the input operands at run time. You can send the signa and signb signals through a dedicated input register. The multiplier offers full precision, regardless of the sign representation.

When the signa and signb signals are unused, the Quartus II software sets the multiplier to perform unsigned multiplication by default.

Output Register

You can register the embedded multiplier output using output registers in either 18- or 36-bit sections. This depends on the operational mode of the multiplier. The following control signals are available for each output register in the embedded multiplier:

Data A Data B

Result

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CLRN

D Q ENA

Data A [17..0]

Data B [17..0]

aclr

clock

ena

signa signb

CLRN

D Q ENA

CLRN

D Q ENA

Data Out [35..0]

18 x 18 Multiplier

Embedded Multiplier

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• Clock

• Clock enable

• Asynchronous clear All input and output registers in a single embedded multiplier are fed by the same clock, clock enable, and

asynchronous clear signals.

Embedded Multipliers Operational Modes

You can use an embedded multiplier block in one of two operational modes, depending on the applica‐ tion needs:

• One 18-bit x 18-bit multiplier

• Up to two 9-bit x 9-bit independent multipliers You can also use embedded multipliers of the MAX® 10 devices to implement multiplier adder and

multiplier accumulator functions. The multiplier portion of the function is implemented using embedded multipliers. The adder or accumulator function is implemented in logic elements (LEs).

18-Bit Multipliers

Embedded Multipliers Operational Modes

2-3

You can configure each embedded multiplier to support a single 18 x 18 multiplier for input widths of 10 to 18 bits.

The following figure shows the embedded multiplier configured to support an 18-bit multiplier.

Figure 2-2: 18-Bit Multiplier Mode

Embedded Multipliers Features and Architecture

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CLRN

D Q ENA

Data A 0 [8..0]

Data B 0 [8..0]

aclr

clock

ena

signa signb

CLRN

D Q ENA

CLRN

D Q ENA

Data Out 0 [17..0]

9 x 9 Multiplier

Embedded Multiplier

CLRN

D Q ENA

Data A 1 [8..0]

Data B 1 [8..0]

CLRN

D Q ENA

CLRN

D Q ENA

Data Out 1 [17..0]

9 x 9 Multiplier

2-4

9-Bit Multipliers

All 18-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Also, you can dynamically change the

signa and signb signals and send these signals through dedicated input registers.

9-Bit Multipliers

You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits.

The following figure shows the embedded multiplier configured to support two 9-bit multipliers.

Figure 2-3: 9-Bit Multiplier Mode

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All 9-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both.

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9-Bit Multipliers

2-5

Each embedded multiplier block has only one signa and one signb signal to control the sign representa‐ tion of the input data to the block. If the embedded multiplier block has two 9 × 9 multipliers the following applies:

• The Data A input of both multipliers share the same signa signal

• The Data B input of both multipliers share the same signb signal

Embedded Multipliers Features and Architecture

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Embedded Multipliers Implementation Guides

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The Quartus II software contains tools for you to create and compile your design, and configure your device.

You can prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores using the Quartus II software.

Embedded Multipliers Implementation Guides

The Quartus II software contains tools for you to create and compile your design, and configure your device.

You can prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores using the Quartus II software.

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your IP variation name, optional ports, architecture features, and output file generation options. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by device.

The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes

Note:

exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog.

Use the following features to help you quickly locate and select an IP core:

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Search and filter IP for your target device

Double-click to customize, right-click for information

3-2

Specifying IP Core Parameters and Options

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, installation location, and links to documentation.

Figure 3-1: Quartus II IP Catalog

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Note: The IP Catalog and parameter editor replace the MegaWizard™ Plug-In Manager in the Quartus II

software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these messages.

Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.

3. Specify parameters and options for your IP variation:

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• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.

The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Files Generated by IP Cores

The following integer arithmetic IP cores use the MAX 10 device embedded multipliers block:

• LPM_MULT

• ALTMULT_ACCUM (MAC)

• ALTMULT_ADD

• ALTMULT_COMPLEX

Files Generated by IP Cores

3-3

Verilog HDL Prototype Location

You can view the Verilog HDL prototype for the IP cores in the following Verilog Design Files (.v):

Table 3-1: Verilog HDL Prototype Location

Integer Arithmetic Megafunctions Directory Verilog Design File (.v)

LPM_MULT <Quartus II installation directory>

lpm.v

\eda\synthesis

• ALTMULT_ACCUM

• ALTMULT_ADD

<Quartus II installation directory> \eda\synthesis

altera_mf.v

• ALTMULT_COMPLEX

VHDL Component Declaration Location

You can view the VHDL component declaration for the IP cores in the following VHDL Design Files (.vhd):

Integer Arithmetic Megafunctions Directory VHDL Design File (.vhd)

LPM_MULT <Quartus II installation directory>

\libraries\vhdl\lpm

• ALTMULT_ACCUM

• ALTMULT_ADD

<Quartus II installation directory> \libraries\vhdl\altera_mf

• ALTMULT_COMPLEX

LPM_PACK.vhd

altera_mf_components.vhd

Embedded Multipliers Implementation Guides

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Altera MAX 10 Embedded Multipliers User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Embedded Multiplier Block Overview

Embedded Multipliers Architecture

Input Register

Multiplier Stage

Output Register

Embedded Multipliers Operational Modes

18-Bit Multipliers

9-Bit Multipliers

Embedded Multipliers Implementation Guides

Embedded Multipliers Implementation Guides

IP Catalog and Parameter Editor

Specifying IP Core Parameters and Options

Files Generated by IP Cores

Verilog HDL Prototype Location

VHDL Component Declaration Location