Altera Low Latency Ethernet 10G MAC User Manual

Low Latency Ethernet 10G MAC

User Guide

Last updated for Altera Complete Design Suite: 15.0

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TOC-2

Low Latency Ethernet 10G MAC User Guide

About LL Ethernet 10G MAC............................................................................. 1-1

Getting Started with LL Ethernet 10G MAC...................................................... 2-1

Features......................................................................................................................................................... 1-2

Release Information.....................................................................................................................................1-3

Device Family Support................................................................................................................................1-3

Definition: Device Support Level...................................................................................................1-4

Performance and Resource Utilization.....................................................................................................1-4

Resource Utilization........................................................................................................................ 1-4

TX and RX Latency..........................................................................................................................1-5

Introduction to Altera IP Cores.................................................................................................................2-1

Installing and Licensing IP Cores..............................................................................................................2-2

Specifying IP Core Parameters and Options............................................................................................2-2

Parameterizing the IP Core........................................................................................................................ 2-3

Parameter Settings....................................................................................................................................... 2-4

Generated Files.............................................................................................................................................2-6

Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7

Upgrading Outdated IP Cores................................................................................................................... 2-8

Migrating IP Cores to a Different Device.................................................................................................2-9

Design Considerations..............................................................................................................................2-11

Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC.................................2-11

Timing Constraints........................................................................................................................2-12

Functional Description of LL Ethernet 10G MAC............................................. 3-1

Architecture..................................................................................................................................................3-1

Interfaces.......................................................................................................................................................3-2

Frame Types..................................................................................................................................................3-4

TX Datapath................................................................................................................................................. 3-4

Padding Bytes Insertion..................................................................................................................3-4

Address Insertion.............................................................................................................................3-4

CRC-32 Insertion.............................................................................................................................3-5

XGMII Encapsulation..................................................................................................................... 3-6

Inter-Packet Gap Generation and Insertion................................................................................ 3-7

XGMII Transmission...................................................................................................................... 3-7

Unidirectional Feature.................................................................................................................... 3-8

TX Timing Diagrams.......................................................................................................................3-9

RX Datapath............................................................................................................................................... 3-13

XGMII Decapsulation...................................................................................................................3-13

CRC Checking................................................................................................................................3-13

Address Checking..........................................................................................................................3-14

Frame Type Checking................................................................................................................... 3-14

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Low Latency Ethernet 10G MAC User Guide

Length Checking............................................................................................................................3-14

CRC and Padding Bytes Removal................................................................................................3-15

Overflow Handling........................................................................................................................3-16

RX Timing Diagrams.................................................................................................................... 3-16

Flow Control...............................................................................................................................................3-17

IEEE 802.3 Flow Control.............................................................................................................. 3-17

Priority-Based Flow Control........................................................................................................ 3-19

Reset Requirements................................................................................................................................... 3-20

Supported PHYs.........................................................................................................................................3-21

10GBASE-R Register Mode..........................................................................................................3-22

XGMII Error Handling (Link Fault).......................................................................................................3-23

IEEE 1588v2................................................................................................................................................3-25

Architecture....................................................................................................................................3-25

Transmit Datapath.........................................................................................................................3-26

Receive Datapath............................................................................................................................3-27

Frame Format.................................................................................................................................3-27

TOC-3

Configuration Registers for LL Ethernet 10G MAC.......................................... 4-1

Register Map.................................................................................................................................................4-1

Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers..................4-2

Register Access............................................................................................................................................. 4-4

Primary MAC Address................................................................................................................................4-5

MAC Reset Control Register......................................................................................................................4-5

TX_Configuration and Status Registers................................................................................................... 4-6

Flow Control Registers..............................................................................................................................4-10

Unidirectional Control Registers.............................................................................................................4-12

RX Configuration and Status Registers.................................................................................................. 4-13

TX Timestamp Registers...........................................................................................................................4-18

Calculating TX Timing Adjustments..........................................................................................4-20

RX Timestamp Registers...........................................................................................................................4-21

Calculating RX Timing Adjustments..........................................................................................4-23

ECC Registers.............................................................................................................................................4-24

Statistics Registers......................................................................................................................................4-25

Interface Signals for LL Ethernet 10G MAC.......................................................5-1

Clock and Reset Signals...............................................................................................................................5-1

Speed Selection Signal................................................................................................................................. 5-3

Error Correction Signals.............................................................................................................................5-3

Unidirectional Signals.................................................................................................................................5-4

Avalon-MM Programming Signals...........................................................................................................5-4

Avalon-ST Data Interfaces..........................................................................................................................5-5

Avalon-ST TX Data Interface Signals........................................................................................... 5-5

Avalon-ST RX Data Interface Signals........................................................................................... 5-6

Avalon-ST Flow Control Signals............................................................................................................... 5-7

Avalon-ST Status Interface.........................................................................................................................5-8

Avalon-ST TX Status Signals..........................................................................................................5-8

Avalon-ST RX Status Signals........................................................................................................5-10

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TOC-4

Low Latency Ethernet 10G MAC User Guide

PHY-side Interfaces...................................................................................................................................5-12

XGMII TX Signals......................................................................................................................... 5-12

XGMII RX Signals......................................................................................................................... 5-15

GMII TX Signals............................................................................................................................ 5-16

GMII RX Signals............................................................................................................................ 5-17

MII TX Signals............................................................................................................................... 5-17

MII RX Signals............................................................................................................................... 5-17

1588v2 Interfaces....................................................................................................................................... 5-18

IEEE 1588v2 Egress Transmit Signals.........................................................................................5-18

IEEE 1588v2 Ingress Receive Signals.......................................................................................... 5-23

Additional Information......................................................................................A-1

Low Latency Ethernet 10G MAC User Guide Document Revision History......................................A-1

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Client

Module

Altera FPGA

External PHY

Interface

Avalon-ST

XGMII/

GMII/MII

10M/100M/

LL 10GbE MAC

PHY

Serial

Interface

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About LL Ethernet 10G MAC

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The Altera® Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) IP core is a configurable component that implements the IEEE 802.3-2008 specification. The MAC IP core offers the following operating modes:

• 10G—single-speed mode that implements the Avalon® Streaming (Avalon-ST) interface on the client side and the 32-bit single data rate (32-bit SDR) XGMII on the network side.

• 1G/10G—dual-speed mode that implements the Avalon-ST interface on the client side and GMII/32bit SDR XGMII on the network side.

• 10M/100M/1G/10G—quad-speed mode that implements the Avalon-ST interface on the client side and MII/GMII/32-bit SDR XGMII on the network side.

To build a complete Ethernet subsystem in an Altera device and connect it to an external device, you can use the LL Ethernet 10G MAC IP core with an Altera PHY IP core such as a soft XAUI PHY or any of the supported PHYs.

The following figure shows a system with the LL Ethernet 10G MAC IP core.

Figure 1-1: Typical Application of LL Ethernet 10G MAC

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1-2

Features

The LL Ethernet 10G MAC supports the following features:

• Full-duplex MAC in four operating modes: 10G, 1G/10G, or 10M/100M/1G/10G).

• Three variations for selected operating modes: MAC Tx only block, MAC Rx only block, and MAC Tx

• Interfaces:

• Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).

• Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC

• Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN

• Optional statistics collection on TX and RX datapaths.

• Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).

• Programmable promiscuous (transparent) mode.

• Optional padding insertion on the TX datapath and termination on the RX datapath.

• Ethernet flow control using pause frames.

• Optional timestamping feature as specified by IEEE 1588v2 for the following configurations:

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and MAC Rx block.

• Client-side—32-bit Avalon-ST interface.

• PHY-side—32-bit XGMII, 16-bit GMII, or 4-bit MII depending on the operating mode.

• Management—32-bit Avalon-MM interface.

checking and forwarding on the RX datapath.

applications.

• 10GbE MAC with 10GBASE-R PHY IP core

• 1G/10GbE MAC with 1G/10GbE PHY IP core

• 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core

• Optional features for 10G operating mode:

• Unidirectional feature as specified by IEEE 802.3 (Clause 66).

• Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority queues.

• Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame. This feature is supported only in the 10G operating mode.

• 10GBASE-R register mode on the TX and RX datapaths, which enables lower latency.

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Release Information

The following table lists information about this release of the LL Ethernet 10G MAC IP core.

Table 1-1: Release Information

Version 15.0

Release Date May 2015

Ordering Code IP-10GEUMAC

Product ID ID 0119

Vendor ID 6AF7

Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function, if this MegaCore function was included in the previous release. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with MegaCore function versions older than the previous release.

Item Description

Release Information

1-3

Related Information

• MegaCore IP Library Release Notes and Errata

• Errata for Low Latency Ethernet 10G MAC MegaCore function in the Knowledge Base

Device Family Support

The IP core provides the following support for Altera device families.

Table 1-2: Device Family Support for LL Ethernet 10G MAC

Device Family Support

With 1588 Feature Without 1588 Feature

Arria® 10 Preliminary -I2 -I3

Arria V GZ Final -I3, -C3 -I4, -C4

Stratix® V Final -I3, -C3 -I4, -C4

The following table lists possible configurations and the devices each configuration supports:

Table 1-3: Device Family Support for Configurations

Minimum Speed Grade

10G MAC with 10GBASE-R PHY Arria V GZ No Yes 10G MAC with 10GBASE-R PHY and IEEE

1588v2

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Configuration Arria V GX/GT/

Arria V GZ No Yes

Arria 10 Stratix V

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1-4

Definition: Device Support Level

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Configuration Arria V GX/GT/

10G MAC with Arria 10 Transceiver Native PHY

No Yes No

Arria 10 Stratix V

presets:

• 10GBASE-R

• 10GBASE-R Low Latency

• 10GBASE-R Register Mode

• 10GBASE-R w/KR-FEC

10M/100M/1G/10G MAC Arria V GZ Yes Yes 10M/100M/1G/10G MAC with IEEE 1588v2 Arria V GZ Yes Yes 10M/100M/1G/10G MAC with Backplane

Arria V GZ Yes Yes

Ethernet 10GBASE-KR PHY 10M/100M/1G/10G MAC with 1G/10GbE PHY

Arria V GZ Yes Yes

MegaCore function and IEEE 1588v2

Definition: Device Support Level

Altera IP cores provide the following support for Altera device families:

• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.

The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution.

• Final support—Altera verifies with IP core with final timing models for this device family. The IP core

meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.

Performance and Resource Utilization

Resource Utilization

The following resource estimation is obtained by compiling the LL 10GbE MAC with the Quartus II software targeting a commercial Stratix V. These estimates are based on the number of ALMs needed minus the recoverable and unavailable ALMs due to the virtual I/Os (in Quartus II Fitter terms). The estimates also apply to other supported devices.

Table 1-4: Resource Utilization for LL Ethernet 10G MAC

MAC Settings

Operating

Mode

10G None. 1,600 2,400 2,800 0 10G Memory-based statistics counters. 2,100 3,200 3,900 4 (M20K) 10M/

100M/ 1G/10G

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Memory-based statistics counters. 2,600 3,900 5,000 4 (M20K)

Enabled Options

ALMs ALUTs

Logic

Registers

Memory Block

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TX and RX Latency

1-5

MAC Settings

Operating

Mode

10M/ 100M/ 1G/10G

Timestamping and memorybased statistics counters.

All options enabled except the options to maintain compatibility with the legacy Ethernet 10G MAC.

TX and RX Latency

The TX and RX latency values are based on the following definitions and assumptions:

• TX latency is the time taken for the data frame to move from the Avalon-ST interface to the PHY-side interface.

• RX latency is the time taken for the data frame to move from the PHY-side interface to the Avalon-ST interface.

• No backpressure on the Avalon-ST TX and RX interfaces.

• All options under Legacy Ethernet 10G MAC interfaces, that allow compatibility with the legacy MAC are disabled.

Enabled Options

Time of day: 96b and 64b.

Time of day: 96b 4,900 6,900 11,000 18 (M20K) Time of day

format: 64b

ALMs ALUTs

Logic

Registers

Memory Block

5,100 7,200 11,700 19 (M20K)

4,300 6,200 10,200 15 (M20K)

5,400 7,600 12,200 27 (M20K)

Table 1-5: TX and RX Latency Values

MAC Operating Mode Speed

TX RX Total

Latency (ns)

10G 10 Gbps 22.4 38.4 60.8

1G/10G 1 Gbps 79.2 277.6 356.8 10M/100M/1G/10G 10 Mbps 1,952.8 27,215.2 29,168 10M/100M/1G/10G 100 Mbps 232.8 2,735.2 2,968

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Getting Started with LL Ethernet 10G MAC

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This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with LL Ethernet 10G MAC. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize the MAC IP core to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports.

Introduction to Altera IP Cores

Altera and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Altera devices. The Quartus® II software installation includes the Altera IP library. You can integrate optimized and verified Altera IP cores into your design to shorten design cycles and maximize performance. You can evaluate any Altera IP core in simulation and compilation in the Quartus II software. The Quartus II software also supports integration of IP cores from other sources. Use the IP Catalog to efficiently parameterize and generate synthesis and simulation files for a custom IP variation.

The Altera IP library includes the following categories of IP cores:

• Basic functions

• DSP functions

• Interface protocols

• Low power functions

• Memory interfaces and controllers

• Processors and peripherals

Note:

The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use the IP Catalog and parameter editor to locate and paramaterize Altera and other supported IP cores.

Related Information

• IP User Guide Documentation

• Altera IP Release Notes

ISO 9001:2008 Registered

acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

2-2

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

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Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

Specifying IP Core Parameters and Options

You can quickly configure a custom IP variation in the parameter editor. Use the following steps to specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.

The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate a simulation testbench, click Generate > Generate Testbench System.

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

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Parameterizing the IP Core

7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

Figure 2-2: IP Parameter Editor

2-3

Parameterizing the IP Core

1. Select the speed for the LL Ethernet 10G MAC IP.

2. Turn on the necessary MAC Options.

3. Type the number of PFC priorities.

4. Select the datapath option.

5. Turn on the necessary resource optimization options. Some options are grayed out if it is not

supported in a selected configuration.

6. Turn on the necessary timestamp options. Some options are grayed out if it is not supported in a selected configuration.

7. Click Finish.

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Parameter Settings

Related Information

• Parameter Settings on page 2-4

Parameter Settings

You customize the MAC IP core by specifying the parameters on the parameter editor in the Quartus II software. The parameter editor enables only the parameters that are applicable to the selected speed.

Parameter Value Description

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Speed 10G, 1G/10G, 10M/

100M/1G/10G

Select the desired speed. By default, 10 Gbps is selected.

If you turn on the Enable 10GBASE-R register mode parameter, only 10 Gbps is available.

Datapath options TX only, RX only, TX &RXSelect the MAC variation to instantiate.

• TX only—instantiates MAC TX.

• RX only—instantiates MAC RX.

• TX & RX—instantiates both MAC TX and RX.

If you turn on the Enable 10GBASE-R register mode parameter, only the TX & RX option is available.

Enable ECC on memory blocks

Enable preamble passthrough mode

On, Off Turn on this option to enable error detection

and correction on memory blocks.

On, Off Turn on this option to enable preamble pass-

through mode. You must also set the tx_

preamble_control, rx_preamble_control,

and rx_custom_preamble_forward registers to

1. When enabled, the MAC IP core allows

custom preamble in data frames on the transmit and receive datapaths.

Enable priority-based flow control (PFC)

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This parameter applies only to 10Gbps MAC variations.

This parameter is not available if you turn on the Enable 10GBASE-R register mode parameter.

On, Off Turn on this option to enable PFC. You must

also set the tx_pfc_priority_enable[n]bit to 1 and specify the number of priority queues in the Number of PFC queues field.

This parameter applies only to 10Gbps MAC variations.

This parameter is not available if you turn on the Enable 10GBASE-R register mode parameter.

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Parameter Settings

Parameter Value Description

Number of PFC queues 2—8 Specify the number of PFC queues. This

parameter is only enabled if you turn Enable priority-based flow control (PFC).

Enable unidirectional feature On, Off Turn on this option to enable unidirectional

feature as specified in the IEEE802.3 specifica‐ tion (Clause 66). This feature is only supported in 10Gbps speed mode.

This parameter is not available if you turn on the Enable 10GBASE-R register mode parameter.

2-5

Enable 10GBASE-R register mode

On, Off Turn on this option to enable 10GBASE-R

register mode on the transmit and receive datapaths to further reduce the MAC and PHY round-trip latency. In this mode, the MAC datapaths must run at 322.265625 MHz. This feature is only supported in 10Gbps speed mode.

Enable supplementary address

On, Off Turn on this option to enable supplementary

addresses. You must also set the EN_SUPP0/1/2/

3 bits in the rx_frame_control register to 1.

Enable statistics collection On, Off Turn on this option to collect statistics on the

transmit and receive datapaths.

Statistics counters Memory-based,

Specify the implementation of the statistics counters. When you turn on Statistics collection, the default implementation of the counters is Memory-based.

• Memory-based—selecting this option frees up logic elements. The MAC IP core does not clear memory-based counters after they are read.

• Register-based—selecting this option frees up the memory. The MAC IP core clears register-based statistic counters after the counters are read.

Enable time stamping

Enable PTP one-step clock support

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On, Off Turn on this option to enable time stamping on

the transmit and receive datapaths. This parameter is not available if you turn on

the Enable 10GBASE-R register mode parameter.

On, Off Turn on this option to enable 1-step time

stamping. This option is enabled only when you turn on time stamping.

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2-6

Generated Files

Parameter Value Description

Timestamp fingerprint width 1–32 Specify the width of the timestamp fingerprint

in bits on the transmit path. The default value is 4 bits.

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Time of Day Format Enable 96b Time of Day

Format only, Enable 64b

Time of Day Format

only, Enable both 96b

and 64b Time of Day

Format

Use legacy Ethernet 10G

On, Off Turn on this option to maintain compability

MAC XGMII

Use legacy Ethernet 10G

On, Off Turn on this option to maintain compability MAC Avalon MemoryMapped Interface

Use legacy Ethernet 10G

On, Off Turn on this option to maintain compability MAC Avalon Streaming Interface

Specify the time of day format.

with the 64-bit Ethernet 10G MAC on the XGMII.

This parameter is not available if you turn on the Enable 10GBASE-R register mode parameter.

with the 64-bit Ethernet 10G MAC on the Avalon-MM Interface.

with the 64-bit Ethernet 10G MAC on the Avalon-ST interface.

This parameter is not available if you turn on the Enable 10GBASE-R register mode parameter.

Generated Files

The following table describes the generated files and other files that might be in your project directory. The names and types of generated files specified in the MegaWizard Plug-In Manager report vary depending on whether you create your design with VHDL or Verilog HDL.

Table 2-1: Generated Files

Extension Description

<variation name>.v or .vhd A MegaCore function variation file, which defines a VHDL or Verilog HDL

<variation name>.cmp A VHDL component declaration file for the MegaCore function variation.

<variation name>.qsys A Qsys file for the MAC IP core design.

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description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.

Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.

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Extension Description

<variation name>.qip Contains Quartus II project information for your MegaCore function

variation.

<variation name>.bsf Quartus II symbol file for the MegaCore function variation. Use this file in

the Quartus II block diagram editor.

<variation name>.sip Contains IP core library mapping information required by the Quartus II

software.The Quartus II software generates a . sip file during generation of some Altera IP cores. You must add any generated .sip file to your project for use by NativeLink simulation and the Quartus II Archiver.

<variation name>.spd Contains a list of required simulation files for your MegaCore function.

Simulating Altera IP Cores in other EDA Tools

The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

Simulating Altera IP Cores in other EDA Tools

2-7

You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink launches your preferred simulator from within the Quartus II software.

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Post-fit timing

simulation netlist

Post-fit timing simulation (3)

Post-fit functional

simulation netlist

Post-fit functional

simulation

Analysis & Synthesis

Fitter

(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow

Gate-Level Simulation

Post-synthesis

functional

simulation

Post-synthesis functional

simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry

(HDL, Qsys, DSP Builder)

Altera Simulation

Models

EDA Netlist Writer

2-8

Upgrading Outdated IP Cores

Figure 2-3: Simulation in Quartus II Design Flow

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Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current

version of the Quartus II software. Altera IP supports a variety of simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

Related Information

Simulating Altera Designs

Upgrading Outdated IP Cores

Altera IP components are version-specific with the Quartus II software. The Quartus II software alerts you when your IP core is outdated. Click Project > Upgrade IP Components to easily identify and upgrade outdated IP cores.

To upgrade outdated IP cores appropriately, your restored project archive must retain the original Quartus II-generated file structure. Failure to upgrade outdated IP cores can result in a mismatch between the outdated IP core variation and the current supporting libraries.

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Migrating IP Cores to a Different Device

Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. The MegaCore IP Library Release Notes and Errata reports any verification exceptions. Altera does not verify compilation for IP cores older than the previous release.

Figure 2-4: Upgrading IP Components in Project Navigator

Related Information

MegaCore IP Library Release Notes and Errata

2-9

Migrating IP Cores to a Different Device

IP migration allows you to target the latest device families with IP originally generated for a different device. Some Altera IP cores migrate automatically, some IP cores require manual IP regeneration, and some do not support device migration and must be replaced in your design. The text and icons in the Upgrade IP Components dialog box identifies the migration support for each IP core in the design.

Note:

Migration of some IP cores requires installed support for the original and migration device families. For example, migration from a Stratix V device to an Arria 10 device requires installation of Stratix V and Arria 10 device families with the Quartus II software.

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Double-click to upgrade in editor (no auto upgrade)

Upgrade required

Migration details

Supports Auto upgrade

Upgrade success

2-10

Migrating IP Cores to a Different Device

Figure 2-5: Upgrading IP Cores

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1. Click File > Open Project and open the Quartus II project containing IP for migration to another

device in the original version of the Quartus II software.

2. To specify a different target device for migration, click Assignments > Device and select the target

device family.

3. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description

field prompts you to run auto update or double-click IP cores for migration.

4. To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status and

Version columns update when upgrade is complete.

5. To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and then click OK. The parameter editor appears.

a. If the parameter editor specifies a Currently selected device family, turn off Match project/

default, and then select the new target device family.

b. Click Finish to migrate the IP variation using best-effort mapping to new parameters and settings.

A new parameter editor opens displaying best-effort mapped parameters.

c. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog HDL is

the defauilt output file format specified. If your original IP core was generated for VHDL, select VHDL to retain the original output format.

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Design Considerations

2-11

6. To regenerate the new IP variation for the new target device, click Generate. When generation is complete, click Close.

7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core files. The Device Family column displays the new target device name when migration is complete. The migration process replaces <my_ip>.qip with the <my_ip>.qsys top-level IP file in your project.

Note: If migration does not replace <my_ip>.qip with <my_ip>.qsys, click Project > Add/Remove

Files in Project to replace the file in your project.

8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration

may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>.bsf after migration.

Note: The migration process may change the IP variation interface, parameters, and functionality.

This may require you to change your design or to re-parameterize your variant after the Upgrade IP Components dialog box indicates that migration is complete. The Description field identifies IP cores that require design or parameter changes.

Related Information

Altera IP Release Notes

Design Considerations

Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC

Altera recommends the following migration path. Migrating your existing design in this manner allows you to take advantage of the benefits of LL Ethernet 10G MAC—low resource count and low latency.

Migration—32-bit Datapath on Avalon-ST Interface

This migration path implements 32-bit datapath on the Avalon ST and Avalon-MM interfaces.

1. Instantiate the LL Ethernet 10G MAC IP core in your design. If you are using a PHY with 64-bit SDR XGMII interface, turn on the Use legacy Ethernet 10G MAC XGMII Interface option.

2. Modify your user logic to accommodate 32-bit datapaths on Avalon-ST TX and RX data interfaces.

3. Ensure that tx_312_5_clk and rx_312_5_clk are connected to 312.5-MHz clock sources. Altera

recommends that you use the same clock source for these clock signals.

4. Update the register offsets to the offsets of the LL Ethernet 10G MAC. The configuration registers of the LL Ethernet 10G MAC allow access to new features such as error correction and detection on memory blocks.

5. If you turn on the Use legacy Ethernet 10G MAC XGMII Interface option, add a 156.25 MHz clock source for tx_156_25_clk and rx_156_25_clk. This 156.25 MHz clock source must be rise-to-rise synchronous to the 312.5 MHz clock source.

6. Ensure that csr_clk is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be accurate.

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Migration—Maintains 64-bit on Avalon-ST Interface

This migration path implements 32-bit to 64-bit adapters on the Avalon ST interface and XGMII, and uses the same register offsets to maintain backward compatibility with the legacy 10-Gbps Ethernet (10GbE) MAC IP Core.

1. Instantiate the LL Ethernet 10G MAC IP core in your design. To maintain compatibility on the interfaces, turn on the Use legacy Ethernet 10G MAC XGMII Interface, Use legacy Ethernet 10G

MAC Avalon Memory-Mapped Interface, and Use legacy Ethernet 10G MAC Avalon Streaming Interface options.

2. Ensure that tx_312_5_clk and rx_312_5_clk are connected to 312.5-MHz clock sources. Altera

recommends that you use the same clock source for these clock signals.

3. Add a 156.25-MHz clock source for tx_156_25_clk and rx_156_25_clk. This 156.25 MHz clock source must be rise-to-rise synchronous to the 312.5 MHz clock source.

4. Ensure that csr_clk is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be accurate.

Timing Constraints

Altera provides timing constraint files (.sdc) to ensure that the IP core meets the design timing requirements in Altera devices. The files constraints the false paths and multi-cycle paths in the IP core. The timing constraints files are specified in the <variation_name>.qip file and is automatically included in the Quartus II project files.

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The timing constraints files are in the IP directory. You can edit these files as necessary. They are for clock crossing logic and grouped as below:

• Pseudo-static CSR fields

• Clock crosser

• Dual clock FIFO

Note:

For the IP to work correctly, there must be no other timing constraints files cutting or overriding the paths, for example, set_false_path, set_clock_groups, at the project level.

Pseudo-Static CSR Fields

Most of the configuration registers in the MAC IP core must not be programmed when the MAC is in operation. As such, they are not synchronized to reduce resource usage. These registers are all in the

set_false_path constraint.

Clock Crosser

Clock crossers perform multi-bit signals crossing from one clock domain to another. The working principle of the clock crosser is to let the crossed-over data stabilize first before indicating

that the data is valid in the latched clock domain. Using such structure, the data bits must not skew for more than one latched clock period. The timing constraint file applies a common timing check over all the clock crossers irrespective of their latched clock domain. This is over-pessimistic for signals crossing into the CSR clock, but there are no side-effects, like significant run-time impact and false violations, during the internal testing. If your design runs into clock crosser timing violation paths within the IP and the latched clock domain is csr_clk, you can dismiss the violation manually or by editing the .sdc file if the violation is less than one csr_clk period.

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Dual Clock FIFO

2-13

The timing constraint file uses the set_net_delay to constraint the fitter placement and set_max_skew to perform timing check on the paths. For a project with very high device utilization, Altera recommends that you implement addition steps like floor planning or LogicLock to aid the place-and-route process. The additional steps can give a more consistent timing closure along these paths instead of only relying on the set_net_delay.

A caveat of using set_max_skew is that it does not analyze whether the insertion delay of the path in concern exceeds a limit. In other words, a path could meet skew requirement but have longer than expected insertion delay. If this is not checked, it may cause functional failure in certain latency-sensitive paths. Therefore, a custom script (alt_em10g32_clock_crosser_timing_info.tcl) is available for you to check that the round-trip clock crosser delay is within expectation. To use this script, manually add it to the user flow and run it. To ensure that the IP core operates correctly, the results must be positive (no error).

The bit skew of the dual clock FIFO gray-coded pointers must be within one 312.5 MHz clock period. The timing constraint file uses the set_net_delay to constraint the fitter placement and set_max_skew to

perform timing check on the paths. For a project with very high device utilization, Altera recommends that you implement addition steps like floor planning or LogicLock to aid the place-and-route process. The additional steps can give a more consistent timing closure along these paths instead of only relying on the set_net_delay.

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MAC TX

Control & Status

Registers

MAC RX

Clock & Reset

LL Ethernet 10G MAC

CSR Adapter

(Optional)

Avalon-ST 32/64b Adapter

(Optional)

XGMII SDR 32/64b Adapter

(Optional)

32-Bit XGMII Transmit Interface 8-Bit GMII Transmit Interface 4-Bit MII Transmit Interface

32-Bit XGMII Receive Interface 8-Bit GMII Receive Interface 4-Bit MII Receive Interface

64-Bit XGMII

Receive Interface

64-Bit XGMII

Transmit Interface

64-Bit XGMII

Receive Interface

64-Bit XGMII

Transmit Interface

Flow

Control

Link

Fault

Respective Domains

Clock & Reset

Signals

Clock & Reset

Signals

Clock & Reset

Signals

32-Bit Avalon-ST

Transmit Interface

32-Bit Avalon-MM

Interface

32-Bit Avalon-ST

Receive Interface

Notes: (1) Applies to 1G/10G and Multi Speed MAC only. (2) Applies to Multi Speed MAC only.

(1)

(2)

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Functional Description of LL Ethernet 10G MAC

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The Low Latency (LL) Ethernet 10G MAC IP core handles the flow of data between a client and an Ethernet network through an Ethernet PHY. On the transmit path, the MAC IP core accepts client frames and constructs Ethernet frames by inserting various control fields, such as checksums before forwarding them to the PHY. Similarly, on the receive path, the MAC accepts Ethernet frames via a PHY, performs checks, and removes the relevant fields before forwarding the frames to the client. You can configure the MAC IP core to collect statistics on both transmit and receive paths.

Architecture

The LL Ethernet 10G MAC IP core is a composition of the following blocks: MAC receiver (MAC RX), MAC transmitter (MAC TX), configuration and status registers, and clock and reset.

Figure 3-1: LL Ethernet 10G MAC Block Diagram

ISO 9001:2008 Registered

3-2

Interfaces

Table 3-1: Interfaces

Interfaces Description

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Avalon-ST Interface

The client-side interface of the MAC employs the Avalon-ST protocol, which is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of the data (sink). The key properties of this interface include:

• Frame transfers marked by startofpacket and endofpacket signals.

• Signals from source to sink are qualified by the valid signal.

• Errors marking a current packet are aligned with the end-of-packet cycle.

• Use of the ready signal by the sink to backpressure the source. In the MAC IP core, the Avalon-ST interface acts as a sink in the TX

datapath and source in the RX datapath. This interface supports packets, backpressure, and error detection. It operates at 312.5 MHz. The ready latency on this interface is 0.

Avalon-MM Control and Status Register Interface

The Avalon-MM control and status register interface is an Avalon-MM slave port. This interface uses word addressing which provides access to the configuration and status registers, and statistics counters.

XGMII In 10G mode, the network-side interface of the MAC IP core implements the

XGMII protocol. Depending on the configuration, the XGMII consists of 32or 64-bit data bus and 4- or 8-bit control bus operating at 312.5 MHz. This interface operates at 322.265625 MHz if the 10GBASE-R register mode is enabled. The data bus carries the MAC frame with the most significant byte occupying the least significant lane.

GMII

MII In 10M or 100M mode, the network-side interface of the MAC IP core

Altera Corporation

In 1G/10G and 10M/100M/1G/10G operating modes, the network-side interface of the MAC IP core implements 8 bits wide GMII protocol when the MAC operates at 1 Gbps. This 8-bit interface supports gigabit operations at 125 MHz.

implements the MII protocol. This 4-bit MII supports 10-Mbps and 100Mbps operations at 125 MHz, with a clock enable signal that divides the clock to effective rates of 2.5 MHz for 10 Mbps and 25 MHz for 100 Mbps.

Functional Description of LL Ethernet 10G MAC

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MAC RX

Clock and

Reset

csr_clk csr_rst_n tx_312_5_clk tx_156_25_clk

rx_156_25_clk

rx_rst_n

tx_rst_n

rx_312_5_clk

Avalon-MM Control and

Status Interface

csr_read csr_readdata[31:0] csr_write csr_writedata[31:0] csr_address[12:0] csr_waitrequest

XGMII Transmit

MAC TX

xgmii_tx_data[31:0]

link_fault_status_xgmii_tx_data[1:0]

GMII Transmit (1G/10Gbps, multi-speed)

gmii_tx_clk

gmii_tx_d[7:0]

gmii_tx_en gmii_tx_err

MII Transmit (multi-speed)

tx_clkena

tx_clkena_half_rate

mii_tx_d[3:0]

mii_tx_en

mii_tx_err

Avalon-ST Transmit

Data Interface

avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_valid avalon_st_tx_ready avalon_st_tx_error avalon_st_tx_data[31:0] avalon_st_tx_empty[1:0]

Avalon-ST Transmit

Flow Control Interface

avalon_st_pause_data[1:0] avalon_st_tx_pause_length_valid avalon_st_tx_pause_length_data[15:0] avalon_st_tx_pfc_gen_data[n]

Avalon-ST Transmit

Status Interface

avalon_st_txstatus_valid avalon_st_txstatus_data[39:0] avalon_st_txstatus_error[6:0] avalon_st_tx_pfc_status_valid

avalon_st_tx_pfc_status_data[n]

IEEE 1588v2 Interface

tx_egress_timestamp_request_valid

tx_egress_timestamp_request_fingerprint[n]

tx_path_delay_10g_data[15:0]

xgmii_rx_data[31:0]

link_fault_status_xgmii_rx_data[1:0]

XGMII Receive

gmii_rx_clk

gmii_rx_d[7:0]

gmii_rx_dv gmii_rx_err

GMII Receive (1G/10Gbps, multi-speed)

rx_clkena

rx_clkena_half_rate

mii_rx_d[3:0]

mii_rx_dv

mii_rx_err

MII Receive (multi-speed)

avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_valid avalon_st_rx_ready avalon_st_rx_error[5:0] avalon_st_rx_data[31:0] avalon_st_rx_empty[1:0]

Avalon-ST Receive

Data Interface

avalon_st_rx_pause_length_valid avalon_st_rx_pause_length_data[15:0]

avalon_st_rx_pfc_pause_data[n]

Avalon-ST

Receive Flow

Control Interface

avalon_st_rxstatus_valid avalon_st_rxstatus_data[39:0] avalon_st_rxstatus_error[6:0] avalon_st_rx_pfc_status_valid avalon_st_rx_pfc_status_data[n]

Avalon-ST Receive

Status Interface

rx_ingress_timestamp_96b_data[95:0]

rx_ingress_timestamp_96b_valid

rx_path_delay_10g_data[15:0]

IEEE 1588v2 Time-Stamp Interface

speed_sel

ecc_err_det_corr

ecc_err_det_uncorr

tx_xcvr_clk

rx_xcvr_clk

xgmii_tx_control[3:0]

unidirectional_en

unidirectional_remote_fault_dis

LL Ethernet 10G MAC

Avalon-MM

Control and Reset

xgmii_rx_control[3:0]

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Figure 3-2: Interface Signals

The inclusion and width of some signals depend on the operating mode and features selected.

Interfaces

3-3

Related Information

Interface Signals for LL Ethernet 10G MAC on page 5-1

Describes each signal in detail.

Functional Description of LL Ethernet 10G MAC

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Client - MAC Tx Interface

(optional)

Client Frame

MAC Frame

Destination Addr[47:0]

Source

Addr[47:0]

Type/

Length[15:0]

Payload

[<p-1>:0]

Destination Addr[47:0]

SFD[7:0]

Preamble

[55:0]

CRC32 [31:0]

PAD [<s>]

Source

Addr[47:0]

Client-Defined Preamble

[63:0]

(optional)

Type/

Length[15:0]

Payload

[<p-1>:0]

PAD [<s>]

CRC32 [31:0]

EFD[7:0]

IPG

[<l-1>:0]

Frame Length

(1) (2)

(3)

3-4

Frame Types

The MAC IP core supports the following frame types:

• Basic Ethernet frames, including jumbo frames.

• VLAN and stacked VLAN frames.

• Control frames, which include pause and PFC frames.

TX Datapath

The MAC TX receives the client payload data with the destination and source addresses, and appends various control fields depending on the MAC configuration.

Figure 3-3: Typical Client Frame at TX Interface

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Padding Bytes Insertion

Address Insertion

Altera Corporation

By default, the MAC TX inserts padding bytes (0x00) into TX frames to meet the following minimum payload length:

• 46 bytes for basic frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames Ensure that CRC-32 insertion is enabled when padding bytes insertion is enabled. You can disable padding bytes insertion by setting the tx_pad_control register to 0. When disabled, the

MAC IP core forwards the frames to the PHY-side interface without padding. Ensure that the minimum payload length is met; otherwise the current frame may get corrupted. You can check for undersized frames by referring to the statistics collected.

By default, the MAC TX retains the source address received from the client. You can configure the MAC TX to replace the source address with the primary MAC address specified in the tx_addrins_macaddr0 and tx_addrins_macaddr1 registers by setting the bit tx_src_addr_override[0] to 1.

Functional Description of LL Ethernet 10G MAC

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tx_312_5_clk

avalon_st_tx_ready

avalon_st_tx_valid

avalon_st_tx_startofpacket

avalon_st_tx_endofpacket

avalon_st_tx_data[31:0]

avalon_st_tx_empty[1:0]

avalon_st_tx_error

...00000000

rx_312_5_clk

avalon_st_rx_ready

avalon_st_rx_valid

avalon_st_rx_startofpacket

avalon_st_rx_endofpacket

avalon_st_rx_data[31:0]

avalon_st_rx_empty[1:0]

avalon_st_rx_error[5:0]

...4EB30AF4

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CRC-32 Insertion

By default, the MAC TX computes and inserts CRC-32 checksum into TX frames. The MAC TX computes the CRC-32 checksum over frame bytes that include the source address, destination address, length, data, and padding bytes. The computation excludes the preamble and SFD bytes. The MAC TX then inserts the CRC-32 checksum into the TX frame. Bit 31st of the checksum occupies the least signifi‐ cant bit of the first byte in the CRC field.

You can disable this function by setting the tx_crc_control[1] register bit to 0. The following figure shows the timing diagram on the Avalon-ST data interfaces where CRC insertion is

enabled on transmit and CRC removal is disabled on receive. The frame from the client is without CRC-32 checksum. The MAC TX inserts the CRC-32 checksum (4EB00AF4) into the frame. The frame is then looped back to the RX datapath with the CRC-32 checksum.

Figure 3-4: Avalon-ST TX and RX Interfaces with CRC Insertion Enabled

CRC-32 Insertion

3-5

Functional Description of LL Ethernet 10G MAC

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tx_312_5_clk

avalon_st_tx_ready

avalon_st_tx_valid

avalon_st_tx_startofpacket

avalon_st_tx_endofpacket

avalon_st_tx_data[31:0]

avalon_st_tx_empty[1:0]

avalon_st_tx_error

rx_312_5_clk

avalon_st_rx_ready

avalon_st_rx_valid

avalon_st_rx_startofpacket

avalon_st_rx_endofpacket

avalon_st_rx_data[31:0]

avalon_st_rx_empty[1:0]

avalon_st_rx_error[5:0]

...4EB30AF4

3-6

XGMII Encapsulation

The following figure shows the timing diagram on the Avalon-ST data interfaces where CRC insertion is disabled on transmit and CRC removal is disabled on receive. The MAC TX receives the frame from the client with a CRC-32 checksum (4EB00AF4). The frame with the same CRC-32 checksum is then looped back to the RX datapath.

Figure 3-5: Avalon-ST TX and RX Interface with CRC Insertion Disabled

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XGMII Encapsulation

By default, the MAC TX inserts 7-byte preamble, 1-byte SFD and 1-byte EFD (0xFD) into frames received from the client.

The MAC TX also supports custom preamble in 10G operations. To use custom preamble, set the

tx_preamble_control register to 1. In this mode, the MAC TX accepts the first 8 bytes in the frame from

the client as custom preamble and inserts only 1-byte EFD (0xFD) into the frame. The MAC TX also replaces the first byte of the preamble with 1-byte START (0xFB).

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Functional Description of LL Ethernet 10G MAC

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An underflow could occur on the Avalon-ST TX interface. An underflow occurs when the

avalon_st_tx_valid signal is deasserted in the middle of frame transmission. When this happens, the

10GbE MAC TX inserts an error character |E| into the frame and forwards the frame to the XGMII.

Inter-Packet Gap Generation and Insertion

The MAC TX maintains an average IPG between TX frames as required by the IEEE 802.3 Ethernet standard. The average IPG is maintained at 96 bit times (12 byte times) using the deficit idle count (DIC). The MAC TX inserts or deletes idle bytes depending on the value of the DIC; the DIC must be between 9 to 15 bytes. Averaging the IPG ensures that the MAC utilizes the maximum available bandwidth.

XGMII Transmission

On the XGMII, the MAC TX performs the following:

• Aligns the first byte of the frame to lane 0 of the interface.

• Performs endian conversion. Transmit frames received from the client on the Avalon-ST interface are big endian. Frames transmitted on the XGMII are little endian; the MAC TX therefore transmits frames on this interface from the least significant byte.

The following figure shows the timing on the Avalon-ST TX data interface and XGMII. The least signifi‐ cant byte of the value in D5 is transmitted first on the XGMII.

Inter-Packet Gap Generation and Insertion

3-7

Functional Description of LL Ethernet 10G MAC

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(1)

D5 CC CC EE 01 05 09 0D

(1)

55 88 EE AA 00 04 08 0C

(1)

55 EE CC 2E 03 07 0B 0F

FB 55 EE AA 88 00 02 06 0A 0E

tx_312_5_clk

0 4

D2 D3 D4 D5 D6 D7 D8

15 19 1D 21 25 29 2D F4 07

14 18 1C 20 24 28 2C 0A 07

13 17 1F 23 27 2B B3 07

12 16 1A 1E 22 26 2A 4E FD

0 4

D10 D11 D12 D13 D14 D15

D16 D17

D1: 555555D5 D2: EECC88CC D3: AAEEEECC D4: 88CCAAEE D5: 002E0001 D6: 02030405 D7: 06070809 D8: 0A0B0C0D D9: 0E0F1011 D10: 12131415 D11: 16171819 D12: 1A1B1C1D D13: 1E1F2021 D14: 22232425 D15: 26272829 D16: 2A2B2C2D D17: 4EB30AF4

avalon_st_tx_ready

avalon_st_tx_valid

avalon_st_tx_startofpacket

avalon_st_tx_endofpacket

avalon_st_tx_data[31:0]

avalon_st_tx_empty[1:0]

avalon_st_tx_error

tx_312_5_clk

xgmii_tx_control[3]

xgmii_tx_data[31:24]

xgmii_tx_control[2]

xgmii_tx_data[23:16]

xgmii_tx_control[1]

xgmii_tx_data[15:8]

xgmii_tx_control[0]

xgmii_tx_data[7:0]

Data value:

3-8

Unidirectional Feature

Figure 3-6: Endian Conversion

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Unidirectional Feature

The MAC TX implements the unidirectional feature as specified by clause 66 in the IEEE802.3 specifica‐ tion. This is an optional feature supported only in 10G operations. When you enable this feature, two output ports—unidirectional_en, unidirectional_remote_fault_dis— and two register fields—

UniDir_En (Bit 0), UniDirRmtFault_Dis (Bit 1)— are accessible to control the TX XGMII interface.

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Functional Description of LL Ethernet 10G MAC

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+ 79 hidden pages

Altera Low Latency Ethernet 10G MAC User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About LL Ethernet 10G MAC

Features

Release Information

Device Family Support

Definition: Device Support Level

Performance and Resource Utilization

Resource Utilization

TX and RX Latency

Getting Started with LL Ethernet 10G MAC

Introduction to Altera IP Cores

Installing and Licensing IP Cores

Specifying IP Core Parameters and Options

Parameterizing the IP Core

Parameter Settings

Generated Files

Simulating Altera IP Cores in other EDA Tools

Upgrading Outdated IP Cores

Migrating IP Cores to a Different Device

Design Considerations

Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC

Migration—32-bit Datapath on Avalon-ST Interface

Migration—Maintains 64-bit on Avalon-ST Interface

Timing Constraints

Pseudo-Static CSR Fields

Clock Crosser

Dual Clock FIFO

Functional Description of LL Ethernet 10G MAC

Architecture

Interfaces

Frame Types

TX Datapath

Padding Bytes Insertion

Address Insertion

CRC-32 Insertion

XGMII Encapsulation

Inter-Packet Gap Generation and Insertion

XGMII Transmission

Unidirectional Feature