Altera LCD Multimedia HSMC User Manual
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San Jose, CA 95134
www.altera.com
LCD Multimedia HSMC
Reference Manual
Document Date: August 2008
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Part Number MNL-01028-1
ii Development Board Version 1.0.0 Altera Corporation
LCD Multimedia HSMC Reference Manual August 2008
Contents
Chapter 1. Overview
General Description ............................................................................................................................... 1–1
Components and Block Diagram ................................................................................................... 1–3
Block Diagram .................................................................................................................................. 1–4
Chapter 2. Board Components and Interfaces
Board Overview ..................................................................................................................................... 2–1
Interface Device ..................................................................................................................................... 2–4
MAX II CPLD-EPM2210F324 (U4) ................................................................................................. 2–4
Block Diagram of bus-controller logic in the MAX II CPLD ..................................................... 2–6
Level Translator ..................................................................................................................................... 2–8
Bidirectional level shift interface .................................................................................................... 2–8
Display .................................................................................................................................................. 2–10
LCD Touch Panel Display ............................................................................................................. 2–10
Interfaces/Connectors ........................................................................................................................ 2–15
Audio Codec Interface ................................................................................................................... 2–15
SD Card ............................................................................................................................................ 2–17
Ethernet PHY .................................................................................................................................. 2–19
RS232 Serial Interface ..................................................................................................................... 2–21
PS/2 Interface ................................................................................................................................. 2–22
Video Decoder Interface ................................................................................................................ 2–23
NTSC PAL Video Decoder Circuit .............................................................................................. 2–25
VGA DAC Interface ....................................................................................................................... 2–26
Clocking Circuitry ............................................................................................................................... 2–30
Power Supply ....................................................................................................................................... 2–31
Power Supplies ............................................................................................................................... 2–31
EEPROM ............................................................................................................................................... 2–32
I2C Serial EEPROM ........................................................................................................................ 2–32
Expansion Interface ............................................................................................................................. 2–34
HSMC Interface .............................................................................................................................. 2–34
Statement of China-RoHS Compliance ............................................................................................ 2–35
Appendix A. Pin Connections HSMC.FPGA for the Cyclone III Starter Board
Introduction ........................................................................................................................................... A–1
Additional Information
Revision History ......................................................................................................................................... i
How to Contact Altera ............................................................................................................................... i
Typographic Conventions ......................................................................................................................... i
Altera Corporation iii
August 2008 Preliminary
1. Overview
General Description
This manual provides comprehensive information about the LCD
Multimedia High Speed Mezzanine Card (HSMC). This HSMC is a fullfeatured multimedia board that can be used for video, audio, and
ethernet applications with many of the Altera FPGA Starter and
Development boards that support the HSMC connectors. For example,
see Figures 1–1
The LCD Multimedia HSMC was created to provide a set of interfaces
including LCD touchscreen, VGA out, composite video in, audio in/out,
microphone in, plus Ethernet, SD-Card, PS/2, and RS-232 interfaces. The
purpose of this reference manual is to describe each of these hardware
interfaces on the LCD HSMC.
.
f For the latest information about available HSMC boards, go to
www.altera.com/products/devkits/kit-index.html.
Figure 1–1. LCD Multimedia HSMC in Nios II Embedded Evaluation Kit
LCD Multimedia HSMC
Cyclone III FPGA Starter Board
The top view of the LCD Multimedia HSMC is shown in Figure 1–2.
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August 2008 Preliminary
There are several sample software applications that highlight the LCD
Touchpanel, SD-Card, and Ethernet components of the LCD Multimedia
HSMC in the Nios II Development Kits.
f For more information, refer Nios II Embedded Evaluation kit Getting Started
User Guide as an example.
Figure 1–2. Top View of the LCD Multimedia HSMC
Connector view1 and connector view2 of the LCD Multimedia HSMC is
shown in Figure 1–3 and Figure 1–4.
1–2 Altera Corporation
LCD Multimedia HSMC August 2008
Figure 1–3. LCD Multimedia HSMC Side View 1
Overview
RS-232
VGA Out
Figure 1–4. LCD Multimedia HSMC Side View 2
SD-Card
Composite
Video In
Ethernet
RJ-45
Audio Out
PS/2
Audio In
Microphone In
Components and Block Diagram
The LCD Multimedia HSMC contains the following components.
■ MAX II CPLD EPM2210F324
● 2210 Logic elements
● 272 User I/Os
● 324 pin FineLine BGA package
■ LCD Touch-screen Display
● 800 X 480 pixel 4.3" Display
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August 2008 LCD Multimedia HSMC
■ 24-bit Audio Codec
■ SD Flash Connector
■ 10/100 Ethernet physical layer (PHY)
■ PS/2 Connector
■ Other Interfaces
● RS-232 Level-shifters
● RCA Jack (Video In)
● 10-bit VGA Output DAC
● Composite Video ADC
Block Diagram
Figure 1–5 shows a functional block diagram of the LCD Multimedia
HSMC.
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LCD Multimedia HSMC August 2008
Figure 1–5. LCD Multimedia HSMC
HSMC
Connector
MAXII CPLD & Level Shift
BUS
Controller
Overview
24-bit AUDIO CODEC
VGA 10-bit Video DAC
Video decoder
PS2 & RS232 Ports
LCD Touch Panel
module
10/100 Ethernet PHY
SD Card
I2C EEPROM
100M Hz OSC
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August 2008 LCD Multimedia HSMC
2. Board Components and Interfaces
Board Overview
f For information on powering-up the LCD Multimedia HSMC and
This chapter provides operational and connectivity detail for the LCD
Multimedia HSMC's major components and interfaces and is divided
into the following major blocks:
■ MAX II CPLD used for
● Time-division multiplexing of signals
● Voltage level shifting
■ Interfaces
● HSMC expansion interface
● Audio codec interface
● Video decoder interface
● VGA interface
● Serial interface
● PS/2 interface
● Ethernet
■ Clocking circuitry
■ Memory
■ Power supply
1 Board schematics, board layout database, and assembly files for
the LCD Multimedia HSMC are included in the
board_design_files subdirectory of the installed kit directory.
installing the demo software and examples, refer to the user guide
provided with your kit.
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August 2008 Preliminary
Figure 2–1 shows the top view of the LCD Multimedia HSMC.
C
Figure 2–1. Top View of the LCD Multimedia HSMC
Board Components and Interfaces
RS-232 PortVGA Video PortVideo inLine OutLine inMic in
VGA 10-bit DA
24-bit Audio Codec
Video Decoder
(NTSC/PAL)
Altera MAX II 2210
CPLD device
100-MHz Oscillator
Notes:
(1) LCD Touch Panel is not shown.
LCD Touch Panel Connector
Ethernet 10/100M PHY
EEPROM
PS/2 Keyboard/
Mouse Port
Ethernet
10/100M Port
SD Card Slot
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August 2008 LCD Multimedia HSMC
Figure 2–2 shows the back view of the LCD Multimedia HSMC.
Figure 2–2. Back View of the LCD Multimedia HSMC
Table 2–1 lists the components and their corresponding board references.
HSMC Connector
Table 2–1. LCD Multimedia HSMC (Part 1 of 2)
Typ e
Interface Device
CPLD MAX II U4 EPM2210F324C4, 272-pin FineLine BGA
Level Translator
I/O Bidirectional
Display
I/O LCD Touch
Connections & Interfaces
Input MIC In J1, U1 Microphone in jack 2–15
2–3 Altera Corporation
LCD Multimedia HSMC August 2008
Component/
Interface
Level Shift
Interface
Screen
Display
Board Reference Description Page
2–4
324-pin package
U10, U11 MAX 3378 Dual Low-Voltage Level
Translators
J10 +Touchscreen, U6 FPC 60B connector 2–10
2–8
Table 2–1. LCD Multimedia HSMC (Part 2 of 2)
Board Components and Interfaces
Typ e
Input Line In J2, U1 24 bit CD quality audio CODEC 2–15
Output Line Out J3, U1 24 bit CD quality audio CODEC 2–15
Input SD Card
I/O Ethernet J5, U2 10/100 Ethernet PHY/MAC controller 2–19
I/O RS 232 J8, U5 9 pin connector and transceiver 2–21
I/O PS/2 J9 5 pin connector, mouse/ keyboard connector 2–22
Input Video
Output VGA J12, U9
Clock Circuitry
Oscillator Clock Y1, Y2, Y3 Various clock oscillators used for system
Powe r Supply
Powe r
Supplies
EEPROM
Memory I2C EEPROM U3 Uses one 2K bit EEPROM. 2–32
Expansion Interface
I/O HSMC J6 Expansion connector used to interface with
Component/
Interface
Socket
Decoder
Analog/Digital
Power
Board Reference Description Page
J4 128 MB Memory Card 2–17
J11 RCA jack 2–23
2–26
2–30
2–31
2–34
Reg1, Reg2, Reg3,
Reg4, Reg5
One VGA output connector (DB15)
10-bit VGA DAC
clock or other dedicated devices.
Switching and linear regulators used for
powering analog and digital components.
Altera starter and development boards
, and
Interface Device
MAX II CPLD-EPM2210F324 (U4)
The LCD Multimedia HSMC uses the MAX II 2210 CPLD
EPM2210F324C3 device (U4)
. Table 2–2 lists MAX II CPLD board
reference and manufacturing information.
Table 2–2. MAX II CPLD Manufacturing Information
Board Reference Device Description Manufacturer
U4 MAX II CPLD for TDM and
level shifting/buffering
Altera Corporation 2–4
August 2008 LCD Multimedia HSMC
Altera EPM2210F324C3N www.altera.com
Manufacturer Part
Number
Manufacturer
Website
Interface Device
The primary functions for this device are to
1. Provide time-division multiplexing (TDM) functions to the LCD
and VGA color data bus.
2. Provide level shifting feature for the 2.5V input (Cyclone III FPGA)
and 3.3V required by many of the interface chips.
This package has 272 user I/Os and comes in a 324-pin Fine-Line BGA
package. Table 2–3 lists Max II device features.
Table 2–3. Max II Device Features
Architectural Feature Results
Altera’s second generation
low-cost CPLDs
Lowest power
consumption CPLD
On-chip user Flash memory ● 8kbit user accessible flash memory
● Low cost packaging
● Large number of logic elements
● LUT based architecture
● Fastest CPLD supports up to 300MHz clock frequency
● Power down capability that conserves the battery life
● Lowest dynamic power
● Hot-socketing support
● Single power supply simplicity
● Enables the integration of discrete and non-volatile storage
reducing chip count and cost
Real time In-signal
programmability
I/O capabilities
● Capable of downloading a second design while the device is
operational
● Supports interfacing with 1.8V, 2.5V and 3.3V logic levels of the
device due to Multivolt I/O capability
● Schmitt triggers, programmable slew rate & programmable drive
strength improve signal integrity
2–5 Altera Corporation
LCD Multimedia HSMC August 2008
Board Components and Interfaces
Table 2–4 lists the Max II EPM2210F324C4 device pin count.
Table 2–4. Max II Device Pin Count
Board Component Pins
SD Card 6
Ethernet 18
Audio Codec 6
RS232 and PS/2 4
LCD Touch Panel 38
Video Decoder 14
VGA 25
MAX II CPLD ISP 4
HSMC(1) 88
Total Pins Used 203
Total EPM2210F324C4 User I/Os 272
Unused pins 69
Note to Ta b l e 2– 4 :
(1) The HSMC pins include all pins between the FPGA and the MAX II CPLD
f For additional information about Altera devices, go to
www.altera.com/products/devices.
Block Diagram of bus-controller logic in the MAX II CPLD
Figures 2–3 shows the block diagram of Bus Controller logic in the MAX
II device. Both the LCD TDM block is a simple 8-bit to 24-bit data
de-multiplexing function which drives the LCD panel. Similarly, the
VGA TDM block is a 10bit to 30bit data de-multiplexing function which
drives the VGA DAC. In the LCD TDM block, the 8-bit input data
(successive BGR color data) comes in at 3x the rate of the 24-bit output
data bus (8-bit B + 8bit G + 8bit R).
1 The purpose of adding this complexity to the design of the LCD
Multimedia HSMC was to allow for more functionality given
the constraint of a pin-limited HSMC connector interface.
The I2CBir_bus block provides birdirectional control for I2C Serial
EEPROM data bus. All other signals that pass through the MAXII device
are uni-directional and are simply buffered and level-shifted in the
MAX II.
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August 2008 LCD Multimedia HSMC
Interface Device
Figure 2–3. The Block Diagram of MAX II Bus Controller
LCD Touch Panel &
AD co nverter
Serial Port Int erface
LCD Col or Dat a B us (RGB )
LCD Timin g Con trol Bu s
MAXII CPLD
LCD TDM
Controller
LCD R dat a
LCD G data
LCD B data
LCD Timi ng Cont rol Bu s
LCD Touch Panel Module
HSMC
Connector
VGA Color Dat a Bus (RGB )
VGA Timing Cont rol Bu s
I2C EE PROM Interf ace
Bi-directional I /Os
The source code for this design in the MAXII device can be found in the
"board_design_files" directory for your development kit.
VGA R dat a
VGA TDM
Controller
I2C_bir_bus
Controller
Other uni -directi onal I /Os
Bi-directional Level
VGA G data
VGA B dat a
VGA Timing Control Bus
Translator
VGA
DAC
I2C E EPROM
AUDIO DAC
Ethernet PHY
SD Card
RS232 Ports
Video Decod er
2–7 Altera Corporation
LCD Multimedia HSMC August 2008
Board Components and Interfaces
Level Translator
Bidirectional level shift interface
The board provides bidirectional level shift feature for the 2.5V input
(Cyclone III FPGA) and 3.3V required by many of the interface chips via
two Maxim MAX3378 level translators. Tab l e 2– 5 lists bidirectional level
shift interface reference and manufacturing information.
Table 2–5. Bidirectional Level Shift Interface Manufacturing Information
Board Reference Device Description Manufacturer
U10, U11 Dual Low-Voltage
Level Translators
Maxim Integrated
Products
Manufacturer Part
MAX3378EEUD www.maxim-ic.com
Figure 2–4 shows the block diagram and pinout of the bidirectional level
shift interface on the board respectively.
Figure 2–4. Block Diagram of Bidirectional Level Shift Interface
HC_I2C_SDAT
HC_PS2_CLK
HC_PS2_DAT
Level
Translator
(U10)
I2C_SDAT
PS2_CLK
PS2_DA T
Number
Manufacturer
Website
Video
Decoder
& Audio
DAC
PS/2
Port
HC_MDIO
MDIO
Eth ern et
PHY
HSMC
Connector
HC_SD_DAT3
HC_SD_CMD
HC_SD_DAT
Level
Translator
SD_DAT3
SD_CMD
SD_DAT
SD Card
Socket
(U11)
LCD
HC_SDA
SDA
Touch
Panel
Module
Altera Corporation 2–8
August 2008 LCD Multimedia HSMC
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