Altera I/O Phase-Locked Loop IP Core User Manual

2015.05.04

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Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core

User Guide

UG-01155

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The Altera IOPLL megafunction IP core allows you to configure the settings of Arria® 10 I/O PLL.
Altera IOPLL IP core supports the following features:

• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buffer, and LVDS mode.

• Generates up to nine clock output signals for the Arria 10 device.

• Switches between two reference input clocks.

• Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.

• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.

• Supports PLL dynamic phase shift.

Related Information

• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.

• Operation Modes on page 8

• Output Clocks on page 8

• Reference Clock Switchover on page 9

• PLL-to-PLL Cascading on page 9

Device Family Support

The Altera IOPLL IP core only supports the Arria 10 device family.

Altera IOPLL IP Core Parameters

The Altera IOPLL IP core parameter editor appears in the PLL category of the IP Catalog.

Altera IOPLL IP Core Parameters - PLL Tab

Table 1: Altera IOPLL IP Core Parameters - PLL Tab

Parameter Legal Value Description

Device Family Arria 10 Specifies the device family.

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Altera IOPLL IP Core Parameters - PLL Tab

Parameter Legal Value Description

Component — Specifies the targeted device.
Speed Grade — Specifies the speed grade for targeted device.
PLL Mode Integer-N PLL Specifies the mode used for the Altera IOPLL IP core. The

only legal selection is Integer-N PLL. If you need a fractional
PLL, you must use the Arria 10 FPLL IP core.

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Reference Clock

— Specifies the input frequency for the input clock, refclk, in

Frequency

Enable Locked Output
Port

Enable physical output
clock parameters

Turn on or

Turn off

Turn on or

Turn off

Operation Mode direct,

external

feedback,

normal,

source

synchronous,

zero delay

buffer or lvds

MHz. The default value is 100.0 MHz. The minimum and
maximum value is dependent on the selected device.

Turn on to enable the locked port.

Turn on to enter physical PLL counter parameters instead of
specifying a desired output clock frequency.

Specifies the operation of the PLL. The default operation is
direct mode.

• If you select the direct mode, the PLL minimizes the

length of the feedback path to produce the smallest
possible jitter at the PLL output.The internal-clock and
external-clock outputs of the PLL are phase-shifted with
respect to the PLL clock input. In this mode, the PLL does
not compensate for any clock networks.

• If you select the normal mode, the PLL compensates for

the delay of the internal clock network used by the clock
output. If the PLL is also used to drive an external clock
output pin, a corresponding phase shift of the signal on
the output pin occurs.

• If you select the source synchronous mode, the clock

delay from pin to I/O input register matches the data
delay from pin to I/O input register.

• If you select the external feedback mode, you must

connect the fbclk input port to an input pin. A board­level connection must connect both the input pin and
external clock output port, fboutclk. The fbclk port is
aligned with the input clock.

• If you select the zero delay buffer mode, the PLL must

feed an external clock output pin and compensate for the
delay introduced by that pin. The signal observed on the
pin is synchronized to the input clock. The PLL clock
output connects to the altbidir port and drives

zdbfbclk as an output port. If the PLL also drives the

internal clock network, a corresponding phase shift of
that network occurs.

• If you select the lvds mode, the same data and clock

timing relationship of the pins at the internal SERDES
capture register is maintained. The mode compensates
for the delays in LVDS clock network, and between the
data pin and clock input pin to the SERDES capture
register paths.

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Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

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Altera IOPLL IP Core Parameters - PLL Tab

Parameter Legal Value Description

Number of Clocks 1–9 Specifies the number of output clocks required for each

device in the PLL design. The requested settings for output
frequency, phase shift, and duty cycle are shown based on
the number of clocks selected.

3

Specify VCO Frequency Turn on or

Turn off

Allows you to restrict the VCO frequency to the specified
value. This is useful when creating a PLL for LVDS external
mode, or if a specific dynamic phase shift step size is desired.

VCO Frequency

(1)

—

• When Enable physical output clock parameters is

turned on—displays the VCO frequency based on the
values for Reference Clock Frequency, Multiply Factor
(M-Counter), and Divide Factor (N-Counter).

• When Enable physical output clock parameters is

turned off—allows you to specify the requested value for
the VCO frequency. The default value is 600.0 MHz.

Give clock global name Turn on or

Allows you to rename the output clock name.

Turn off
Clock Name — The user clock name for Synopsis Design Constraints (SDC).
Desired Frequency — Specifies the output clock frequency of the corresponding

output clock port, outclk[], in MHz. The default value is

100.0 MHz. The minimum and maximum values depend on
the device used. The PLL only reads the numerals in the first
six decimal places.

Actual Frequency — Allows you to select the actual output clock frequency from a

list of achievable frequencies. The default value is the closest
achievable frequency to the desired frequency.

Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output

Desired Phase Shift — Specifies the requested value for the phase shift. The default

Actual Phase Shift — Allows you to select the actual phase shift from a list of

Desired Duty Cycle 0.0–100.0 Specifies the requested value for the duty cycle. The default

Actual Duty Cycle — Allows you to select the actual duty cycle from a list of

(1)

This parameter is only available when Enable physical output clock parameters is turned off.

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

clock port, outclk[], in picoseconds (ps) or degrees.

value is 0 ps.

achievable phase shift values. The default value is the closest
achievable phase shift to the desired phase shift.

value is 50.0%.

achievable duty cycle values. The default value is the closest
achievable duty cycle to the desired duty cycle.

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Altera IOPLL IP Core Parameters - Settings Tab

Parameter Legal Value Description

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Multiply Factor (M­Counter)

(2)

4–511

Specifies the multiply factor of M-counter.
The legal range of the M counter is 4–511. However, restric‐

tions on the minimum legal PFD frequency and maximum
legal VCO frequency restrict the effective M counter range to
4–160.

Divide Factor (N­Counter)

(2)

1–511

Specifies the divide factor of N-counter.
The legal range of the N counter is 1–511. However, restric‐

tions on the minimum legal PFD frequency restrict the
effective range of the N counter to 1–80.

Divide Factor (C­Counter)

(2)

1-511 Specifies the divide factor for the output clock (C-counter).

Altera IOPLL IP Core Parameters - Settings Tab

Table 2: Altera IOPLL IP Core Parameters - Settings Tab

Parameter Legal Value Description

PLL Bandwidth Preset Low, Medium,

or High

Specifies the PLL bandwidth preset setting. The default
selection is Low.

PLL Auto Reset Turn on or

Turn off

Create a second input clk
‘refclk1’

Second Reference Clock

Turn on or

Turn off

— Selects the frequency of the second input clock signal. The

Frequency

Create an ‘active_clk’ signal
to indicate the input clock

Turn on or

Turn off

in use

Create a ‘clkbad’ signal for
each of the input clocks

Turn on or

Turn off

Automatically self-resets the PLL on loss of lock.

Turn on to provide a backup clock attached to your PLL
that can switch with your original reference clock.

default value is 100.0 MHz. The minimum and maximum
value is dependent on the device used.

Turn on to create the activeclk output. The activeclk
output indicates the input clock which is in use by the PLL.
Output signal low indicates refclk and output signal high
indicates refclk1.

Turn on to create two clkbad outputs, one for each input
clock. Output signal low indicates the clock is working and
output signal high indicates the clock is not working.

(2)

This parameter is only available when Enable physical output clock parameters is turned on.

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Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

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