Altera Internal Memory IP Core User Manual

Embedded Memory (RAM: 1-PORT, RAM:

2-PORT, ROM: 1-PORT, and ROM: 2-PORT)

User Guide

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TOC-2

About RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT

IP Cores............................................................................................................1-1

Customizing Embedded Memory IP Cores........................................................2-1

Embedded Memory Functional Description......................................................3-1

Embedded Memory Features..................................................................................................................... 1-1

Supported Memory Operation Modes......................................................................................................1-2

Installing and Licensing IP Cores..............................................................................................................2-1

IP Catalog and Parameter Editor...............................................................................................................2-2

Using the Parameter Editor........................................................................................................................2-2

Specifying IP Core Parameters and Options............................................................................................2-3

Migrating IP Cores to a Different Device.................................................................................................2-4

Memory Block Types...................................................................................................................................3-1

Write and Read Operations Triggering....................................................................................................3-2

Port Width Configurations.........................................................................................................................3-4

Mixed-width Port Configuration...............................................................................................................3-5

Maximum Block Depth Configuration.....................................................................................................3-5

Clocking Modes and Clock Enable............................................................................................................3-6

Memory Blocks Address Clock Enable Support......................................................................................3-7

Byte Enable ...................................................................................................................................................3-8

Asynchronous Clear..................................................................................................................................3-10

Read Enable................................................................................................................................................ 3-10

Read-During-Write................................................................................................................................... 3-11

Selecting RDW Output Choices for Various Memory Blocks.................................................3-12

Power-Up Conditions and Memory Initialization................................................................................3-14

Error Correction Code .............................................................................................................................3-15

Embedded Memory Signals and Parameters......................................................4-1

Design Example...................................................................................................5-1

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Signals............................................................................................................................................................4-1

RAM:1-Port IP Core Parameters...............................................................................................................4-6

RAM: 2-Port IP Core Parameters..............................................................................................................4-9

ROM: 1-PORT IP Core Parameters........................................................................................................4-16

ROM: 2-PORT IP Core Parameters........................................................................................................4-18

External ECC Implementation with True-Dual-Port RAM..................................................................5-1

Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-

PORT IP Core.............................................................................................................................5-2

TOC-3

Simulating the Design..................................................................................................................... 5-4

Document Revision History...............................................................................A-1

Document Revision History......................................................................................................................A-1

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About RAM: 1-PORT, RAM: 2-PORT, ROM: 1-

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PORT, and ROM: 2-PORT IP Cores

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The Quartus® II software automatically selects one of megafunction IP cores to implement memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.

Table 1-1: IP Cores for Embedded Memory Blocks

This table lists the IP cores for embedded memory blocks.

IP Core Memory Mode

RAM: 1-PORT Single-port RAM RAM: 2-PORT Dual-port RAM ROM: 1-PORT Single-port ROM ROM: 2-PORT Dual-port ROM

Embedded Memory Features

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The embedded memory blocks provide the following features:

• Memory Modes Configuration

• Memory Block Types

• Write and Read Operations Triggering

• Port Width Configuration

• Mixed-width Port Configuration

• Maximum Block Depth Configuration

• Clocking Modes and Clock Enable

• Address Clock Enable

• Byte Enable

• Asynchronous Clear

• Read Enable

• Read-During-Write

• Power-Up Conditions and Memory Initialization

• Error Correction Code

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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1-2

Supported Memory Operation Modes

This table lists the supported memory operation mode and the related IP core for each operation mode.

Table 1-2: Supported Memory Operation Modes

Memory Operation Mode Related IP Core Description

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Single-port RAM RAM: 1-PORT IP

Core

Simple dual-port RAM

RAM: 2-PORT IP Core

True dual-port RAM RAM: 2-PORT IP

Core

Single-port ROM ROM: 1-PORT IP

Core

Single-port mode supports non-simultaneous read and write operations from a single address.

Use the read enable port to control the RAM output ports behavior during a write operation:

• To show either the new data being written or the old data at that address, activate the read enable during a write operation.

• To retain the previous values that are held during the most recent active read enable, perform the write operation with the read enable port deasserted.

You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.

You can perform any combination of two port operations:

• two reads, two writes, or,

• one read and one write at two different clock frequencies.

Only one address port is available for read operation. You can use the memory blocks as a ROM.

Dual-port ROM ROM: 2-PORT IP

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Core

• Initialize the ROM contents of the memory blocks using a .mif or .hex file.

• The address lines of the ROM are registered.

• The outputs can be registered or unregistered.

• The ROM read operation is identical to the read operation in the single-port RAM configuration.

The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.

You can use the memory blocks as a ROM.

• Initialize the ROM contents of the memory blocks using a .mif or .hex file.

• The address lines of the ROM are registered.

• The outputs can be registered or unregistered.

• The ROM read operation is identical to the read operation in the single-port RAM configuration.

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for production use without purchasing an additional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions, require that you purchase a separate license for production use. You can use the OpenCore Plus feature to evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

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2-2

IP Catalog and Parameter Editor

The Qsys IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

The Virtual Processing Image Suite is available only through the Qsys IP Catalog (View > IP Catalog). Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your IP variation name, optional ports, architec‐ ture features, and output file generation options. The parameter editor generates a top-level .qsys file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by device.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, installation location, and links to documentation.

Note:

The IP Catalog and parameter editor replace the MegaWizard™ Plug-In Manager in the Quartus II software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these messages.

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Upgrading VIP Designs in 14.0

In Quartus, if you open a design from a 13.1 or previous version that contains VIP components in a Qsys system, Quartus will show a warning message with the title "Upgrade IP Components". This message is just letting you know that VIP components within your Qsys system need to be updated to their latest versions, and to do this the Qsys system must be regenerated before the design can be compiled within Quartus. The recommended way of doing this with a VIP system is to close the warning message and open the design in Qsys so that it is easier to spot any errors or potential errors that have arisen because of the design being upgraded.

Related Information

Creating a System With Qsys

For more information on how to simulate Qsys designs.

Using the Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications.

• View port and parameter descriptions, and links to documentation.

• Generate testbench systems or example designs (where provided).

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

Legacy parameter editors

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Figure 2-2: IP Parameter Editors

Specifying IP Core Parameters and Options

2-3

Specifying IP Core Parameters and Options

The parameter editor GUI allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus II software.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate a simulation testbench, click Generate > Generate Testbench System.

Customizing Embedded Memory IP Cores

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

2-4

Migrating IP Cores to a Different Device

7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

Figure 2-3: IP Parameter Editor

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Migrating IP Cores to a Different Device

IP migration allows you to target the latest device families with IP originally generated for a different device. Some Altera IP cores require individual migration to upgrade. The Upgrade IP Components dialog box prompts you to double-click IP cores that require individual migration.

1. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description

2. Double-click the IP core name, and then click OK after reading the information panel.

3. In the parameter editor, click Generate, and then click OK if prompted to overwrite IP files.

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field prompts you to double-click IP cores that require individual migration.

The parameter editor appears showing the original IP core parameters.

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Migrating IP Cores to a Different Device

2-5

The new parameter editor appears when the generation is complete.

4. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the parameter editor default HDL for synthesis files. If your original IP core was generated for VHDL, select VHDL to retain the original output HDL format.

5. To regenerate the new IP variation for the new target device, click Generate. When generation is complete, click Close.

6. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core files. The Device Family column displays the migrated device support. The migration process replaces <my_ip>.qip with the <my_ip>.qsys top-level IP file in your project.

Note: If migration does not replace <my_ip>.qip with <my_ip>.qsys, click Project > Add/Remove

Files in Project to replace the file in your project.

7. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration

may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>.bsf after migration.

Note: The migration process may change the IP variation interface, parameters, and functionality.

This may require you to change your design or to re-parameterize your variant after the Upgrade IP Components dialog box indicates that migration is complete. The Description field identifies IP cores that require design or parameter changes.

Related Information

Altera IP Release Notes

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Embedded Memory Functional Description

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Describes the features and functionality of the embedded memory blocks and the ports of the RAM: 1PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT IP cores.

Memory Block Types

Altera provides various sizes of embedded memory blocks for various devices. The parameter editor allows you to implement your memory in the following ways:

• Select the type of memory blocks available based on your target device. To select the appropriate memory block type for your device, obtain more information about the features of your selected embedded memory block in your target device, such as the maximum performance, supported configurations (depth × width), byte enable, power-up condition, and the write and read operation triggering.

• Use logic cells. As compared to embedded memory resources, using logic cells to create memory reduces the design performance and utilizes more area. This implementation is normally used when you have used up all the embedded memory resources. When logic cells are used, the parameter editor provides you with the following two types of logic cell implementations:

• Default logic cell style—the write operation triggers (internally) on the rising edge of the write clock

and have continuous read. This implementation uses less logic cells and is faster, but it is not fully compatible with the Stratix M512 emulation style.

• Stratix M512 emulation logic cell style—the write operation triggers (internally) on the falling edge

of the write clock and performs read only on the rising edge of the read clock.

• Select the Auto option, which allows the software to automatically select the appropriate embedded memory resource. When you set the memory block type to Auto, the compiler favors larger block types that can support the memory capacity you require in a single embedded memory block. This setting gives the best performance and requires no logic elements (LEs) for glue logic. When you create the memory with specific embedded memory blocks, such as M9K, the compiler is still able to emulate wider and deeper memories than the block type supported natively. The compiler spans multiple embedded memory blocks (only of the same type) with glue logic added in the LEs as needed.

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To obtain proper implementation based on the memory configuration you set, allow the Quartus II

Note:

software to automatically choose the memory type. This gives the compiler the flexibility to place the memory function in any available memory resources based on the functionality and size.

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3-2

Write and Read Operations Triggering

Table 3-1: Embedded Memory Blocks in Altera Devices

Device Family

M512

(512

bits)

M4K (4

Kbits)

(1)

M-RAM

(512

Kbits)

(2)

MLAB

(640 bits)

(3)

Memory Block Type

M9K (9

Kbits)

M144K

(144

Kbits)

M10K (10

Kbits)

M20K

(20

Kbits)

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Logic Cell

(LC)

Arria II GX

Arria II

— — — Yes Yes — — — Yes

— — — Yes Yes Yes — — Yes

GZ Arria V — — — Yes — — Yes — Yes Cyclone

— — — — Yes — — — Yes

IV Cyclone

— — — Yes — — Yes — Yes

V Max II — — — — — — — — Yes Stratix IV — — — Yes Yes Yes — — Yes Stratix V — — — Yes — — — Yes Yes

Note: To identify the type of memory block that the software selects to create your memory, refer to the

Fitter report after compilation.

Write and Read Operations Triggering

The embedded memory blocks vary slightly in its supported features and behaviors. One important variation is the difference in the write and read operations triggering.

Table 3-2: Write and Read Operations Triggering for Embedded Memory Blocks

This table lists the write and read operations triggering for various embedded memory blocks.

Embedded Memory Blocks Write Operation

(4)

Read Operation

M10K Rising clock edges Rising clock edges M20K Rising clock edges Rising clock edges

M144K Rising clock edges Rising clock edges

M9K Rising clock edges Rising clock edges

(1)

M512 blocks are not supported in true dual-port RAM mode, and dual-port ROM mode.

(2)

M-RAM blocks are not supported in ROM mode.

(3)

MLAB blocks are not supported in simple dual-port RAM mode with mixed-width port feature, true dualport RAM mode, and dual-port ROM mode.

(4)

Write operation triggering is not applicable to ROMs.

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Embedded Memory Functional Description

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clock_a

address_a

wren_a

data_a

clock_b

address_b

wren_b

data_b

twc

Valid Write

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Write and Read Operations Triggering

3-3

Embedded Memory Blocks Write Operation

(4)

MLAB Falling clock edges

Rising clock edges (in Arria V, Cyclone V, and Stratix V

devices only)

M-RAM Rising clock edges Rising clock edges

M4K Falling clock edges Rising clock edges

M512 Falling clock edges Rising clock edges

It is important that you understand the write operation triggering to avoid potential write contentions that can result in unknown data storage at that location.

These figures show the valid write operation that triggers at the rising and falling clock edge, respectively.

Figure 3-1: Valid Write Operation that Triggers at Rising Clock Edges

This figure assumes that twc is the maximum write cycle time interval. Write operation of data 03 through port B does not meet the criteria and causes write contention with the write operation at port A, which result in unknown data at address 01. The write operation at the next rising edge is valid because it meets the criteria and data 04 replaces the unknown data.

Read Operation

Rising clock edges

(5)

(4)

Write operation triggering is not applicable to ROMs.

(5)

MLAB supports continuos reads. For example, when you write a data at the write clock rising edge and after the write operation is complete, you see the written data at the output port without the need for a read clock rising edge.

Embedded Memory Functional Description

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clock_a

address_a

wren_a

data_a

clock_b

address_b

wren_b

data_b

Actual Write

Valid Write

3-4

Port Width Configurations

Figure 3-2: Valid Write Operation that Triggers at Falling Clock Edges

This figure assumes that twc is the maximum write cycle time interval. Write operation of data 04 through port B does not meet the criteria and therefore causes write contention with the write operation at port A that result in unknown data at address 01. The next data (05) is latched at the next rising clock edge that meets the criteria and is written into the memory block at the falling clock edge.

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Note: Data and addresses are latched at the rising edge of the write clock regardless of the different write

operation triggering.

Port Width Configurations

The following equation defines the port width configuration: Memory depth (number of words) × Width of the data input bus.

• If your port width configuration (either the depth or the width) is more than the amount an internal memory block can support, additional memory blocks (of the same type) are used. For example, if you configure your M9K as 512 × 36, which exceeds the supported port width of 512 × 18, two M9Ks are used to implement your RAM.

• In addition to the supported configuration provided, you can set the memory depth to a non-power of two, but the actual memory depth allocated can vary. The variation depends on the type of resource implemented.

• If the memory is implemented in dedicated memory blocks, setting a non-power of two for the memory depth reflects the actual memory depth.

• When you implement your memory using dedicated memory blocks, refer to the Fitter report to check the actual memory depth.

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Embedded Memory Functional Description

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Mixed-width Port Configuration

Only dual-port RAM and dual-port ROM support mixed-width port configuration for all memory block types except when they are implemented with LEs. The support for mixed-width port depends on the width ratio between port A and port B. In addition, the supporting ratio varies for various memory modes, memory blocks, and target devices.

Note: MLABs do not have native support for mixed-width operation, thus the option to select MLABs is

disabled in the parameter editor. However, the Quartus II software can implement mixed-width memories in MLABs by using more than one MLAB. Therefore, if you select AUTO for your memory block type, it is possible to implement mixed-width port memory using multiple MLABs.

Memory depth of 1 word is not supported in simple dual-port and true dual-port RAMs with mixedwidth port. The parameter editor prompts an error message when the memory depth is less than 2 words. For example, if the width for port A is 4 bits and the width for port B is 8 bits, the smallest depth supported by the RAM is 4 words. This configuration results in memory size of 16 bits (4 × 4) and can be represented by memory depth of 2 words for port B. If you set the memory depth to 2 words that results in memory size of 8 bits (2 × 4), it can only be represented by memory depth of 1 word for port B, and therefore the width of the port is not supported.

Mixed-width Port Configuration

3-5

Maximum Block Depth Configuration

You can limit the maximum block depth of the dedicated memory block you use. The memory block can be sliced to your desired maximum block depth. For example, the capacity of an

M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).

You can use this option to save power usage in your devices. However, this parameter might increase the number of LEs and affects the design performance.

When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices.

You can also use this option to reduce the total number of memory blocks used (but at the expense of LEs). The 8K × 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K × 1. By setting the maximum block depth to 1K, the 8K × 36 RAM can fit into 32 M9K blocks.

The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.

Table 3-3: Valid Range of Maximum Block Depth for Various Embedded Memory Blocks

Embedded Memory Blocks Valid Range

(6)

M10K 256–8K M20K 512–16K

(6)

The maximum block depth must be in a power of two.

Embedded Memory Functional Description

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3-6

Clocking Modes and Clock Enable

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Embedded Memory Blocks Valid Range

M144K 2K–16K

M9K 256–8K

MLAB 32–64

M512 32–512

M4K 128–4K

M-RAM 4K–64K

The parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Altera recommends that you set the value to Auto if you are not sure of the appropriate maximum block depth to set or the setting is not important for your design. This setting enables the compiler to select the maximum block depth with the appropriate port width configuration for the type of embedded memory block of your memory.

Clocking Modes and Clock Enable

The embedded memory block supports various types of clocking modes depending on the memory mode you select.

(6)

(7)

Table 3-4: Clocking Modes

Clocking Modes Description

Single Clock Mode In the single clock mode, a single clock, together with a clock enable, controls all

registers of the memory block.

Read/Write Clock Mode

In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.

Input/Output Clock Mode

In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.

Independent Clock Mode

In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.

Note: You can create independent clock enable for different input and

output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More Options (beside the clock enable option) to set the available independent clock enable that you prefer.

(6)

The maximum block depth must be in a power of two.

(7)

The maximum block depth setting (64) for MLAB is not available for Arria V and Cyclone V devices.

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Embedded Memory Functional Description

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address[0]

address[N]

addressstall

clock

1 0

address[0]

address[N]

address[0]

1 0

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Table 3-5: Clocking Modes

This table lists the embedded memory clocking modes.

Clocking Modes Single-port

RAM

Simple Dual-

port RAM

True Dual-port

Single clock Supported Supported Supported Supported Supported

Read/Write — Supported — — —

Input/Output Supported Supported Supported Supported Supported

Independent — — Supported — Supported

Note: Asynchronous clock mode is only supported in MAX series of devices, and not supported in Stratix

and newer devices. However, Stratix III and newer devices support asynchronous read memory for simple dual-port RAM mode if you choose MLAB memory block with unregistered rdaddress port.

Note: The clock enable signals are not supported for write address, byte enable, and data input registers

on Arria V, Cyclone V, and Stratix V MLAB blocks.

Memory Blocks Address Clock Enable Support

RAM

Single-port

ROM

Dual-port ROM

3-7

The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dualport mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).

Figure 3-3: Address Clock Enable

This figure shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall.

Embedded Memory Functional Description

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inclock

rden

rdaddress

q (synch)

a0 a1 a2 a3 a4 a5

q (asynch)

an a0

latched address (inside memory)

dout0

dout1

dout4

dout5

addressstall

doutn-1

doutn

dout0

dout1

inclock

wren

wraddress

a0 a1 a2 a3 a4 a5

an a0

a4 a5

latched address (inside memory)

addressstall

data

01 02

03 04

contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5

3-8

Byte Enable

Figure 3-4: Address Clock Enable During Read Cycle Waveform

This figure shows the address clock enable waveform during the read cycle.

Figure 3-5: Address Clock Enable During the Write Cycle Waveform

This figure shows the address clock enable waveform during the write cycle.

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Byte Enable

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All embedded memory blocks that are implemented as RAMs support byte enables that mask the input data so that only specific bytes, nibbles, or bits of data are written. The unwritten bytes or bits retain the previously written value.

The LSB of the byte-enable port corresponds to the LSB of the data bus. For example, if you use a RAM block in x18 mode and the byte-enable port is 01, data [8..0] is enabled and data [17..9] is disabled. Similarly, if the byte-enable port is 11, both data bytes are enabled.

Embedded Memory Functional Description

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Altera Internal Memory IP Core User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Embedded Memory Features

Supported Memory Operation Modes

Customizing Embedded Memory IP Cores

Installing and Licensing IP Cores

IP Catalog and Parameter Editor

Using the Parameter Editor

Specifying IP Core Parameters and Options

Migrating IP Cores to a Different Device

Embedded Memory Functional Description

Memory Block Types

Write and Read Operations Triggering

Port Width Configurations

Mixed-width Port Configuration

Maximum Block Depth Configuration

Clocking Modes and Clock Enable

Memory Blocks Address Clock Enable Support

Byte Enable