Altera Integer Arithmetic IP User Manual
Integer Arithmetic IP Cores User Guide
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TOC-2
Integer Arithmetic IP Cores User Guide
Contents
Integer Arithmetic Megafunctions..................................................................... 1-1
LPM_COUNTER (Counter)................................................................................2-1
Design Example Files...................................................................................................................................1-2
Installing and Licensing IP Cores..............................................................................................................1-2
Customizing and Generating IP Cores.....................................................................................................1-2
IP Catalog and Parameter Editor...............................................................................................................1-3
Using the Parameter Editor........................................................................................................................1-4
Specifying IP Core Parameters and Options............................................................................................1-4
Specifying IP Core Parameters and Options (Legacy Parameter Editors)...........................................1-6
Files Generated for Altera IP Cores (Legacy Parameter Editor)............................................... 1-7
Upgrading IP Cores.....................................................................................................................................1-8
Migrating IP Cores to a Different Device...............................................................................................1-11
Simulating Altera IP Cores in other EDA Tools................................................................................... 1-12
Features......................................................................................................................................................... 2-1
Resource Utilization and Performance.....................................................................................................2-2
Verilog HDL Prototype...............................................................................................................................2-2
VHDL Component Declaration................................................................................................................ 2-3
VHDL LIBRARY_USE Declaration..........................................................................................................2-3
Ports...............................................................................................................................................................2-3
Parameters.....................................................................................................................................................2-5
LPM_DIVIDE (Divider)......................................................................................3-1
Features......................................................................................................................................................... 3-1
Resource Utilization and Performance.....................................................................................................3-1
Verilog HDL Prototype...............................................................................................................................3-2
VHDL Component Declaration................................................................................................................ 3-2
VHDL LIBRARY_USE Declaration..........................................................................................................3-3
Ports...............................................................................................................................................................3-3
Parameters.....................................................................................................................................................3-3
LPM_MULT (Multiplier)....................................................................................4-1
Features......................................................................................................................................................... 4-1
Resource Utilization and Performance.....................................................................................................4-1
Verilog HDL Prototype...............................................................................................................................4-2
VHDL Component Declaration................................................................................................................ 4-3
VHDL LIBRARY_USE Declaration..........................................................................................................4-3
LPM_MULT Ports.......................................................................................................................................4-3
LPM_MULT Parameters............................................................................................................................ 4-4
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Integer Arithmetic IP Cores User Guide
TOC-3
ALTECC (Error Correction Code: Encoder/Decoder).......................................5-1
ALTECC_ENCODER Features..................................................................................................................5-2
Resource Utilization and Performance.....................................................................................................5-3
Verilog HDL Prototype (ALTECC_ENCODER)....................................................................................5-5
Verilog HDL Prototype (ALTECC_DECODER)....................................................................................5-5
VHDL Component Declaration (ALTECC_ENCODER)..................................................................... 5-6
VHDL Component Declaration (ALTECC_DECODER)..................................................................... 5-6
VHDL LIBRARY_USE Declaration..........................................................................................................5-7
Ports (ALTECC_ENCODER)....................................................................................................................5-7
Ports (ALTECC_DECODER)....................................................................................................................5-7
Parameters (ALTECC_ENCODER)..........................................................................................................5-8
Parameters (ALTECC_DECODER)..........................................................................................................5-8
Design Example 1: ALTECC_ENCODER................................................................................................5-9
Understanding the Simulation Results......................................................................................... 5-9
Design Example 2: ALTECC_DECODER..............................................................................................5-12
Understanding the Simulation Results.......................................................................................5-12
ALTERA_MULT_ADD (Multiply-Adder)......................................................... 6-1
Features......................................................................................................................................................... 6-2
Pre-adder...........................................................................................................................................6-3
Systolic Delay Register.....................................................................................................................6-6
Pre-load Constant............................................................................................................................6-9
Double Accumulator.......................................................................................................................6-9
Verilog HDL Prototype.............................................................................................................................6-10
VHDL Component Declaration.............................................................................................................. 6-10
VHDL LIBRARY_USE Declaration........................................................................................................6-10
Ports.............................................................................................................................................................6-10
ALTERA_MULT_ADD Parameters.......................................................................................................6-12
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter.............................6-19
Understanding the Simulation Results...................................................................................................6-20
ALTMEMMULT (Memory-based Constant Coefficient Multiplier).................7-1
Features......................................................................................................................................................... 7-1
Resource Utilization and Performance.....................................................................................................7-2
Verilog HDL Prototype...............................................................................................................................7-2
VHDL Component Declaration................................................................................................................ 7-3
Ports...............................................................................................................................................................7-3
Parameters.....................................................................................................................................................7-4
Design Example: 8 × 8 Multiplier..............................................................................................................7-5
Understanding the Simulation Results..................................................................................................... 7-6
ALTMULT_ACCUM (Multiply-Accumulate)....................................................8-1
Features......................................................................................................................................................... 8-2
Resource Utilization and Performance.....................................................................................................8-2
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TOC-4
Integer Arithmetic IP Cores User Guide
Verilog HDL Prototype...............................................................................................................................8-4
VHDL Component Declaration................................................................................................................ 8-4
VHDL LIBRARY_USE Declaration..........................................................................................................8-4
ALTMULT_ACCUM Ports........................................................................................................................8-4
ALTMULT_ACCUM Parameters.............................................................................................................8-6
Design Example: Shift Accumulator.......................................................................................................8-19
Understanding the Simulation Results...................................................................................................8-19
ALTMULT_ADD (Multiply-Adder)...................................................................9-1
Features......................................................................................................................................................... 9-3
Pre-adder...........................................................................................................................................9-4
Systolic Delay Register.....................................................................................................................9-7
Pre-load Constant..........................................................................................................................9-10
Double Accumulator.....................................................................................................................9-10
Resource Utilization and Performance...................................................................................................9-11
Verilog HDL Prototype.............................................................................................................................9-11
VHDL Component Declaration.............................................................................................................. 9-11
VHDL LIBRARY_USE Declaration........................................................................................................9-12
ALTMULT_ADD Ports............................................................................................................................9-12
ALTMULT_ADD Parameters................................................................................................................. 9-14
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter.............................9-34
Understanding the Simulation Results...................................................................................................9-35
ALTMULT_COMPLEX (Complex Multiplier)................................................ 10-1
Complex Multiplication............................................................................................................................10-2
Canonical Representation.........................................................................................................................10-2
Conventional Representation...................................................................................................................10-3
Features....................................................................................................................................................... 10-3
Resource Utilization and Performance...................................................................................................10-4
Verilog HDL Prototype.............................................................................................................................10-4
VHDL Component Declaration.............................................................................................................. 10-5
VHDL LIBRARY_USE Declaration........................................................................................................10-5
ALTMULT_COMPLEX Ports.................................................................................................................10-6
ALTMULT_COMPLEX Parameters.......................................................................................................10-6
Design Example: Multiplication of 8-bit Complex Numbers Using Canonical Representation...
10-8
Understanding the Simulation Results...................................................................................................10-8
ALTSQRT (Integer Square Root)..................................................................... 11-1
Features....................................................................................................................................................... 11-1
Resource Utilization and Performance...................................................................................................11-1
Verilog HDL Prototype.............................................................................................................................11-2
VHDL Component Declaration.............................................................................................................. 11-2
VHDL LIBRARY_USE Declaration........................................................................................................11-3
Ports.............................................................................................................................................................11-3
Parameters.................................................................................................................................................. 11-3
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Integer Arithmetic IP Cores User Guide
Design Example: 9-bit Square Root.........................................................................................................11-4
Understanding the Simulation Results...................................................................................................11-4
TOC-5
PARALLEL_ADD (Parallel Adder).................................................................. 12-1
Feature.........................................................................................................................................................12-1
Resource Utilization and Performance...................................................................................................12-1
Verilog HDL Prototype.............................................................................................................................12-2
VHDL Component Declaration.............................................................................................................. 12-2
VHDL LIBRARY_USE Declaration........................................................................................................12-3
Ports.............................................................................................................................................................12-3
Parameters.................................................................................................................................................. 12-4
Design Example: Shift Accumulator.......................................................................................................12-4
Understanding the Simulation Results...................................................................................................12-5
Document Revision History..............................................................................13-1
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Integer Arithmetic Megafunctions
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You can use Altera® integer megafunction IP cores to perform mathematical operations in your design.
These functions offer more efficient logic synthesis and device implementation than coding your own
functions. You can customize the IP cores to accommodate your design requirements.
Altera integer arithmetic megafunctions are divided into the following two categories:
• Library of parameterized modules (LPM) IP cores
• Altera-specific (ALT) IP cores
The following table lists the integer arithmetic IP cores.
Table 1-1: List of IP Cores
IP Cores Function Overview
LPM Megafunctions
LPM_COUNTER (Counter) Counter
LPM_DIVIDE (Divider) Divider
LPM_MULT (Multiplier) Multiplier
Altera-specific (ALT) Megafunctions
ALTECC ECC Encoder/Decoder
ALTERA_MULT_ADD (Multiply-Adder) Multiplier-Adder
ALTMEMMULT (Memory-based Constant
Memory-based Constant Coefficient Multiplier
Coefficient Multiplier)
ALTMULT_ACCUM (Multiply-Accumulate) Multiplier-Accumulator
ALTERA_MULT_ADD (Multiply-Adder) Multiplier-Adder
ALTMULT_COMPLEX (Complex Multiplier) Complex Multiplier
ALTSQRT (Integer Square Root) Integer Square-Root
PARALLEL_ADD (Parallel Adder) Parallel Adder
If you are unfamiliar with IP cores, refer to the Introduction to IP Cores User Guide.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
1-2
Design Example Files
Altera also provides floating-point IP cores. For more information about the floating-point IP cores, refer
to the Floating-Point IP Cores User Guide.
Design Example Files
Altera provides design example files that are simulated in the ModelSim®-Altera software to generate a
waveform display of the device behavior.
You should be familiar with the ModelSim-Altera software before using the design examples. To get
started with the ModelSim-Altera software, refer to the ModelSim-Altera Software Support page on the
Altera website. The support page includes links to such topics as installation, usage, and troubleshooting.
For more details about the design example for a specific IP core, refer to the “Design Example” section for
that megafunction.
Design examples are provided only for some IP cores in this user guide.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II
software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions,
require that you purchase a separate license for production use. You can use the OpenCore Plus feature to
evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and
performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license
number for any Altera product.
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Figure 1-1: IP Core Installation Path
Note:
The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and
parameter editor allow you to quickly select and configure IP core ports, features, and output files.
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Search and filter IP for your target device
Double-click to customize, right-click for information
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IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter
editor and generate files representing your IP variation. The parameter editor prompts you to specify an
IP variation name, optional ports, and output file generation options. The parameter editor generates a
top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You
can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
partner IP information on the Altera website.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, andor view links to documentation.
IP Catalog and Parameter Editor
1-3
Figure 1-2: Quartus II IP Catalog
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View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
Legacy parameter
editors
1-4
Using the Parameter Editor
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Using the Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file generation options.
• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values
for specific applications.
• View port and parameter descriptions, and links to documentation.
• Generate testbench systems or example designs (where provided).
Figure 1-3: IP Parameter Editors
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Specifying IP Core Parameters and Options
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The parameter editor GUI allows you to quickly configure your custom IP variation. Use the following
steps to specify IP core options and parameters in the Quartus II software. Refer to Specifying IP Core
Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy
parameter editor.
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Specifying IP Core Parameters and Options
1-5
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Optionally select preset parameter values if provided for your IP core. Presets specify initial
parameter values for specific applications.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
7. To generate an HDL instantiation template that you can copy and paste into your text editor, click
Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If
you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in
Project to add the file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
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View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
1-6
Specifying IP Core Parameters and Options (Legacy Parameter Editors)
Figure 1-4: IP Parameter Editor
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Specifying IP Core Parameters and Options (Legacy Parameter Editors)
Some IP cores use a legacy version of the parameter editor for configuration and generation. Use the
following steps to configure and generate an IP variation using a legacy parameter editor.
Note:
The legacy parameter editor generates a different output file structure than the latest parameter
editor. Refer to Specifying IP Core Parameters and Options for configuration of IP cores that use the
latest parameter editor.
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Legacy parameter
editors
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Files Generated for Altera IP Cores (Legacy Parameter Editor)
Figure 1-5: Legacy Parameter Editors
1-7
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name and output HDL file type for your IP variation. This name identifies the IP
core variation files in your project. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor. Refer to your IP core
user guide for information about specific IP core parameters.
4. Click Finish or Generate (depending on the parameter editor version). The parameter editor generates
the files for your IP variation according to your specifications. Click Exit if prompted when generation
is complete. The parameter editor adds the top-level .qip file to the current project automatically.
Note:
To manually add an IP variation generated with legacy parameter editor to a project, click
Project > Add/Remove Files in Project and add the IP variation .qip file.
Files Generated for Altera IP Cores (Legacy Parameter Editor)
The Quartus II software version generates the following output for your IP core that uses the legacy
parameter editor.
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Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
<Project Directory>
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
<your_ip>.qip - Lists files for synthesis
testbench - Simulation testbench files
1
<testbench_hdl_files>
<simulator_vendor> - Testbench for supported simulators
<simulation_testbench_files>
<your_ip>.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
<your_ip>.sip - NativeLink simulation integration file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
<your_ip> - IP core variation files
<your_ip>.qip or .qsys - System or IP integration file
<your_ip>_generation.rpt - IP generation report
<your_ip>.bsf - Block symbol schematic file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation startup scripts
1
<your_ip>.html - Contains memory map
<your_ip>.sopcinfo - Software tool-chain integration file
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist
1
<your_ip>.debuginfo - Lists files for synthesis
<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models
2
<your_ip>_tb - Testbench for supported simulators
<your_ip>_tb.v or .vhd - Top-level HDL testbench file
1-8
Upgrading IP Cores
Figure 1-6: IP Core Generated Files
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Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
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compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.
The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_
BAK.v, .sv, .vhd in the project directory.
Table 1-2: IP Core Upgrade Status
IP Core Status Corrective Action
Upgrading IP Cores
1-9
Required Upgrade IP
Components
Optional Upgrade IP
Components
You must upgrade the IP variation before compiling in the current version of
the Quartus II software.
Upgrade is optional for this IP variation in the current version of the Quartus
II software. You can upgrade this IP variation to take advantage of the latest
development of this IP core. Alternatively you can retain previous IP core
characteristics by declining to upgrade.
Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the
Quartus II software due to IP core end of life or incompatibility with the
current version of the Quartus II software. You are prompted to replace the
obsolete IP core with a current equivalent IP core from the IP Catalog.
Before you begin
• Archive the Quartus II project containing outdated IP cores in the original version of the Quartus II
software: Click Project > Archive Project to save the project in your previous version of the Quartus II
software. This archive preserves your original design source and project files.
• Restore the archived project in the latest version of the Quartus II software: Click Project > Restore
Archived Project. Click OK if prompted to change to a supported device or overwrite the project
database. File paths in the archive must be relative to the project directory. File paths in the archive
must reference the IP variation .v or .vhd file or .qsys file (not the .qip file).
1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP
core variation. The Upgrade IP Components dialog automatically displays the status of IP cores in
your project, along with instructions for upgrading each core. Click Project > Upgrade IP
Components to access this dialog box manually.
2. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic
Upgrade. The Status and Version columns update when upgrade is complete. Example designs
provided with any Altera IP core regenerate automatically whenever you upgrade the IP core.
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Displays upgrade
status for all IP cores
in the Project
Upgrades all IP core that support “Auto Upgrade”
Upgrades individual IP cores unsupported by “Auto Upgrade”
Checked IP cores
support “Auto Upgrade”
Successful
“Auto Upgrade”
Upgrade
unavailable
Double-click to
individually migrate
1-10
Upgrading IP Cores
Figure 1-7: Upgrading IP Cores
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Example 1-1: Upgrading IP Cores at the Command Line
You can upgrade IP cores that support auto upgrade at the command line. IP cores that do not
support automatic upgrade do not support command line upgrade.
• To upgrade a single IP core that supports auto-upgrade, type the following command:
quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl>
<qii_project>
Example:
quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx
• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following
command:
quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>;
<my_ip_filepath/my_ip2>.<hdl>” <qii_project>
Example:
quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v"
hps_testx
IP cores older than Quartus II software version 12.0 do not support upgrade.
Note:
Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. The Altera IP Release Notes reports any verifica‐
tion exceptions for Altera IP cores. Altera does not verify compilation for IP cores
older than the previous two releases.
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Related Information
Altera IP Release Notes
Migrating IP Cores to a Different Device
IP migration allows you to target the latest device families with IP originally generated for a different
device. Some Altera IP cores require individual migration to upgrade. The Upgrade IP Components
dialog box prompts you to double-click IP cores that require individual migration.
1. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description
field prompts you to double-click IP cores that require individual migration.
2. Double-click the IP core name, and then click OK after reading the information panel.
The parameter editor appears showing the original IP core parameters.
3. For the Currently selected device family, turn off Match project/default, and then select the new
target device family.
4. Click Finish, and then click Finish again to migrate the IP variation using best-effort mapping to new
parameters and settings. Click OK if you are prompted that the IP core is unsupported for the current
device. A new parameter editor opens displaying best-effort mapped parameters.
5. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the
parameter editor default HDL for synthesis files. If your original IP core was generated for VHDL,
select VHDL to retain the original output HDL format.
6. To regenerate the new IP variation for the new target device, click Generate. When generation is
complete, click Close.
7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core
files. The Device Family column displays the migrated device support. The migration process replaces
<my_ip>.qip with the <my_ip>.qsys top-level IP file in your project.
Migrating IP Cores to a Different Device
1-11
If migration does not replace <my_ip>.qip with <my_ip>.qsys, click Project > Add/Remove
Note:
Files in Project to replace the file in your project.
8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration
may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL
generates into a library that is different from the original output location of the IP core. Update any
assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a
supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>.bsf
after migration.
The migration process may change the IP variation interface, parameters, and functionality.
Note:
This may require you to change your design or to re-parameterize your variant after the
Upgrade IP Components dialog box indicates that migration is complete. The Description
field identifies IP cores that require design or parameter changes.
Related Information
Altera IP Release Notes
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Post-fit timing
simulation netlist
Post-fit timing
simulation (3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
1-12
Simulating Altera IP Cores in other EDA Tools
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
Figure 1-8: Simulation in Quartus II Design Flow
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Note: Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IP
supports a variety of simulation models, including simulation-specific IP functional simulation
models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate
models. The models support fast functional simulation of your IP core instance using industrystandard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is
generated, and you can simulate that model. Use the simulation models only for simulation and
not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional
design.
Integer Arithmetic Megafunctions
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Integer Arithmetic Megafunctions
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ssclr
sload
inst
LPM_COUNTER
q[]
sset
cout
data[]
clk_en
cnt_en
cin
aclr
aload
aset
updown
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LPM_COUNTER (Counter)
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The LPM_COUNTER megafunction is a binary counter that creates up counters, down counters and up
or down counters with outputs of up to 256 bits wide.
The following figure shows the ports for the LPM_COUNTER megafunction.
Figure 2-1: LPM_COUNTER Ports
Features
The LPM_COUNTER megafunction offers the following features:
• Generates up, down, and up/down counters
• Generates the following counter types:
• Plain binary— the counter increments starting from zero or decrements starting from 255
• Modulus—the counter increments to or decrements from the modulus value specified by the user
• Supports optional synchronous clear, load, and set input ports
• Supports optional asynchronous clear, load, and set input ports
• Supports optional count enable and clock enable input ports
©
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
• Supports optional carry-in and carry-out ports
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
and repeats
ISO
9001:2008
Registered
2-2
Resource Utilization and Performance
Resource Utilization and Performance
The following table provides resource utilization and performance information for the LPM_COUNTER
megafunction.
Table 2-1: LPM_COUNTER Resource Utilization and Performance
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Logic Usage
Device family
Stratix III
Stratix IV
Input data
width
Output
latency
Adaptive
Look-Up
Table (ALUT)
Dedicated
Logic
Register
(DLR)
Adaptive
Logic
Module
(ALM)
4 - 9 4 6 723
8 - 9 8 5 808
16 - 17 16 9 705
24 - 25 24 13 583
32 - 33 32 17 489
64 - 65 64 33 329
4 - 9 4 6 768
8 - 9 8 5 896
16 - 17 16 9 825
24 - 25 24 13 716
32 - 33 32 17 639
64 - 65 64 33 470
f
MAX
(MHz)
(1)
Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v) lpm.v in the <Quartus II
installation directory>\eda\synthesis directory.
module lpm_counter ( q, data, clock, cin, cout, clk_en, cnt_en, updown,
aset, aclr, aload, sset, sclr, sload, eq );
parameter lpm_type = "lpm_counter";
parameter lpm_width = 1;
parameter lpm_modulus = 0;
parameter lpm_direction = "UNUSED";
parameter lpm_avalue = "UNUSED";
parameter lpm_svalue = "UNUSED";
parameter lpm_pvalue = "UNUSED";
parameter lpm_port_updown = "PORT_CONNECTIVITY";
parameter lpm_hint = "UNUSED";
output [lpm_width-1:0] q;
(1)
The performance of the megafunction is dependant on the value of the maximum allowable ceiling f
that the selected device can achieve. Therefore, results may vary from the numbers stated in this column.
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MAX
LPM_COUNTER (Counter)
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output cout;
output [15:0] eq;
input cin;
input [lpm_width-1:0] data;
input clock, clk_en, cnt_en, updown;
input aset, aclr, aload;
input sset, sclr, sload;
endmodule
VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd) LPM_PACK.vhd in the
<Quartus II installation directory>\libraries\vhdl\lpm directory.
component LPM_MULT
generic ( LPM_WIDTHA : natural;
LPM_WIDTHB : natural;
LPM_WIDTHS : natural := 1;
LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_MULT;
LPM_HINT : string := "UNUSED");
port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
VHDL Component Declaration
2-3
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY lpm;
USE lpm.lpm_components.all;
Ports
The following tables list the input and output ports for the LPM_COUNTER megafunction.
Table 2-2: LPM_COUNTER Megafunction Input Ports
Port Name Required Description
data[] No Parallel data input to the counter. The size of the input port
depends on the LPM_WIDTH parameter value.
clock Yes Positive-edge-triggered clock input.
clk_en No Clock enable input to enable all synchronous activities. If omitted,
the default value is 1.
LPM_COUNTER (Counter)
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Ports
Port Name Required Description
cnt_en No Count enable input to disable the count when asserted low
without affecting sload, sset, or sclr. If omitted, the default
value is 1.
updown No Controls the direction of the count. When asserted high (1), the
count direction is up, and when asserted low (0), the count
direction is down. If the LPM_DIRECTION parameter is used, the
updown port cannot be connected. If LPM_DIRECTION is not used,
the updown port is optional. If omitted, the default value is up (1).
cin No Carry-in to the low-order bit. For up counters, the behavior of the
cin input is identical to the behavior of the cnt_en input. If
omitted, the default value is 1 (VCC).
aclr No Asynchronous clear input. If both aset and aclr are used and
asserted, aclr overrides aset. If omitted, the default value is 0
(disabled).
aset No Asynchronous set input. Specifies the q[] outputs as all 1s, or to
the value specified by the LPM_AVALUE parameter. If both the aset
and aclr ports are used and asserted, the value of the aclr port
overrides the value of the aset port. If omitted, the default value is
0, disabled.
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aload No Asynchronous load input that asynchronously loads the counter
with the value on the data input. When the aload port is used, the
data[] port must be connected. If omitted, the default value is 0,
disabled.
sclr No Synchronous clear input that clears the counter on the next active
clock edge. If both the sset and sclr ports are used and asserted,
the value of the sclr port overrides the value of the sset port. If
omitted, the default value is 0, disabled.
sset No Synchronous set input that sets the counter on the next active
clock edge. Specifies the value of the q outputs as all 1s, or to the
value specified by the LPM_SVALUE parameter. If both the sset and
sclr ports are used and asserted, the value of the sclr port
overrides the value of the sset port. If omitted, the default value is
0 (disabled).
sload No Synchronous load input that loads the counter with data[] on the
next active clock edge. When the sload port is used, the data[]
port must be connected. If omitted, the default value is 0
(disabled).
Table 2-3: LPM_COUNTER Megafunction Output Ports
Port Name Required Description
q[] No Data output from the counter. The size of the output port
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depends on the LPM_WIDTH parameter value. Either q[] or at least
one of the eq[15..0] ports must be connected.
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eq[15..0] No Counter decode output. The eq[15..0] port is not accessible
cout No Carry-out port of the counter's MSB bit. It can be used to connect
Parameters
Port Name Required Description
using the MegaWizard Plug-In Manager as it is for AHDL use
only.
Either the q[] port or eq[] port must be connected. Up to c eq
ports can be used (0 <= c <= 15). Only the 16 lowest count values
are decoded. When the count value is c, the eqc output is asserted
high (1). For example, when the count is 0, eq0 = 1, when the
count is 1, eq1 = 1, and when the count is 15, eq 15 = 1. Decoded
output for count values of 16 or greater require external decoding.
The eq[15..0] outputs are asynchronous to the q[] output.
to another counter to create a larger counter.
The following table lists the parameters for the LPM_COUNTER megafunction.
Parameters
2-5
Table 2-4: LPM_COUNTER Megafunction Parameters
Parameter Name Type Required Description
LPM_WIDTH Integer Yes Specifies the widths of the data[] and q[]
ports, if they are used.
LPM_DIRECTION String No Values are UP, DOWN, and UNUSED. If the LPM_
DIRECTION parameter is used, the updown
port cannot be connected. When the
updown port is not connected, the LPM_
DIRECTION parameter default value is UP.
LPM_MODULUS Integer No The maximum count, plus one. Number of
unique states in the counter's cycle. If the
load value is larger than the LPM_MODULUS
parameter, the behavior of the counter is
not specified.
LPM_AVALUE Integer/
String
No Constant value that is loaded when aset is
asserted high. If the value specified is larger
than or equal to <modulus>, the behavior of
the counter is an undefined (X) logic level,
where <modulus> is LPM_MODULUS, if
present, or 2 ^ LPM_WIDTH. Altera
recommends that you specify this value as a
decimal number for AHDL designs.
LPM_SVALUE Integer/
LPM_COUNTER (Counter)
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String
No Constant value that is loaded on the rising
edge of the clock port when the sset port is
asserted high. Altera recommends that you
specify this value as a decimal number for
AHDL designs.
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Parameters
Parameter Name Type Required Description
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LPM_HINT String No
When you instantiate a library of
parameterized modules (LPM) function in a
VHDL Design File (.vhd), you must use the
LPM_HINT parameter to specify an Altera-
specific parameter. For example: LPM_HINT
= "CHAIN_SIZE = 8, ONE_INPUT_IS_
CONSTANT = YES"
The default value is UNUSED.
LPM_TYPE String No Identifies the library of parameterized
modules (LPM) entity name in VHDL
design files.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and
behavioral simulation purposes. Create the
LPM_COUNTER megafunction with the
MegaWizard Plug-In Manager to calculate
the value for this parameter.
CARRY_CNT_EN String No Altera-specific parameter. You must use the
LPM_HINT parameter to specify the CARRY_
CNT_EN parameter in VHDL design files.
Values are SMART, ON, OFF, and UNUSED.
Enables the LPM_COUNTER function to
propagate the cnt_en signal through the
carry chain. In some cases, the CARRY_CNT_
EN parameter setting might have a slight
impact on the speed, so you might want to
turn it off. The default value is SMART, which
provides the best trade-off between size and
speed.
LABWIDE_SCLR
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String No Altera-specific parameter. You must use the
LPM_HINT parameter to specify the
LABWIDE_SCLR parameter in VHDL design
files. Values are ON, OFF, or UNUSED. The
default value is ON. Allows you to disable the
use of the LAB-wide sclr feature found in
obsoleted device families. Turning this
option off increases the chances of fully
using the partially filled LABs, and thus may
allow higher logic density when SCLR does
not apply to a complete LAB. This
parameter is available for backward
compatibility, and Altera recommends you
not to use this parameter.
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Parameters
Parameter Name Type Required Description
LPM_PORT_UPDOWN String No Specifies the usage of the updown input port.
If omitted the default value is PORT_
CONNECTIVITY. When the port value is set
to PORT_USED, the port is treated as used.
When the port value is set to PORT_UNUSED,
the port is treated as unused. When the port
value is set to PORT_CONNECTIVITY, the port
usage is determined by checking the port
connectivity.
2-7
LPM_COUNTER (Counter)
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numer[]
denom[]
inst
LPM_DIVIDE
quotient[]
clken
clock
aclr
remain[]
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LPM_DIVIDE (Divider)
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The LPM_DIVIDE megafunction implements a divider to divide a numerator input value by a
denominator input value to produce a quotient and a remainder.
The following figure shows the ports for the LPM_DIVIDE megafunction.
Figure 3-1: LPM_DIVIDE Ports
Features
The LPM_DIVIDE megafunction offers the following features:
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• Generates a divider that divides a numerator input value by a denominator input value to produce a
• Supports data width of 1–256 bits.
• Supports signed and unsigned data representation format for both the numerator and denominator
• Supports area or speed optimization.
• Provides an option to specify a positive remainder output.
• Supports pipelining configurable output latency.
• Supports optional asynchronous clear and clock enable ports.
Resource Utilization and Performance
The following table provides resource utilization and performance information for the LPM_DIVIDE
megafunction.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
quotient and a remainder.
values.
ISO
9001:2008
Registered
3-2
Verilog HDL Prototype
Table 3-1: LPM_DIVIDE Resource Utilization and Performance
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Logic Usage
Device family
Input data
width
10 1 131 0 70 133
Stratix III
30 5 1017 0 635 71
64 10 4345 0 2623 41
10 1 131 0 70 138
Stratix IV
30 5 1018 0 642 82
64 10 4347 0 2634 48
Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v) lpm.v in the <Quartus II
installation directory>\eda\synthesis directory.
module lpm_divide ( quotient, remain, numer, denom, clock, clken, aclr);
parameter lpm_type = "lpm_divide";
parameter lpm_widthn = 1;
parameter lpm_widthd = 1;
parameter lpm_nrepresentation = "UNSIGNED";
parameter lpm_drepresentation = "UNSIGNED";
parameter lpm_remainderpositive = "TRUE";
parameter lpm_pipeline = 0;
parameter lpm_hint = "UNUSED";
input clock;
input clken;
input aclr;
input [lpm_widthn-1:0] numer;
input [lpm_widthd-1:0] denom;
output [lpm_widthn-1:0] quotient;
output [lpm_widthd-1:0] remain;
endmodule
Output
latency
Adaptive
Look-Up
Table (ALUT)
Dedicated
Logic
Register
(DLR)
Adaptive
Logic
Module
(ALM)
f
MAX
(MHz)
VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd) LPM_PACK.vhd in the
<Quartus II installation directory>\libraries\vhdl\lpm directory.
component LPM_DIVIDE
generic (LPM_WIDTHN : natural;
LPM_WIDTHD : natural;
LPM_NREPRESENTATION : string := "UNSIGNED";
LPM_DREPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_DIVIDE;
LPM_HINT : string := "UNUSED");
port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0);
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LPM_DIVIDE (Divider)
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DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0);
REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0));
end component;
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY lpm;
USE lpm.lpm_components.all;
Ports
The following tables list the input and output ports for the LPM_DIVIDE megafunction.
Table 3-2: LPM_DIVIDE Megafunction Input Ports
VHDL LIBRARY_USE Declaration
3-3
Port Name Required Description
numer[] Yes Numerator data input. The size of the input port
depends on the LPM_WIDTHN parameter value.
denom[] Yes Denominator data input. The size of the input port
depends on the LPM_WIDTHD parameter value.
clock No Clock input for pipelined usage. For LPM_PIPELINE
values other than 0 (default), the clock port must be
enabled.
clken No Clock enable pipelined usage. When the clken port is
asserted high, the division operation takes place.
When the signal is low, no operation occurs. If
omitted, the default value is 1.
aclr No Asynchronous clear port used at any time to reset the
pipeline to all '0's asynchronously to the clock input.
Table 3-3: LPM_DIVIDE Megafunction Output Ports
Port Name Required Description
quotient[] Yes Data output. The size of the output port depends on
the LPM_WIDTHN parameter value.
remain[] Yes Data output. The size of the output port depends on
the LPM_WIDTHD parameter value.
Parameters
LPM_DIVIDE (Divider)
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Parameters
The following table lists the parameters for the LPM_DIVIDE megafunction.
Parameter Name Type Required Description
LPM_WIDTHN Integer Yes Specifies the widths of the numer[]
and quotient[] ports. Values are 1 to
64.
LPM_WIDTHD Integer Yes Specifies the widths of the denom[]
and remain[] ports. Values are 1 to
64.
LPM_NREPRESENTATION String No Sign representation of the numerator
input. Values are SIGNED and
UNSIGNED. When this parameter is set
to SIGNED, the divider interprets the
numer[] input as signed two's
complement.
LPM_DREPRESENTATION String No Sign representation of the
denominator input. Values are SIGNED
and UNSIGNED. When this parameter is
set to SIGNED, the divider interprets
the denom[] input as signed two's
complement.
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LPM_TYPE String No Identifies the library of parameterized
modules (LPM) entity name in VHDL
design files (.vhd).
LPM_HINT String No
When you instantiate a library of
parameterized modules (LPM)
function in a VHDL Design File (.vhd)
, you must use the LPM_HINT
parameter to specify an Altera-specific
parameter. For example: LPM_HINT =
"CHAIN_SIZE = 8, ONE_INPUT_IS_
CONSTANT = YES"
The default value is UNUSED.
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LPM_DIVIDE (Divider)
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Parameters
Parameter Name Type Required Description
LPM_REMAINDERPOSITIVE String No Altera-specific parameter. You must
use the LPM_HINT parameter to specify
the LPM_REMAINDERPOSITIVE
parameter in VHDL design files.
Values are TRUE or FALSE. If this
parameter is set to TRUE, then the value
of the remain[] port must be greater
than or equal to zero. If this parameter
is set to TRUE, then the value of the
remain[] port is either zero, or the
value is the same sign, either positive
or negative, as the value of the numer
port. In order to reduce area and
improve speed, Altera recommends
setting this parameter to TRUE in
operations where the remainder must
be positive or where the remainder is
unimportant.
3-5
MAXIMIZE_SPEED
LPM_PIPELINE
Integer No Altera-specific parameter. You must
use the LPM_HINT parameter to specify
the MAXIMIZE_SPEED parameter in
VHDL design files. Values are [0..9].
If used, the Quartus II software
attempts to optimize a specific
instance of the LPM_DIVIDE function
for speed rather than routability, and
overrides the setting of the Optimiza‐
tion Technique logic option. If
MAXIMIZE_SPEED is unused, the value
of the Optimization Technique option
is used instead. If the value of
MAXIMIZE_SPEED is 6 or higher, the
Compiler optimizes the LPM_DIVIDE
megafunctions for higher speed by
using carry chains; if the value is 5 or
less, the compiler implements the
design without carry chains.
Integer No Specifies the number of clock cycles of
latency associated with the
quotient[] and remain[] outputs. A
value of zero (0) indicates that no
latency exists, and that a purely
combinational function is instantiated.
If omitted, the default value is 0 (nonpipelined). You cannot specify a value
for the LPM_PIPELINE parameter that
is higher than LPM_WIDTHN.
LPM_DIVIDE (Divider)
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