Altera Arria 10 Avalon-MM User Manual
Arria 10 Avalon-MM Interface for PCIe
Solutions
User Guide
Last updated for Altera Complete Design Suite: 15.0
Subscribe
Send Feedback
UG-01145_avm
2015.05.14
101 Innovation Drive
m
San Jose, CA 95134
www.altera.com
TOC-2
Contents
Datasheet............................................................................................................. 1-1
Arria 10 Avalon-MM Interface for PCIe Datasheet ...............................................................................1-1
Features ........................................................................................................................................................ 1-2
Release Information ....................................................................................................................................1-6
Device Family Support ...............................................................................................................................1-7
Configurations .............................................................................................................................................1-7
Example Designs..........................................................................................................................................1-9
Debug Features ..........................................................................................................................................1-10
IP Core Verification ..................................................................................................................................1-10
Compatibility Testing Environment ..........................................................................................1-10
Performance and Resource Utilization ..................................................................................................1-10
Recommended Speed Grades ..................................................................................................................1-11
Steps in Creating a Design for PCI Express........................................................................................... 1-11
Getting Started with the Avalon-MM Arria 10 Hard IP for PCI Express .........2-1
Running Qsys .............................................................................................................................................. 2-2
Generating the Example Design ............................................................................................................... 2-3
Understanding Simulation Log File Generation..................................................................................... 2-5
Running a Gate-Level Simulation..............................................................................................................2-5
Simulating the Single DWord Design ......................................................................................................2-5
Generating Quartus II Synthesis Files.......................................................................................................2-6
Creating a Quartus II Project .................................................................................................................... 2-6
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)................................................. 2-7
Compiling the Design .................................................................................................................................2-7
Programming a Device ...............................................................................................................................2-7
Understanding Channel Placement Guidelines ..................................................................................... 2-7
Parameter Settings.............................................................................................. 3-1
Arria 10 Avalon-MM System Settings ..................................................................................................... 3-1
Interface System Settings ........................................................................................................................... 3-4
Base Address Register (BAR) Settings ......................................................................................................3-6
Device Identification Registers ..................................................................................................................3-7
PCI Express and PCI Capabilities Parameters ........................................................................................3-8
Device Capabilities ..........................................................................................................................3-8
Error Reporting ...............................................................................................................................3-9
Link Capabilities ........................................................................................................................... 3-10
MSI and MSI-X Capabilities ........................................................................................................3-11
Slot Capabilities .............................................................................................................................3-12
Power Management ......................................................................................................................3-13
Altera Corporation
TOC-3
Physical Layout of Hard IP In Arria 10 Devices.................................................4-1
Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates..............................................4-4
Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates............................................4-5
Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate...................................... 4-7
64- or 128-Bit Avalon-MM Interface to the Application Layer......................... 5-1
32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals .............................5-3
RX Avalon-MM Master Signals ................................................................................................................5-3
64- or 128-Bit Bursting TX Avalon-MM Slave Signals ..........................................................................5-5
Clock Signals ................................................................................................................................................5-8
Reset...............................................................................................................................................................5-8
Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled .......................................5-10
Hard IP Reconfiguration Interface .........................................................................................................5-11
Physical Layer Interface Signals ..............................................................................................................5-13
Serial Data Signals .........................................................................................................................5-13
PIPE Interface Signals .................................................................................................................. 5-14
Test Signals .................................................................................................................................... 5-19
Registers...............................................................................................................6-1
Correspondence between Configuration Space Registers and the PCIe Specification .....................6-1
Type 0 Configuration Space Registers ..................................................................................................... 6-5
Type 1 Configuration Space Registers ..................................................................................................... 6-6
PCI Express Capability Structures.............................................................................................................6-6
Altera-Defined VSEC Registers................................................................................................................. 6-9
CvP Registers..............................................................................................................................................6-10
64- or 128-Bit Avalon-MM Bridge Register Descriptions .................................................................. 6-13
Avalon-MM to PCI Express Interrupt Registers ......................................................................6-15
Programming Model for Avalon-MM Root Port .................................................................................6-26
Sending a Write TLP .................................................................................................................... 6-27
Sending a Read TLP or Receiving a Non-Posted Completion TLP .......................................6-28
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports ............6-28
Root Port TLP Data Registers ..................................................................................................... 6-29
Uncorrectable Internal Error Mask Register ........................................................................................ 6-31
Uncorrectable Internal Error Status Register ....................................................................................... 6-32
Correctable Internal Error Mask Register .............................................................................................6-33
Correctable Internal Error Status Register ............................................................................................6-34
Arria 10 Reset and Clocks................................................................................... 7-1
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer ....................................7-2
Clocks ........................................................................................................................................................... 7-4
Clock Domains ................................................................................................................................7-4
Clock Summary ...............................................................................................................................7-6
Interrupts for Endpoints ....................................................................................8-1
Altera Corporation
TOC-4
Enabling MSI or Legacy Interrupts .......................................................................................................... 8-2
Generation of Avalon-MM Interrupts .....................................................................................................8-3
Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
...................................................................................................................................................................8-3
Error Handling ................................................................................................... 9-1
Physical Layer Errors ..................................................................................................................................9-2
Data Link Layer Errors ...............................................................................................................................9-2
Transaction Layer Errors ...........................................................................................................................9-3
Error Reporting and Data Poisoning ....................................................................................................... 9-6
Uncorrectable and Correctable Error Status Bits ...................................................................................9-7
IP Core Architecture......................................................................................... 10-1
Top-Level Interfaces .................................................................................................................................10-3
Avalon-MM Interface............................................................................................................................... 10-3
Clocks and Reset ....................................................................................................................................... 10-3
Interrupts ................................................................................................................................................... 10-3
PIPE ............................................................................................................................................................ 10-3
Data Link Layer .........................................................................................................................................10-4
Physical Layer ............................................................................................................................................10-6
32-Bit PCI Express Avalon-MM Bridge ................................................................................................ 10-8
Avalon-MM Bridge TLPs .......................................................................................................... 10-11
Avalon-MM-to-PCI Express Write Requests .........................................................................10-11
Avalon-MM-to-PCI Express Upstream Read Requests ........................................................10-11
PCI Express-to-Avalon-MM Read Completions ................................................................... 10-12
PCI Express-to-Avalon-MM Downstream Write Requests ................................................. 10-12
PCI Express-to-Avalon-MM Downstream Read Requests ...................................................10-12
Avalon-MM-to-PCI Express Read Completions ................................................................... 10-13
PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge ..................................10-13
Minimizing BAR Sizes and the PCIe Address Space .............................................................10-15
Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing ......10-17
Completer Only Single Dword Endpoint ............................................................................................10-19
RX Block .......................................................................................................................................10-20
Avalon-MM RX Master Block .................................................................................................. 10-20
TX Block .......................................................................................................................................10-21
Interrupt Handler Block ............................................................................................................ 10-21
Design Implementation.................................................................................... 11-1
Throughput Optimization................................................................................ 12-1
Altera Corporation
Making Pin Assignments to Assign I/O Standard to Serial Data Pins ..............................................11-1
Recommended Reset Sequence to Avoid Link Training Issues ......................................................... 11-1
SDC Timing Constraints.......................................................................................................................... 11-2
Throughput of Posted Writes ................................................................................................................. 12-3
Throughput of Non-Posted Reads ......................................................................................................... 12-3
TOC-5
Optional Features..............................................................................................13-1
Configuration via Protocol (CvP) .......................................................................................................... 13-1
ECRC ..........................................................................................................................................................13-2
ECRC on the RX Path .................................................................................................................. 13-2
ECRC on the TX Path .................................................................................................................. 13-3
Avalon-MM Testbench and Design Example .................................................. 14-1
Arria 10 Avalon-MM Endpoint Testbench ...........................................................................................14-2
Arria 10 Avalon-MM Root Port Testbench ..........................................................................................14-4
Endpoint Design Example........................................................................................................................14-4
BAR/Address Map ........................................................................................................................14-6
Avalon-MM Test Driver Module ........................................................................................................... 14-7
DMA Write Cycles ................................................................................................................................... 14-8
DMA Read Cycles ...................................................................................................................................14-10
Avalon-MM Root Port Design Example .............................................................................................14-12
Root Port BFM ........................................................................................................................................14-14
BFM Memory Map .....................................................................................................................14-16
Configuration Space Bus and Device Numbering ................................................................. 14-16
Configuration of Root Port and Endpoint ..............................................................................14-16
Issuing Read and Write Transactions to the Application Layer .......................................... 14-21
BFM Procedures and Functions ........................................................................................................... 14-22
ebfm_barwr Procedure .............................................................................................................. 14-22
ebfm_barwr_imm Procedure ....................................................................................................14-23
ebfm_barrd_wait Procedure ..................................................................................................... 14-24
ebfm_barrd_nowt Procedure ....................................................................................................14-25
ebfm_cfgwr_imm_wait Procedure ...........................................................................................14-26
ebfm_cfgwr_imm_nowt Procedure ......................................................................................... 14-26
ebfm_cfgrd_wait Procedure ......................................................................................................14-27
ebfm_cfgrd_nowt Procedure .....................................................................................................14-28
BFM Configuration Procedures................................................................................................ 14-29
BFM Shared Memory Access Procedures ............................................................................... 14-31
BFM Log and Message Procedures .......................................................................................... 14-34
Verilog HDL Formatting Functions ........................................................................................ 14-38
Procedures and Functions Specific to the Chaining DMA Design Example......................14-42
Setting Up Simulation.............................................................................................................................14-49
Changing Between Serial and PIPE Simulation ..................................................................... 14-49
Using the PIPE Interface for Gen1 and Gen2 Variants .........................................................14-49
Viewing the Important PIPE Interface Signals........................................................................14-49
Disabling the Scrambler for Gen1 and Gen2 Simulations ....................................................14-49
Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations.....................14-50
Debugging .........................................................................................................15-1
Simulation Fails To Progress Beyond Polling.Active State..................................................................15-1
Hardware Bring-Up Issues ......................................................................................................................15-1
Link Training .............................................................................................................................................15-2
Altera Corporation
TOC-6
Use Third-Party PCIe Analyzer ..............................................................................................................15-2
BIOS Enumeration Issues ........................................................................................................................15-3
Frequently Asked Questions.............................................................................. A-1
Lane Initialization and Reversal ........................................................................B-1
Additional Information......................................................................................C-1
Revision History for the Avalon-MM Interface......................................................................................C-1
How to Contact Altera............................................................................................................................... C-4
Typographic Conventions......................................................................................................................... C-5
Altera Corporation
2015.05.14
Bridge
PCIe Hard IP
Block
PIPE
Interface
PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
Application
Layer
(User Logic)
Avalon-MM
Interface
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Datasheet
1
UG-01145_avmm
Subscribe
Send Feedback
Arria 10 Avalon-MM Interface for PCIe Datasheet
Altera® Arria® 10 FPGAs include a configurable, hardened protocol stack for PCI Express
compliant with PCI Express Base Specification 3.0.
The Hard IP for PCI Express IP core using the Avalon ® Memory-Mapped (Avalon-MM) interface
removes some of the complexities associated with the PCIe protocol. For example, it handles all of the
Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design
more quickly. The Avalon-MM interface is implemented as a bridge in soft logic. It is available in Qsys.
Figure 1-1: Arria 10 PCIe Variant with Avalon-MM Interface
The following figure shows the high-level modules and connecting interfaces for this variant.
®
that is
Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4,
and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2,
and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive
(RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces
a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding
to less than 1%.
PCI Express Gen1
(2.5 Gbps)
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Link Width in Gigabits Per Second (Gbps)
x1 x2 x4 x8
2 4 8 16
ISO
9001:2008
Registered
1-2
Features
UG-01145_avmm
2015.05.14
Link Width in Gigabits Per Second (Gbps)
x1 x2 x4 x8
PCI Express Gen2
(5.0 Gbps)
PCI Express Gen3
(8.0 Gbps)
Refer to AN 456: PCI Express High Performance Reference Design for more information about calculating
bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Arria 10
Hard IP for PCI Express IP core.
Related Information
• PCI Express Base Specification 3.0
• AN 456: PCI Express High Performance Reference Design
• Creating a System with Qsys
Features
New features in the Quartus® II 15.0 software release:
• Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY
register programming with the Altera System Console.
• Dynamic generation of Qsys design examples using the parameters that you specify.
• Added Root Port support for transmitting messages of length greater than one dword.
4 8 16 32
7.87 15.75 31.51 63
The Arria 10 Hard IP for PCI Express with the Avalon-MM interface supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and
Endpoints.
• Dedicated 16 KByte receive buffer.
• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core
bitstreams to be stored separately.
• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error
reporting (AER) for high reliability applications.
• Easy to use:
• Flexible configuration.
• No license requirement.
• Example designs to get started.
Altera Corporation
Datasheet
Send Feedback
UG-01145_avmm
2015.05.14
Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores
The table compares the features of the four Hard IP for PCI Express IP Cores.
Features
1-3
Feature Avalon-ST Interface Avalon-MM
Interface
Avalon-MM DMA Avalon-ST Interface with SR-
IP Core License Free Free Free Free
Native
Supported Supported Supported Supported
Endpoint
Legacy
Endpoint
(1)
Supported Not Supported Not Supported Not Supported
Root port Supported Supported Not Supported Not Supported
Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported
Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8
Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×2, ×4, ×8
64-bit Applica‐
Supported Supported Not supported Not supported
×8
×4, ×8
×2, ×4, ×8
tion Layer
interface
IOV
128-bit
Supported Supported Supported Supported
Application
Layer interface
256-bit
Supported Not Supported Supported Supported
Application
Layer interface
Maximum
payload size
Number of tags
128, 256, 512,
1024, 2048 bytes
256 8 16 256
supported for
non-posted
requests
(1)
Not recommended for new designs.
128, 256 bytes 128, 256 bytes 128, 256 bytes
Datasheet
Altera Corporation
Send Feedback
1-4
Features
UG-01145_avmm
2015.05.14
Feature Avalon-ST Interface Avalon-MM
Interface
Automatically
Not supported Supported Supported Not supported
handle out-oforder
completions
(transparent to
the Application
Layer)
Automatically
Not supported Supported Supported Not Supported
handle requests
that cross 4
KByte address
boundary
(transparent to
the Application
Layer)
Polarity
Supported Supported Supported Supported
Inversion of
PIPE interface
signals
Avalon-MM DMA Avalon-ST Interface with SR-
IOV
Number of MSI
requests
1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for
Physical Functions)
MSI-X Supported Supported Supported Supported
Legacy
Supported Supported Supported Supported
interrupts
Expansion
Supported Not supported Not supported Not supported
ROM
Table 1-3: TLP Support Comparison for all Hard IP for PCI Express IP Cores
The table compares the TLP types that the four Hard IP for PCI Express IP Cores can transmit. Each entry
indicates whether this TLP type is supported (for transmit) by endpoints (EP), Root Ports (RP), or both (EP/RP).
Transaction Layer
Packet type (TLP)
(transmit support)
Memory Read
Avalon-ST Interface Avalon-MM
Interface
Avalon-MM DMA Avalon-ST Interface with SR-
EP/RP EP/RP EP EP
IOV
Request (Mrd)
Altera Corporation
Datasheet
Send Feedback
UG-01145_avmm
2015.05.14
Features
1-5
Transaction Layer
Packet type (TLP)
(transmit support)
Memory Read
Lock Request
(MRdLk)
Memory Write
Request (MWr)
I/O Read
Request (IORd)
I/O Write
Request (IOWr)
Config Type 0
Read Request
(CfgRd0)
Config Type 0
Write Request
(CfgWr0)
Config Type 1
Read Request
(CfgRd1)
Avalon-ST Interface Avalon-MM
Interface
Avalon-MM DMA Avalon-ST Interface with SR-
EP/RP EP EP
EP/RP EP/RP EP EP
EP/RP EP/RP EP
EP/RP EP/RP EP
RP RP EP
RP RP EP
RP RP EP
IOV
Config Type 1
Write Request
(CfgWr1)
Message
Request (Msg)
Message
Request with
Data (MsgD)
Completion
(Cpl)
Completion
with Data
(CplD)
CompletionLocked (CplLk)
Completion
Lock with Data
(CplDLk)
RP RP EP
EP/RP EP/RP EP
EP/RP EP/RP EP
EP/RP EP/RP EP EP
EP/RP EP EP
EP/RP EP
EP/RP EP
Datasheet
Altera Corporation
Send Feedback
1-6
Release Information
UG-01145_avmm
2015.05.14
Transaction Layer
Packet type (TLP)
(transmit support)
Fetch and Add
Avalon-ST Interface Avalon-MM
EP
AtomicOp
Request
(FetchAdd)
The Arria 10 Avalon-MM Interface for PCIe Solutions User Guide explains how to use this IP core and not
the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this
document only in conjunction with an understanding of the PCI Express Base Specification.
Note: This release provides separate user guides for the different variants. The Related Information
provides links to all versions.
Related Information
• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
• Arria 10 Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide
• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
Release Information
Interface
Avalon-MM DMA Avalon-ST Interface with SR-
IOV
Table 1-4: Hard IP for PCI Express Release Information
Item Description
Version 15.0
Release Date May 2015
Ordering Codes No ordering code is required
Product IDs There are no encrypted files for the Arria 10 Hard
IP for PCI Express. The Product ID and Vendor ID
Vendor ID
are not required because this IP core does not
require a license.
Altera Corporation
Datasheet
Send Feedback
UG-01145_avmm
2015.05.14
Device Family Support
Table 1-5: Device Family Support
Device Family Support
Device Family Support
1-7
Arria 10
Preliminary. The IP core is verified with prelimi‐
nary timing models for this device family. The IP
core meets all functional requirements, but might
still be undergoing timing analysis for the device
family. It can be used in production designs with
caution.
Other device families Refer to the Altera's PCI Express IP Solutions web
page for support information on other device
families.
Related Information
• Altera's PCI Express IP Solutions web page
Configurations
The Avalon-MM Arria 10 Hard IP for PCI Express includes a full hard IP implementation of the PCI
Express stack comprising the following layers:
• Physical (PHY), including:
• Physical Media Attachment (PMA)
• Physical Coding Sublayer (PCS)
• Media Access Control (MAC)
• Data Link Layer (DL)
• Transaction Layer (TL)
Datasheet
When configured as an Endpoint, the Arria 10 Hard IP for PCI Express using the Avalon-MM supports
memory read and write requests and completions with or without data.
Altera Corporation
Send Feedback
Altera FPGA
User Application
Logic
PCIe
Hard IP
RP
PCIe
Hard IP
EP
User Application
Logic
PCI Express Link
Altera FPGA
1-8
Configurations
Figure 1-2: PCI Express Application with a Single Root Port and Endpoint
The following figure shows a PCI Express link between two Arria 10 FPGAs.
Figure 1-3: PCI Express Application Using Configuration via Protocol
The Arria 10 design below includes the following components:
• A Root Port that connects directly to a second FPGA that includes an Endpoint.
• Two Endpoints that connect to a PCIe switch.
• A host CPU that implements CvP using the PCI Express link connects through the switch. For more
information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP)
on page 13-1.
UG-01145_avmm
2015.05.14
Altera Corporation
Datasheet
Send Feedback
PCIe Link
PCIe Hard IP
RP
Switch
PCIe
Hard IP
RP
User Application
Logic
PCIe Hard IP
EP
PCIe Link
PCIe Link
User Application
Logic
Altera FPGA Hard IP for PCI Express
Altera FPGA with Hard IP for PCI Express
Active Serial or
Active Quad
Device Configuration
Configuration via Protocol (CvP)
using the PCI Express Link
Serial or
Quad Flash
USB
Download
cable
PCIe
Hard IP
EP
User
Application
Logic
Altera FPGA with Hard IP for PCI Express
Config
Control
CVP
USB
Host CPU
PCIe
UG-01145_avmm
2015.05.14
Example Designs
1-9
Related Information
Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide
Example Designs
Qsys example designs are available for the Avalon-MM Arria 10 Hard IP for PCI Express IP Core. You
can download them from the <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10
directory:
When you click the Example Design button in the Parameter Editor, you are prompted to specify the
example design location. After example design generation completes, this directory contains one or two
example designs. One is the example design from the <install_dir> that best matches the current parameter
settings. This example design provides a static DUT. The other example design is a customized example
design that matches your parameter settings exactly; starting in the Quartus II software v15.0, this feature
is available for most but not all IP core variations. If this feature is not available for your particular
parameter settings, the Parameter Editor displays a warning.
Related Information
Getting Started with the Avalon-MM Arria 10 Hard IP for PCI Express on page 2-1
Datasheet
Send Feedback
Altera Corporation
1-10
Debug Features
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
Debugging on page 15-1
IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration
Space, and all types and sizes of TLPs
• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and
check for the proper responses
• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
UG-01145_avmm
2015.05.14
Altera provides example designs that you can leverage to test your PCBs and complete compliance base
board testing (CBB testing) at PCI-SIG, upon request.
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no
ALMs and no embedded memory).
The Avalon-MM soft logic bridge functions as a front end to the hardened protocol stack. The following
table shows the typical device resource utilization for selected configurations using the current version of
the Quartus II software. With the exception of M20K memory blocks, the numbers of ALMs and logic
registers are rounded up to the nearest 50.
Table 1-6: Performance and Resource Utilization Avalon-MM Hard IP for PCI Express
Interface Width ALMs M20K Memory Blocks Logic Registers
Altera Corporation
Avalon-MM Bridge
64 1100 17 1500
Datasheet
Send Feedback
UG-01145_avmm
2015.05.14
Interface Width ALMs M20K Memory Blocks Logic Registers
128 1900 25 2900
64 650 8 1000
128 1400 12 2400
64 250 0 350
Related Information
Fitter Resources Reports
Recommended Speed Grades
Recommended speed grades are pending characterization of production Arria 10 devices.
Recommended Speed Grades
Avalon-MM Interface–Completer Only
Avalon-MM–Completer Only Single Dword
1-11
Related Information
• Area and Timing Optimization
• Altera Software Installation and Licensing Manual
• Setting up and Running Analysis and Synthesis
Steps in Creating a Design for PCI Express
Before you begin
Select the PCIe variant that best meets your design requirements.
• Is your design an Endpoint or Root Port?
• What Generation do you intend to implement?
• What link width do you intend to implement?
• What bandwidth does your application require?
• Does your design require CvP?
1. Select parameters for that variant.
2. Simulate using an Altera-provided example design. All of Altera's static PCI Express example designs
are available under <install_dir>/ip/altera/altera_pcie/. Alternatively, generate an example design that
matches your parameter settings, or create a simulation model and use your own custom or thirdparty BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim-Altera
Datasheet
Altera Corporation
Send Feedback
1-12
Steps in Creating a Design for PCI Express
UG-01145_avmm
2015.05.14
for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim,
and Synopsys VCS and VCS-MX simulators.
3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II
software you are running do not match, regenerate your PCIe design.
4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐
ment Kits link below for a list of Altera's development boards.
5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol
analyzer to observe behavior.
6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then
repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test).
The Application Layer logic is typically called APPS.
Related Information
• Parameter Settings on page 3-1
• Getting Started with the Avalon-MM Arria 10 Hard IP for PCI Express on page 2-1
• All Development Kits
Altera Corporation
Datasheet
Send Feedback
Getting Started with the Avalon‑MM Arria 10
Transaction,
Data Link,
and PHY
Layers
O n-C hip
Memory
DMA
Qsys System Design for PCI Express
PCI Express
Link
PCI
Express
Avalon-MM
Bridge
Interconnect
Avalon-MM Hard IP for PCI Express
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Hard IP for PCI Express
2015.05.14
UG-01145_avmm
Subscribe
This Qsys design example provides detailed step-by-step instructions to generate a Qsys system. When
you install the Quartus II software you also install the IP Library. This installation includes design
examples for the Avalon-MM Arria 10 Hard IP for PCI Express in the <install_dir>/ip/altera/altera_pcie/
altera_pcie_a10_ed/example_design/a10 directory. This walkthrough uses a Gen2 x4 Endpoint,
ep_g2x4_avmm128.qsys.
The design examples contain the following components:
• Avalon-MM Arria 10 Hard IP for PCI Express IP core
• On-Chip memory
• DMA controller
Figure 2-1: Qsys Generated Endpoint
Send Feedback
2
The design example transfers data between an on-chip memory buffer located on the Avalon-MM side
and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA
component which is programmed by the PCI Express software application running on the Root Complex
processor.
Related Information
©
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
• Generating the Example Design on page 2-3
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
ISO
9001:2008
Registered
2-2
Running Qsys
• Creating a System with Qsys
This document provides an introduction to Qsys.
Running Qsys
1. Choose Programs > Altera > Quartus II><version_number> (Windows Start menu) to run the
Quartus II software. Alternatively, you can also use the Quartus II Web Edition software.
2. On the File menu, select New, then Qsys System File.
3. Open the ep_g2x4_avmm128.qsys example design.
The following figure shows a Qsys system that includes the Transceiver Reconfiguration Controller and
the Altera PCIe Reconfig Driver IP Cores. The Transceiver Reconfiguration Controller performs dynamic
reconfiguration of the analog transceiver settings to optimize signal quality. You must include these
components to the Qsys system to run successfully in hardware.
Figure 2-2: Qsys Avalon-MM Design for PCIe with Transceiver Reconfiguration Components
UG-01145_avmm
2015.05.14
Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about
how to use Qsys. For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.
Related Information
• Creating a System with Qsys
• About Qsys
Altera Corporation
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
UG-01145_avmm
2015.05.14
Generating the Example Design
1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.
2. Under Testbench System, set the following options:
a. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.
b. For Create testbench simulation model, select Verilog.
3. You can retain the default values for all other parameters.
4. Click Generate.
5. After Qsys reports Generation Completed, click Close.
6. On the File menu, click Save.
The following table lists the testbench and simulation directories Qsys generates.
Table 2-1: Qsys System Generated Directories
Directory Location
Generating the Example Design
2-3
Qsys system
Simulation Directory
<project_dir>/ep_g2x4_avmm128_tb
<project_dir>/ep_g2x4_avmm128_tb/ep_g2x4_tb/sim/
<cad_vendor>
The design example simulation includes the following components and software:
• The Qsys system
• A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4_avmm128_tb/ep_
g2x4_avmm128_tb.qsys.
• The ModelSim software
Note:
You can also use any other supported third-party simulator to simulate your design.
Complete the following steps to run the Qsys testbench:
1. In a terminal window, change to the <project_dir>/ep_g2x4_avmm128_tb/ep_g2x4_avmm128_tb/sim/
mentor directory.
2. Start the ModelSim® simulator.
3. Type the following commands in a terminal window:
a. do msim_setup.tcl
b. ld_debug
c. run 140000 ns
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
Altera Corporation
2-4
Generating the Example Design
The driver performs the following transactions with status of the transactions displayed in the ModelSim
simulation message window:
1. Various configuration accesses to the Avalon-MM Arria 10 Hard IP for PCI Express in your system
after the link is initialized
2. Setup of the Address Translation Table for requests that are coming from the DMA component
3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared
memory
4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared
memory
5. Data comparison and report of any mismatch
The following example shows the transcript from a successful simulation run.
Example 2-1: Transcript from ModelSim Simulation of Gen2 x4 Endpoint
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17257 ns RP LTSSM State: DETECT.QUIET
# INFO: 17353 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 17405 ns RP LTSSM State: DETECT.QUIET
# INFO: 17485 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 18249 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 23685 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 28510 ns RP LTSSM State: DETECT.QUIET
. . .
# INFO: 44777 ns RP LTSSM State: POLLING.CONFIG
# INFO: 45865 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 46213 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 46885 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 47353 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 48549 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 48825 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 48869 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 49145 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 49337 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 49657 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 50149 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 51429 ns RP LTSSM State: CONFIG.IDLE
# INFO: 51456 ns EP LTSSM State: CONFIG.IDLE
# INFO: 51609 ns RP LTSSM State: L0
# INFO: 51909 ns EP LTSSM State: L0
. . .
# INFO: 82248 ns Completed configuration of Endpoint BARs.
# INFO: 83016 ns Starting Target Write/Read Test.
# INFO: 83016 ns Target BAR = 0
# INFO: 83016 ns Length = 000512,Start Offset=000000
# INFO: 85264 ns Target Write and Read compared okay
# INFO: 85264 ns Starting DMA Read/Write Test.
# INFO: 85264 ns Setup BAR = 2
# INFO: 85264 ns Length = 000512, Start Offset = 000000
# INFO: 88616 ns Interrupt Monitor: Interrupt INTA Asserted
# INFO: 88616 ns Clear Interrupt INTA
# INFO: 89400 ns Interrupt Monitor: Interrupt INTA Deasserted
# INFO: 92892 ns MSI received!
# INFO: 92896 ns DMA Read and Write compared okay!
# SUCCESS: Simulation stopped due to successful completion!
# Break in Function ebfm_log_stop_sim at ./..//ep_g1x4_avmm64_tb/simulation/
submodules//altpcietb_bfm_log.v line 78
UG-01145_avmm
2015.05.14
Altera Corporation
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
UG-01145_avmm
2015.05.14
Related Information
Simulating Altera Designs
Understanding Simulation Log File Generation
Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_
monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.
Table 2-2: Sample Simulation Log File Entries
Understanding Simulation Log File Generation
2-5
Time TLP Type Payload
(Bytes)
17989 RX CfgRd0 0004 04000001_0000000F_01080008
17989 RX MRd 0000 00000000_00000000_01080000
18021 RX CfgRd0 0004 04000001_0000010F_0108002C
18053 RX CfgRd0 0004 04000001_0000030F_0108003C
18085 RX MRd 0000 00000000_00000000_0108000C
Running a Gate-Level Simulation
The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to
create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an
example that illustrate how to create a gate-level simulation from the RTL testbench.
Simulating the Single DWord Design
You can use the same testbench to simulate the Completer-Only Single Dword IP core by changing the
settings in the driver file.
TLP Header
1. In a terminal window, change to the <variant>_tb/<variant>_tb/altera_pcie_a10_tbed_140/sim/ directory.
2. Open altpcietb_bfm_driver_avmm.v in your text editor.
3. To enable target memory tests and specify the completer-only single dword variant, specify the
following parameters:
a. parameter RUN_TGT_MEM_TST = 1;
b. parameter RUN_DMA_MEM_TST = 0;
c. parameter AVALON_MM_LITE = 1;
4. Change to the <variant>_tb/<variant>_tb/sim/mentor directory.
5. Start the ModelSim simulator.
6. To run the simulation, type the following commands in a terminal window:
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
Altera Corporation
2-6
Generating Quartus II Synthesis Files
a. do msim_setup.tcl
b. ld_debug (The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.)
c. run 140000 ns
Generating Quartus II Synthesis Files
1. On the Generate menu, select Generate HDL.
2. For Create HDL design files for synthesis, select Verilog.
You can leave the default settings for all other items.
3. Click Generate to generate files for Quartus II synthesis.
4. Click Finish when the generation completes.
Creating a Quartus II Project
You can create a new Quartus II project with the New Project Wizard, which helps you specify the
working directory for the project, assign the project name, and designate the name of the top-level design
entity.
1. On the Quartus II File menu, click then New Project Wizard, then Next.
2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you
previously turned it off.)
3. On the Directory, Name, Top-Level Entity page, enter the following information:
UG-01145_avmm
2015.05.14
a. For What is the working directory for this project, browse to <project_dir>/ep_g2x4_avmm128/
synth.
b. For What is the name of this project, select ep_g2x4_avmm128.v from the <project_dir>/ep_g2x4_
avmm128/synth directory.
c. For Project Type select Empty project.
4. Click Next.
5. On the Add Files page, add <project_dir>/ep_g2x4_128avmm/ep_g2x4_avmm128.qip to your Quartus II
project.
6. Click Next to display the Family & Device Settings page.
7. On the Device page, choose the following target device family and options:
a. In the Family list, select Arria 10.
b. In the Devices list, select All.
c. In the Available devices list, select the appropriate device. For Arria 10 ES2 development kits, select
10AX115S1F45I3SGE2.
8. Click Next to close this page and display the EDA Tool Settings page.
9. From the Simulation list, select ModelSim. From the Format list, select the HDL language you intend
to use for simulation.
10.Click Next to display the Summary page.
11.Check the Summary page to ensure that you have entered all the information correctly.
Altera Corporation
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
UG-01145_avmm
2015.05.14
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
To compile successfully you must add a virtual pin assignment statement for the PIPE interface to
your .qsf file. The PIPE interface is useful for debugging, but is not a top-level interface of the IP core.
1. Browse to the synthesis directory that includes the .qsf for your project, <project_dir>/ep_g2x4_avmm128/
synth
2. Open ep_g2x4_avmm128.qsf.
3. Add the following assignment statement:
set_instance_assignment -name VIRTUAL_PIN ON -to pcie_a10_hip_0_hip_pipe_*
4. Save the .qsf file.
Compiling the Design
1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design
that you can successfully download to a PCB.
a. In the <project_dir>/ep_g2x4_avmm128/synth/, open ep_g2x4_avmm128.v.
b. Comment out the declaration for pcie_a10_hip_0_hip_ctrl_test_in.
c. Add a wire [31:0] pcie_a10_hip_0_hip_ctrl_test_in declaration to the same the same file.
d. Assign pcie_a10_hip_0_hip_ctrl_test_in = 0x000000A8.
e. Connect pcie_a10_hip_0_hip_ctrl_test_in to the test_in port on the Arria 10 Hard IP for
PCI Express instance.
2. On the Quartus II Processing menu, click Start Compilation.
3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
2-7
If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design
Space Explorer on the Tools menu.
Programming a Device
After you compile your design, you can program your targeted Altera device and verify your design in
hardware.
For more information about programming Altera FPGAs, refer to Quartus II Programmer.
Related Information
Quartus II Programmer
Understanding Channel Placement Guidelines
Arria 10 transceivers are organized in banks of six channels. The transceiver bank boundaries are
important for clocking resources, bonding channels, and fitting. Refer to the Channel Placement for the
Gen1 and Gen2 Data Rates and Channel Placment and fPLL and ATX PLL Usage for the Gen3 Data Rates
for illustrations of channel placement for x1, x2, x4, and x8 variants.
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Altera Corporation
Send Feedback
2-8
Understanding Channel Placement Guidelines
Related Information
• Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates on page 4-5
• Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate on page 4-7
UG-01145_avmm
2015.05.14
Altera Corporation
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Send Feedback
2015.05.14
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Parameter Settings
3
UG-01145_avmm
Subscribe
Send Feedback
Arria 10 Avalon-MM System Settings
Table 3-1: System Settings for PCI Express
Parameter Value Description
Number of Lanes x1, x2, x4, x8 Specifies the maximum number of lanes supported.
Lane Rate Gen1 (2.5 Gbps)
Gen2 (2.5/5.0 Gbps)
Gen3 (2.5/5.0/8.0
Gbps)
Port type Native Endpoint
Root Port
Legacy endpoint
Specifies the maximum data rate at which the link can operate.
Specifies the port type. Altera recommends Native Endpoint
for all new Endpoint designs. Select Legacy Endpoint only
when you require I/O transaction support for compatibility.
The Endpoint stores parameters in the Type 0 Configuration
Space. The Root Port stores parameters in the Type 1 Configu‐
ration Space.
Application
Interface Type
RX Buffer credit
allocation performance for
received requests
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Avalon-ST
Avalon-MM
Avalon-MM with
DMA
Avalon-ST with SR-
IOV
Minimum
Low
Balanced
Selects either the Avalon-ST interface, Avalon-MM interface,
Avalon-MM with DMA interface, or Avalon-ST with SR-IOV
interface.
Determines the allocation of posted header credits, posted
data credits, non-posted header credits, completion header
credits, and completion data credits in the 16 KByte RX buffer.
The 5 settings allow you to adjust the credit allocation to
ISO
9001:2008
Registered
3-2
Arria 10 Avalon-MM System Settings
Parameter Value Description
UG-01145_avmm
2015.05.14
High
Maximum100 MHz
optimize your system. The credit allocation for the selected
setting displays in the message pane.
Refer to the Throughput Optimization chapter for more
information about optimizing performance. The Flow Control
chapter explains how the RX credit allocation and the
Maximum payload RX Buffer credit allocation and the
Maximum payload size that you choose affect the allocation
of flow control credits. You can set the Maximum payload
size parameter on the Device tab.
The Message window dynamically updates the number of
credits for Posted, Non-Posted Headers and Data, and
Completion Headers and Data as you change this selection.
• Minimum—configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving
most of the RX Buffer space for received completion
header and data. Select this option for variations where
application logic generates many read requests and only
infrequently receives single requests from the PCIe link.
• Low—configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still
dedicates most of the space for received completion header
and data. Select this option for variations where application
logic generates many read requests and infrequently
receives small bursts of requests from the PCIe link. This
option is recommended for typical endpoint applications
where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer
logic.
• Balanced—configures approximately half the RX Buffer
space to received requests and the other half of the RX
Buffer space to received completions. Select this option for
variations where the received requests and received
completions are roughly equal.
Use 62.5 MHz
application clock
Enable byte
parity ports on
Avalon-ST
interface
Altera Corporation
On/Off This mode is only available only for Gen1 ×1.
On/Off When On, the RX and TX datapaths are parity protected.
Parity is odd.
This parameter is only available for the Avalon-ST Arria 10
Hard IP for PCI Express.
Parameter Settings
Send Feedback
UG-01145_avmm
2015.05.14
Arria 10 Avalon-MM System Settings
Parameter Value Description
3-3
Enable multiple
packets per cycle
for the 256-bit
interface
Enable configu‐
ration via PCI
Express (CvP)
Enable credit
consumed
selection port
Enable dynamic
reconfiguration
of PCIE readonly registers
On/Off When On, the 256-bit Avalon-ST interface supports the
transmission of TLPs starting at any 128-bit address
boundary, allowing support for multiple packets in a single
cycle. To support multiple packets per cycle, the Avalon-ST
interface includes 2 start of packet and end of packet signals
for the 256-bit Avalon-ST interfaces. This feature is only
supported for Gen3 x8.
On/Off When On, the Quartus II software places the Endpoint in the
location required for configuration via protocol (CvP). For
more information about CvP, click the Configuration via
Protocol (CvP) link below.
A single hard IP block in each device includes the CvP
functionality. Refer to thePhysical Layout of Hard IP in Arria
10 Devices for more information.
On/Off When you turn on this option, the core includes the tx_cons_
cred_sel port. This parameter does not apply to the Avalon-
MM interface.
On/Off When On, you can use the Hard IP reconfiguration bus to
dynamically reconfigure Hard IP read-only registers. For more
information refer to Hard IP Reconfiguration Interface.
Enable Altera
Debug Master
On/Off When On, you can use the Altera System Console to read and
write the embedded Arria 10 Native PHY registers.
Endpoint
(ADME)
Related Information
• Physical Layout of Hard IP In Arria 10 Devices on page 4-1
• PCI Express Base Specification 3.0
• Arria 10 Transceiver PHY User Guide
Provides information about the ADME feature for Arria 10 devices.
Parameter Settings
Send Feedback
Altera Corporation
3-4
Interface System Settings
Interface System Settings
Table 3-2: Interface System Settings
Parameter Value Description
UG-01145_avmm
2015.05.14
Application Interface
width
Avalon-MM address
width
Enable completer-only
Endpoint
64-bit
128-bit
256-bit
32, 64
On/Off
Specifies the data width for the Application Layer to
Transaction Layer interface. Refer to Application Layer
Clock Frequency for All Combinations of Link Width,
Data Rate and Application Layer Interface Widths for all
legal combinations of data width, number of lanes,
Application Layer clock frequency, and data rate. The
Avalon-MM with DMA interface does not support the
64-bit interface width.
Specifies the address width for Avalon-MM RX master
ports that access Avalon-MM slaves in the Avalon
address domain. When you select 32-bit addresses, the
PCI Express Avalon-MM bridge performs address
translation. When you specify 64-bits addresses, no
address translation is performed in either direction. The
destination address specified is forwarded to the
Avalon-MM interface without any changes.
For the Avalon-MM interface with DMA, this value
must be set to 64.
In this mode, the Hard IP can receive requests, but
cannot initiate upstream requests. However, it can
transmit completion packets on the PCI Express TX
link. This mode removes the Avalon-MM TX slave port
and thereby reduces logic utilization.
Enable completer-only
Endpoint with 4-byte
payload
Altera Corporation
On/Off
This is a non-pipelined version of Completer Only
mode. At any time, only a single request can be
outstanding. Single dword completer uses fewer
resources than completer only Endpoint. This variant
is targeted for systems that require simple read and
write register accesses from a host CPU. If you select
this option, the width of the data for RXM BAR masters
is always 32 bits, regardless of the Avalon-MM width.
For the Avalon-MM interface with DMA, this value
must be Off .
Parameter Settings
Send Feedback
Loading...