Altera AMBA AXI4-Stream User Manual

Mentor Verification IP Altera Edition

AMBA AXI4-Stream User Guide

Software Version 10.3

April 2014

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information.

This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws.

TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a thirdparty Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’ trademarks may be viewed at: www.mentor.com/trademarks.

The registered trademark Linux

is used pursuant to a sublicense from LMI, the exclusive licensee of

Linus Torvalds, owner of the mark on a world-wide basis.

Mentor Graphics Corporation

8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777

Telephone: 503.685.7000

Toll-Free Telephone: 800.592.2210

Website: www.mentor.com

SupportNet: supportnet.mentor.com/

Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AMBA AXI4-Stream Protocol Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Mentor VIP AE License Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Supported Simulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Simulator GCC Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 1

Mentor VIP Altera Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Advantages of Using BFMs and Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Implementation of BFMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

What Is a Transaction? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

AXI4-Stream Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Master BFM and Slave BFM Roles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 2

SystemVerilog API Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Creating Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Transaction Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

create_*_transaction(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Executing Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

execute_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Waiting Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

get_packet(), get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Access Transaction Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

set*() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

get*(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Operational Transaction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Handshake Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Transfer Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Transaction Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Chapter 3

SystemVerilog Master BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Master BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Master Timing and Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Master BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Master Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SystemVerilog Master API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

create_master_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

execute_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

execute_transfer() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

get_stream_ready() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Chapter 4

SystemVerilog Slave BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Slave BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Slave Timing and Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Slave BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Slave Assertions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SystemVerilog Slave API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

create_slave_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

execute_stream_ready() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Chapter 5

SystemVerilog Monitor BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Inline Monitor Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Monitor BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Monitor Timing and Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Monitor BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Monitor Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

SystemVerilog Monitor API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

create_monitor_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

get_packet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

get_stream_ready() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 6

SystemVerilog Tutorials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Verifying a Slave DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Master BFM Test Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Verifying a Master DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Slave BFM Test Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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Chapter 7

VHDL API Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Creating Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Transaction Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

create*_transaction(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Executing Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

execute_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Waiting Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

get_packet(), get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Access Transaction Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

set*() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

get*(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Operational Transaction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Handshake Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Transfer Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Transaction Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Chapter 8

VHDL Master BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Overloaded Procedure Common Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Master BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Master Timing and Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Master BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Master Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

VHDL Master BFM API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

create_master_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

set_data(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

get_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

set_byte_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

get_byte_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

set_id() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

get_id() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

set_dest(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

get_dest() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

set_user_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

get_user_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

set_valid_delay(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

get_valid_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

set_ready_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

get_ready_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

set_operation_mode() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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get_operation_mode(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

set_transfer_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

get_transfer_done(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

set_transaction_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

get_transaction_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

execute_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

execute_transfer() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

get_stream_ready() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

print() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

destruct_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Chapter 9

VHDL Slave BFM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Slave BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Slave Timing and Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Slave BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Slave Assertions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

VHDL Slave BFM API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

create_slave_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

set_data(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

get_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

set_byte_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

get_byte_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

set_id() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

get_id() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

set_dest(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

get_dest() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

set_user_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

get_user_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

set_valid_delay(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

get_valid_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

set_ready_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

get_ready_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

set_operation_mode() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

get_operation_mode(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

set_transfer_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

get_transfer_done(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

set_transaction_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

get_transaction_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

get_packet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

execute_stream_ready() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

print() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

destruct_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

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Chapter 10

VHDL Monitor BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Inline Monitor Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Monitor BFM Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Monitor Timing and Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Monitor BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Monitor Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

VHDL Monitor BFM API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

set_config() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

get_config(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

create_monitor_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

get_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

get_byte_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

get_id() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

get_dest() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

get_user_data() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

get_valid_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

get_ready_delay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

get_operation_mode(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

get_transfer_done(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

get_transaction_done() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

get_packet() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

get_transfer(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

print() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

destruct_transaction() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

wait_on(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Chapter 11

VHDL Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Verifying a Slave DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Master BFM Test Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Verifying a Master DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Slave BFM Test Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Chapter 12

Getting Started with Qsys and the BFMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Setting Up a Simulation from a UNIX Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Setting Up Simulation from the Windows GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Running the Qsys Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Running a Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Chapter 13

Assertions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Appendix A

SystemVerilog Master and Slave Test Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

SystemVerilog Master Test Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

SystemVerilog Slave Test Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

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Appendix B

VHDL Master and Slave Test Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

VHDL Master BFM Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

VHDL Slave BFM Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Third-party Software for Mentor Verification IP Altera Edition

End-User License Agreement

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List of Examples

Example 2-1. BFM Test Program Set Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Example 2-2. BFM Test Program Get Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Example 2-3. Transaction Record Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Example 2-4. Master BFM Test Program Transaction Creation . . . . . . . . . . . . . . . . . . . . . . 26

Example 2-5. Slave BFM Test Program Transaction Creation . . . . . . . . . . . . . . . . . . . . . . . 26

Example 2-6. Master Test Program Transaction Execution . . . . . . . . . . . . . . . . . . . . . . . . . 26

Example 2-7. Test Program Wait for Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Example 2-8. Slave Test Program get_transfer() Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Example 2-9. Master Test Program set_byte_type() Task. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Example 2-10. Slave Test Program get_byte_type() Task . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Example 2-11. Master Test Program operation_mode() Task. . . . . . . . . . . . . . . . . . . . . . . . 29

Example 2-12. Slave Test Program ready_delay() Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Example 3-1. Master BFM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Example 3-2. Master BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Example 3-3. Master BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . . . 34

Example 4-1. Slave BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Example 4-2. Slave BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Example 4-3. Slave BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . . . . 46

Example 5-1. Monitor BFM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Example 5-2. Monitor BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Example 5-3. Monitor BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . . 59

Example 6-1. Definition and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Example 6-2. Master Transaction Creation and Execution . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Example 6-3. Master Transfer Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Example 6-4. m_insert_wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Example 6-5. ready_delay(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Example 6-6. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Example 6-7. Transfer Receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Example 7-1. BFM Test Program Set Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Example 7-2. BFM Test Program Get Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Example 7-3. Transaction Record Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Example 7-4. Master BFM Test Program Transaction Creation . . . . . . . . . . . . . . . . . . . . . . 81

Example 7-5. Slave BFM Test Program Transaction Creation . . . . . . . . . . . . . . . . . . . . . . . 81

Example 7-6. Master Test Program Transaction Execution . . . . . . . . . . . . . . . . . . . . . . . . . 81

Example 7-7. Test Program Wait for Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Example 7-8. Slave Test Program get_packet() Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Example 7-9. Master Test Program set_byte_type() Procedure . . . . . . . . . . . . . . . . . . . . . . 83

Example 7-10. Slave Test Program get_byte_type() Procedure . . . . . . . . . . . . . . . . . . . . . . 83

Example 7-11. Master Test Program set_operation_mode() Procedure . . . . . . . . . . . . . . . . 84

Example 7-12. Slave Test Program ready_delay() Procedure . . . . . . . . . . . . . . . . . . . . . . . . 85

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List of Examples

Example 8-1. Master BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Example 8-2. Master BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . . . 90

Example 9-1. Slave BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Example 9-2. Slave BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . . . . 126

Example 10-1. Monitor BFM Disable All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Example 10-2. Monitor BFM Individual Assertion Enable/Disable . . . . . . . . . . . . . . . . . . . 160

Example 11-1. Definition and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Example 11-2. Master Transaction Creation and Execution . . . . . . . . . . . . . . . . . . . . . . . . . 183

Example 11-3. Master Transfer Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Example 11-4. m_insert_wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Example 11-5. ready_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Example 11-6. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Example 11-7. Transfer Receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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List of Figures

Figure 1-1. Master BFM Test Program Role. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 1-2. Slave BFM Test Program Role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 2-1. SystemVerilog BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 6-1. Slave DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 6-2. Master DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 7-1. VHDL BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 10-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 11-1. Slave DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 11-2. Master DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . 185

Figure 12-1. Copy qsys-examples from the Installation Folder. . . . . . . . . . . . . . . . . . . . . . . 191

Figure 12-2. Paste qsys-examples from Installation to Work Folder . . . . . . . . . . . . . . . . . . 192

Figure 12-3. Select Qsys from the Quartus II Software Top-Level Menu . . . . . . . . . . . . . . 193

Figure 12-4. Open the ex1_back_to_back_sv.qsys Example. . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 12-5. Quartus II Software Displays the Connectivity of the Example. . . . . . . . . . . . 194

Figure 12-6. Qsys Generation Window Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 12-7. Select the Work Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

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List of Tables

Table 1. Simulator GCC Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2-1. Transaction Record Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 3-1. Master BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 3-2. Master BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 4-1. Slave BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 4-2. Slave BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 5-1. Monitor BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 5-2. Monitor BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 7-1. Transaction Record Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 8-1. Master BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 8-2. Master BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 9-1. Slave BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 9-2. Slave BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 10-1. Monitor BFM Signal Width Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 10-2. Monitor BFM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 12-1. SystemVerilog README Files and Script Names for all Simulators . . . . . . . 196

Table 13-1. AXI4-Stream Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

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Preface

Note

About This User Guide

This user guide describes the application interface (API) of the Mentor® Verification IP (VIP)

Altera Specification, Version 1.0, Issue A (ARM IHI 0051A).

AMBA AXI4-Stream Protocol Specification

The Mentor VIP AE conforms to the AMBA 4 AXI4-Stream Protocol Specification, Version 1.0, Issue A (ARM IHI 0051A). This user guide refers to this specification as the “AMBA AXI4-Stream Protocol Specification.”

Mentor VIP AE License Requirements

Edition (AE) and how it conforms to the AMBA® 4 AXI4-Stream Protocol

A license is required to access the Mentor Graphics VIP AE bus functional models and inline monitor.

• To access the Mentor Graphics VIP AE and upgrade to the Quartus II Subscription

Edition software, Version 14.0, from a previous version, you must regenerate your license file.

• To access the Mentor VIP AE with the Quartus II Web Edition software, you must

upgrade to Version 14.0 and purchase a Mentor VIP AE seat license by contacting your Altera sales representative.

You can generate and manage license files for Altera software and IP products by visiting the Self-Service Licensing Center of the Altera website.

Supported Simulators

Mentor VIP AE supports the following simulators:

• Mentor Graphics Modelsim 10.1e (including Altera Editions) and Questa Sim 10.2c

• Synopsys

VCS® and VCS-MX 2013.06

• Cadence

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Incisive® Enterprise Simulator (IES) 13.10.001

Preface

Simulator GCC Requirements

Mentor VIP requires that the installation directory of the simulator includes the GCC libraries shown in Table 1. If the installation of the GCC libraries was an optional part of the simulator’s installation and the Mentor VIP does not find these libraries, an error message similar to the following appears:

ModelSim / Questa SIM # ** Error: (vsim-8388) Could not find the MVC shared library : GCC not found in installation directory (/home/user/altera2/14.0/modelsim_ase) for platform "linux". Please install GCC version "gcc-4.5.0-linux"

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Simulator GCC Requirements

Table 1. Simulator GCC Requirements

Simulator Version GCC Version(s) Search Path

Mentor Questa SIM

10.2c 4.5.0 (Linux 32 bit) <install dir>/gcc-4.5.0-linux

4.5.0 (Linux 64 bit) <install dir>/gcc-4.5.0-linux_x86_64

4.2.1 (Windows 32 bit) <install dir>/gcc-4.2.1-mingw32vc9

Mentor ModelSim

10.1e 4.5.0 (Linux 32 bit) <install dir>/gcc-4.5.0-linux

4.5.0 (Linux 64 bit) <install dir>/gcc-4.5.0-linux_x86_64

4.2.1 (Windows 32 bit) <install dir>/gcc-4.2.1-mingw32vc9

Synopsys VCS/VCS-MX

2013.06 4.5.2 (Linux 32 bit) $VCS_HOME/gnu/linux/4.5.2_32-shared

$VCS_HOME/gnu/4.5.2_32-shared

Preface

4.5.2 (Linux 64 bit) $VCS_HOME/gnu/linux/4.5.2_64-shared

$VCS_HOME/gnu/4.5.2_64-shared

Note: If you set the environment variable VG_GNU_PACKAGE, then it is used instead of the VCS_HOME environment variable.

Cadence Incisive

13.10.001 4.4 (Linux 32/64 bit) <install dir>/tools/cdsgcc/gcc/4.4

Note: Use the cds_tools.sh executable to find the Incisive installation. Ensure $PATH includes the installation path and <install dir>/tools/cdsgcc/gcc/4.4/install/bin. Also, ensure the LD_LIBRARY_PATH includes <install dir>/tools/cdsgcc/gcc/4.4/install/lib.

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Simulator GCC Requirements

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Chapter 1

Mentor VIP Altera Edition

The Mentor VIP AE provides bus functional models (BFMs) to simulate the behavior and to facilitate the verification of the IP. The Mentor VIP AE includes the following interfaces:

• AXI3 with master, slave, and inline monitor BFMs

• AXI4 with master, slave, and inline monitor BFMs

• AXI4-Lite with master, slave, and inline monitor BFMs

• AXI4-Stream with master, slave, and inline monitor BFMs

This user guide covers the AXI4-Stream BFMs only. Refer to the Mentor Verification IP Altera

Edition AXI3/AXI4 User Guide for details of the AXI3 and AXI4 BFMs, and the Mentor Verification IP Altera Edition AXI4-Lite User Guide for details of the AXI4-Lite BFMs.

Advantages of Using BFMs and Monitors

Using the Mentor VIP AE has the following advantages:

• Accelerates the verification process by providing key verification test bench

components

• Provides BFM components that implement the AMBA 4 AXI4-Stream Protocol

Specification, which serves as a reference for the protocol

• Provides a full suite of configurable assertion checking within each BFM

Implementation of BFMs

The Mentor VIP AE BFMs, master, slave, and inline monitor components are implemented in SystemVerilog. Also included are wrapper components so that you can use the BFMs in VHDL verification environments with simulators that support mixed-language simulation.

The Mentor VIP AE provides a set of APIs for each BFM that you can use to construct, instantiate, control, and query signals in all BFM components. Your test programs must use only these public access methods and events to communicate with each BFM. To ensure support in current and future releases, your test programs must use the standard set of APIs to interface with the BFMs. Nonstandard APIs and user-generated interfaces may not be supported in future releases.

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What Is a Transaction?

The test program drives the stimulus to the DUT and determines whether the behavior of the DUT is correct by analyzing the responses. The BFMs translate the test program stimuli (transactions), creating the signaling for the AMBA 4 AXI4-Stream Protocol Specification. The BFMs also check for protocol compliance by firing an assertion when a protocol error is observed.

What Is a Transaction?

A transaction for Mentor VIP AE represents an instance of information that is transferred between a master and a slave peripheral, and that it adheres to the protocol used to transfer the information. For example, a master transaction can communicate a data stream packet consisting of a number of transfers to a slave DUT. A subsequent data stream packet requires a new and unique transaction.

Each transaction has a dynamic Transaction Record that exists for the life of the transaction. The life of a transaction record starts when it is created, and ends when the transaction completes. The transaction record is automatically discarded when the transaction ends.

When created, a transaction contains transaction fields that you set to define two transaction aspects:

• Protocol fields are transferred over the protocol signals

• Operation fields determine how the information is transferred, and when the transaction

is complete

For example, a master transaction record holds a byte definition in the byte_type protocol field, the value of this field is transferred over the TKEEP and TSTRB protocol signals. A master transaction also has a transaction_done operation field that indicates when the transaction is complete; this operation field is not transferred over the protocol signals. These two types of transaction fields, protocol and operation, establish a dynamic record during the life of the transaction.

In addition to transaction fields, you specify arguments to tasks, functions, and procedures that permit you to create, set, and get the dynamic transaction record during the lifetime of a transaction. Each BFM has an API that controls how you access the transaction record. How you access the record also depends on the source code language, whether it is VHDL or SystemVerilog. Methods for accessing transactions based on the language you use are explained in detail in the relevant chapters of this user guide.

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Note

execute_transaction(t) – Master

execute_transfer() – Master

Master BFM

Test program

Slave DUT

Transfer Transfer TransferTransfer

AXI4-Stream Transactions

A complete transaction communicates information between a master and a slave. Transaction fields, described in the previous section, What Is a Transaction?, determine what is transferred and how information is transferred. During the lifetime of a transaction, the roles of the master and slave ensure that a transaction completes successfully, and that transferred information adheres to the protocol specification. Information flows from the master to the slave during a transaction, with the master initiating the transaction.

The AXI4-Stream protocol has a single channel to transfer protocol information. It has a pair of handshake signals, TVALID and TREADY, that indicate valid information on the channel, and the acceptance of the information from the channel.

Master BFM and Slave BFM Roles

The following description of a master transaction references SystemVerilog BFM API tasks. There are equivalent VHDL BFM API procedures that perform the same functionality.

For a master transaction, the master calls the create_master_transaction() task to define the information to be transferred, and then calls the execute_transaction() task to initiate the communication of information, as shown in Figure 1-1.

The execute_transaction() task results in the master calling the execute_transfer() task a multiple number of times, equal to the number of transfers in the transaction.

Figure 1-1. Master BFM Test Program Role

The slave also creates a transaction by calling the create_slave_transaction() task to accept the transfer of information from the master. The transfer is received by the slave calling the

get_transfer() task, as shown in Figure 1-2.

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execute_stream_ready() – Slave

Master

DUT

Slave BFM

Test

Program

Transfer Transfer TransferTransfer

get_transfer() – Slave

AXI4-Stream Transactions

Figure 1-2. Slave BFM Test Program Role

The slave can cause back-pressure to the master using the execute_stream_ready() task to set the TREADY protocol signal to “0” to inhibit subsequent “transfers” from the master.

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Chapter 2

Test Program SystemVerilog

Notes: 1. Refer to create_*_transaction()

2. Refer to execute_transaction()

3. Refer to set*()

SystemVerilog BFM API

Configuration Creating Transaction

Waiting Events

Executing Transaction

Access Transaction

create_*_transaction

set_config/get_config

get_packet/get_transfer wait_on

Rx_Transaction

queue

Tx_Transaction

Configuration

Wire level

get*/set*

execute_transaction/execute_transfer

SystemVerilog interface

SystemVerilog API Overview

This section provides the functional description of the SystemVerilog (SV) API for all the BFM (master, slave, and monitor) components. For each BFM, you can configure the protocol transaction fields that are executed on the protocol signals, as well as control the operational transaction fields that set delay and timeout values.

In addition, each BFM API has tasks that wait for certain events to occur on the system clock and reset signals, and tasks to get and set information about a particular transaction.

Figure 2-1. SystemVerilog BFM Internal Structure

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SystemVerilog API Overview

Configuration

Configuration sets timeout delays, error reporting, and other attributes of the BFM.

Each BFM has a set_config() function that sets the configuration of the BFM. Refer to the individual BFM APIs for details.

Each BFM also has a get_config() function that returns the configuration of the BFM. Refer to the individual BFM APIs for details.

set_config()

Example 2-1 shows how to set the burst timeout factor to 1000 for a transaction in the master

BFM test program.

Example 2-1. BFM Test Program Set Configuration

// Setting the burst timeout factor to 1000 master_bfm.set_config(AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR, 1000);

get_config()

Example 2-2 shows how to get the signal hold time in the master BFM test program.

Example 2-2. BFM Test Program Get Configuration

// Getting hold time value

hold_time = master_bfm.get_config(AXI4STREAM_CONFIG_HOLD_TIME);

Creating Transactions

To transfer information between a master BFM and slave DUT over the protocol signals, you must create a transaction in the master test program. Similarly, to transfer information between a master DUT and a slave BFM, you must create a transaction in the slave test program. To monitor the transfer of information using a monitor BFM, you must create a transaction in the monitor test program.

When you create a transaction, a Transaction Record is created and exists for the life of the transaction. This transaction record can be accessed by the BFM test programs during the life of the transaction as it transfers information between the master and slave.

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SystemVerilog API Overview

Note

Creating Transactions

Transaction Record

The transaction record contains two types of transaction fields, protocol and operational, that either transfer information over the protocol signals, or define how and when a transfer occurs, respectively.

Protocol fields contain transaction information that is transferred over the protocol signals. For example, the id field is transferred over the TID protocol signals during a transaction to identify a data stream.

Operational fields define how and when the transaction is transferred. Their content is not transferred over protocol signals. For example, the operation_mode field controls the blocking/nonblocking operation of a transaction, but this information is not transferred over the protocol signals.

Transaction Definition

The transaction record exists as a SystemVerilog class definition in each BFM. Example 2-3 shows the definition of the axi4stream_transaction class members that form the transaction record.

Example 2-3. Transaction Record Definition

// Global Transaction Class class axi4stream_transaction; // Protocol byte unsigned data[]; axi4stream_byte_type_e byte_type[]; bit [((`MAX_AXI4_ID_WIDTH) - 1):0] id; bit [((`MAX_AXI4_DEST_WIDTH) - 1):0] dest; bit [((`MAX_AXI4_USER_WIDTH) - 1):0] user_data []; int valid_delay[]; int ready_delay[];

// Housekeeping axi4stream_operation_mode_e

operation_mode = AXI4STREAM_TRANSACTION_BLOCKING; bit transfer_done[]; bit transaction_done;

...

endclass

The axi4stream_transaction class code above is shown for information only. Access to each transaction record during its life is performed by various set*() and get*() tasks described later in this chapter.

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Creating Transactions

The contents of the transaction record is detailed in Table 2-1.

Table 2-1. Transaction Record Fields

Transaction Field Description

Protocol Transaction Fields

data An unsized array of bytes to hold the data of an AXI4-Stream

packet. The field content is transferred over the TDATA protocol signals during a transaction.

byte_type An unsized array to hold the enumerated type of each data byte

within an AXI4-Stream packet. The field content is transferred over the TSTRB and TKEEP protocol signals during a transaction. The following are types of byte:

AXI4STREAM_DATA_BYTE AXI4STREAM_NULL_BYTE AXI4STREAM_POS_BYTE AXI4STREAM_ILLEGAL_BYTE

id A bit vector (of length equal to the TID protocol signal bus

width) to hold the data stream identifier of the data packet. The field content is transferred over the TID protocol signals during a transaction.

dest A bit vector (of length equal to the TDEST protocol signal bus

width) to hold the routing information for the data stream packet. The field content is transferred over the TDEST protocol signals during a transaction.

user_data An unsized bit vector (of length equal to the TUSER protocol

signal bus width) to hold the user-defined sideband information. The field content is transferred over the TUSER protocol signals during a transaction.

Operational Transaction Fields

valid_delay An unsized array of integers to hold the delay value of the

TVALID protocol signal (measured in ACLK cycles) for each transfer within a packet. The field content is not transferred over the protocol signals during a transaction.

ready_delay An unsized array of integers to hold the delay value of the

TREADY protocol signal (measured in ACLK cycles) for each transfer within a packet. The field content is not transferred over the protocol signals during a transaction.

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Note

Creating Transactions

Table 2-1. Transaction Record Fields (cont.)

Transaction Field Description

operation_mode An enumeration to hold the operation mode of the transaction.

The following are two types of operation mode:

AXI4STREAM_TRANSACTION_NON_BLOCKING AXI4STREAM_TRANSACTION_BLOCKING

The field content is not transferred over the AXI4-Stream protocol signals during a transaction.

transfer_done An unsized bit array to hold the done flag for each transfer within

a packet. The field content is not transferred over the protocol signals during a transaction.

transaction_done A bit to hold the done flag for a complete transaction. The field

content is not transferred over the protocol signals during a transaction.

The SystemVerilog Master BFM API allows you to create a master transaction by providing only an optional burst_length argument to indicate the number of transfers within a packet. All other protocol transaction fields automatically default to legal protocol values to create a master transaction record. Refer to create_master_transaction() for default protocol transaction field values.

The SystemVerilog Slave BFM API allows you to create a slave transaction with no arguments. All protocol transaction fields automatically default to legal protocol values to create a slave transaction record. Refer to create_slave_transaction() for default protocol transaction field values.

The SystemVerilog Monitor BFM API allows you to create a monitor transaction with no arguments. All protocol transaction fields automatically default to legal protocol values to create a complete monitor transaction record. Refer to create_monitor_transaction() for default protocol transaction field values.

If you change the default value of a protocol transaction field, it is valid for all future transactions until you set a new value.

create_*_transaction()

The create_master_transaction(), create_slave_transaction() and create_monitor_transaction() BFM API functions create a master, a slave, and a monitor transaction, respectively.

Example 2-4 shows a master BFM test program creating a master transaction with a packet

length of 10 transfers.

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Executing Transactions

Example 2-4. Master BFM Test Program Transaction Creation

// Define a variable trans of type axi4stream_transaction to hold // master transaction record axi4stream_transaction trans;

...

// Create master transaction with 10 transfers trans = bfm.create_master_transaction(10);

Example 2-5 shows a slave BFM test program creating a slave transaction.

Example 2-5. Slave BFM Test Program Transaction Creation

// Define a variable trans of type axi4stream_transaction to hold // slave transaction record axi4stream_transaction trans;

...

// Create a slave transaction trans = bfm.create_slave_transaction();

Executing Transactions

Executing a transaction in a master/slave BFM test program initiates the transaction onto the protocol signals. Each master/slave BFM API has execution tasks that push transactions into the BFM internal transaction queues. Figure 2-1 on page 21 illustrates the internal BFM structure.

execute_transaction()

If the DUT is a slave, then the execute_transaction() task is called in the master BFM test program. Example 2-6 shows a master test program executing a master transaction.

Example 2-6. Master Test Program Transaction Execution

// Define a variable trans of type axi4stream_transaction to hold the // master transaction record. axi4stream_transaction trans;

...

// Create a master transaction with 10 transfers. trans = bfm.create_master_transaction(10);

...

// By default the execution of a transaction will block. bfm.execute_transaction(trans);

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Note

Waiting Events

Each BFM API has tasks that block the test program code execution until an event has occurred.

The wait_on() task blocks the test program execution until an ACLK or ARESETn signal event has occurred before proceeding.

The get_packet(), get_transfer() tasks block the test program code execution until a complete stream packet, or transfer, has occurred.

wait_on()

Example 2-7 shows a BFM test program waiting for the positive edge of the ARESETn signal.

Example 2-7. Test Program Wait for Event

// Block test program execution until the positive edge of the // ARESETn signal. bfm.wait_on(AXI4STREAM_RESET_POSEDGE);

get_packet(), get_transfer()

Example 2-8 shows a slave BFM test program using the get_transfer() task to block until it has

received a data stream transfer.

Example 2-8. Slave Test Program get_transfer() Task

// Create a slave transaction. trans = bfm.create_slave_transaction();

...

// Wait for a data stream transfer to occur. bfm.get_transfer(trans, 0, last);

Access Transaction Record

Each BFM API has tasks that can access a complete or partially complete Transaction Record. The set*() and get*() tasks are used in a test program to set and get information from the transaction record.

The set*() and get*() tasks are not explicitly detailed within each BFM API chapter. The simple rule for the task name is set_ or get_ followed by the name of the transaction field to be accessed. Refer to “Transaction Record Fields” on page 24 for transaction field name details.

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Operational Transaction Fields

set*()

Example 2-9 shows the master test program calling the set_byte_type() task to set the first data

byte_type in the transaction.

Example 2-9. Master Test Program set_byte_type() Task

trans.set_byte_type(AXI4STREAM_DATA_BYTE, 0);

get*()

Example 2-10 shows the slave test program calling the get_byte_type() task to get the first data

byte_type in the transaction.

Example 2-10. Slave Test Program get_byte_type() Task

// Define a variable of type axi4stream_byte_type_e to hold the byte // type of the data stream byte. axi4stream_byte_type_e slave_byte_type;

...

// Create a slave transaction. trans = bfm.create_slave_transaction();

...

// Wait for a data stream transfer to occur. bfm.get_transfer(trans, 0, last);

...

// Get the byte_type for the first data byte of the data stream transfer slave_byte_type = trans.get_byte_type(0);

Operational Transaction Fields

Operational transaction fields control the way in which a transaction is executed onto the protocol signals. These fields also indicate when an individual data transfer or transaction is complete.

Operation Mode

By default, each transaction performs a blocking operation, which prevents a following transaction from starting until the current active transaction completes.

You can configure this behavior to be nonblocking by setting the operation_mode transaction field to the enumerate type value AXI4STREAM_TRANSACTION_NON_BLOCKING instead of the default AXI4STREAM_TRANSACTION_BLOCKING.

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Operational Transaction Fields

Example 2-11 shows a master BFM test program creating a transaction by calling the create_master_transaction() task. Before executing the transaction, the operation_mode task is

changed to nonblocking.

Example 2-11. Master Test Program operation_mode() Task

// Define a variable trans of type axi4stream_transaction to hold the // master transaction record. axi4stream_transaction trans;

// Create a master transaction to create a transaction record trans = bfm.create_master_transaction(1);

// Change the operation_mode to be nonblocking in the transaction record trans.operation_mode(AXI4STREAM_TRANSACTION_NON_BLOCKING);

Handshake Delay

You can configure the TVALID and TREADY handshake signals to insert a delay before their assertion.

TVALID Signal Delay Transaction Field

The Transaction Record contains a valid_delay transaction field to configure the delay of the TVALID signal. The setting of the valid_delay transaction field is performed in the master BFM test program by calling the set_valid_delay() task.

TREADY Signal Delay Transaction Field

The Transaction Record contains a ready_delay transaction field to configure the delay of the TREADY signal. The setting of the ready_delay transaction field is performed in the slave BFM test program by calling the local ready_delay() task.

Example 2-12 shows the slave BFM test program implementing a ready_delay() task that

inserts a specified delay before the assertion of the TREADY signal.

Example 2-12. Slave Test Program ready_delay() Task

// Task : ready_delay // This is used to set ready delay to extend the transfer task ready_delay();

// Making TREADY '0'. This will consume one cycle. bfm.execute_stream_ready(0); // Two clock cycle wait. In total 3 clock wait. repeat(2) bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE); // Making TREADY '1'. bfm.execute_stream_ready(1);

endtask

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SystemVerilog API Overview

Operational Transaction Fields

Transfer Done

A transfer_done transaction field is set to 1 to indicate when each protocol “transfer” completes.

Transaction Done

A transaction_done transaction field is set to 1 to indicate when each protocol “transaction” completes.

In a slave BFM test program, you call the get_transfer() task to investigate whether a transaction is complete. If complete, the task returns the last argument of the task set to 1, and the transaction record will have the transaction_done field set to 1.

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Chapter 3

SystemVerilog Master BFM

This section provides information about the SystemVerilog master BFM. It has an API that contains tasks and functions to configure the BFM and to access the dynamic Transaction

Record during the life of the transaction.

Master BFM Protocol Support

The master BFM supports the full AMBA AXI4-Stream protocol.

Master Timing and Events

For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI4-Stream Protocol Specification chapter, which you can use to reference details of the following master BFM API timing and events.

The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period with signal events sampled and driven at rising ACLK edges. Therefore, the master BFM does not contain any timescale, timeunit, or timeprecision declarations. The signal setup and hold times are specified in units of simulator time-steps.

The simulator time-step resolves to the smallest of all the time-precision declarations in the test bench and design IP as a result of these directives, declarations, options, or initialization files:

• ` timescale directives in design elements

• Timeprecision declarations in design elements

• Compiler command-line options

• Simulation command-line options

• Local, or site-wide, simulator initialization files

If there is no timescale directive, the default time unit and time precision are tool specific. The recommended practice is to use timeunit and timeprecision declarations. For details, refer to Section 3.14, “System Time Units and Precision,” of the IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800™-2012 , February 21, 2013. This user guide refers to this document as the IEEE Standard for

SystemVerilog.

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SystemVerilog Master BFM

Note

Master BFM Configuration

A master BFM supports the full range of signals defined for the AMBA AXI4-Stream Protocol Specification. It has parameters that you use to configure the widths of the data and ID signals, and transaction fields to configure timeout factors, setup and hold times, and so on.

You can change the data and ID signals widths from their default settings by assigning them new values, usually in the top-level module of the test bench. These new values are then passed into the master BFM using a parameter port list of the master BFM module. Example 3-1 shows the master BFM with the data and ID signal widths defined in module top() and passed in to the master BFM mgc_axi4stream_master parameter port list.

Example 3-1. Master BFM Configuration

module top ();

parameter AXI4STREAM_ID_WIDTH = 18; parameter AXI4STREAM_USER_WIDTH = 4; parameter AXI4STREAM_DEST_WIDTH = 4; parameter AXI4STREAM_DATA_WIDTH = 32;

mgc_axi4stream_master #(AXI4STREAM_ID_WIDTH, AXI4STREAM_USER_WIDTH,

AXI4STREAM_DEST_WIDTH, AXI4STREAM_DATA_WIDTH) bfm_master(....);

In the above code extract, the mgc_axi4stream_master is the master BFM interface.

Table 3-1 lists the parameter names for the data and ID signals, and their default values.

Table 3-1. Master BFM Signal Width Parameters

Signal Width Parameter Description

AXI4_ID_WIDTH ID signal width in bits. This applies to the TID signal.

Refer to the AMBA AXI4-Stream Protocol Specification for more details. Default: 18.

AXI4_USER_WIDTH User data signal width in bits. This applies to the TUSER

signal. Refer to the AMBA AXI4-Stream Protocol Specification for more details. Default: 8.

AXI4_DEST_WIDTH Destination routing signal width in bits. This applies to

the TDEST signal. Refer to the AMBA AXI4-Stream Protocol Specification for more details. Default: 18.

AXI4_DATA_WIDTH Data signal width in bits. This applies to the TDATA

signal. Refer to the AMBA AXI4-Stream Protocol Specification for more details. Default: 1024.

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SystemVerilog Master BFM

Master BFM Configuration

A master BFM has configuration fields that you set by calling the set_config() function to configure timeout factors, setup and hold times, and so on. You get the value of a configuration field using the get_config() function. Table 3-2 describes the full list of configuration fields.

Table 3-2. Master BFM Configuration

Configuration Field Description

Timing Variables

AXI4STREAM_CONFIG_SETUP_TIME The setup-time prior to the active

edge of ACLK, in units of simulator time-steps for all signals.1 Default: 0.

AXI4STREAM_CONFIG_HOLD_TIME The hold-time after the active

edge of ACLK, in units of simulator time-steps for all

signals.

Default: 0.

AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay permitted

between the individual transfer transactions in clock cycles. Default: 10000.

AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_ ASSERTION_TO_TREADY

The maximum delay permitted between the assertion of TVALID to the assertion of TREADY. Default: 10000.

Master Attributes

AXI4STREAM_LAST_DURING_IDLE Controls the value of TLAST

during idle. 0 = TLAST driven to 0 during idle (default) 1 = TLAST driven to 1 during idle

Error Detection

AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all

assertion checks in the BFM. 0 = disabled

1 = enabled (default)

AXI4STREAM_CONFIG_ENABLE_ASSERTION Individual enable/disable of an

assertion check in the BFM. Refer to the Master Assertions chapter for details 0 = disabled 1 = enabled (default)

Refer to Master Timing and Events for details of simulator time-steps.

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SystemVerilog Master BFM

Note

Master Assertions

The master BFM performs protocol error checking using built-in assertions.

The built-in BFM assertions are independent of programming language and simulator.

By default, all built-in assertions are enabled in the master BFM. To globally disable them in the master BFM, use the set_config() command as shown in Example 3-2.

Example 3-2. Master BFM Disable All Assertions

set_config(AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS,0)

Alternatively, you can disable individual built-in assertions by using a sequence of get_config() and set_config() commands on the respective assertion. Example 3-3 shows how to disable assertion checking for the TLAST signal changing between the TVALID and TREADY handshake signals.

Example 3-3. Master BFM Individual Assertion Enable/Disable

// Define a local bit vector to hold the value of the assertion bit vector bit [255:0] config_assert_bitvector;

// Get the current value of the assertion bit vector config_assert_bitvector = bfm.get_config(AXI4STREAM_CONFIG_ENABLE_ASSERTION);

// Assign the AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY assertion bit to 0 config_assert_bitvector[AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY] = 0;

// Set the new value of the assertion bit vector bfm.set_config(AXI4STREAM_CONFIG_ENABLE_ASSERTION, config_assert_bitvector);

Do not confuse the AXI4STREAM_CONFIG_ENABLE_ASSERTION bit vector with the AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS global enable/disable.

To re-enable the AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY assertion, follow the code sequence in Example 3-3 and assign the assertion enable within the AXI4STREAM_CONFIG_ENABLE_ASSERTION bit vector to 1.

For a complete listing of AXI4-Stream assertions, refer to “Assertions” on page 205.

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SystemVerilog Master BFM

Note

SystemVerilog Master API

This section describes the SystemVerilog master BFM API.

Each task and function available within the master BFM API is detailed with the exception of the set*() and get*() tasks that operate on the Transaction Record. The simple rule for the task name is set_ or get_ followed by the name of the transaction field to be accessed. Refer to “Transaction Record” on page 23 for details of transaction field names.

The master BFM API is the axi4stream/bfm//mgc_axi4stream_master.sv file packaged within the Mentor Verification IP Altera Edition.

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SystemVerilog Master BFM

set_config()

This function sets the configuration of the master BFM.

Prototype

Arguments

Returns

function void set_config (

input axi4stream_config_e config_name, input axi4stream_max_bits_t config_val

);

config_name Configuration name:

AXI4STREAM_CONFIG_SETUP_TIME AXI4STREAM_CONFIG_HOLD_TIME AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR AXI4STREAM_CONFIG_LAST_DURING_IDLE AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_ASSERTION_

TO_TREADY

AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS AXI4STREAM_CONFIG_ENABLE_ASSERTION

config_val See “Master BFM Configuration” on page 32 for more details.

None

Example

set_config(AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR, 1000);

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get_config()

This function gets the configuration of the master BFM.

SystemVerilog Master BFM

get_config()

Prototype

Arguments config_name

Returns

function axi4stream_max_bits_t get_config (

input axi4stream_config_e config_name,

);

Configuration name:

AXI4STREAM_CONFIG_SETUP_TIME AXI4STREAM_CONFIG_HOLD_TIME AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR AXI4STREAM_CONFIG_LAST_DURING_IDLE AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_ASSERTION_

TO_TREADY

AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS AXI4STREAM_CONFIG_ENABLE_ASSERTION

config_val See “Master BFM Configuration” on page 32 for more details.

Example

get_config(AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR);

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SystemVerilog Master BFM

create_master_transaction()

This nonblocking function creates a master transaction with an optional burst_length argument. All other transaction fields default to legal protocol values, unless previously assigned a value. It returns with the axi4stream_transaction record.

Prototype

Arguments Protocol

Transaction Fields

Operational Transaction Fields

Returns

function automatic axi4stream_transaction create_master_transaction (

input int burst_length = 1 // optional

);

burst_length (Optional) Number of transfers within a packet. Default: 1.

data Data array in bytes. byte_type Byte type array:

AXI4STREAM_DATA_BYTE; (default) AXI4STREAM_NULL_BYTE; AXI4STREAM_POS_BYTE;

AXI4STREAM_ILLEGAL_BYTE; id Data stream identifier. dest Destination routing information. user_data User data array. operation_

mode

valid_delay TVALID delay measured in ACLK cycles for this transaction.

ready_delay TREADY delay measured in ACLK cycles for this transaction.

transfer_done Transfer done flag array for this transaction transaction_

done trans The axi4stream_transaction record.

Operation mode:

AXI4STREAM_TRANSACTION_NON_BLOCKING;

AXI4STREAM_TRANSACTION_BLOCKING; (default)

(default = 0).

Transaction done flag for this transaction

Example

// Create a master transaction with a data burst length of 3. trans = bfm.create_write_transaction(3); trans.set_data[0] = 'hACE0ACE1; trans.set_data[1] = 'hACE2ACE3; trans.set_data[2] = 'hACE4ACE5;

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SystemVerilog Master BFM

execute_transaction()

This task executes a master transaction previously created by the create_master_transaction() function. The transaction may be blocking (default) or nonblocking, as defined by the transaction record operation_mode field.

It calls the execute_transfer() task for each transfer within a packet, with the number of transfers defined by the transaction burst_length field.

Prototype

task automatic execute_transaction (

axi4stream_transaction trans

)

Arguments Returns

trans The axi4stream_transaction record.

None

Example

// Declare a local variable trans to hold the transaction record. axi4stream_transaction trans;

// Create a master transaction with a transfer count of 3 and assign // it to the local trans variable. trans = bfm.create_master_transaction(3);

....

// Execute the trans transaction. bfm.execute_transaction(trans);

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SystemVerilog Master BFM

execute_transfer()

This task executes a master transfer previously created by the create_master_transaction() function. This task may be blocking (default) or nonblocking, as defined by the transaction operation_mode field.

It sets the TVALID protocol signal at the appropriate time defined by the transaction valid_delay field, and sets the transfer_done array index element field to 1 when the transfer is complete.

If this is the last transfer of the transaction, then it sets the transaction_done field to 1 and returns the last argument set to 1 to indicate the whole transaction is complete.

Prototype

Arguments

Returns

task automatic execute_transfer (

axi4stream_transaction trans, int index = 0, // Optional output bit last

);

trans The axi4stream_transaction record.

index (Optional) Transfer number. last

Example

// Declare a local variable to hold the transaction record. axi4stream_transaction trans;

// Create a master transaction with a transfer count of 3 and assign // it to the local trans variable. trans = bfm.create_master_transaction(3);

....

// Execute the first transfer of the trans transaction. bfm.execute_transfer(trans, 0, last);

// Execute the second transfer of the trans transaction0. bfm.execute_transfer(trans, 1, last);

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SystemVerilog Master BFM

get_stream_ready()

This blocking task returns the value of the TREADY signal using the ready argument. It will block for one ACLK period.

Prototype

Arguments Returns

task automatic get_stream_ready (

output bit ready

);

ready The value of the TREADY signal.

ready

Example

// Get the value of the TREADY signal bfm.get_stream_ready(ready);

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SystemVerilog Master BFM

wait_on()

This blocking task waits for an event on the ACLK or ARESETn signals to occur before proceeding. An optional count argument waits for the number of events equal to count.

Prototype

Arguments

task automatic wait_on (

axi4stream_wait_e phase, input int count = 1 //Optional

);

phase Wait for:

AXI4STREAM_CLOCK_POSEDGE AXI4STREAM_CLOCK_NEGEDGE AXI4STREAM_CLOCK_ANYEDGE AXI4STREAM_CLOCK_0_TO_1 AXI4STREAM_CLOCK_1_TO_0 AXI4STREAM_RESET_POSEDGE AXI4STREAM_RESET_NEGEDGE AXI4STREAM_RESET_ANYEDGE AXI4STREAM_RESET_0_TO_1 AXI4STREAM_RESET_1_TO_0

Example

bfm.wait_on(AXI4STREAM_RESET_POSEDGE); bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE, 10);

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Chapter 4

SystemVerilog Slave BFM

This section provides information about the SystemVerilog slave BFM. It has an API that contains tasks and functions to configure the BFM and to access the dynamic Transaction

Record during the lifetime of a transaction.

Slave BFM Protocol Support

The slave BFM supports the full AMBA AXI4-Stream protocol.

Slave Timing and Events

For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI4-Stream Protocol Specification chapter, which you can reference for details of the following slave BFM API timing and events.

The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period with signal events sampled and driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale, timeunit, or timeprecision declarations with the signal setup and hold times specified in units of simulator time-steps.

• ` timescale directives in design elements

• Timeprecision declarations in design elements

• Compiler command-line options

• Simulation command-line options

• Local or site-wide simulator initialization files

If there is no timescale directive, the default time unit and time precision are tool specific. The recommended practice is to use timeunit and timeprecision declarations. Refer to the IEEE Standard for SystemVerilog, Section 3.14, for details.

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SystemVerilog Slave BFM

Note

Slave BFM Configuration

The slave BFM supports the full range of signals defined for the AMBA AXI4-Stream Protocol Specification. It has parameters that you use to configure the widths of the data and ID signals, and transaction fields to configure timeout factors, setup and hold times, and so on.

You can change the data and ID signal widths from their default settings by assigning them new values, usually in the top-level module of the test bench. These new values are then passed into the slave BFM using a parameter port list of the slave BFM module. Example 4-1 shows the slave BFM with the data and ID signal widths defined in module top() and passed in to the slave BFM mgc_axi4stream_slave parameter port list.

Example 4-1. Slave BFM Configuration

module top ();

parameter AXI4STREAM_ID_WIDTH = 18; parameter AXI4STREAM_USER_WIDTH = 4; parameter AXI4STREAM_DEST_WIDTH = 4; parameter AXI4STREAM_DATA_WIDTH = 32;

mgc_axi4stream_slave #(AXI4STREAM_ID_WIDTH, AXI4STREAM_USER_WIDTH,

AXI4STREAM_DEST_WIDTH, AXI4STREAM_DATA_WIDTH) bfm_slave(....);

In the Example 4-1 code extract, the mgc_axi4stream_slave is the slave BFM interface.

Table 4-1 lists the parameter names for the data and ID signals and their default values.

Table 4-1. Slave BFM Signal Width Parameters