Altera Active Serial Memory Interface User Manual

2014.12.15

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Altera ASMI Parallel IP Core User Guide

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About This IP Core

The Altera ASMI Parallel IP core provides access to erasable programmable configurable serial (EPCS),
quad-serial configuration (EPCQ), and low-voltage quad-serial configuration (EPCQ-L) devices through
parallel data input and output ports.

An EPCS device is a serial configuration device that you use to perform an active serial (AS) configuration
on supported Altera® devices.

An EPCQ/EPCQ-L device is a serial or quad-serial configuration that supports AS x1 or AS x4 configura‐
tion scheme. During AS configuration, the Altera device is the master and the EPCS/EPCQ/EPCQ-L
device is the slave.

The Altera ASMI Parallel IP core implements a basic active serial memory interface (ASMI). To use this
IP core, you do not need to know the details of the serial interface and the read and write protocol of an
EPCS/EPCQ/EPCQ-L device.

Note:

Beginning from the Quartus® II software version 14.0, the name of this IP core has been changed
from ALTASMI_PARALLEL to Altera ASMI Parallel IP core.

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You can perform the following tasks with the Altera ASMI Parallel IP core:

• Read the EPCS silicon identification (device identification)

• Protect a certain sector in the EPCS/EPCQ/EPCQ-L device from write or erase

• Read the data at a specified address from the EPCS/EPCQ/EPCQ-L device

• Perform single-byte write to the EPCS/EPCQ/EPCQ-L device

• Perform page write to the EPCS/EPCQ/EPCQ-L device

• Read the status of the EPCS/EPCQ/EPCQ-L device

• Erase a specified sector on the EPCS/EPCQ/EPCQ-L device

• Erase a specified die on the EPCQ-L512 and EPCQ-L1024

• Erase memory in bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-L512 device
The memory in the EPCS/EPCQ/EPCQ-L device contains two sections:

• Configuration memory—contains the bitstream of the configuration data

• General purpose memory—used for an application-specific storage

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

ISO
9001:2008
Registered

Altera Device

ASMI Controller

read_block

write_block

erase_bulk_block/erase_die_block

read_silicon_id_block (3)

write_status_block

Clock

Divider

ASDI

nCS

DCLK
DATA

EPCS Device

User Design

stratixii_asmiblock,

stratixiigx_asmiblock,

stratixiii_asmiblock,

stratixv_asmiblock

arriagx_asmiblock
arriavgz_asmiblock,
stratixiv_asmiblock,

arriav_asmiblock,

arriaiigz_asmiblock,

arriaii_asmiblock,

cycloneii_asmiblock ,

(2)

cyclone_asmiblock,
cyclonev_asmiblock,

ASMI Device Primitives

Altera ASMI PARALLEL IP Core

read_memory_capacity_id(1)

fast_read (1)

nCS

DCLK
DATA0

DATA1

DATA2

DATA3

EPCQ/EPCQ-L

Device

(1) Not applicable for EPCS1 and EPCS4.
(2) The synthesis operations for Cyclone III, Cyclone IV GX, and Cyclone IV E devices use the cycloneii_asmi primitive.
(3) The read_silicon_id block is supported only for EPCS1, EPCS4, EPCS16 and EPCS64.

erase_sector_block

twentynm_asmiblock

(5)

(4)

(4) Only available for Arria 10 devices.
(5) The erase_die_bloack is only available for EPCQ-L512 and EPCQ-L1024 device.

2

Device Family Support

This figure shows that you can use the Altera ASMI Parallel IP core to access the general purpose memory
portion of the EPCS/EPCQ/EPCQ-L devices through the supported Altera devices.

Caution: Altera recommends you to be cautious when accessing the configuration memory in the EPCS/

EPCQ/EPCQ-L device to avoid corrupting the configuration bits.

Example 1: Accessing General Purpose Memory in Altera Devices

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Device Family Support

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Related Information

• Introduction to Altera IP Cores

For more information about Altera IP cores

• Active Serial Configuration

For more information about AS configuration

• Serial Configuration Devices Datasheet

For more information about EPCS devices

• Quad-Serial Configuration (EPCQ) Device Datasheet

• EPCQ-L Serial Configuration Devices Datasheet

• Altera Configuration Device

The Altera ASMI Parallel IP core is available for all Altera device families supported by the Quartus II
software except the MAX® series.

For more information about features, memory array organization, and operation codes of the EPCS
device

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Altera ASMI Parallel

clkin (1)

fast_read (9), (4)
rden (1)

read_sid

(2), (5)

read_status

(1)

write

(1)

datain[]

(1)

shift_bytes

(1)

sector_protect (1)
sector_erase

(1)

bulk_erase

(11)

wren

(1)

read_rdid

(1), (6)

addr[]

(1)

dataout[] (1)
busy (1)
data_valid (1)

status_out[] (1)
illegal_write (1)

illegal_erase (1)
read_address[] (1)

rdid_out[] (1), (6)

epcs_id[] (2), (5)

read

(1), (4)

read_dummyclk

(3), (7)

reset

(1)

asmi_dataout[] (1)

asmi_dclk (1)
asmi_scein (1)

asmi_sdoin[] (1)
asmi_dataoe[] (1)

en4b_addr

(3), (8)

ex4b_addr (3), (8)

Applicable for EPCS/EPCQ/EPCQ-L devices.
Applicable for EPCS devices only.
Applicable for EPCQ/EPCQ-L devices only.
The read and fast_read signals cannot be present simultaneously.
EPCS128 does not support the read_sid and epcs_id signals.
EPCS1 and EPCS4 do not support read_rdid and rdid_out signals.
The read_dummyclk is available only when you select the Use ‘fast_read’ port option.
The en4b_addr and ex4b_addr signals are supported only for EPCQ256/EPCQ-L256 or larger devices.
Applicable for all EPCS/EPCQ/EPCQ-L devices, except for EPCS1 and EPCS4 devices.

die_erase

(12)

sce[2..0]

Applicable for Arria 10 devices only.
Applicable for all EPCS/EPCQ/EPCQ-L devices, except for EPCQ512, EPCQ-L512 and EPCQL-1024.
Applicable for EPCQ-L512 and EPCQL-1024 devices.

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

(10)
(11)
(12)
(13)

Applicable for Arria 10 devices only.

(13)

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Ports and Parameters

This figure shows a typical block diagram of the Altera ASMI Parallel IP core.

Figure 1: Altera ASMI Parallel Block Diagram

Ports and Parameters

3

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4

Parameters

Parameters

Table 1: Parameter Settings

Parameter Legal Values Descriptions

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Currently selected device
family

Arria GX,
Arria V GZ,
Arria II GX,
Arria II GZ,

Arria V,

Cyclone,

Cyclone II,

Cyclone III,

Cyclone III LS,

Cyclone IV E,

Cyclone IV GX,

Cyclone V,
HardCopy III,
HardCopy IV,

Stratix II,

• Specifies the device family you intend to use. Use this
parameter for modeling and behavioral simulation
purposes, as each device family has its own ASMI
primitive.

Stratix II GX,

Stratix III,
Stratix IV,

Stratix V,

Arria 10

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Parameter Legal Values Descriptions

Parameters

5

Configuration device

EPCS1,

type

EPCS4,
EPCS16,
EPCS64,

EPCS128,

EPCQ16,
EPCQ32,

EPCQ64,
EPCQ128,
EPCQ256,
EPCQ512,

EPCQ-L256,
EPCQ-L512,

EPCQ-L1024

Use ‘read_sid’ port —

• Specify the EPCS/EPCQ/EPCQ-L type you want to use.

• The default value is EPCS4.

• Enables the ability to read the silicon ID of the EPCS
device with an active-high read_sid input signal.
When this signal is asserted, the IP core reads the
silicon ID of the EPCS device. After reading the silicon
ID, the 8-bit silicon ID appears on the epcs_

id[7..0]signal until the device resets.

• This option is available only for EPCS1, EPCS4,
EPCS16, and EPCS64 devices.

Use ‘read_status’ port —

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• Enables the ability to read the port status using an
active-high input signal named read_status. When
this signal is asserted, the IP core reads the EPCS/
EPCQ/EPCQ-L status register. As the status register is
read, the 8-bit value appears on the status_

out[7..0]signal.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

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Parameters

Parameter Legal Values Descriptions

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Use ‘read_rdid’ and

—

‘rdid_out’ ports

Enable write operation —

• Enables the ability to read the memory capacity ID of
the EPCS/EPCQ/EPCQ-L device with an active-high
input signal named read_rdid. When this signal is
asserted, the IP core reads the memory capacity ID of
the EPCS/EPCQ/EPCQ-L device. The 8-bit ID appears
on the rdid_out[7..0]signal until the device resets.

• This option is available for all devices, except for
EPCS1 and EPCS4.

• Enables the ability to write to the EPCS/EPCQ/EPCQ­L device with an active-high input signal named write.
When this port is asserted, the IP core writes the data
from the datain[7..0]signal (for single-byte write) or
from the page-write buffer (for page-write) to the
address that appears on the addr[23..0]port, and to
subsequent addresses for page-write. For EPCQ256/
EPCQ-L256 or larger devices, the width of the addr
and read_address signals is 32 bit.

• In page-write mode, you must use the shift_byte
signal to shift in data bytes before asserting the write
signal.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

Use ‘wren’ port —

• Enables write and erase operations to the EPCS/EPCQ/
EPCQ-L memory with an active-high input signal
named wren. If this signal is asserted, the write and
erase operations are enabled, and disabled if the signal
is deasserted. If you are not using the wren signal, all
write and erase operations are automatically enabled
when the command appears on the relevant IP core
input port. The affected commands are write, sector
protect, bulk erase, and sector erase.

• This option is only available when you turn on the

Enable write operation, Use ‘sector protect’ port or
die erase port, Use ‘bulk erase’ port, or Use ‘sector

erase’ port option.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

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Parameter Legal Values Descriptions

Parameters

7

Write mode —

Use ‘fast_read’ port —

• This option is only available when you turn on the
Enable ‘write’ operation option.

• When you select this option, the Altera ASMI Parallel
IP core defines two parameters, which are PAGE_SIZE
and PORT_SHIFT_BYTES for the following writing
mode to the EPCS/EPCQ/EPCQ-L device:

Single byte write: PAGE_SIZE = 1, PORT_SHIFT_
BYTES = PORT_UNUSED

Page write: PAGE_SIZE = 1 to 256, if 1 then PORT_
SHIFT_BYTES = PORT_UNUSED, else PORT_USED

Store ‘page write’ data in logic elements.

• Enables the ability to perform a fast read operation
with an active-high input signal named fast_read.
When this signal is asserted, the IP core performs a fast
read from the memory address that appears on the

addr[23..0]signal. Each data byte appears on the
dataout[7..0] signal as it is read. For EPCQ256/

EPCQ-L256 or larger devices, the width of the addr
and read_address signals is 32 bit.

• The fast_read signal supports single-byte fast read
and sequential fast read. If a write or erase operation is
in progress (the busy signal is asserted), the fast read
command is ignored. The fast read operation occurs
only when allowed by the rden signal.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices, except for EPCS1 and EPCS4 devices.The fast
read operation replaces the normal settings.

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Parameters

Parameter Legal Values Descriptions

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Choose I/O mode STANDARD,

DUAL, QUAD

Read device dummy clock —

• The following commands are the instructions from the
EPCQ/EPCQ-L extended serial peripheral interface
(SPI) protocol which uses multiple data lines:

Dual Fast Read (Dual Input/Output Fast Read)
Quad Fast Read (Quad Input/Output Fast Read)
Dual Write (Dual Input Extended Fast Program)
Quad Write (Quad Input Extended Fast Program)

• These commands are combined into the following
ports:

Fast read port – fast read (x1), dual fast read and quad
fast read

Write port – write (x1), dual write and quad write

• You can choose which I/O mode to use, the choices are
Standard (x1), Dual (x2) or Quad (x4) mode.

• This option is only available for EPCQ/EPCQ-L
devices.

• This option is disabled by default and the IP core
generates the design file as per usual.

• To perform fast read operation, align the dummy
cycles of EPCQ/EPCQ-L devices with Altera ASMI
Parallel designated value.

• When enabling this option, the read_dummyclk input
pin is created. The Altera ASMI Parallel IP core reads
the dummy clock stored in a non-volatile configuration
register of a flash at the beginning of the operation.

• When the signal is asserted high, the Altera ASMI
Parallel IP core reads the dummy clock in the volatile
configuration register of the flash. The value is held till
the next signal is asserted or when the device resets.

• This option is available for EPCQ/EPCQ-L devices
only.

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Parameter Legal Values Descriptions

Parameters

9

Use ‘sector_protect’ port —

Use ‘bulk_erase’ port —

Use ‘sector_erase’ port —

• Enables the ability to protect sectors in the EPCS/
EPCQ/EPCQ-L device from write and erase operations
with an active-high input port named sector_

protect. When this port is asserted, the IP core reads

the block protection code value on the

datain[7..0]signal and writes it to the EPCS/EPCQ/

EPCQ-L status register. To protect specific memory
sectors, you must send their block protection code to
the datain[7..0] signal.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

• Enables the ability to erase the entire memory of the
EPCS/EPCQ/EPCQ-L256 device, including the
configuration data portion with an active-high input
signal named bulk_erase. When this signal is asserted,
the IP core implements a full erase that sets the entire
memory bits of the EPCS/EPCQ/EPCQ-L256 device to
a value of one.

• This option is available for all EPCS/EPCQ devices.

• Enables the ability to erase a certain sector in the
EPCS/EPCQ memory with an active-high input signal
named sector_erase. When the signal is asserted, the
IP core implements a full erase of the sector. The value
of the addr[23..0]signal indicates the sector to erase.
For EPCQ256/EPCQ-L256 or larger devices, the width
of the addr and read_address signals is 32 bit.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

Use ‘die_erase’ port —

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• Enables the ability to erase each die in your device.
When the signal is asserted, the IP core implements a
full erase of a single die in your device. You need to
issue the erase die operation twice for EPCQ-L512
device and four times for the EPCQ-L1024.

• This option is available for Arria 10 devices with
EPCQL-512 and EPCQL-1024.

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Parameters

Parameter Legal Values Descriptions

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Use ‘read_address’ port —

Use 'ex4b_addr’ —

• This signal holds the address from which data is being
read. This signal works together with the

dataout[7..0]signal. As data appears on
dataout[7..0], the address from which the data byte

was read appears on the read-address output port. For
EPCQ256/EPCQ-L256 or larger devices, the width of
the addr and read_address signals is 32 bit. For other
devices, the width of the addr and read_address
signals is 24 bit.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

• To exit the 4-byte addressing mode when you use an
EPCQ256/EPCQ-L256 or larger devices, pull the
WREN signal high, followed by at least one clock cycle.
If WREN signal is zero, the 4-byte addressing mode
exit operation will not be carried out even though the
ex4b_addr is high. After the IP core receives the
command, the IP core asserts the busy signal to
indicate that the exit operation is in progress.

• Only applicable for EPCQ256/EPCQ-L256 or larger
devices.

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Parameter Legal Values Descriptions

Parameters

11

Disable dedicated Active
Serial interface

—

• This option is disabled by default and the IP core
generates the design file as per usual.

• The Altera ASMI Parallel IP core instantiates the ASMI
block internally and connects to the block automati‐
cally.

• The IP core creates the following input/output pins
when you enable this option:

asmi_dataout,
asmi_dclk,
asmi_scein,
asmi_sdoin,
asmi_dataoe.

• When you enable this option, the Altera ASMI Parallel
IP core will not instantiate ASMI block automatically,
and all signals to interface with ASMI block are routed
to the top level of your design. You must then
instantiate the ASMI block externally, and assign the
ASMI ports in the Altera ASMI Parallel IP core to the
dedicated pins location.

• The CLI parameter to disable this option is USE_

ASMIBLOCK=ON.

• This option is available for all EPCS/EPCQ/EPCQ-L
devices.

Related Information

• Introduction to Altera IP Cores

For more information about starting the IP Parameter Editor

• Quad-Serial Configuration (EPCQ) Devices Datasheet

For the designated Altera ASMI Parallel dummy cycles values

• on page 20

For more information about the Use ‘read_sid’ port parameter

• on page 29

For more information about the Use ‘read_status’ port parameter

• on page 19

For more information about the Use ‘read_rdid’ and ‘rdid_out’ ports parameter

• on page 26

For more information about the Enable write operation parameter

• on page 23

For more information about the Use ‘fast_read’ port parameter

• on page 21

For more information about the Use ‘sector_protect’ port parameter

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