8B10B Encoder/Decoder MegaCore Function User Guide
8B10B Encoder/Decoder MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
c The 8B10B Encoder/Decoder MegaCore function is scheduled for product
obsolescence and discontinued support as described in PDN1304. Therefore, Altera
does not recommend use of this IP in new designs. For more information about
Altera’s current IP offering, refer to Altera’s Intellectual Property website.
UG-IPED8B10B-1.4
Document last updated for Altera Complete Design Suite version:
Document publication date:
11.0
May 2011
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customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
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8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Contents
Chapter 1. About This MegaCore Function
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
8B10B Encoder /Decoder Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Create a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Launch MegaWizard Plug-in Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Generate Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
IP Functional Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. Specifications
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Generic Framing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Character Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Cascaded Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Encoding Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Fibre Channel and IEEE 802.3z 1000BaseX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Cascaded Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Decoding Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Encoder Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Decoder Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
iv Contents
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Release Information
1. About This MegaCore Function
Tab le 1– 1 provides information about this release of the Altera® 8B10B
Encoder/Decoder MegaCore
Table 1–1. 8B10B Encoder/Decoder MegaCore Function Release Information
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata.
Altera verifies that the current version of the Quartus
previous version of each MegaCore
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release."
Device Family Support
®
function.
Item Description
Version 11.0
Release Date May 2011
Ordering Code IP-ED8B10B
Product ID 0079
Vendor ID 6AF7
®
®
function. The MegaCore IP Library Release Notes
II software compiles the
MegaCore functions provide either full or preliminary support for target Altera
device families:
■ Full support means the MegaCore function meets all functional and timing
requirements for the device family and may be used in production designs.
■ Preliminary support means the MegaCore function meets all functional
requirements, but may still be undergoing timing analysis for the device family; it
may be used in production designs with caution.
Tab le 1– 2 shows the level of support offered by the 8B10B Encoder/Decoder
MegaCore function to each Altera device family.
Table 1–2. Device Family Support (Part 1 of 2)
Device Family Support
®
Arria
GX Full
Arria II GX Full
®
Cyclone
Cyclone II Full
Cyclone III Full
Cyclone III LS Full
Full
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
1–2 Chapter 1: About This MegaCore Function
Features
Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support
Cyclone IV E Full
Cyclone IV GX Full
®
HardCopy
II Full
HardCopy III Preliminary
HardCopy IV E Preliminary
HardCopy IV GX Preliminary
®
Stratix
Full
Stratix GX Full
Stratix II Full
Stratix II GX Full
Stratix III Full
Stratix IV Full
Other device families No support
Features
The following list summarizes the features of the 8B10B Encoder/Decoder MegaCore
function:
■ 8b/10b encoding and decoding.
■ Cascaded encoding and decoding.
■ Industry compatible special character coding.
■ Easy-to-use IP MegaWizard
■ Support for OpenCore Plus evaluation.
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators.
General Description
Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre
Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates
a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum
run length of 5. Some of the individual 10-bit codes will have an equal number of 1s
and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s. In the
latter case, the disparity between 1s and 0s is used as an input to the next 10-bit code
generation, so that the disparity can be reversed, and maintain an overall balanced
stream. For this reason, some 8-bit inputs have two valid 10-bit codes, depending on
the input disparity.
™
interface.
The Altera 8B10B Encoder/Decoder is a compact, high performance MegaCore
function capable of encoding and decoding in multi-gigabit applications.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 1: About This MegaCore Function 1–3
Performance and Resource Utilization
Performance and Resource Utilization
This section lists the resource utilization and performance of the 8B10B
Encoder/Decoder MegaCore function in different Altera device families. These
results were obtained using the Quartus
replacement feature disabled. Enabling this feature produces a smaller but slower
MegaCore function.
Tab le 1– 3 shows the performance and resource utilization for Cyclone II
(EP2C35F484C6) and Cyclone III (EP3C80F780C6).
Table 1–3. Resource Utilization and Performance (Cyclone II and Cyclone III)
Parameters
Device
Mode of Operation
Register
Inputs/Outputs
Encoder On 100 250
Cyclone II
Encoder Off 107 403
Decoder – 131 403
Encoder On 100 250
Cyclone III
Encoder Off 107 403
Decoder – 131 403
Note to Table 1–3:
(1) f
is for non-cascaded encoders/decoders.
MAX
®
II software version 9.1 with the auto-ROM
LEs f
(MHz) (1)
MAX
Tab le 1– 4 shows the performance and resource utilization for Stratix II
(EP2S30F484C3) and Stratix III (EP3SE110F780C2). The performance of the MegaCore
function in Stratix IV devices is similar to Stratix III devices.
Table 1–4. Resource Utilization and Performance (Stratix II and Stratix III)
Parameters
Device
Mode of Operation
Register
Inputs/Outputs
Combinational
Encoder On 61 51 444
Stratix II
Encoder Off 68 13 585
Decoder – 55 33 447
Encoder On 60 51 510
Stratix III
Encoder Off 68 13 675
Decoder – 55 33 520
Note to Table 1–4:
(1) f
is for non-cascaded encoders/decoders.
MAX
ALUTs
Logic
Registers
f
MAX
(MHz) (1)
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
1–4 Chapter 1: About This MegaCore Function
ed8b10b
Contains the MegaCore function files and documentation.
doc
Contains the documentation for the MegaCore function.
lib
Contains encrypted lower-level design files.
<path>
common
Contains the shared components.
ip
Contains the MegaCore IP Library.
Installation directory
altera
Contains all MegaCore IP Library from Altera.
Installation and Licensing
Installation and Licensing
The 8B10B Encoder/Decoder MegaCore Function is part of the MegaCore® IP Library,
which is distributed with the Quartus
®
Altera
website, www.altera.com.
®
II software and downloadable from the
f For system requirements and installation instructions, refer to Altera Software
Installation and Licensing.
Figure 1–1 shows the directory structure after you install the 8B10B Encoder/Decoder
MegaCore Function, where
<
path> is the installation directory. The default installation
directory on Windows is c:\altera\90; on UNIX and Linux it is /opt/altera/90.
Figure 1–1. Directory Structure
OpenCore Plus Evaluation
f For more information on OpenCore Plus hardware evaluation using the 8B10B
With Altera’s free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction within your system
■ Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
■ Generate time-limited device programming files for designs that include
megafunctions
■ Program a device and verify your design in hardware
You only need to purchase a license for the megafunction when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
After you purchase a license for 8B10B Encoder/Decoder, you can request a license
file from the Altera website at www.altera.com/licensing and install it on your
computer. When you request a license file, Altera emails you a license.dat file. If you
do not have Internet access, contact your local Altera representative.
Encoder/Decoder, refer to AN 320: OpenCore Plus Evaluation of Megafunctions.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 1: About This MegaCore Function 1–5
Installation and Licensing
OpenCore Plus Time-Out Behavior
OpenCore® Plus hardware evaluation can support the following two modes of
operation:
■ Untethered—the design runs for a limited time
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1 For MegaCore functions, the untethered timeout is 1 hour; the tethered timeout value
is indefinite.
Your design stops working after the hardware evaluation time expires, and the
following events occur:
■ For the encoder:
■ The
■ The
■ The
■ For the decoder:
■ The
■ The
■ The
ena
input signal is forced low (deasserted).
dataout
valid
output is forced low (deasserted).
ena
input signal is forced low (deasserted).
dataout
valid
output is forced low (deasserted).
output is forced to the k28.5 pattern.
output is forced to all zeros.
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
1–6 Chapter 1: About This MegaCore Function
Installation and Licensing
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Design Flow
2. Getting Started
To evaluate the 8B10B Encoder/Decoder MegaCore® function using the OpenCore
Plus feature include these steps in your design flow:
1. Obtain and install the 8B10B Encoder/Decoder MegaCore Function.
f For more information on installation and licensing, refer to “Installation
and Licensing” on page 1–4.
2. Create a custom variation of the 8B10B Encoder/Decoder MegaCore Function.
3. Implement the rest of your design using the design entry method of your choice.
4. Use the IP functional simulation model to verify the operation of your design.
f For more information on IP functional simulation models, refer to the
Simulating Altera IP in Third-Party Simulation Tools chapter in Volume 3 of
the Quartus II Handbook.
5. Use the Quartus II software to compile your design.
1 You can also generate an OpenCore Plus time-limited programming file,
which you can use to verify the operation of your design in hardware.
6. Purchase a license for the 8B10B Encoder/Decoder MegaCore Function.
After you have purchased a license for the 8B10B Encoder/Decoder MegaCore
Function, follow these additional steps:
1. Set up licensing.
2. Generate a programming file for the Altera
3. Program the Altera device(s) with the completed design.
8B10B Encoder /Decoder Walkthrough
This walkthrough shows you how to create an 8B10B Encoder/Decoder MegaCore
function using the MegaWizard interface and the Quartus II software. After
generating a custom variation of the 8B10B Encoder/Decoder MegaCore function,
you can incorporate it into your overall project.
This walkthrough consists of the following steps:
■ Create a New Quartus II Project
®
device(s) on your board.
■ Launch MegaWizard Plug-in Manager
■ Parameterize
■ Set Up Simulation
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
2–2 Chapter 2: Getting Started
■ Generate Files
■ Set Constraints
8B10B Encoder /Decoder Walkthrough
Create a New Quartus II Project
You need to create a new Quartus II project with the New Project Wizard, which
specifies the working directory for the project, assigns the project name, and
designates the name of the top-level design entity.
To create a new project follow these steps:
1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. Alternatively, you can use the Quartus II Web Edition
software.
2. Choose New Project Wizard (File menu).
3. Click Next in the New Project Wizard Introduction page (the introduction does
not display if you turned it off previously).
4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the
following information:
a. Specify the working directory for your project. For example, this walkthrough
uses the directory:
c:\altera\projects\ed8b10b_project
b. Specify the name of the project. This walkthrough uses the project name:
ed8b10b_example
1 The Quartus II software automatically specifies a top-level design entity
that has the same name as the project. Do not change it.
5. Click Next to close this page and display the New Project Wizard: Add Files page.
1 When you specify a directory that does not already exist, a message asks if
the specified directory should be created. Click Yes to create the directory.
6. If you installed the MegaCore IP Library in a different directory from where you
installed the Quartus II software, you must add the user libraries:
a. Click User Libraries.
b. Type <path>
\ip\altera
into the Library name box, where <path> is the
directory in which you installed the 8B10B Encoder/Decoder MegaCore
Function.
c. Click Add to add the path to the Quartus II project.
d. Click OK to save the library path in the project.
7. Click Next to close this page and display the New Project Wizard: Family &
Device Settings page.
8. On the New Project Wizard: Family & Device Settings page, choose the target
device family in the Family list.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 2: Getting Started 2–3
8B10B Encoder /Decoder Walkthrough
9. The remaining pages in the New Project Wizard are optional. Click Finish to
complete the Quartus II project.
You have finished creating your new Quartus II project.
Launch MegaWizard Plug-in Manager
To launch the MegaWizard Plug-in Manager in the Quartus II software, follow these
steps:
1. Start the MegaWizard
Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box
displays.
f Refer to the Quartus II Help for more information on how to use the
MegaWizard Plug-In Manager.
2. Specify that you want to create a new custom megafunction variation and click
Next.
3. Expand the Communications > Encoding/Decoding directory, then click 8B10B
Encoder-Decoder v9.1.
®
Plug-In Manager by choosing the MegaWizard Plug-In
4. Choose the device family you want to use for this MegaCore function, for example
Stratix II GX.
5. Select the output file type for your design; the MegaWizard interface supports
VHDL and Verilog HDL.
6. The MegaWizard Plug-In Manager shows the project path that you specified in the
New Project Wizard. Append a variation name for the MegaCore function output
files <project path>\<variation name>.
7. Click Next to display the Parameter Settings page for the 8B10B Encoder/Decoder
MegaCore Function.
1 You can change the page that the MegaWizard Plug-In Manager displays by
Parameterize
To parameterize your MegaCore function, perform the following steps:
1. Select the mode of operation, either Encoder or Decoder.
2. If you selected Encoder, turn on the Register inputs/outputs check box for a three-
cycle latency, or turn off the Register inputs/outputs check box for a single-cycle
latency.
clicking Next or Back at the bottom of the dialog box. You can move
directly to a named page by clicking the Parameter Settings, EDA, or
Summary tab.
1 The Decoder always has registered inputs and outputs.
3. Click Next (or the EDA tab) to display the simulation setup page .
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
2–4 Chapter 2: Getting Started
8B10B Encoder /Decoder Walkthrough
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
file produced by the Quartus II software. The model allows for fast functional
simulation of IP using industry-standard VHDL and Verilog HDL simulators.
c You may only use these models for simulation purposes and expressly not for
synthesis or any other purposes. Using these models for synthesis creates a
nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Turn on Generate Simulation Model.
2. Click Next (or the Summary page) to display the summary page .
Generate Files
To generate the files, perform the following steps:
1. On the Summary page, turn on the files you want to generate.
1 A gray checkmark indicates a file that is automatically generated; a red
checkmark indicates an optional file.
2. To generate the specified files and close the MegaWizard Plug-in Manager, click
Finish.
1 The generation phase may take several minutes to complete.
3. After you review the generation report, click Exit to close the MegaWizard Plug-In
Manager.
1 The Quartus II IP File (.qip) is a file generated by the MegaWizard interface
or SOPC Builder that contains information about a generated IP core. You
are prompted to add this .qip file to the current Quartus II project at the
time of file generation. In most cases, the .qip file contains all of the
necessary assignments and information required to process the core or
system in the Quartus II compiler. Generally, a single .qip file is generated
for each MegaCore function and for each SOPC Builder system. However,
some more complex SOPC Builder components generate a separate .qip
file, so the system .qip file references the component .qip file.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 2: Getting Started 2–5
8B10B Encoder /Decoder Walkthrough
Tab le 2– 1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the summary vary based on
whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files (Note 1)
Filename (2) Description
Quartus II symbol file for the MegaCore function
<variation name>.bsf
<
variation name>.cmp VHDL component declaration file
<variation name>.html The MegaCore function report file.
<variation name>.v
<
variation name>.vo Verilog HDL IP functional simulation model.
<variation name>_bb.v
<
variation name>_constraints.tcl
<
variation name>_enc8b10b.ocp
<
variation name>_enc8b10b.v Verilog HDL RTL for this MegaCore function variation.
<
variation name>_run_modelsim.tcl
<
variation name>_tb.v
Notes to Table 2–1:
(1) These files are variation dependent, some may be absent or their names may change.
(2) <variation name> is a prefix variation name supplied automatically by the MegaWizard interface.
(3) If you choose the decoder mode, the file name is <variation name>_dec8b10b.
variation. You can use this file in the Quartus II block
diagram editor.
A MegaCore function variation file, which defines a
Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
Verilog HDL black-box file for the MegaCore function
variation. Use this file when using a third-party EDA tool
to synthesize your design.
Tool command language (tcl) script used to set
constraints.
An OpenCore Plus file, needed for time-limited or tethered
hardware evaluation.
A Tcl script to automate the process of running the
provided demo testbench with the IP functional
simulation model.
A Verilog HDL module with the top-level demo testbench
for the core.
Set Constraints
The 8B10B Encoder/Decoder MegaCore function variations include a tool command
language (Tcl) script. Use this Tcl script to constrain your design.
To run the Tcl script in the Quartus II software, in a Win32 operating system, follow
either of these sets of steps:
1. Select TCL Scripts (Tools menu).
2. Select the applicable Tcl file for your variation:
<variation name>_constraints. tcl
3. Click Run.
or
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
2–6 Chapter 2: Getting Started
Simulate the Design
4. Click on Tcl Co n so l e under Utility_Windows (View menu).
5. In the Tcl console window, type:
source
To run the Tcl script in a UNIX or Linux operating system terminal, type:
cd..<project_directory>
quartus_sh -t <variation name>
1 Depending on the type of constraints applied by the Tcl script, analysis and synthesis
may be run twice. For example, if hierarchy independent constraints are needed, the
Tcl script runs analysis and synthesis before applying the constraints. Therefore, when
you run a full compilation, after running the Tcl script, the analysis and synthesis are
run a second time.
You can now integrate your custom MegaCore function variation into your design,
simulate, and compile.
Simulate the Design
You can simulate your design using the generated VHDL and Verilog HDL IP
functional simulation models.
f For more information on IP functional simulation models, refer to the Simulating
Altera IP in Third-Party Simulation Tools chapter in Volume 3 of the Quartus II Handbook.
Altera also provides a Verilog HDL demonstration testbench, including scripts to
compile and run the demonstration testbench using a variety of simulators and
models. This testbench demonstrates the typical behavior of an 8B10B MegaCore
function, and how to instantiate a model in a design. The demonstration testbench
does not perform any error checking.
<variation name>
_constraints.tcl
_constraints.tcl
f For a complete list of models or libraries required to simulate the 8B10B
Encoder/Decoder MegaCore function, refer to the _run_modelsim.tcl scripts
provided with the demonstration testbench.
IP Functional Simulation Model
To use the demonstration testbench with IP functional simulation models in the
ModelSim
1. Start the ModelSim simulator.
2. From the ModelSim File menu, use Change Directory to change the working
directory to the directory where you created your 8B10B Encoder/Decoder
variation.
3. In the ModelSim Transcript window, execute the command
do <variation_name>_run_modelsim.tcl
compiles the netlist files, and runs the testbench. The ModelSim Transcript
window displays messages from the testbench reflecting the results of the
simulation.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
®
simulator, follow these steps:
which sets up the required libraries,
Chapter 2: Getting Started 2–7
Compile the Design
1 In all cases, the testbench is in Verilog HDL, therefore a license to run mixed language
simulations is required to run the testbench with the VHDL model.
Altera recommends that you disable the auto-ROM replacement feature in the
Quartus II software. Enabling this feature produces a smaller but slower MegaCore
function.
Compile the Design
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on compiling your design.
Program a Device
After you have compiled your design, program your targeted Altera device, and
verify your design in hardware.
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
2–8 Chapter 2: Getting Started
Program a Device
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Functional Description
The MegaCore® function consists of an encoder (ENC8B10B) and a decoder
(DEC8B10B). See Figure 3–2 on page 3–2. The encoder encodes one 8-bit byte of data
into a 10-bit transmission code, and the decoder decodes a 10-bit code into one 8-bit
byte of data. Figure 3–1 illustrates the bidirectional conversion process.
3. Specifications
The eight input bits are named
and bit
group
H
is the most significant bit (MSB). They are split into two groups: the five-bit
A, B, C, D, E
, and the three-bit group F, G, H.
The coded bits are named
bits are also split into two groups: the six-bit group
group
f, g, h, j
Figure 3–1. 8b10b Conversion
.
7654321
HGFEDCBA
9876543210
A, B, C, D, E, F, G, H
a, b, c, d, e, i, f, g, h, j
Conversion8b10b
. Bit A is the least significant bit (LSB),
(the order is not alphabetical). These
a, b, c, d, e, i
, and the four-bit
0
abcdeifghj
LSB sent firstMSB sent last
In bit serial transmission, the LSB is usually transmitted first, while the MSB is usually
transmitted last.
Disparity
Disparity is the difference between the number of 1s and 0s in the encoded word.
■ Neutral disparity indicates the number of 1s and 0s are equal.
■ Positive disparity indicates more 1s than 0s.
■ Negative disparity indicates more 0s than 1s.
The MegaCore function is designed to maintain a neutral average disparity. Average
disparity determines the direct current (DC) component of a serial line. Running
disparity is a record of the cumulative disparity of every encoded word, and is
tracked by the encoder. To guarantee neutral average disparity, a positive running
disparity must be followed by neutral or negative disparity; a negative running
disparity must be followed by neutral or positive disparity.
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
3–2 Chapter 3: Specifications
(64B/65B Encoded)
Transport Network
GFP Data Stream
Demapper
GFP
Encoder
8B/10B
Decoder
8B/10B
Mapper
GFP
Gigabit
Ethernet
Stream
(8B/10B Encoded)
Gigabit
Ethernet
Stream
(8B/10B Encoded)
Ingress Egress
Functional Description
The running disparity error output (
rderr
) is asserted when any of the following rules
apply:
■ The current running disparity is positive and the 6-bit group has more ones than
zeros or is 111000.
■ The current running disparity is negative and the 6-bit group has more zeros than
ones or is 000111.
■ The running disparity after 6-bit group is positive and the 4-bit group has more
ones than zeros or is 1100.
■ The running disparity after 6-bit group is negative and the 4-bit group has more
zeros than ones or is 0011.
1
rderr
is asserted for some invalid 10-bit codes and not for others, strictly
based on the rules stated above. The computation of
independent of that of the special control character error (
rderr
is completely
kerr
) signal.
A 10-bit code that corresponds to a valid encoding but that has the wrong
disparity—though technically an invalid code—does not cause the
signal to be asserted. Only
rderr
is asserted.
kerr
f For details on running disparity rules, refer to the IEEE 802.3z specification, paragraph
36.2.4.4.
Generic Framing Procedure
The 8B10B Encoder/Decoder MegaCore function can be used within generic framing
procedure (GFP) applications. See Figure 3–2 on page 3–2 for an example.
Figure 3–2. 8B10B Encoder/Decoder GFP Typical Application
On ingress to the transport network, if the decoder receives an unrecognized
codeword, such as an illegal codeword or a legal codeword with a running disparity
kerr
or
error, it asserts the
the decoder indicates to the mapper that an invalid codeword has been received, the
mapper then generates a special control character, the 10B_ERR code. In addition, the
mapper remaps the 8B/10B codewords into 64B/65B codewords before sending the
data to the transport network.
On egress from the transport network, the demapper decodes the 64B/65B codewords
and sends them to the 8B/10B encoder. When the encoder receives the 10B_ERR code,
it sends out one of the two 10-bit illegal codewords with neutral disparity: 001111
0001(RD-) or 110000 1110(RD+), depending on the running disparity.
rderr
signals respectively. By asserting these error signals,
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 3: Specifications 3–3
Functional Description
Character Codes
In addition to 256 data characters, the 8b/10b code defines thirteen out-of-band
indicators, also called special control characters. The 256 data characters are named
Dx.y, and the special control characters are named Kx.y—except for the special code
10B_ERR (see Table 3–1 on page 3–3). The x value corresponds to the five-bit group,
and the y value to the three-bit group.
The special control characters indicate, for example, whether the data is idle, test data,
or data delimiters. In applications where encoded characters are transmitted bitserially, the comma character (K28.5) is usually used for alignment purposes as its 10bit code is guaranteed not to occur elsewhere in the encoded bit stream, except after
K28.7 which is normally only sent during diagnostic.
Tab le 3– 1 lists the special K codes used by the MegaCore function.
Table 3–1. Character Codes
10-Bit Special K Codes Equivalent 8-Bit Codes
K28.0 8'b000_11100
K28.1 8'b001_11100
K28.2 8'b010_11100
K28.3 8'b011_11100
K28.4 8'b100_11100
K28.5 (1) 8'b101_11100
K28.6 8'b110_11100
K28.7 8'b111_11100
K23.7 8'b111_10111
K27.7 8'b111_11011
K29.7 8'b111_11101
K30.7 8'b111_11110
10B_ERR 8'b111_11111
Note to Tab le 3–1:
(1) K28.5 is a comma character used for alignment purposes, and to represent the IDLE code.
Encoder
To encode an 8-bit word, the 8-bit value must be applied to the
ena
input must be asserted (active high).
When one of the thirteen special 10-bit codes is to be inserted, the equivalent 8-bit
code is placed on the
datain
lines and the
kin
input is asserted. The MegaCore
function performs error checking to ensure the out-of-band 8-bit code is valid. If not,
the
kerr
output is asserted. See Table 3–1 for a list of the valid K codes.
1 Although the 10B_ERR code is considered to be an invalid special character, it does
not cause the
kerr
signal to be asserted.
Idle (K28.5) characters can be automatically inserted when
asserting the
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
idle_ins
input.
datain
ena
is not asserted by
inputs and the
3–4 Chapter 3: Specifications
Functional Description
The encoder encodes invalid characters in the same way it encodes Idle (K28.5) codes.
The decoder treats invalid characters as Idle codes.
Figure 3–3 shows a block diagram of the encoder.
Figure 3–3. Encoder
clk
reset_n
kin
ena
idle_ins
datain [7:0]
rdin
rdforce
kerr
dataout [9:0]
valid
rdout
rdcascade
Disparity
The running disparity can be forced to positive or negative, allowing the user to insert
a special resynchronization pattern, or disparity errors.
When the
current running disparity. Setting
word with negative or neutral disparity. Setting
rdforce
input is asserted, the value on the
rdin
to 0 forces the encoder to produce an encoded
rdin
rdin
port is assumed to be the
to 1 forces the encoder to
produce an encoded word with positive or neutral disparity.
Cascaded Encoding
Two encoders can be cascaded to allow for 16-bit word encoding. The encoders are
cascaded by connecting the
encoder to the
connecting the
rdin
input of the least significant byte (LSByte) encoder, and by
rdout
output of the LSByte encoder to the
encoder. These connections ensure proper running disparity computation. The
rdforce
value on the
Both
datain[15:8]
inputs must be asserted (active high) for the encoders to take into account the
rdin
inputs, rather than use their internally generated running disparity.
ena
inputs must be high or low at the same time. The
, and
kin[0]
encoders connected together to perform cascaded encoding.
rdcascade
relates to
output of the most significant byte (MSByte)
rdin
input of the MSByte
datain[7:0]
kin [1]
. Figure 3–4 on page 3–5 shows two
signal relates to
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 3: Specifications 3–5
Functional Description
If the encoded words are to be transmitted serially, the result of encoding
datain[15:8]
should be transmitted first.
Figure 3–4. Cascaded Encoding
clk
reset_n
[1:0]kin
[15:0]datain
kin [1]
ena
idle_ins
datain [15:8]
rdin
rdforce
kerr
dataout [19:10]
valid
rdout
rdcascade
clk
reset_n
kin [0]
ena
idle_ins
datain [7:0]
rdin
rdforce
Note to Figure 3–4:
(1) The ena, idle_ins, and rdforce signals are set high (logic 1).
Encoding Latency
When the register inputs/outputs parameter is turned on, the encoder is pipelined,
thus it takes three clock cycles for a character to be encoded. The encoded value—
corresponding to the values of
n
—is output shortly after rising edge
edge of clock cycle
the data paths fed by the
and
rdin
are normally only used in cascaded configurations, this should not be a
problem. In cases where the
configurations, they should be delayed two clock cycles with respect to their
corresponding
n+3
datain
. (See Figure 3–5 on page 3–6). To enable cascaded encoding,
rdforce
rdforce
and
kin
datain
and
values.
kerr
dataout [9:0]
valid
rdout
rdcascade
and
kin
sampled by the encoder on rising edge
n+2
, and is available to be sampled on the rising
rdin
inputs are not pipelined. Because
and
rdin
inputs are to be used in noncascaded
rdforce
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
3–6 Chapter 3: Specifications
clk
datain, kin, en, idle_ins
dataout, rdout, kerr, valid
rdforce, rdin
rdcascade
a b c d e f g
a b c d e
a b c d e f
a b c def
n+1 n+2 n+3n
clk
datain, kin, en, idle_ins
dataout, rdout, kerr, valid
rdforce, rdin
rdcascade
a b c d e f g
a b c d e f
a b c d e f g
n+1
a b cdefg
n
Functional Description
When the register inputs/outputs parameter is turned off, the encoder takes one clock
cycle to encode a character. The encoded value—corresponding to the values of
datain
and
kin
sampled by the encoder on rising edge n—is output shortly after
rising edge
n
, and is available to be sampled on the rising edge of clock cycle
n+1
. (See
Figure 3–6).
Figure 3–5. Encoder Timing Diagram—Three Cycle Latency
Figure 3–6. Encoder Timing Diagram—One Cycle Latency
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Fibre Channel and IEEE 802.3z 1000BaseX
In Fibre Channel and IEEE 802.3z 1000BaseX applications the encoder does not
automatically select the correct 8-bit data for Fibre Channel EOF or 1000BaseX Idle
ordered sets. The running disparity based selection of the correct 8-bit data must be
made before passing the data to the encoder.
Decoder
Data and identified 10-bit special K codes are converted from 10 bits to 8 bits; see
Table 3–1 on page 3–3 for a list of the valid K codes, and Figure 3–1 on page 3–1 for an
illustration of the conversion process.
When special 10-bit K codes are received, the special K codes are translated to 8-bit
values, and the
codes.
When the decoder receives an invalid code, it asserts the
value to an arbitrary number.
1 The decoder flags the 10B_ERR characters as invalid codes and asserts the
When the
special IDLE character of K28.5.
kout
kerr
signal.
idle_del
signal is asserted. The decoder also checks for invalid 10-bit
kerr
signal and decodes the
signal is asserted, it deletes all 10-bit words identified as the
Chapter 3: Specifications 3–7
clk
reset_n
idle_del
ena
datain [9:0]
valid
dataout [7:0]
kout
kerr
rderr
rdin
rdforce
rdout
rdcascade
clk
datain, ena
rdforce, rdin
a b c d e f g
a b c d e
a b c d e f
n+1n n+2 n+3
dataout, kout
kerr, rdout, rderr
Functional Description
When the receiver detects a disparity error, the
rderr
signal is asserted.
Figure 3–7 shows a block diagram of the decoder.
Figure 3–7. Decoder
Cascaded Decoding
Two decoders can be cascaded to decode two words simultaneously. The decoders are
cascaded—in a similar fashion as the encoders—by connecting the
of the first decoder to the
rdout
output of the second decoder to the
rdin
input of the second decoder, and by connecting the
rdin
input of the first decoder. The
inputs of both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the
rdin
not pipelined. If these inputs are to be used in non-cascaded decoders, they should be
delayed by one clock cycle with respect to their corresponding
and
datain
rdcascade
rdforce
and
output
rdforce
inputs are
kin
inputs.
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to be decoded.
The decoded value—corresponding to the value of
rising edge
on the rising edge of clock cycle
n
—is output shortly after rising edge
n+2
. (See Figure 3–6 on page 3–6).
Figure 3–8. Decoder Timing Diagram
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
datain
n+1
sampled by the decoder on
, and is available to be sampled
3–8 Chapter 3: Specifications
Parameters
Parameters
Tab le 3– 2 shows the 8B10B Encoder/Decoder function parameters, which can only be
set in the MegaWizard Interface (see “Parameterize” on page 2–3).
Table 3–2. 8B10B Encoder/Decoder Parameters
Parameter Value
Mode of operation Encoder or Decoder
Register inputs/outputs
On for a three cycle latency.
Off for a one-cycle latency.
Signals
This section describes all interface signals.
Encoder Signals
Tab le 3– 3 show the encoder signals.
Table 3–3. Encoder Signals
Signal Name Direction Description
clk
reset_n
kin
ena
idle_ins
datain[7:0]
rdin
rdforce
kerr
dataout[9:0]
valid
rdout
rdcascade
Input
Input
Input
Input
Input
Input Data input. This is the 8-bit input word, data or command.
Input
Input
Output
Output Data output. This is the 10-bit encoded output.
Output
Output
Output Cascaded running disparity. Used when encoders are cascaded.
Clock. The input is latched, and the result is output on this clock. There is a three clock
cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the MegaCore function. This
signal should be deasserted synchronously to the rising edge of
Command byte indicator. When high, indicates that the input is a command byte, not a
data byte.
Enable encoder signal. When high, indicates that the data currently present on the
datain
input is to be encoded.
Idle character insert. When high, idle (K28.5) characters are inserted when
asserted.
Running disparity input. When
current running disparity instead of the internally generated one.
Force running disparity. When high, the
running disparity.
Special K character error. This signal is set high when
datain
value on
Valid signal. When high, indicates that a valid encoded word is present on the
dataout
Running disparity output. The current running disparity (after encoding the word
present on the
is not a valid special K character.
output.
dataout
rdforce
output).
clk
.
ena
is not
is high, the value on this pin is used as the
rdin
value overrides the internally generated
ena
and
kin
are high and the
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Chapter 3: Specifications 3–9
Signals
Decoder Signals
Tab le 3– 4 show the decoder signals.
Table 3–4. Decoder Signals
Signal Name Direction Description
clk
reset_n
idle_del
ena
datain[9:0]
rdin
rdforce
valid
Input
Input
Input
Input
Input Data input. This is the 10-bit encoded input word.
Input
Input
Output
Clock. The input is latched, and the result output on this clock. There is a one clock
cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the MegaCore function. This
signal must be deasserted synchronously to the rising edge of
Idle delete signal. When high, idle words (K28.5) are removed from the stream (i.e.
valid
is set low when idle words are received).
Enable decoder signal. When high, indicates that the data currently present on the
datain
input is to be decoded.
Running disparity input. When
current running disparity instead of the internally generated one.
Force running disparity. When high, the
running disparity.
Valid signal. This signal is asserted when
present on
codeword is received,
dataout
, even if it is the result of an illegal codeword. If an illegal
kerr
rdforce
is also asserted.
is high, the value on this pin is used as the
rdin
ena
value overrides the internally generated
is asserted and new, non-idle data is
clk
.
dataout[7:0]
kout
kerr
rderr
rdout
rdcascade
valid
is also asserted for idle characters (K28.5) when
is not asserted.
Output Data output. This is the 8-bit decoded data or command.
Output
Output
Output
Output
Output Cascaded running disparity. Used when decoders are cascaded.
Command output. When high, indicates that the output is a command byte, not a data
byte.
Special K error. Asserted high when an invalid 10-bit word is received, or when a
10B_ERR character is received.
Running disparity error. When high indicates the running disparity rules have been
violated.
Running disparity output. The current running disparity (after decoding the word
present on the
dataout
output).
ena
is asserted and
idle_del
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
3–10 Chapter 3: Specifications
Signals
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date Version Changes
October 2013 13.0 Added obsolescence notice. Refer to PDN1304.
■ Updated the f
■ Updated the encoder disparity description.
■ Updated support for Arria II GX and Stratix IV GX device family from preliminary to full.
May 2011 11.0
■ Added support for Cyclone III LS, Cyclone IV GX, Cyclone IV E, HardCopy III, and
HardCopy IV (E, GX) device family.
■ Maintenance release; updated product release information.
■ Converted the document to new frame template and made textual and style changes.
■ Updated the MegaWizard Plug-in Manager GUI.
November 2009 9.1
March 2009 9.0
■ Removed support for HardCopy Stratix device family.
■ Maintenance release.
■ Added support for Arria II GX device family.
■ Maintenance release.
November 2008 8.1 Maintenance release.
May 2008 8.0
October 2007 7.2
■ Added support for Stratix IV GX device family.
■ Maintenance release; updated product release information.
■ Corrected error in text: the decoder (not the encoder) asserts
invalid code.
■ Updated discussion of Encoder in the Specifications chapter and timing diagrams
Figure 3–5 and Figure 3–6.
May 2007 7.1
■ Added support for Arria GX device family.
■ Maintenance release; updated product release information.
value in Table 1–3.
MAX
Additional Information
kerr
upon receiving an
May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
Info–2 Additional Information
How to Contact Altera
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training
Product literature Website www.altera.com/literature
Non-technical support (General) Email nacomp@altera.com
(Software Licensing) Email authorization@altera.com
Note:
(1) You can also contact your local Altera sales office or sales representative.
Website www.altera.com/training
Email custrain@altera.com
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue Meaning
Bold Type with Initial Capital
Letters
bold type
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
italic type
Initial Capital Letters
“Subheading Title”
Courier type
r An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.
1 The hand points to information that requires special attention.
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Indicates signal, port, register, bit, block, and primitive names. For example,
tdi
, and
input
. The suffix n denotes an active-low signal. For example,
Indicates command line commands and anything that must be typed exactly as it
appears. For example,
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword
example,
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
TRI
).
c:\qdesigns\tutorial\chiptrip.gdf
SUBDESIGN
), and logic function names (for
.
data1
resetn
,
.
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
Additional Information Info–3
Typographic Conventions
Visual Cue Meaning
h A question mark directs you to a software help system with related information.
f The feet direct you to another document or website with related information.
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May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide
Info–4 Additional Information
Typographic Conventions
8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation
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