Altera 50G Interlaken MegaCore Function User Manual

50G Interlaken MegaCore Function User

Guide

Last updated for Altera Complete Design Suite: 15.0

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TOC-2

About This MegaCore Function

About This MegaCore Function......................................................................... 1-1

Getting Started With the 50G Interlaken IP Core..............................................2-1

Features......................................................................................................................................................... 1-1

IP Core Supported Combinations of Number of Lanes and Data Rate...................................1-2

IP Core Raw Aggregate Bandwidth...............................................................................................1-2

Device Family Support................................................................................................................................1-2

IP Core Verification.....................................................................................................................................1-3

Performance and Resource Utilization.....................................................................................................1-3

Device Speed Grade Support......................................................................................................................1-4

Release Information.....................................................................................................................................1-4

Installing and Licensing IP Cores..............................................................................................................2-1

OpenCore Plus IP Evaluation........................................................................................................ 2-1

Specifying the 50G Interlaken IP Core Parameters and Options .........................................................2-2

Files Generated for Arria V GZ and Stratix V Variations......................................................................2-3

Files Generated for Arria 10 Variations....................................................................................................2-4

Simulating the50G Interlaken IP Core......................................................................................................2-6

Integrating Your IP Core in Your Design................................................................................................ 2-6

Pin Assignments...............................................................................................................................2-6

Transceiver Logical Channel Numbering.....................................................................................2-7

Adding the Reconfiguration Controller..................................................................................... 2-10

Adding the External PLL.............................................................................................................. 2-12

Compiling the Full Design and Programming the FPGA....................................................................2-14

50G Interlaken IP Core Parameter Settings.......................................................3-1

Functional Description....................................................................................... 4-1

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Meta Frame Length in Words....................................................................................................................3-1

Transceiver Reference Clock Frequency...................................................................................................3-1

Number of Calendar Pages.........................................................................................................................3-2

TX Scrambler Seed.......................................................................................................................................3-2

Transfer Mode Selection.............................................................................................................................3-2

Interfaces Overview.....................................................................................................................................4-1

Application Interface.......................................................................................................................4-1

Interlaken Interface..........................................................................................................................4-1

Out-of-Band Flow Control Interface.............................................................................................4-2

Management Interface.................................................................................................................... 4-2

Transceiver Control Interfaces.......................................................................................................4-2

High Level Block Diagram..........................................................................................................................4-4

Clocking and Reset Structure for IP Core................................................................................................ 4-4

About This MegaCore Function

50G Interlaken IP Core Clock Signals...........................................................................................4-5

IP Core Reset.................................................................................................................................... 4-5

IP Core Reset Sequence with the Reconfiguration Controller.................................................. 4-7

Interleaved and Packet Modes................................................................................................................... 4-7

50G Interlaken IP Core Transmit Path.....................................................................................................4-8

50G Interlaken IP Core Transmit User Data Interface Examples.............................................4-8

50G Interlaken IP Core In-Band Calendar Bits on Transmit Side......................................... 4-12

50G Interlaken IP Core Transmit Path Blocks..........................................................................4-13

50G Interlaken IP Core Receive Path......................................................................................................4-14

50G Interlaken IP Core Receive User Data Interface Examples............................................. 4-14

50G Interlaken IP Core RX Errored Packet Handling............................................................. 4-16

In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface.........4-18

50G Interlaken IP Core Receive Path Blocks.............................................................................4-19

TOC-3

50G Interlaken MegaCore Function Signals.......................................................5-1

50G Interlaken IP Core Clock Interface Signals......................................................................................5-1

50G Interlaken IP Core Reset Interface Signals.......................................................................................5-2

50G Interlaken IP Core User Data Transfer Interface Signals.............................................................. 5-4

50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals................................... 5-8

50G Interlaken IP Core Management Interface....................................................................................5-12

Device Dependent Signals........................................................................................................................ 5-14

Transceiver Reconfiguration Controller Interface Signals.......................................................5-14

Arria 10 External PLL Interface Signals......................................................................................5-15

Arria 10 Transceiver Reconfiguration Interface Signals.......................................................... 5-15

50G Interlaken IP Core Register Map.................................................................6-1

50G Interlaken IP Core Testbench..................................................................... 7-1

50G Interlaken IP Core Testbench Interface Signals..............................................................................7-2

Testbench Simulation Behavior.................................................................................................................7-3

Running the Testbench With the Example Design.................................................................................7-3

Setting Up the Testbench Example................................................................................................7-3

Simulating the Example Design.....................................................................................................7-3

50G Interlaken IP Core Test Features................................................................ 8-1

Internal Serial Loopback Mode..................................................................................................................8-1

External Loopback Mode............................................................................................................................8-1

PRBS Generation and Validation.............................................................................................................. 8-2

Setting up PRBS Mode in Arria V and Stratix V Devices.......................................................... 8-2

Setting up PRBS Mode in Arria 10 Devices..................................................................................8-4

CRC32 Error Injection ...............................................................................................................................8-7

Advanced Parameter Settings............................................................................. 9-1

Hidden Parameters......................................................................................................................................9-1

Required User Clock Frequency....................................................................................................9-1

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TOC-4

About This MegaCore Function

Counter Reset Bits............................................................................................................................9-2

Include Temp Sense.........................................................................................................................9-2

RXFIFO Address Width..................................................................................................................9-2

SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)..........................9-2

Use ATX or CMU PLL....................................................................................................................9-4

Lane Profile.......................................................................................................................................9-4

Modifying Hidden Parameter Values.......................................................................................................9-4

Out-of-Band Flow Control in the 50G Interlaken MegaCore Function..........10-1

Out-of-Band Flow Control Block Clocks...............................................................................................10-2

TX Out-of-Band Flow Control Signals...................................................................................................10-2

RX Out-of-Band Flow Control Signals...................................................................................................10-4

Performance and Fmax Requirements for 40G Ethernet Traffic..................... A-1

Additional Information......................................................................................B-1

Document Revision History...................................................................................................................... B-1

How to Contact Altera................................................................................................................................B-3

Typographic Conventions..........................................................................................................................B-3

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FPGA/

ASIC

Interlaken

FPGA/

ASIC

Interlaken

FPGA/

ASIC

Interlaken

Up to

50 Gbps

Up to

50 Gbps

Traffic

Management

Packet

Processing

Ethernet

MAC/Framer

Switch

Fabric

To Line Interface

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About This MegaCore Function

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Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The Altera 50G Interlaken MegaCore® function implements the Interlaken Protocol Specification, Revision 1.2 . It supports eight lanes at a lane rate of 6.25 gigabits per second (Gbps), on Stratix® V, Arria® V GZ, and Arria 10 devices, providing raw bandwidth of 50 Gbps.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The 50G Interlaken MegaCore function incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Figure 1-1: Typical Interlaken Application

Related Information

Interlaken Protocol Specification, Revision 1.2

Features

The 50G Interlaken MegaCore function has the following features:

• Compliant with the Interlaken Protocol Specification, Rev 1.2.

• Supports eight serial lanes in configurations that provide up to 50 Gbps raw bandwidth.

• Supports per-lane data rate of 6.25 Gbps using Altera on-chip high-speed transceivers.

• Supports dynamically configurable BurstMax and BurstMin values.

• Supports Packet mode and Interleaved (Segmented) mode for user data transfer.

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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1-2

IP Core Supported Combinations of Number of Lanes and Data Rate

• Supports up to 256 logical channels in out-of-the-box configuration.

• Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.

• Supports optional out-of-band flow control blocks.

Related Information

Interlaken Protocol Specification, Rev 1.2

IP Core Supported Combinations of Number of Lanes and Data Rate

Table 1-1: 50G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate

The 50G Interlaken IP core supports only the following combination of number of lanes and data rate.

Number of Lanes Lane Rate (Gbps)

8 6.25

IP Core Raw Aggregate Bandwidth

The raw aggregate bandwidth of the 50G Interlaken IP core is 8 × 6.25 Gbps = 50 Gbps.

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Device Family Support

The following table lists the device support level definitions for Altera IP cores.

Table 1-2: Altera IP Core Device Support Levels

FPGA Device Families

Preliminary support — The core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final support — The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

The following table shows the level of support offered by the 50G Interlaken MegaCore function for each Altera device family.

Table 1-3: Device Family Support

Device Family Support

Stratix V (GS, GT, and GX) Final

Arria V (GZ) Final

Arria 10 Preliminary

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Device Family Support

Other device families No support

IP Core Verification

Before releasing a version of the 50G Interlaken IP core, Altera runs comprehensive regression tests in the current version of the Quartus® II software. These tests use standalone methods. These files are tested in simulation and hardware to confirm functionality. Altera tests and verifies the 50G Interlaken IP core in hardware for different platforms and environments.

Constrained random techniques generate appropriate stimulus for the functional verification of the IP core. Functional coverage metrics measure the quality of the random stimulus, and ensure that all important features are verified.

Performance and Resource Utilization

Table 1-4: 50G Interlaken MegaCore Function FPGA Resource Utilization

IP Core Verification

1-3

The table shows results obtained using the Quartus II software v13.1 and v13.1 Arria 10 edition releases for the following devices:

• Arria 10 device 10AX115S2F45I2SGES

• Arria V GZ device 5AGZE1H2F35I3

• Stratix V GX device 5SGXMA7N2F45I3 The results in this table do not include the out-of-band flow control block. The numbers of ALMs and logic registers are rounded up to the nearest 100. The numbers of ALMs, before

rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

Resource Utilization

Device

ALMs

Primary Secondary

Logic Registers

M20K Blocks

Arria 10 9900 20600 1500 17

Arria V GZ 9800 20800 1600 17

Stratix V GX 9800 20700 1700 17

Stratix V GT 9800 20700 1600 17

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Device Speed Grade Support

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• Fitter Resources Reports in the Quartus II Help Information about Quartus II resource utilization reporting for 28-nm devices, including ALMs needed.

• Quartus II Handbook, Volume 1: Design and Synthesis Includes information about how to apply the Speed setting.

Device Speed Grade Support

Table 1-5: Minimum Recommended Device Family Speed Grades

For each device family the 50G Interlaken IP core supports, Altera recommends that you configure the 50G Interlaken IP core only in the device speed grades listed in the table, and any faster (lower numbered) device speed grades that are available. Altera does not support configuration of this IP core in slower speed grades.

Device Family

Minimum Supported Speed Grade

Arria 10 I2, E2

Arria V GZ I3, C3

Stratix V GX I3, C3

Stratix V GT I3, C3

Stratix V GS I3, C3

Release Information

Table 1-6: 50G Interlaken MegaCore Function Release Information

Item Value

Version 15.0

Release Date May 2015

Ordering Code IP–ILKN/50G

Vendor ID 6AF7

Product ID 010D

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Release Information

1-5

Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function, if this MegaCore function was included in the previous release. Any exceptions to this verification are reported in the Altera IP Core Release Notes. Altera does not verify compilation with MegaCore function versions older than the previous release.

Related Information

Altera IP Core Release Notes

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Getting Started With the 50G Interlaken IP Core

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The following sections explain how to install, parameterize, simulate, and initialize the 50G Interlaken IP core.

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera® IP core in simulation and compilation in the Quartus II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

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Specifying the 50G Interlaken IP Core Parameters and Options

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware. OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

out.

Specifying the 50G Interlaken IP Core Parameters and Options

The parameter editor GUI allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus II software.

The 50G Interlaken IP core is not supported in Qsys. You must use the IP Catalog accessible from the Quartus II Tools menu.

The 50G Interlaken IP core does not support VHDL simulation models. Altera recommends that you specify the Verilog HDL for both synthesis and simulation models.

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1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

Note:

For Arria V GZ and Stratix V variations, you are prompted to specify an IP variation file type. To generate the demonstration testbench and example design, you must select the Verilog HDL and specify the Verilog file extension (.v).

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to 50G Interlaken IP Core Parameter Settings for information about specific IP core parameters.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. For Arria 10 variations, follow these steps: a. Click Generate HDL. The Generation dialog box appears.

b. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

Note:

To generate the demonstration testbench and example design, you must specify Verilog HDL for both synthesis and simulation models.

c. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically.

If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files

in Project to add the file.

5. For Arria V GZ and Stratix V variations, follow these steps:

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

3. If example design is generated

<your_ip>_sim

ilk_core_50g.sv - IPFS model

<simulator_vendor>

<your_ip>.qip - Quartus II IP integration file

<your_ip>.sip - Lists files for simulation

<your_ip>.v, .sv. or .vhd - Top-level IP synthesis file

ilk_core_50g

<your_ip>.cmp - VHDL component declaration file

<your_ip>.bsf - Block symbol schematic file

<your_ip> - IP core synthesis files

ilk_core_50g.sv - HDL synthesis file

ilk_50g_top.sdc - Timing constraints file

<your_ip>.ppf - XML I/O pin information file <your_ip>.spd - Combines individual simulation scripts

<your_ip>_sim.f - Refers to simulation models and scripts

testbench

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Files Generated for Arria V GZ and Stratix V Variations

a. Click Finish. The Generation dialog box appears. b. Click Exit. The parameter editor adds the top-level .qsys file to the current project automatically. If

you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

6. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

If you specify the Verilog HDL for your IP core files, the Quartus II software creates the demonstration testbench and example design when it generates the IP core.

Related Information

50G Interlaken IP Core Parameter Settings on page 3-1

Details about the parameters available in the 50G Interlaken parameter editor.

Files Generated for Arria V GZ and Stratix V Variations

The Quartus II software generates multiple files during generation of your 50G Interlaken IP core Arria V GZ or Stratix V variation.

Figure 2-2: IP Core Generated Files

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Files Generated for Arria 10 Variations

If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench and example design files are located in <your_ip>_sim/ilk_core_50g/testbench.

Files Generated for Arria 10 Variations

The Quartus II software generates multiple files during generation of your 50G Interlaken IP core Arria 10 variation.

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<your_ip >.cmp - VHDL component declaration file

<your_ip >.ppf - XML I/O pin information file <your_ip >.qip - Lists IP synthesis files <your_ip >.sip - Lists files for simulation

<your_ip >.v or .vhd Top-level IP synthesis file

<your_ip >.v or .vhd Top-level simulation file

<simulator_setup_scripts >

<your_ip >.qsys - System or IP integration file

<your_ip >_bb.v - Verilog HDL black box EDA synthesis file <your_ip >_inst.v or .vhd - Sample instantiation template

<your_ip >_generation.rpt - IP generation report <your_ip >.debuginfo - Contains post-generation information

<your_ip >.html - Connection and memor y map data <your_ip >.bsf - Block symbol schematic <your_ip >.spd - Combines individual simulation scripts

<your_ip >.sopcinfo - Software tool-chain integration file

<your_ip>

IP variation files

sim

Simulation files

synth

IP synthesis files

Simulator scripts

ilk_core_50g_<version>

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench

Testbench files

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Figure 2-3: IP Core Generated Files

Files Generated for Arria 10 Variations

2-5

If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench and example design files are located in <your_ip>/ilk_core_50g_<version>/sim/testbench.

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Simulating the50G Interlaken IP Core

You can simulate your 50G Interlaken MegaCore function variation using any of the vendor-specific IEEE encrypted functional simulation models which are generated in the new <instance name>_sim subdirec‐ tory of your project directory.

The 50G Interlaken MegaCore function supports the Synopsys VCS, Cadence NC Sim, and Mentor Graphics Modelsim-SE simulators.

The 50G Interlaken IP core generates only a Verilog HDL simulation model and testbench. The IP core parameter editor appears to offer you the option of generating a VHDL simulation model, but this IP core does not support a VHDL simulation model or testbench.

For more information about functional simulation models for Altera IP cores, refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.

If you specify the models are in Verilog HDL when you parameterize your IP core variation, the Quartus II software generates a testbench which demonstrates the resetting, clocking, and toggling of the 50G Interlaken IP core user interfaces.

Related Information

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• 50G Interlaken IP Core Testbench on page 7-1 When you generate the IP core, the Quartus II software generates a testbench.

• Simulating Altera Designs

Integrating Your IP Core in Your Design

After you generate your 50G Interlaken IP core variation, you can instantiate it in the RTL for your design. When you integrate your IP core instance in your design, you must pay attention to the following items.

Pin Assignments

When you integrate your 50G Interlaken MegaCore function instance in your design, you must make appropriate pin assignments. You do not need to specify pin assignments for simulation. However, you should make the pin assignments before you compile, to provide direction to the Quartus II Fitter and to specify the signals that should be assigned to device pins.

You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware. Do not create virtual pins for clock or Interlaken link data signals.

For the Arria 10 device family, you must configure a PLL external to the 50G Interlaken IP core. The required number of PLLs depends on the distribution of your Interlaken lane data pins in the different A10 transceiver blocks.

Related Information

Quartus II Help

For information about the Quartus II software, including virtual pins.

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Transceiver Logical Channel Numbering

In Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channel numbering starts at the bottom of the die with logical channel 0 and continues in physical pin order through the four ordered transceiver blocks on the same side of the device. Each data channel and TX PLL has its own dedicated reconfiguration interface with an assigned logical channel.

In Arria 10 devices, you control the mapping of Interlaken lanes directly in the Arria 10 Native PHY IP core that is included in the 50G Interlaken IP core.

In Arria V and Stratix V devices, you can control the logical channel assignments in the IP core. You typically assign lanes to match the logical channel numbering. However, the default Interlaken lane assignment does not assign a lane to Channel 1 or Channel 4 in a transceiver block, leaving either available for the CMU PLL. You can use the information in the following table to map the lanes to their default logical channel numbering. The logical channel numbering always starts at the bottom of a transceiver block.

Table 2-1: Transceiver Logical Channel Numbering

The default expected mapping of logical channels to Interlaken lanes in Arria V and Stratix V devices.

2-7

Transceiver Block Number Logical Channel Number in

Device

27 TX PLL 3

Direction Interlaken Lane Number in

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Transceiver Logical Channel Numbering

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Transceiver Block Number Logical Channel Number in

Device

20 TX PLL 2

Direction Interlaken Lane Number in

IP Core

13 TX PLL 1

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Transceiver Logical Channel Numbering

2-9

Transceiver Block Number Logical Channel Number in

Device

Direction Interlaken Lane Number in

IP Core

(Left available for CMU PLL)

6 TX PLL 0

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Adding the Reconfiguration Controller

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Transceiver Block Number Logical Channel Number in

Device

Direction Interlaken Lane Number in

IP Core

(Left available for CMU PLL)

For example, in an Arria V or Stratix V device, to change the VOD setting for lane 7, you write logical channel 12 to the Reconfiguration Controller.

Related Information

• Lane Profile on page 9-4 Describes how to modify the logical channel mapping. Use this option with caution.

• Altera Transceiver PHY IP User Guide Background information to better understand logical channel numbering.

Adding the Reconfiguration Controller

50G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi‐ guration controller to function correctly in hardware. 50G Interlaken IP core variations that target an Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration controller.

Keeping the Reconfiguration Controller external to the IP core in Arria V and Stratix V devices provides the flexibility to share the Reconfiguration Controller among multiple IP cores and to accommodate FPGA transceiver layouts based on the usage model of your application. In Arria 10 devices, you can configure individual transceiver channels flexibly through an Avalon-MM Arria 10 transceiver reconfigu‐ ration interface.

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The following simple instructions show you how to instantiate an Altera Transceiver Reconfiguration Controller and how to connect the design blocks:

Generating the Reconfiguration Controller

You can use the IP Catalog to generate an Altera Transceiver Reconfiguration Controller. In the Transceiver Reconfiguration Controller parameter editor, you select the features of the transceiver

that can be dynamically reconfigured. However, you must ensure that the following two features are turned on:

1. Enable PLL calibration

2. Enable Analog controls

You must also set the value of the Number of reconfiguration interfaces parameter. Each TX PLL requires its own reconfiguration interface, whether or not you intend to reconfigure it. The following formula determines the correct number of reconfiguration interfaces:

NUMBER_OF_RECONFIGURATION_INTERFACES = NUMBER_OF_LANES + NUMBER_OF_TX_PLLs

where

• NUMBER_OF_LANES is the total number of physical lanes used in your implemented design.

• NUMBER_OF_TX_PLLs is the total number of transceiver blocks (number of TX PLLs) used in your design.

Generating the Reconfiguration Controller

2-11

For example, for a design that includes an Interlaken variation that is configured in two transceiver blocks, you must set Number of reconfiguration interfaces to the value of 10.

Connecting the Reconfiguration Controller to the IP Core

The Reconfiguration Controller communicates with the 50G Interlaken IP core on two busses:

• reconfig_to_xcvr (output)

• reconfig_from_xcvr (input)

Each of these busses connects to the bus of the same name in the 50G Interlaken IP core. You must also connect the following signals:

• mgmt_clk_clk: Reconfiguration Controller clock (input)

• mgmt_rst_reset: Reconfiguration Controller reset (input)

• reconfig_busy: Reconfiguration Controller busy indication (output)

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50G Interlaken

MegaCore

Function

Reconfiguration

Controller

mgmt_clk_clk

mgmt_rst_reset

Avalon-MM IF

reconfig_to_xcvr

reconfig_from_xcvr

reset_n

reconfig_busy

2-12

Adding the External PLL

Figure 2-4: Typical Connection of Reconfiguration Controller to 50G Interlaken IP Core

Altera recommends that you set the Reconfiguration Controller input clock frequency in the range of 100 MHz to 125 MHz. Refer to the Altera Transceiver PHY IP Core User Guide for frequency range require‐ ments specific to the device family.

The Reconfiguration Controller reset input should be asserted high during power up and remain asserted until its clock input becomes stable with the mgmt_clk_locked signal indicating a locked condition of the clock. Upon power up, the Reconfiguration Controller asserts reconfig_busy output high. The

reconfig_busy signal remains asserted until the Reconfiguration Controller completes the configuration

of all transceivers.

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Related Information

• Altera Transceiver PHY IP Core User Guide

Adding the External PLL

50G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 50G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs.

You can use the IP Catalog to generate an external PLL IP core that configures a TX PLL on the device.

• Select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, or Arria 10 FPLL.

• In the parameter editor, set the following parameter values:

• PLL output frequency to one half the per-lane data rate of the IP core variation. The transceiver

performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the Interlaken lanes.

• PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference

clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter.

The number of external PLLs you must define depends on the distribution of your Interlaken TX serial lines across physical transceiver channels. You specify the clock network to which each PLL output connects by setting the clock network in the PLL parameter editor.

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ATX PLL

pll_powerdown

50G Interlaken IP Core

Txvr Block N

Txvr Block N+1

tx_pll_locked

tx_pll_powerdown

tx_serial_clk[11] (Channel 5) (Lane 11) tx_serial_clk[10] (Channel 4) (Lane 10)

tx_serial_clk[9] (Channel 3) (Lane 9) tx_serial_clk[8] (Channel 2) (Lane 8) tx_serial_clk[7] (Channel 1) (Lane 7) tx_serial_clk[6] (Channel 0) (Lane 6)

tx_serial_clk[5] (Channel 5) (Lane 5) tx_serial_clk[4] (Channel 4) (Lane 4) tx_serial_clk[3] (Channel 3) (Lane 3) tx_serial_clk[2] (Channel 2) (Lane 2) tx_serial_clk[1] (Channel 1) (Lane 1) tx_serial_clk[0] (Channel 0) (Lane 0)

pll_locked

pll_cal_busy

tx_serial_clk

(8 Lanes)

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Adding the External PLL

You must connect the external PLL signals and the Arria 10 50G Interlaken IP core transceiver Tx PLL interface signals according to the following rules:

• Connect the tx_serial_clk input pin for each Interlaken lane to the output port of the same name in the corresponding external PLL.

• Connect the tx_pll_locked input pin of the 50G Interlaken IP core to the logical AND of the

pll_locked output signals of the external PLLs for all of the Interlaken lanes and the inverse of each of

the pll_cal_busy signals from the external PLLs.

• Connect the tx_pll_powerdown output pin of the 50G Interlaken IP core to the pll_powerdown reset pin of the external PLLs for all of the Interlaken lanes.

User logic must provide the AND function and connections. The following figure provides an example of one correct method, among many, to implement connection logic. You can also refer to the example design for example working user logic including one correct method to instantiate and connect an external PLL.

Figure 2-5: Example Connection of ATX PLL with 50G Interlaken IP Core Using Arria 10 xN Clock Network

2-13

Related Information

• Arria 10 External PLL Interface on page 4-3

• 50G Interlaken IP Core Testbench on page 7-1

Getting Started With the 50G Interlaken IP Core

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Compiling the Full Design and Programming the FPGA

• Pin Assignments on page 2-6

• Arria 10 External PLL Interface Signals on page 5-15

• Arria 10 Transceiver PHY User Guide Information about the correspondence between PLLs and transceiver channels, and information about how to configure an external PLL for your own design. You specify the clock network to which the PLL output connects by setting the clock network in the PLL parameter editor.

Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Quartus II software to compile your design. After successfully compiling your design, program the targeted Altera device with the Programmer and verify the design in hardware.

Related Information

• Quartus II Incremental Compilation for Hierarchical and Team-Based Design Information about compiling your design. Chapter in volume 1 of the Quartus II Handbook.

• Quartus II Programmer Information about programming the device. Chapter in volume 3 of the Quartus II Handbook.

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50G Interlaken IP Core Parameter Settings

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You customize the 50G Interlaken IP core by specifying parameters in the 50G Interlaken parameter editor, which you access from the Quartus II IP Catalog.

This chapter describes the parameters and how they affect the behavior of the IP core. To customize your 50G Interlaken IP core, you can modify parameters to specify the following properties:

Meta Frame Length in Words on page 3-1 Transceiver Reference Clock Frequency on page 3-1 Number of Calendar Pages on page 3-2 TX Scrambler Seed on page 3-2 Transfer Mode Selection on page 3-2

Meta Frame Length in Words

The Meta frame length in words parameter specifies the length of the meta frame, in 64-bit (8-byte) words. In the Interlaken specification, this parameter is called the MetaFrameLength parameter.

Smaller values for this parameter shorten the time to achieve lock. Larger values reduce overhead while transferring data, after lock is achieved.

For simulation, you can set the Meta frame length in words parameter to the value of 128 for fast lane locking. For hardware testing, Altera recommends that you set the Meta frame length in words parameter to the value of 2048.

The default value of the Meta frame length in words parameter is 2048.

Transceiver Reference Clock Frequency

The Transceiver reference clock frequency parameter specifies the expected frequency of the

pll_ref_clk input clock.

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.

The 50G Interlaken IP core supports the following pll_ref_clk frequencies: 156.25 MHz, 195.3125 MHz, 250 MHz, 312.5 MHz, 390.625 MHz, 500 MHz, and 625 MHz.

The default value of the Transceiver reference clock frequency parameter is 312.5 MHz.

ISO 9001:2008 Registered

3-2

Number of Calendar Pages

Related Information

• 50G Interlaken IP Core Clock Signals on page 4-5

• 50G Interlaken IP Core Clock Interface Signals on page 5-1

Number of Calendar Pages

The Number of calendar pages parameter specifies the number of 16-bit pages of in-band flow control data that your 50G Interlaken MegaCore function supports. The supported values are 1, 2, 4, 8, and 16.

Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpre‐ tation of the in-band flow control bits. The IP core supports a maximum of 256 channels with in-band flow control.

If your design requires a different number of pages, select the lowest supported number of pages which is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, you can set Number of Calendar pages to 4 and use pages 3, 2, and 1 while ignoring page 0.

The default value of the Number of calendar pages parameter is 1.

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TX Scrambler Seed

The TX scrambler seed parameter specifies the initial scrambler state. If a single 50G Interlaken IP Core is configured on your device, you can use the default value of this

parameter. If multiple 50G Interlaken IP Cores are configured on your device, you must use a different initial

scrambler state for each IP core to reduce crosstalk. Try to select random values for each 50G Interlaken IP core, such that they have an approximately even mix of ones and zeros and differ from the other scramblers in multiple spread out bit positions.

The default value of this parameter is 58’hdeadbeef123.

Transfer Mode Selection

The Transfer mode selection parameter specifies whether the 50G Interlaken transmitter expects incoming traffic to the TX user data transfer interface to be interleaved or packet based. The supported values are Interleaved and Packet. Interleaved mode is also called Segmented mode. The value of this parameter cannot be modified dynamically; it is determined when you generate the IP core.

If the value of this parameter is Packet, the 50G Interlaken transmitter expects incoming traffic to the TX user data transfer interface to be packet based. This setting enables the internal enhanced scheduler and causes the IP core to send data on the Interlaken link based on the programmed BurstMax and BurstMin parameter settings.

If the value of this parameter is Interleaved, the 50G Interlaken transmitter expects you to provide scheduling information on the Start of Burst and End of Burst signals. In Interleaved mode, you can send either packet-based traffic or interleaved traffic, but you must provide the correct SOB and EOB signals even when sending non-interleaved packets.

If packets are always sent contiguously in your application, Altera recommends that you set this parameter to the value of Packet. This setting enables simpler transfers on the user data transfer interface,

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Transfer Mode Selection

and enables the 50G Interlaken IP core to perform enhanced scheduling based on the BurstMax and

BurstMin settings. If the data bursts that arrive on the TX application interface might be interleaved

between channels, then you must set Transfer mode selection to the value of Interleaved. The default value of the Transfer mode selection parameter is Interleaved.

Related Information

Interleaved and Packet Modes on page 4-7

3-3

50G Interlaken IP Core Parameter Settings

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Functional Description

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The 50G Interlaken MegaCore function provides the functionality described in the Interlaken Protocol Specification, Revision 1.2.

Related Information

Interlaken Protocol Specification, Revision 1.2

Interfaces Overview

The Altera 50G Interlaken MegaCore function supports the following interfaces:

Application Interface on page 4-1 Interlaken Interface on page 4-1 Out-of-Band Flow Control Interface on page 4-2 Management Interface on page 4-2 Transceiver Control Interfaces on page 4-2

Application Interface

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The application interface, also called the user data transfer interface, provides up to 256 channels of communication to and from the Interlaken link.

Related Information

• High Level Block Diagram on page 4-4

The figure lists the major application interface signals.

• 50G Interlaken IP Core User Data Transfer Interface Signals on page 5-4

Comprehensive list of application interface signals and information about required signal behavior.

Interlaken Interface

The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.2. It provides a high-speed transceiver interface to an Interlaken link.

ISO 9001:2008 Registered

4-2

Out‑of‑Band Flow Control Interface

The 50G Interlaken MegaCore function value for the Interlaken BurstMax parameter is determined by the value you specify on the burst_max_in input signal. The 50G Interlaken MegaCore function supports two values for BurstMax, 128 bytes and 256 bytes.

Note: You should only modify the value of the burst_max_in signal when no traffic is present. You can configure your 50G Interlaken MegaCore function to use 1, 2, 4, 8, or 16 pages of 16 calendar

bits. The application determines the use of the in-band flow control bits that the MegaCore function receives on the incoming Interlaken link, and the application is responsible for specifying the values of the in-band flow control bits the MegaCore function transmits on the outgoing Interlaken link.

Related Information

• 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals on page 5-8

Information about setting the BurstMax and BurstShort values, including the encoding of your desired value on the burst_max_in or burst_short_in input signal.

• 50G Interlaken IP Core User Data Transfer Interface Signals on page 5-4

Information about the in-band flow control signals.

• Interlaken Protocol Specification, Revision 1.2

Available from the Interlaken Alliance web site at www.interlakenalliance.com.

Out‑of‑Band Flow Control Interface

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The optional out-of-band flow control interface conforms to the out-of-band requirements in Section

5.3.4.2, Out-of-Band Flow Control, of the Interlaken Protocol Specification, Revision 1.2.

Related Information

• Out-of-Band Flow Control in the 50G Interlaken MegaCore Function on page 10-1

• Interlaken Protocol Specification, Revision 1.2

Available from the Interlaken Alliance web site at www.interlakenalliance.com.

Management Interface

The management interface provides access to the 50G Interlaken IP core internal status and control registers. This interface does not provide access to the hard PCS registers on the device.

The management interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.

Related Information

Avalon Interface Specifications

Transceiver Control Interfaces

The 50G Interlaken IP core provides several interfaces to control the transceiver. The transceiver control interfaces in your 50G Interlaken IP core variation depend on the device family the variation targets.

The 50G Interlaken IP core supports the following transceiver control interfaces:

Transceiver Reconfiguration Controller Interface on page 4-3 Arria 10 External PLL Interface on page 4-3

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Functional Description

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Arria 10 Transceiver Reconfiguration Interface on page 4-3

Transceiver Reconfiguration Controller Interface

Related Information

• Altera Transceiver PHY IP Core User Guide

Describes the Altera Transceiver Reconfiguration Controller and the signals that connect to the 50G Interlaken IP core transceiver reconfiguration controller interface.

Arria 10 External PLL Interface

Related Information

Transceiver Reconfiguration Controller Interface

4-3

• Adding the External PLL on page 2-12

Describes how to generate an external TX PLL, including parameter requirements.

• Arria 10 External PLL Interface Signals on page 5-15

• Arria 10 Transceiver PHY User Guide

Information about the Arria 10 transceiver PLLs and clock network.

Arria 10 Transceiver Reconfiguration Interface

The Arria 10 transceiver reconfiguration interface provides access to the registers in the embedded Arria 10 Native PHY IP core. This interface provides direct access to the hard PCS registers on the device.

This interface is available only in variations that target an Arria 10 device. In variations that target an Arria V device or a Stratix V device, user logic reconfigures the transceivers through the transceiver reconfiguration controller, an external block that you must instantiate in your design outside the 50G Interlaken IP core.

The Arria 10 transceiver reconfiguration interface complies with the Avalon Memory-Mapped (AvalonMM) specification defined in the Avalon Interface Specifications.

Related Information

Avalon Interface Specifications

Defines the Avalon Memory-Mapped (Avalon-MM) specification.

Arria 10 Transceiver PHY User Guide

Information about the Arria 10 transceiver reconfiguration interface.

Arria 10 Transceiver Registers

Information about the Arria 10 transceiver registers.

Functional Description

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+ 65 hidden pages

Altera 50G Interlaken MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About This MegaCore Function

Features

IP Core Supported Combinations of Number of Lanes and Data Rate

IP Core Raw Aggregate Bandwidth

Device Family Support

IP Core Verification

Performance and Resource Utilization

Device Speed Grade Support

Release Information

Getting Started With the 50G Interlaken IP Core

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Specifying the 50G Interlaken IP Core Parameters and Options

Files Generated for Arria V GZ and Stratix V Variations

Files Generated for Arria 10 Variations

Simulating the50G Interlaken IP Core

Integrating Your IP Core in Your Design

Pin Assignments

Transceiver Logical Channel Numbering

Adding the Reconfiguration Controller

Generating the Reconfiguration Controller

Connecting the Reconfiguration Controller to the IP Core

Adding the External PLL

Compiling the Full Design and Programming the FPGA

50G Interlaken IP Core Parameter Settings

Meta Frame Length in Words

Transceiver Reference Clock Frequency

Number of Calendar Pages

TX Scrambler Seed

Transfer Mode Selection

Functional Description

Interfaces Overview

Application Interface

Interlaken Interface

Out‑of‑Band Flow Control Interface

Management Interface

Transceiver Control Interfaces

Transceiver Reconfiguration Controller Interface

Arria 10 External PLL Interface

Arria 10 Transceiver Reconfiguration Interface