Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
40- and 100-Gbps Ethernet MAC and PHY
MegaCore Function User Guide
Last updated for Altera Complete Design Suite: 14.1
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TOC-2
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Contents
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function.....1-1
Getting Started.................................................................................................... 2-1
40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features...........................................1-3
40-100GbE IP Core Device Family and Speed Grade Support..............................................................1-4
Device Family Support....................................................................................................................1-4
40-100GbE IP Core Device Speed Grade Support...................................................................... 1-5
IP Core Verification.....................................................................................................................................1-6
Simulation Environment................................................................................................................ 1-7
Hardware Testing.............................................................................................................................1-7
Performance and Resource Utilization.....................................................................................................1-7
Resource Utilization for 40GbE IP Cores.....................................................................................1-7
Resource Utilization for 100GbE IP Cores.................................................................................1-12
Release Information...................................................................................................................................1-18
Installing and Licensing IP Cores..............................................................................................................2-2
OpenCore Plus IP Evaluation........................................................................................................ 2-2
Specifying the 40-100GbE IP Core Parameters and Options................................................................ 2-3
IP Core Parameters......................................................................................................................................2-3
Files Generated for the 40-100GbE IP Core...........................................................................................2-10
Simulating the IP Core..............................................................................................................................2-10
Integrating Your IP Core in Your Design..............................................................................................2-11
Pin Assignments.............................................................................................................................2-11
External Transceiver Reconfiguration Controller.....................................................................2-11
Placement Settings for the 40-100GbE IP Core.........................................................................2-14
40-100GbE IP Core Testbenches.............................................................................................................2-14
Testbenches with Adapters...........................................................................................................2-15
Testbenches without Adapters.....................................................................................................2-18
Understanding the Testbench Behavior.....................................................................................2-19
Simulating the 40-100GbE IP Core With the Testbenches..................................................................2-20
Generating the 40-100GbE Testbench........................................................................................2-21
Simulating with the Modelsim Simulator...................................................................................2-21
Simulating with the NCSim Simulator....................................................................................... 2-21
Simulating with the VCS Simulator............................................................................................ 2-21
Testbench Output Example: 40GbE IP Core with Adapters................................................... 2-21
Testbench Output Example: 100GbE IP Core with Adapters.................................................2-23
Compiling the Full Design and Programming the FPGA....................................................................2-24
Initializing the IP Core..............................................................................................................................2-24
Functional Description....................................................................................... 3-1
Altera Corporation
High Level System Overview......................................................................................................................3-2
40-100GbE MAC and PHY Functional Description.............................................................................. 3-2
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
40-100GbE IP Core TX Datapath..................................................................................................3-3
40-100GbE IP Core TX Data Bus Interfaces................................................................................3-6
40-100GbE IP Core RX Datapath................................................................................................3-20
40-100GbE IP Core RX Data Bus Interfaces..............................................................................3-25
40GbE Lower Rate 24.24 Gbps MAC and PHY.........................................................................3-32
100GbE CAUI–4 PHY.................................................................................................................. 3-32
External Reconfiguration Controller.......................................................................................... 3-32
Congestion and Flow Control Using Pause Frames................................................................. 3-33
Pause Control and Generation Interface....................................................................................3-35
Pause Control Frame and Non-Pause Control Frame Filtering and Forwarding................3-36
40-100GbE IP Core Modes of Operation ..................................................................................3-37
Link Fault Signaling Interface......................................................................................................3-37
Statistics Counters Interface.........................................................................................................3-39
MAC – PHY XLGMII or CGMII Interface................................................................................3-42
Lane to Lane Deskew Interface.................................................................................................... 3-43
PCS Test Pattern Generation and Test Pattern Check.............................................................3-44
Transceiver PHY Serial Data Interface.......................................................................................3-45
40GBASE-KR4 IP Core Variations............................................................................................. 3-46
Control and Status Interface.........................................................................................................3-51
Clocks.............................................................................................................................................. 3-51
Resets............................................................................................................................................... 3-54
Signals..........................................................................................................................................................3-55
Signals of MAC and PHY Variations Without Adapters.........................................................3-55
Signals of MAC and PHY Variations With Adapters...............................................................3-66
Signals of 40-100GbE MAC-Only IP Core Variations............................................................. 3-68
Signals of 40-100GbE PHY-Only IP Core Variations...............................................................3-72
Software Interface: Registers.................................................................................................................... 3-76
40-100GbE IP Core Registers.......................................................................................................3-79
40-100GbE Example Design Registers......................................................................................3-116
Ethernet Glossary.....................................................................................................................................3-119
TOC-3
Debugging the 40GbE and 100GbE Link............................................................4-1
40-100GbE IP Core Example Design................................................................. A-1
Address Map Changes for the 40-100GbE IP Core v12.0 Release..................... B-1
10GBASE-KR Registers......................................................................................C-1
10GBASE-KR PHY Register Definitions.................................................................................................C-1
Additional Information..................................................................................... D-1
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History
..................................................................................................................................................................D-1
How to Contact Altera...............................................................................................................................D-9
Typographic Conventions.........................................................................................................................D-9
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PHY MegaCore Function
2014.12.15
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The Altera® 40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY
MegaCore® functions implement the IEEE 802.3ba 40G and 100G Ethernet Standard with an option to
support the IEEE 802.3ap-2007 Backplane Ethernet Standard. This product is included in the Altera
MegaCore IP Library and available from the Quartus II IP Catalog.
This product provides support for Stratix IV, Arria V GZ, and Stratix V devices. For Arria 10 40- and 100Gbps Ethernet support, please refer to the Low Latency 40- and 100-Gbps Ethernet MAC and PHY
MegaCore Function User Guide.
Note: The full product name, 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, is
shortened to 40-100GbE IP core in this document. In addition, although multiple variations are
available from the parameter editor, this document refers to this product as a single IP core,
because all variations are configurable from the same parameter editor.
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2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
40- or 100-Gbps Ethernet MAC and PHY MegaCore Function
TX
FIFO
TX
MAC
RX
MAC
40- or 100-GbE MAC
PMA
PMAPCS
PHY
TX
Adapter
PCS
XLGMII w/data_valid signal
or CGMII w/data_valid signal
4 x 40 bits or
10 x 40 bits
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps
CAUI-4: 4 x 25.78125 Gbps
Custom Streaming
Avalon-ST
Avalon-ST
Control and
Status Interface
Avalon-MM
Avalon-MM
RX
Adapter
Custom Streaming
Reconfiguration
Controller
1-2
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Figure 1-1: 40GbE and 100GbE MAC and PHY MegaCore Function
Main block, internal connections, and external block requirements.
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As illustrated, on the MAC client side you can choose a wide, standard Avalon® Streaming (Avalon-ST)
interface, or a narrower, custom streaming interface. Depending on the variant you choose, the MAC
client side Avalon Streaming (Avalon-ST) interface is either 256 or 512 bits of data mapped to either four
or ten 10.3125 Gbps transceiver PHY links, depending on data rate, or to four 25.78125 Gbps transceiver
PHY links.
The 40GbE (XLAUI) interface has 4x10.3125 Gbps links. The 100GbE (CAUI) interface has 10x10.3125
Gbps links. Several additional options are available. For Arria V GZ, Stratix IV, and Stratix V devices, you
can configure a lower-rate 40GbE option with 4x6.25 Gbps links. For Stratix V devices only, you can
configure a 40GbE 40GBASE-KR4 variation to support Backplane Ethernet. For Stratix V GT devices
only, you can configure a 100GbE CAUI-4 option, with 4x25.78125 Gbps links.
The FPGA serial transceivers are compliant with the IEEE 802.3ba standard XLAUI, CAUI, and CAUI-4
specifications. The IP core configures the transceivers to implement the relevant specification for your IP
core variation. You can connect the transceiver interfaces directly to an external physical medium
dependent (PMD) optical module or to another device.
You can configure and generate most configurations of the 40-100GbE IP core in transmit (TX) only,
receive (RX) only, or duplex mode. The 100GbE CAUI-4 option and the 40GBASE-KR4 options are
available in duplex mode only.
The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of
configuration and status registers. You can exclude the statistics registers. If you exclude these registers,
you can monitor the statistics counter increment vectors that the IP core provides at the client side
interface and maintain your own counters.
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40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
The 40- and 100-Gbps Ethernet MAC and PHY IP core offers the following features:
• Parameterizable through the IP Catalog available with the Quartus II software.
• Compliant with the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website
(www.ieee.org).
• Soft PCS logic that interfaces seamlessly to Altera 10.3125 Gbps and 25.78125 Gbps serial transceivers.
• Standard XLAUI or CAUI external interface consisting of serial transceiver lanes operating at 10.3125
Gbps, or the CAUI-4 external interface consisting of four serial transceiver lanes operating at
25.78125 Gbps.
• Supports 40GBASE-R4, 100GBASE-R4, and 100GBASE-R10 PHY based on 64B/66B encoding with
data striping and alignment markers to align data from multiple lanes.
• Supports 40GBASE-KR4 PHY and FEC option for interfacing to backplanes
• Supports Synchronous Ethernet (Sync-E)
• Provides CDR recovered clock output signal to the device fabric.
• Optionally accepts two separate input reference clocks for the transmit and receive transceiver
paths.
• Supports a lower–rate 40GbE option at 24.24 Gbps (4 x 6.25 Gbps line rate).
• Ethernet MAC supports the 40GbE or 100GbE line rate with a flexible and configurable feature set.
• Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status
registers.
• Avalon-ST data path interface connects to client logic with the start of frame in the most significant
byte (MSB) when optional adapters are used. Interface has data width 256 or 512 bits depending on the
data rate.
• Optional custom streaming data path interface with narrower bus width and a start frame possible on
64-bit word boundaries without the optional adapters. Interface has data width 128 or 320 bits
depending on the data rate.
• MAC, PHY, or MAC and PHY options configurable at IP generation.
• TX only configuration options, RX only configuration options, and duplex configuration options; the
100GbE CAUI-4 option is available only in duplex mode.
• TX and RX CRC pass-through control.
• RX and TX preamble pass-through option for applications that require proprietary user management
information transfer.
• TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the 40-100GbE
Ethernet connection.
• Hardware and software reset control.
• TX MAC source address insertion control.
• One MAC address register for configurable RX destination address filtering.
• RX MAC padding removal control.
• Pause frame filtering control.
• Soft error detection on all internal RAMs for high reliability systems.
• RX FIFO in MAC provides cut-through or store-and-forward frame processing.
• Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
1-3
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40-100GbE IP Core Device Family and Speed Grade Support
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• Programmable IPG fine adjustment for Ethernet repeater/bump-in-the-wire applications and traffic
shaping.
• Ethernet flow control using the pause registers or pause interface.
• Programmable maximum receive frame length up to 9600 bytes (jumbo frame) in store-and-forward
mode; there is no frame size limitation for cut-through mode.
• Promiscuous (transparent) and non-promiscuous (filtered) operation modes or received frame address
filtering.
• Configurable received frame filtering with cyclic redundancy check (CRC), runt, or oversized frame
error.
• Optional statistics counters.
• Additional testbench logic to demonstrate Ethernet IP core behavior and customize the interface.
• Statistics real-time output status signals vector.
• Fault signaling: detects and reports local fault and generates remote fault.
The 40-100GbE IP core can support full wire line speed with a 64-byte frame length and back-to-back or
mixed length traffic, up to a programmable frame size greater than 9600 bytes, with no dropped packets.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet
Standard.
Related Information
IEEE website
The IEEE 802.3ba-2010 High Speed Ethernet Standard is available on the IEEE website.
40-100GbE IP Core Device Family and Speed Grade Support
The following sections list the device family and device speed grade support offered by the 40-100GbE IP
core:
Device Family Support on page 1-4
40-100GbE IP Core Device Speed Grade Support on page 1-5
Device Family Support
Table 1-1: Altera IP Core Device Support Levels
Device Support Level Definition
Preliminary The IP core is verified with preliminary timing
models for this device family. The IP core meets all
functional requirements, but might still be
undergoing timing analysis for the device family. It
can be used in production designs with caution.
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Device Support Level Definition
40-100GbE IP Core Device Speed Grade Support
Final The IP core is verified with final timing models for
this device family. The IP core meets all functional
and timing requirements for the device family and
can be used in production designs.
Table 1-2: 40-100GbE IP Core Device Family Support
Shows the level of support offered by the 40-100GbE IP core for each Altera device family.
Device Family Support
Arria V GZ Preliminary
Stratix IV (GX and GT) Final
Stratix V (GX, GT, and GS) Final
1-5
Other device families
Related Information
(1)
Not supported
40-100GbE IP Core Device Speed Grade Support on page 1-5
40-100GbE IP Core Device Speed Grade Support
Table 1-3: Slowest Supported Device Speed Grades
Lists the slowest supported device speed grades for different variations of the 40-100GbE IP core.
MegaCore Function Device Family Supported Speed Grades
Arria V GZ I3, C3
Stratix IV (GT) I2
40GbE
Stratix V (GX) I3, C3
Stratix V (GT) I3, C2
Stratix V (GS) I3, C3
(1)
This product does not provide support for Arria 10 devices. For information about Arria 10 40-100GbE
support, refer to the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide.
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IP Core Verification
MegaCore Function Device Family Supported Speed Grades
40GbE (24.24 Gbps option)
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Arria V GZ I3, C3
Stratix IV (GX) I3, C3
Stratix IV (GT) I3
Stratix V (GX) I3, C3
Stratix V (GT) I3, C2
Stratix V (GS) I3, C3
Stratix V (GX) I3, C3
40GbE (40GBASE-KR4 option)
Stratix V (GT) I3, C2
Stratix V (GS) I3, C3
Arria V GZ I3, C3
Stratix IV (GT) I2
100GbE
Stratix V (GX) I3, C3
Stratix V (GT) I3, C2
Stratix V (GS) I3, C3
100GbE (CAUI–4 option) Stratix V GT C2
IP Core Verification
To ensure functional correctness of the 40-100GbE IP core, Altera performs extensive validation through
both simulation and hardware testing. Before releasing a version of the 40- and 100-Gbps Ethernet MAC
and PHY IP core, Altera runs comprehensive regression tests in the current version of the Quartus® II
software.
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Any exceptions to this verification are reported in the Altera IP Release Notes. Altera does not verify
compilation with IP core versions older than the previous release.
Related Information
Altera IP Release Notes
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Simulation Environment
Altera performs the following tests on the 40-100GbE MAC and PHY IP core in the simulation environ‐
ment using internal and third party standard bus functional models (BFM):
• Constrained random tests that cover randomized frame size and contents
• Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets,
and corrupt control characters, and then check for the proper response from the IP core
• Assertion based tests to confirm proper behavior of the IP core with respect to the specification
• Extensive coverage of our runtime configuration space and proper behavior in all possible modes of
operation
Hardware Testing
Altera performs hardware testing of the key functions of the 40-100GbE MAC and PHY IP core. The
Altera hardware tests of the 40-100GbE IP core also ensure reliable solution coverage for hardware related
areas such as synchronization, and reset recovery. The IP core is tested with Stratix IV and Stratix V
devices.
Performance and Resource Utilization
Simulation Environment
1-7
The following sections provide performance and resource utilization data for the 40GbE and 100GbE IP
cores.
Resource Utilization for 40GbE IP Cores
Resource utilization changes if the statistics counters are configured in the IP core. You can specify
whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you
cannot change the setting dynamically.
The 24.24 Gbps variations of the 40-100GbE IP core use the same resources as the standard 40GbE IP
core variations. The 40GBASE-KR4 variations require more resources only for the PHY component.
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Resource Utilization for 40GbE IP Cores
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Table 1-4: 40GbE IP Core FPGA Resource Utilization in Stratix V and Arria V GZ Devices
Lists the resources and expected performance for selected variations of the 40GbE IP cores in an Arria V GZ or
Stratix V device. The results were obtained using the Quartus II software v13.1 for a Stratix V 5SGXEA7N2F45C2
device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.
Memory
Module ALMs Logic Registers
M20K
MAC&PHY with
Avalon-ST client
interface without
statistics counters
MAC&PHY with
Avalon-ST client
interface and with
statistics counters
MAC with Avalon-ST
client interface
without statistics
counters
MAC with Avalon-ST
client interface and
with statistics
counters
• alt_e40_adapter_
rx:adapter_rx
13600 23500 9
17700 30900 9
7100 15000 9
11300 22300 9
500 900 0
• alt_e40_adapter_
tx:adapter_tx
MAC with custom
streaming client
interface without
statistics counters
MAC with custom
streaming client
interface and with
statistics counters
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300 700 0
6200 13400 9
10400 20700 9
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Resource Utilization for 40GbE IP Cores
Module ALMs Logic Registers
1-9
Memory
M20K
• alt_e40_mac_
3000 7000 9
rx:mac_rx
• alt_e40_mac_
2600 4800 0
tx:mac_tx
• alt_e40_mac_
700 2000 0
csr:mac_csr without
statistics counters
• alt_e40_mac_
4600 8500 0
csr:mac_csr with
statistics counters
PHY 6800 8600 0
• alt_e40_phy_
6200 8200 0
pcs:phy_pcs
• • alt_e40_pcs_
2800 3800 0
rx:pcs_rx
• • alt_e40_pcs_
tx:pcs_tx
• • alt_e40_phy_
csr:phy_csr
• alt_e40_phy_
pma:phy_pma
40GBASE-KR4 PHY
• No auto-negotiation
(AN)
• No link training
(LT)
• Forward error
correction (FEC)
only
• Use M20K blocks
for FEC buffer
2900 3300 0
500 1100 0
200 400 0
14800
16700 8
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Resource Utilization for 40GbE IP Cores
Module ALMs Logic Registers
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Memory
M20K
40GBASE-KR4 PHY
23800 24500 8
• AN
• LT
• FEC
• Use M20K blocks
for FEC buffer
40GBASE-KR4 PHY
31900 41600 0
• AN
• LT
• FEC
• Do not use M20K
blocks for FEC
buffer
Table 1-5: 40GbE IP Core FPGA Resource Utilization in Stratix IV Devices
Lists the resources and expected performance for selected variations of the 40GbE IP cores in a Stratix IV device.
The results were obtained using the Quartus II software v13.1 for a Stratix IV EP4S100G5F45C2 device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
Module ALMs Logic Registers
MAC&PHY with
18100 25000 20
Avalon-ST client
interface without
statistics counters
MAC&PHY with
22100 32100 20
Avalon-ST client
interface and with
statistics counters
MAC with Avalon-ST
9700 15200 20
client interface
without statistics
counters
Memory
M9K
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Resource Utilization for 40GbE IP Cores
Module ALMs Logic Registers
1-11
Memory
M9K
MAC with Avalon-ST
client interface and
with statistics
counters
• alt_e40_adapter_
rx:adapter_rx
• alt_e40_adapter_
tx:adapter_tx
MAC with custom
streaming client
interface without
statistics counters
MAC with custom
streaming client
interface and with
statistics counters
• alt_e40_mac_
rx:mac_rx
13700 22200 20
700 1000 0
500 800 0
8500 13400 20
12500 20400 20
4300 7000 20
• alt_e40_mac_
3400 4800 0
tx:mac_tx
• alt_e40_mac_
1400 1900 0
csr:mac_csr without
statistics counters
• alt_e40_mac_
5000 8300 0
csr:mac_csr with
statistics counters
PHY 8600 9900 0
• alt_e40_phy_
8100 9400 0
pcs:phy_pcs
• • alt_e40_pcs_
3700 4400 0
rx:pcs_rx
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Resource Utilization for 100GbE IP Cores
Module ALMs Logic Registers
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Memory
M9K
• • alt_e40_pcs_
3600 3900 0
tx:pcs_tx
• • alt_e40_phy_
700 1100 0
csr:phy_csr
• alt_e40_phy_pma_
600 500 0
siv:pma
Related Information
Fitter Resources Reports in the Quartus II Help
Information about Quartus II resource utilization reporting, including ALMs needed.
Resource Utilization for 100GbE IP Cores
Resource utilization changes if the statistics counters are configured in the IP core. You can specify
whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you
cannot change the setting dynamically.
Table 1-6: 100GbE IP Core FPGA Resource Utilization in Stratix V and Arria V GZ Devices
Lists the resources and expected performance for selected variations of the 100GbE IP cores in an Arria V GZ or
Stratix V device. The results were obtained using the Quartus II software v13.1 for a Stratix V 5SGXEA7N2F45C2
device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.
Memory
Module ALMs Logic Registers
M20K
MAC&PHY with
45100 87700 28
Avalon-ST client
interface without
statistics counters
MAC&PHY with
49700 95500 28
Avalon-ST client
interface and with
statistics counters
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Resource Utilization for 100GbE IP Cores
Module ALMs Logic Registers
1-13
Memory
M20K
MAC with Avalon-ST
client interface
without statistics
counters
MAC with Avalon-ST
client interface and
with statistics
counters
• alt_e100_adapter_
rx:adapter_rx
• alt_e100_adapter_
tx:adapter_tx
MAC with custom
streaming client
interface without
statistics counters
MAC with custom
streaming client
interface and with
statistics counters
21600 45200 28
26100 53000 28
2700 6600 17
2600 4900 0
16200 33700 11
20700 41500 11
• alt_e100_mac_
6500 14900 11
rx:mac_rx
• alt_e100_mac_
9200 17500 0
tx:mac_tx
• alt_e100_mac_
700 2000 0
csr:mac_csr without
statistics counters
• alt_e100_mac_
4700 8500 0
csr:mac_csr with
statistics counters
PHY 23500 42500 0
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Resource Utilization for 100GbE IP Cores
Module ALMs Logic Registers
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Memory
M20K
• alt_e100_phy_
23000 41700 0
pcs:phy_pcs
• • alt_e100_pcs_
13600 26300 0
rx:pcs_rx
• • alt_e100_pcs_
8700 13700 0
tx:pcs_tx
• • alt_e100_phy_
700 1700 0
csr:phy_csr
• alt_e100_phy_pma_
500 800 0
sv:pma
Table 1-7: 100GbE IP Core FPGA Resource Utilization in Stratix IV Devices
Lists the resources and expected performance for selected variations of the 100GbE IP cores in a Stratix IV device.
The results were obtained using the Quartus II software v13.1 for a Stratix IV EP4S100G5F45C2 device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
Module ALMs Logic Registers
MAC&PHY with
60300 96000 29
Avalon-ST client
interface without
statistics counters
MAC&PHY with
65200 102400 29
Avalon-ST client
interface and with
statistics counters
MAC with Avalon-ST
30700 48600 29
client interface
without statistics
counters
Memory
M9K
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Resource Utilization for 100GbE IP Cores
Module ALMs Logic Registers
1-15
Memory
M9K
MAC with Avalon-ST
client interface and
with statistics
counters
• alt_e100_adapter_
rx:adapter_rx
• alt_e100_adapter_
tx:adapter_tx
MAC with custom
streaming client
interface without
statistics counters
MAC with custom
streaming client
interface and with
statistics counters
• alt_e100_mac_
rx:mac_rx
35600 55000 29
4100 6300 17
3900 6400 0
23300 35900 12
26900 42300 12
9500 15600 12
• alt_e100_mac_
12600 18400 0
tx:mac_tx
• alt_e100_mac_
1200 1900 0
csr:mac_csr without
statistics counters
• alt_e100_mac_
4900 8300 0
csr:mac_csr with
statistics counters
PHY 8600 9900 0
• alt_e100_phy_
2900 46900 0
pcs:phy_pcs
• • alt_e100_pcs_
16700 28500 0
rx:pcs_rx
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Resource Utilization for 100GbE CAUI–4 IP Cores
Module ALMs Logic Registers
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Memory
M9K
• • alt_e100_pcs_
11200 16600 0
tx:pcs_tx
• • alt_e100_phy_
1100 1700 0
csr:phy_csr
• alt_e100_phy_pma_
600 500 0
siv:pma
In the standard 100GbE variations, as in the 40GbE variations, some resource utilization numbers
decrease when statistics counters are not configured in the IP core. For example, compare the values for
the MAC with custom streaming client interface on a Stratix IV device with statistics counters included or
not included. When counters are included, the MAC requires 26600 ALMs, but when the counters are not
included, the MAC requires 23000 ALMs. The difference is 3600 ALMs. In a Stratix V device, the
difference is 2900 ALMs.
Related Information
Fitter Resources Reports in the Quartus II Help
Information about Quartus II resource utilization reporting, including ALMs needed.
Resource Utilization for 100GbE CAUI–4 IP Cores
Resource utilization changes if the statistics counters are configured in the IP core. You can specify
whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you
cannot change the setting dynamically.
Table 1-8: 100GbE CAUI–4 IP Core FPGA Resource Utilization
Lists the resources and expected performance for selected variations of the 100GbE CAUI-4 IP core with statistics
counters included or not included. The results were obtained using the Quartus II software v13.1 for a Stratix V
5SGTMC7K2F40C2 device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.
Memory
Module ALMs Logic Registers
M20K
MAC&PHY with
50100 102700 28
Avalon-ST client
interface without
statistics counters
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Resource Utilization for 100GbE CAUI–4 IP Cores
Module ALMs Logic Registers
1-17
Memory
M20K
MAC&PHY with
Avalon-ST client
interface and with
statistics counters
MAC with Avalon-ST
client interface
without statistics
counters
MAC with Avalon-ST
client interface and
with statistics
counters
• alt_e100_adapter_
rx:adapter_rx
• alt_e100_adapter_
tx:adapter_tx
MAC with custom
streaming client
interface without
statistics counters
54600 110100 28
21500 45100 28
26100 52800 28
2700 6500 17
2600 4900 0
16200 33700 11
MAC with custom
20700 41300 11
streaming client
interface and with
statistics counters
• alt_e100_mac_
6500 14800 11
rx:mac_rx
• alt_e100_mac_
9200 17400 0
tx:mac_tx
• alt_e100_mac_
700 2000 0
csr:mac_csr without
statistics counters
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Release Information
Module ALMs Logic Registers
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Memory
M20K
• alt_e100_mac_
4600 8500 0
csr:mac_csr with
statistics counters
PHY 28600 57400 0
• alt_e100_phy_pcs_
27200 55000 0
caui4:phy_pcs
• • alt_e100_pcs_
18000 35700 0
rx_caui4:pcs_rx
• • alt_e100_pcs_
8400 17500 0
tx_caui4:pcs_tx
• • alt_e100_phy_
700 1700 0
csr_caui4:phy_
csr
• alt_e100_phy_pma_
1400 2500 0
sv_caui4:pma
Related Information
Fitter Resources Reports in the Quartus II Help
Information about Quartus II resource utilization reporting, including ALMs needed.
Release Information
Table 1-9: 40‑100GbE IP Core Current Release Information
Item Description
Version 14.1
Release Date 2014.12.15
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Item Description
Ordering Codes IP-40GEMAC
IP-40GEPHY
IP-100GEMAC
IP-100GEPHY
IP-40GEMACPHY
IP-100GEMACPHY
IP-40GBASEKR4PHY
Product ID 40Gb Ethernet MAC: 00DF
40Gb Ethernet PHY: 00E0
100Gb Ethernet MAC: 00DD
100Gb Ethernet PHY: 00DE
40GBASE-KR4 with FEC: 0113
Release Information
1-19
Vendor ID 6AF7
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www.altera.com
101 Innovation Drive, San Jose, CA 95134
Getting Started
2
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The following sections explain how to install, parameterize, simulate, and initialize the 40-100GbE IP
core:
Installing and Licensing IP Cores on page 2-2
The 40-100GbE IP core is available with the Quartus II software in the Altera MegaCore IP Library.
Specifying the 40-100GbE IP Core Parameters and Options on page 2-3
The 40-100GbE IP core supports a standard customization and generation process from the Quartus II IP
Catalog.. This IP core is not supported in Qsys.
IP Core Parameters on page 2-3
The 40-100GbE parameter editor provides the parameters you can set to configure the 40-100GbE IP core
and simulation testbenches.
Files Generated for the 40-100GbE IP Core on page 2-10
The Quartus II software version 14.1 generates the following output for your 40-100GbE IP core.
Simulating the IP Core on page 2-10
Integrating Your IP Core in Your Design on page 2-11
40-100GbE IP Core Testbenches on page 2-14
Altera provides a testbench and an example design with most variations of the 40-100GbE IP core. The
testbench is available for simulation of your IP core, and the example design targets a C2 speed grade
device and can be run on hardware. You can run the testbench to observe the IP core behavior on the
various interfaces in simulation.
Simulating the 40-100GbE IP Core With the Testbenches on page 2-20
Compiling the Full Design and Programming the FPGA on page 2-24
Initializing the IP Core on page 2-24
Related Information
Managing Quartus II Projects
Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information
about generating an Altera IP core and integrating it in your Quartus II project.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
2-2
Installing and Licensing IP Cores
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera IP core in simulation and compilation in the Quartus II
software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore functions,
require that you purchase a separate license for production use. You can use the OpenCore Plus feature to
evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and
performance. After you purchase a license, visit the Self Service Licensing Center to obtain a license
number for any Altera product.
Figure 2-1: IP Core Installation Path
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Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
Note:
out.
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Specifying the 40-100GbE IP Core Parameters and Options
Specifying the 40-100GbE IP Core Parameters and Options
The 40-100GbE parameter editor allows you to quickly configure your custom IP variation. Use the
following steps to specify IP core options and parameters in the Quartus II software.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
4. Generate the IP core by following these steps:
a. Click Generate.
b. Optionally, to generate a simulation testbench or example project, follow the instructions in
Generating the 40-100GbE Testbench on page 2-21.
5. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If
you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in
Project to add the file.
6. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
2-3
IP Core Parameters
The 40-100GbE parameter editor provides the parameters you can set to configure the 40-100GbE IP core
and simulation testbenches.
The 40-100GbE parameter editor has two tabs, the Main tab and the 40GBASE-KR4 tab. The 40GBASE-
KR4 tab in the 40-100GbE parameter editor is relevant only for certain variations that target a Stratix V
device; for other variations, the parameters on the tab are unavailable.
Table 2-1: 40-100GbE Parameters: Main Tab
Describes the parameters for customizing the 40-100GbE IP core, on the Main tab of the 40-100GbE parameter
editor.
Parameter Type Range Default Setting Parameter Description
General Design Options
Device family String • Stratix IV
• Stratix V
• Arria V GZ
Stratix V Selects the device family.
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IP Core Parameters
Parameter Type Range Default Setting Parameter Description
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MAC configu‐
ration
String • 40 GbE
• 100 GbE
Core options String • PHY
• MAC
• MAC & PHY
PHY configu‐
ration
(2) (3) (4)
Integer 40 GbE:
• 24.24 Gbps
(4x6.25)
• 40 Gbps (4x10)
100 GbE:
• 100 Gbps
(10x10)
• CAUI-4 (4x25)
MAC client
interface
(5)
String • Custom–ST
interface
• Avalon–ST
interface
100 GbE Selects the MAC datapath width.
MAC & PHY Selects the core components to
generate.
The default value
depends on the
Selects the Ethernet speed and lane
configuration.
MAC configura‐
tion value.
40 GbE:
• 40 Gbps (4x10)
100 GbE:
• 100 Gbps
(10x10)
Avalon–ST
interface
Selects the Avalon–ST interface or
the narrower, custom streaming
client interface to the MAC.
Duplex mode
(6)
Integer • RX
• TX
Full Duplex Selects datapath mode to generate.
• Full Duplex
PHY Configuration Options
PHY PLL type
(2) (7) (8)
(2)
This parameter is disabled in MAC-only operation.
(3)
The PHY configuration parameter is disabled when MAC configuration is set to 100GbE and Device
String • ATX
• CMU
ATX Configures the PHY PLL.
family is not Stratix V. If the parameter is disabled, the IP core must always be set to the regular 10 Gbps
PHY link option of 4 x 10.3125 or 10 x 10.3125.
(4)
For the Device family parameter, the CAUI-4 option requires the Stratix V GT device.
(5)
This parameter is disabled in PHY-only operation.
(6)
The Duplex mode parameter is disabled when PHY configuration is set to CAUI–4; CAUI–4 variations
must always be set to the duplex configuration.
(7)
The PHY PLL type parameter is disabled when PHY configuration is set to CAUI–4; CAUI–4 variations
must always be set to the ATX configuration.
(8)
The PHY PLL type parameter is disabled when the IP core targets a Stratix IV device; Stratix IV variations
must always be set to the CMU configuration.
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IP Core Parameters
Parameter Type Range Default Setting Parameter Description
2-5
PHY reference
frequency
(2)
Integer
(encodi
ng)
Advanced Design Options
Status clock
(2)
rate
Statistics
counters
(5)
Float • Stratix IV:
Boolean • True
The range and default settings depend
on the PHY configuration.
Despite its apparent availability in the
parameter editor, CAUI–4 variations
do not support the 322.265625 MHz
clock frequency. For correct
functioning of CAUI–4 variations, you
must set this parameter to the value of
644.53125 MHz.
• Stratix IV: 37.5
37.5–50.0
• Arria V GZ or
• Arria V GZ or
Stratix V: 100.0
Stratix V:
100.0–125.0
True If turned on, the IP core includes
• False
Sets the expected incoming PHY
clk_ref reference frequency. The
input clock frequency must match
the frequency you specify for this
parameter.
In Sync-E variations, the input clock
frequencies for the rx_ref_clk and
tx_ref_clk clocks must match the
frequency you specify for this
parameter, although the two clocks
can be driven from different sources
and need not be aligned with each
other.
Sets the clock rate of clk_status in
MHz.
built–in statistics counters. If turned
off, the IP core is configured without
statistics counters.
Enable SyncE
support
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Boolean • True
• False
False Enables or disables a separate
reference clock for the RX CDR
block in the transceiver and exposes
the RX recovered clock as an output
signal. If this option is turned on
(set to true), the TX PLL and the RX
CDR in the transceiver have
separate input reference clocks and
the RX recovered clock is visible as
an IP core output signal. If it is
turned off, the two PLLs share one
input reference clock and the RX
recovered clock is not available as an
output signal.
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IP Core Parameters
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Table 2-2: 40-100GbE Parameters: 40GBASE-KR4 Tab
Describes the parameters for customizing a 40GBASE-KR4 40-100GbE IP core, on the 40GBASE-KR4 tab of the
40-100GbE parameter editor. The parameters on this tab are available only if the following conditions hold:
• Your IP core targets a Stratix V device. You set the target device family for your Quartus II project or in the
Quartus II software before you acess the IP Catalog.
• You select the value of 40 GbE for the MAC configuration parameter on the Main tab.
• You select a Core option value that includes a PHY component (PHY or MAC & PHY) on the Main tab.
• You select the value of 40 Gbps (4x10) for the PHY configuration parameter on the Main tab.
• You select the value of Full Duplex for the Duplex mode parameter on the Main tab.
Parameter Type Range Default
Setting
KR4 General Options
Enable KR4 Boolean • True
False If this parameter is turned on, the IP core is a
• False
Enable KR4
Reconfigura‐
Boolean • True
• False
True If this parameter is turned on, the IP core supports
tion
Auto-Negotiation
Enable AutoNegotiation
Boolean • True
• False
True If this parameter is turned on, the IP core includes
Parameter Description
40GBASE-KR4 variation. If this parameter is turned
off, the IP core is not a 40GBASE-KR4 variation, and
the other parameters on this tab are not available.
dynamic analog reconfiguration through a dedicated
reconfiguration interface. If this parameter is turned
off, the IP core cannot support auto-negotiation (AN)
or link training (LT) modes, and the AN and LT
parameters on this tab are not available. This
parameter does not affect FEC availability.
logic to implement auto-negotiation as defined in
Clause 73 of IEEE Std 802.3ap–2007. If this parameter
is turned off, the IP core does not include autonegotiation logic and cannot perform auto-negotia‐
tion.
Link fail inhibit
time for 40Gb
Ethernet
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Integer
(Unit:
ms)
Currently the IP core can only negotiate to KR4
mode.
500–510ms504 ms Specifies the time before link_status is set to FAIL
or OK. A link fails if the time duration specified by
this parameter expires before link_status is set to
OK. For more information, refer to Clause 73 Auto-
Negotiation for Backplane Ethernet in IEEE Standard
802.3ap–2007.
The 40GBASE-KR4 IP core asserts the lanes_
deskewed signal to indicate link_status is OK.
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IP Core Parameters
2-7
Parameter Type Range Default
Setting
Auto-Negotia‐
tion Master
String • Lane 0
• Lane 1
Lane 0 Selects the master channel for auto-negotiation.
• Lane 2
• Lane 3
Pause ability–C0Boolean • True
True If this parameter is turned on, the IP core supports
• False
Pause ability–C1Boolean • True
True If this parameter is turned on, the IP core supports
• False
Link Training: PMA Parameters
VMAXRULE Integer
VMINRULE Integer
0–63 60
0–63 9
Parameter Description
symmetric pauses as defined in Annex 28B of Section
2 of IEEE Std 802.3–2008.
asymmetric pauses as defined in Annex 28B of
Section 2 of IEEE Std 802.3–2008.
Specifies the maximum VOD. The default value, 60,
represents 1200 mV.
Specifies the minimum VOD. The default value, 9,
represents 165 mV.
VODMINRULE Integer
VPOSTRULE Integer
VPRERULE Integer
PREMAINVAL Integer
PREPOSTVAL Integer
PREPREVAL Integer
INITMAINVAL Integer
0–63 24
0–31 31
0–15 15
0–63 60
0–31 0
0–15 0
0–63 52
Specifies the minimum VOD for the first tap. The
default value, 24, represents 440 mV.
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum post-tap setting.
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum pre-tap setting.
Specifies the Preset VOD value. This value is set by the
Preset command of the link training protocol,
defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3ap–
2007.
Specifies the preset Post-tap value.
Specifies the preset Pre-tap value.
Specifies the initial VOD value. This value is set by the
Initialize command of the link training protocol,
defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap–
2007.
INITPOSTVAL Integer
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Specifies the initial Post-tap value.
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IP Core Parameters
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Parameter Type Range Default
Setting
INITPREVAL Integer
0–15 5
Link Training: General
Enable Link
Training
Enable
microcessor
Boolean • True
• False
Boolean • True
• False
True If this parameter is turned on, the IP core includes
False If this parameter is turned on, the IP core includes a
interface
Enable RX
equalization
Boolean • True
• False
False If this parameter is turned on, the IP core includes
Parameter Description
Specifies the initial Pre-tap value.
the link training module, which configures the
remote link partner TX PMD for the lowest Bit Error
Rate (BER). LT is defined in Clause 72 of IEEE Std
802.3ap–2007.
dedicated interface through which you can control
the link training.
the RX part of the link training module. This part of
the link training configures local receiver RX
Continuous Linear Time Equalizer (CTLE) and
Decision Feedback Equalizer (DFE) to achieve the
lowest Bit Error Rate (BER) .
Maximum bit
error count
Number of
frames to send
before sending
actual data
Integer
2n – 1 for
n an
integer in
the range
4–12.
Integer • 127
• 255
4095
127
Specifies the maximum number of errors on a lane
before the Link Training Error bit (40GBASEKR4 register offset 0xD2, bit 4, 12, 20, or 28,
depending on the lane) is set, indicating an unaccept‐
able bit error rate.
n is the width of the Bit Error Counter that is
configured in the IP core. The value to which you set
this parameter determines n, and thus the width of
the Bit Error Counter. Because the default value of
this parameter is 4095, the default width of the Bit
Error Counter is 12 bits.
You can use this parameter to tune PMA settings. For
example, if you see no difference in error rates
between two different sets of PMA settings, you can
increase the width of the bit error counter to
determine if a larger counter enables you to
distinguish between PMA settings.
Specifies the number of additional training frames
the local link partner delivers to ensure that the link
partner can correctly detect the local receiver state.
FEC Options
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