Alinco DX-SR8E, DX-SR8T, DX-SR8 Service Manual

DX-SR8 / T / E

Service Manual

CONTENTS

SPECIFICATIONS

General...............................................................................2

Transmitter........................................................................2

Receiver.............................................................................2

C IR C U IT D E S C R IP TIO N

1) Receiver System

2) Transmitter System.................................................5,6

3) Peripheral Circuits...................................................7,8

4) PLL Synthesizer Circuits...........................................8

5) R5F2L3ACANFP#U1 (XA1400 /XA 144 2 )

SEM IC O N D U C TO R DA TA

1) NJM4558M (XA0097)

2) BD1754HFN (XA1403)............................................ 11

3) NJM78M05DL1A (XA1118)

4) NJM7808FA (XA1106).............................................12

5) TC 4S66F (XA0115)..................................................12

6) BU4052BCF (XA 0236)............................................12

7) BU4001 BF (X A 0299 )

8) TA75S01F (XA0332)............................................... 12

9) LA4425A (XA0410 ) ..................................................12

10) TC74HC74AF (XA0459).......................................13

11) NJM3357M (XA0742)............................................13

12) NJM7805FA (XA0812 ) ......................................... 13

13) UPC2710TB (XA0968)......................................... 13

14) NJM2594V (XA 0995)............................................13

15) TC74HC390AF (XA1001).....................................13

16) MB15A01PFV1 (XA 1010)....................................14

17) LM2904PWR (XA1103)........................................14

18) LM2902PWR (XA1106)

19) S80845CLNB (XA1120)

20) TC4SU11F (XA1396)

21) TC74VHC393FT (XA 13 97)

22) XC9504B092AR (XA1398)

23) AD9833BRM A (X A1399)

24) R1EX24256ASAS0A#S0 (XA1401)

25) M61545AFP#DF0R (XA1402)

26) NJM 2068V (XA 1404)............................................16

27) Transistor, Diode and LED Outline Drawing.... 16

28) LCD Connection (EL0064 )

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9-11

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14 14

15 15

15 16

EXP L O D E D V IE W

1) Front V iew

2) Main Side..............................................................20-22

PA RTS LIS T

FRONT Unit.....................................................................23

LCD Unit...........................................................................23

PA Unit........................................................................24,25

MAIN Unit..................................................................25-35

Mechanical Unit..............................................................35

Packing Unit....................................................................35

AD JU S T M E N T

1) Required Test Equipment.......................................36

2) Adjustment Spot........................................................37

3) PA Unit Adjustment...................................................38

4) MAIN Unit Adjustment.............................................38

5) RX Test Specification..............................................40

6) TX Test Specification............................................... 41

PC BO A R D VIEW

FRONT Unit Side A........................................................42

FRONT Unit Side B .......................................................43

MAIN Side A ....................................................................44

MAIN Side A No.1.......................................................... 45

MAIN Side A No.2 .......................................................... 46

MAIN S ide B ....................................................................47

MAIN Side B No .1.........................................................48

MAIN Side B No.2 .........................................................49

PA Side A .........................................................................50

SCH E M A TIC D IA G R A M

FRONT Unit.....................................................................51

MAIN Unit (MAIN C P U )

MAIN Unit (MAIN 1).......................................................53

MAIN Unit (MAIN 2 ).......................................................54

MAIN Unit (MAIN 3 ).......................................................55

MAIN Unit (PLL)

PA Unit (PA).....................................................................57

PA Unit (FILTER)............................................................58

B LO C K D IA G R A M .....................................................59

............................................................ 18,19

...............................................

...........................................................

A LIN CO , Inc

SPE CIFI CA TIONS

General Operating mode J3E (USB, LSB),A3E (AM), A1A (CW), F3E (FM) Number of memory channels 600 channels simplex Antenna impedance Frequency stability Power requirement Ground method Current drain Receive 1.0A(max.) 0.7A (Squelched)

Operating temperature Dimensions 240 (w) x 94 (h) x255 (d) mm (Projections not included)

Weight

Transmitter

Power output SSB, CW, FM

Modulation system

Spurious emissions Less than -50 dB (Less than -45dB in 30 m band) Carrier suppression More than 40 dB Unwanted sideband More than 50dB (1 kHz) Maximum FM deviation Receiver Receiver type

Sensitivity SSB

Intermediate frequency

Selectivity

Spurious and image rejection ratio Audio output power

RIT variable range

Transmit 20A

AM SSB AM FM

CW AM

FM (28 to 30 MHz) -6dBu (0.5uV)

SSB, CW, AM (narrow) AM, FM

DX-SR8 ALL MODELS

500 unbalanced ±1ppm

13.8V DC±15%(11.7to 15.8V) Negative ground

-10°C to 60°C (+14°F to +140°F)

(9.45" (w) x 3.7"(h) x 10”(d)) 240 (w) x 100 (h) x 293 (d) mm (9.45"(w) x 3.94" (h) x 11.54"(d))

Approx. 4.1kg (9 pounds)

100W (Hi) Approx. 10W (LOW) Approx.lW (S-LOW) 40W (Hi) Approw.4W (LOW) Approx.0.4W (S-LOW) Balanced modulation

Lo power modulation

Reactance modulation

±2.5 kHz

Double conversion superheterodyne {0.15 to 1.8 MHz) OdBu (1uV) (1.8 to 30MHz) -12dBu (10uV) (0.15 to 1. 8M Hz) +20dBu (1 OuV) (1.8 to 30 MHz) +6dBu (2uV)

1** 71.75MHz 2nd 455kHz

2.4kHz/-6dB 4.5kHz /-60dB 6kHz/-6dB 18kHz/-60dB More than 70dB More than 2.QW (8Q, 10%THD) ±1.2 kHz

Microphone impedance 2kO Transmit Frequency coverage

Receiver Frequency coverage

DX-SR8

1.6MHz-29.99999MHz

30kHz - 34.99999MHz

M icro p h o n e im pe d a n ce Tr a n s m it F re q u en cy covera g e

160m b a n d (1 .8M ) 80m ban d (3 .5 M ) *60m band (5 .3 M )

300Q 1 .8 0 0 0 0- 1 .99 9 9 9M H z 1 .8 0 00 0 -1 .9 99 9 9 M H z

3.5 0 00 0 - 3.9 999 9 M H z

5.3 3 0 5 0 M H z

3.4 0 0 00 - 3.999 9 9M Hz

5.346 5 0M H z

5.3 6650 M H z

5.371 5 0M H z

5.403 5 0M H z

D X -S R 8 T | D X -S R 8 E

40m band (7M ) 30m band (10 M ) 20m band (1 4M )

17m band (18M ) 15m b a n d (2 1M) 12m b a n d (2 4 M ) 10m b a n d (2 8 M )

Rece iver F re q u ency coverage

7.0 0 00 0 - 7.2 999 9 M H z 6.9 0 00 0 - 7.49 9 9 9M H z 10 .1 00 0 0 - 10.1499 9 M H z 9 .9 0 0 0 0 -1 0 .4 99 99 M H z 14 .0 0 00 0 -1 4 .3 4 9 9 9 M H z 13 .9 0 0 0 0-1 4 .4 9 9 9 9M H z 1 8 .0 6 8 0 0 - 1 8 .1 6 7 99M H z 17 .9 00 0 0-1 8 .4 9 9 9 9M H z 2 1 .0 00 0 0--2 1 .4 9 9 9 M H z 2 0 .9 0 0 0 0-2 1 .4 9 99 9M H z 2 4 .8 90 0 0-2 4 .9 8 9 9 9 M H z

28.0 0 0 0 0 - 29.699 9 9M H z 13 5k H z -2 9.9 9 9 9 9 M H z

24.4 0 0 00 - 25 .0 9 999 M H z

28.0 0 0 00 - 29 .9 9 999 M H z 135kahz - 2 9.9 9999 M hz

* T X ou tput po w er of 6 0 m b and is limited to 50 W . (H ig h ; L O W 1 0W , S -L O W 1 W )

CIRCU I T DE SCRIPT I ON

1) Receiver System

1. PA Unit

SA901 and R903 are installed in the input part of antenna terminal as the countermeasure against the thunder. The electric charge of antenna is discharged at R903, and when the voltage becomes over about 300V, the gap of SA901 is discharged so that the receiving input circuit Is protected. The input signal from antenna is passed through the Tx/Rx selecting relay (RL903) and passes thru the attenuator of about 20dB (RL906 ON or OFF). The followings are prevented in LPF consisting of L904, L905, C913, C914, and C915: 2m band image receiving, passing through the First IF (71.75MHz) and leaking of the first local oscillating frequency (71.88654-106.75153) to the antenna terminal.

2. Main Unit a. Front End

The receiving signal output from PA Unit is fed to Main unit through CN108. HPF, consisting of L122, L123, C154, C156, C158, C160, 0167, and C168, eliminates the strong radio signal of MW band of 1.6MHz or below. In case of receiving the signal of 1.6MHz or below, the received signal is passed through the low pass Filter (L118, L119, 0155, 0162, and 0163). BPF consists of 8 filters. Each filter covers the following frequency range. The frequency of

2.5MHz or more consists of Chebyshev BPF, and under 2.5MHz frequency band Is LPF.

Range

-1.6MHz

-2.5MHz BPF2 1.8MHz

1.6

-4.5MHz BPF3

2.5

-7.5MHz BPF4

4.5

-10.5MHz

7.5

-14.5MHz BPF2

10.5

-21.5MHz BPF3

14.5

-30MHz BPF4

21.5

-54MHz BPF5

Passing through BPF, the signal turns ON/OFF in the switching diode, D120 and D121. This preamplifier is the parallel grounded gate operation of Q128 and Q130 ( 2SK2539 ), so the unit can obtain a good performance at a high level input signal with low NF. The wide range frequency from about 1 MHz to 60MHz is amplified about 10dB. This 10dB preamplifier and 20dB attenuator in the PA unit are combined, then by pressing RF gain switch on the front panel, one of four steps, -20, -10,0, or + lOdB is selected. The LPF consisting of L146, L147, 0235, 0236, 0252 and 0253, prevents the following first receiving mixer from the local oscillation leaking, and also prevents the first IF and image of the spurious receiving. The first receiving mixer consisting of Q128 and Q130 is the balanced mixer, in which the local oscillating signal is led to the gate of 2SK2539. The 3rd intercept point is about 20dBm, and local oscillator of about 2V P-P is led to the gate. The receiving signal is converted into the first IF of 71.75MHz.

BPF1

For amateur band

3.5MHz 7MHz 10MHz 14MHz 18,21 MHz 24,28MHz 50MHz

b. The First IF Amplifier Circuit

XF102 and XF103 are the crystal filters of 71,75MHz. By the combination of two filters, the unit has the characteristics of the band width of 15kHz or more 3dB and the value of guaranteed attenuation of 70dB or more. Here the image ratio is determined 70dB or more (approx. 80dB). The first IF amplifier circuit of Q124 located between the crystal filters to prevent the loss in the front-end and mutual interference. The first IF amplifier circuit Q124 decides the sensitivity after passing the mixer. AGC voltage is applied to the second gate.

c. The Second Mixer Circuit, The Second Amplifier Circuit

DBM (Double Balanced Mixer) consists of L114, D111 and L115. The signal is passed in the opposite direction while receiving or transmitting in this DBM. Approximately OdBm is fed as the second local oscillating level, and the third IP is approximately 10dBm. The receiving signal (71,75MHz) and the second local oscillating frequency (71,295MHz) is mixed, and unwanted signal is eliminated in LPF consisting of L101, L102 and C119, then the signal of 455kHz is generated. After passing through the switching diode D108, the signal is amplified in Q110. The source of Q110 is controlled by the output of the noise blanker circuit.

d. IF Filter

After passing through the transmission/reception switching diode D110, the signal Is led to one of three ceramic filters of 455kHz. The selectivity is decided here except CW narrow.

SSB, AM-NARROW FL3(CFJ455K5) 2.4kHz/-6dB 4.5kHz/-6QdB SSB-NARROW, CW FL2(CFJ455KB) 1.0kHz/-6dB 3.0kHz/-60dB FM, AM FL4(CFW455G) 9kHz/-6dB 20kHz/-50dB

e. Second I.F.Amp

There are two switching diodes for input and output of each filter (D129 to D150), securing isolation. The isolation required Is more than the guaranteed attenuation for each filter (about 70dB). The filters not used are shorted by diodes parallel to the filters and cut by the diodes in series, therefore the combination achieves high level of isolation from the signal. The filter switching is done by the Q141, Q142, Q143, Q145, D128, D145, D146 and D151, and the switching configuration depends on the mode, Tx/Rx, and Wide/Narrow status.

After the filter, passing thru a Tx/Rx switching diode (D128), the signal is amplified by the Q138 and Q139, and buffered by the Q137. The second gates of the Q110, Q138 and Q139 are controlled by the AGC circuit. The level of the received signal for which AGC is applied Is of high amplitude and constant at the output of the Q137. This output is used for demodulation of SSB, AM, and CW modes besides used for AGC detection. In the FM mode, the signal having amplified by the Q138 is partly input to the IC110 (MC3357) thru the C353 and Is amplified and demodu lated. The demodulated signal is amplified by an op-amp inside the IC110. A feedback resistor (R351) has a parallel capacitor (C365) for de-emphasls. The Q110, Q138 and Q139 are also operational during the FM mode and the AGC is effected.

f. Demodulator

When in SSB or CW mode, the local oscillation signal mentioned below from DDS circuit Is Input to the balanced mixer of the IC104. The received signal is input to pin No.5, the local signal at 5V p-p to pin No.7. The Q610 is amplifier that amplifies the local signal to 5V p-p.

Local Osc: USB 456.5kHz + IF SHIFT

g. CW Audio Filter

The IC4 is an active filter combined of high pass and low pass filters by op-amps, which has a passband of about 600Hz (-6dB) with its centre at about 800Hz.

h. AF Switchlng/AGC Time-Constant Switching

The IC107 is an analogue multiplexer with two channels and four contacts, which switches the demodulated output and AGO time-constant dependent on mode. The mode voltage is made by combination of the D139 and D140, which is Input to pin No.9 and 10, thereby switching CW audio filter output and demodulated output of (SSB), FM, and AM. While transmitting, 8V is imposed to pin No.6 (inhibit) turning the demodulated output off.

I. AF Amplifier

The AF signal, after passing thru an analogue switch, is amplified by about 50dB with the IC113:A. The output of pin No.1 of the 1C113A is fed to AF Gain potentiometer for audio output control. The potentiometer output is voltage- divided with the R383 and R392 and is fed to the IC112, an AF amp. By said voltage division, input level is adjusted at the same time the input impedance is lowered for the IC112 therefore residue noise is lowered. The 1C112 is an AF power amp, while the Q147 and C393 form ripple filter. Over 2W output is obtained at 8 ohm load and 10% distortion. This output is used as the terminal of packet RTTY, SSTV, etc.

]. AGC

The AGC is affecting to one stage in the first IF circuit, and three stages in the second IF circuit, a total of four stages. Each amplifier stage is made of 3SK293 with AGC on the second gate. The bias on the first gate of 3SK293, and the source resistor and voltage at the second gate have been determined their operational level so that the gain Is lowered linearly against the voltage lowering at the second gate. (The source resistor: 470 ohm; the first gate about

3.7). The D144 is for signal detection and the Q140 is for DC amplification. The anode of the D135 Is set at 4.1V by the R321, D135, R280 and R292. Since little current flows through the IC106C feedback resistor the VR104, input resistor R290 and D135 to R321, the voltage of AGC line is about 4.2V. When there is detection voltage on the D144 due to receiver input signal, the Q140 attempts to lower the AGC voltage. When AGC Is set FAST in SSB or CW, there is the C336 between AGC line and the power supply. The raise in receiver input signal is AGC controlled dependent on the time-constant which is determined by R326 and C336 hence the transient response Is set. Discharging is determined by the C336 and R290 and the resulting characteris tic is of fast-attack/slow delay type.

LSB 453.5kHz + IF SHIFT CWU 455.0kHz + (sidetone freq) + IF SHIFT CWL 455.0kHz - (sidetone freq) + IF SHIFT

k. S-meter, Squelch

I. Noise Blanker

When the AGC is set to SLOW, an analogue switch in the IC108 turns ON and the R333 and C351 comes in parallel, and R333 with C351 makes discharge time longer without affecting the attack time.When in AM mode, the C325 is further added in parallel, which delays the attack time and the AGC response becomes of average-value type. The D135 are for temperature compensation. If the received signal delays with a narrow filter before AGC detection followed by AGC-detectlon and amplification further delaying for AGC-detection, it would cause amplifying with more gain and this loop would start hunting effects. For anti-hunting purpose in this regard, the AGC has more OR time-constant and slower operation as applicable stage comes closer to the antenna input. The final stage of I.F. varies its amplification immediately by the AGC detection voltage resulting in uniform level received signal, dependent on the transient response. That is, if the received signal suddenly increases, the received output would first be controlled for uniform output by the I.F. final stage, then step by step the AGC is applied to earlier stages, finally affecting the AGC on the final stage to be smaller. For AM reception, there is already AGC voltage due to carrier, and the AGC is averaged independent of the modulation level.

TThe output of IC106C Is sent to the CPU to display the S-meter. The output signal of IC106C is fed to pin IC106D. The voltage of pin No. 13 of IC106D is determined by the squelch VR of front unit. Comparing with this voltage, the squelch is opened or closed. During the check operation the CPU output decreases the voltage of squelch VR in front side to open the squelch deliber ately. The squelch output controls the IC106C, at the same time it is provided

to the front unit to light RX LED.

This circuit eliminates the pulse noise of a car, etc. Because the noise emitting time is short, in this duration the operation of receiver is stopped to prevent the unit from emitting a noise. The pulse noise is delayed when it is passed through the narrow band filter, and the emitting time becomes longer. It makes difficult to eliminate the noise, so it is necessary to eliminate the noise in the earlier stage. A part of the second mixer output, whose band width is limited, is amplified in Q118, Q114, Q115, and Q116. The signal is detected in D115 and

D118, and the AGC voltage is applied to Q115, Q114 and Q116.

The charge time constant of this AGC is determined by R192 and C201, and also the discharge constant is determined by R191+R192, C201. The voltage of AGC does not rise suddenly because of the charge constant, so that this voltage is not applied to almost all the short signals such as pulse noise, but is applied to the continuous signals such as receiving signal and amplifier gain is decreased.nal.

2) Transmitter

1. MAIN Unit

a. Mic Amp

b. Balanced Mixer

The input signal from microphone goes thru mic-gain pot the VR117 and is fed to a low noise amp the Q180. At the mic terminal there is an 5 V bias thru the

R109 for providing voltage to certain type of mics. The IC119A has the gain (about 20dB) which is determined by the R492 and R512. When in FM mode, the gain increases by about 35dB due to the R494 parallel to the R512 thru the Q175, and by the C465 the lower cut-off frequency is Increased thereby activating pre-emphasis and limiter. When in SSB or AM, if the speech compressor is turned ON, the gain increases by about 35dB due to the C460, R487, and Q172, and the IC119:A works as a limiter. The C460 cuts off lower spectrum portion and the audio quality becomes suitable for speech compres sion. The in FM, the gain is adequately obtained and there is no effect of speech compression. If the FM sub-tone is activated, the output of the 1C119:A pin No.1 is voltage divided by the R499 and R509, and the sub-tone fed thru the R509. The IC119:B Is a low pass filter which works as a splatter filter when in FM and a low pass filter when speech compressor is in use. The output is either fed to PLL circuit for FM modulating, or to the 10105 for balanced modulation. The output of the 10105 is muted by the Q178 when in CW or FM.

IC105 Is the balanced mixer, and the carrier is suppressed in SSB mode. To get more ratio or carrier suppression, the balance adjustment of VR102 and VR103 are applied. The carrier is necessary in CW/FM/AM mode, so the input of Pln7 is made unbalanced by applying the DC voltage to obtain the carrier. By applying the DC in AM/FM mode, or by keying in CW mode, the balance Is broken to obtain the carrier wave. VR115 is used for the adjustment or carrier level in AM/FM mode. VR118 is used for the adjustment of carrier level in CW mode. In the AM mode, the DC and modulation is added simultaneously. In SSB mode, the modulation Is added by R488. In AM mode, D174 Is DC-biased and turned ON. Then the attenuator consisting of R488 and R443 or R523 limits the modulation.

c. IF filter

d. IF Amp, Second Mixer

The output of the 1C105 goes thru a temperature compensating thermistor TH101 and the D128 and is fed to bandwidth limiting I.F. filter. Pulling up cathode of the D128 when in Tx (and L when in Rx) makes Tx/Rx isolation better. When in SSB mode, the signal becomes DSB without the carrier. Switching of the filters is done by the diode switching mentioned before. For each respective mode, filters are used as follows.

SSB, CW, AM-NARROW FL102 (CFJ455K5) 2.4KHz/-6dB 4.5KHz/-60dB CW-NARROW FL101 (CFJ455K8) 1.0KHz/-6dB 3.0KHz/-60dB FM, AM FL103 (CFW455G) 9.0KHz/-6dB 20KHz/-50dB

Having passed the filter, the signal passes thru a switching diode (D110), amp (Q104), and the D108, and thru the second mixer in reverse direction of Rx, making 71.75 MHz signal. The Q107 depends on CW keying that improves isolation when CW key is up. An ALC voltage is applied on the second gate of the Q104. Signals from 71.295MHz local oscillator and reverse heterodyne are filtered by the XF102. The signal is amplified by the Q614 and is input to a balanced mixer. (D111).

e. Transmitter First Mixer

f. Tx Pre AMP

g. CW Keying Circuit

The first transmit mixer comprising of the Q103, Q108, L104 and L117 is a balanced type mixer and Input about 3dBm of local oscillator (71.75MHz+TxFreq) to obtain the wanted frequency. The signal converted to the wanted frequency by the first Tx mixer Is passed thru an LPF to filter out the local frequency and image components before it Is Input to the Tx preamp.

The Q105 Is a wide band amplifier. It can put out high power with saturating

output of about + 13dBm and more than 20dB gain. Inserting attenuators on both the input and output make It widen Its range with more stability, The output

at the Transmitter First Mixer Is about OdBm when the transmitter power is

100W.

By keying, the Q165 is turned on to the base of the Q162 in the main unit is pulled to Low which causes the collector to output a voltage. This output controls all the circuit which operates by CW keying. The output of the Q162

collector goes thru the D180, IC105, VR103, and D126 and by applying a DC voltage to the balanced mixer it unbalances the mixer and generates a carrier. VR118 determines the CW waveform of rising edges and falling edges by adjusting the carrier level in R525 and C488. At the same time, the Q159 is turned ON to turn OFF the Q107 isolating in keying. The C428 makes the Q107 OFF duration longer than keying duration to avoid effects to the output waveform. By the D180 a voltage is input to pin No.10 of the 1C119:C, and by the output from pin N0.8 the Q161 is turned ON and the D171 pulling the PTT line down to Low brings the transmitter ON. The capacitors at the input of pin No.10 of the 10119:0 (C246, C247) determines transmit time delay after stop of keying. The BK1, BK2, and BK3 are 3 bit break-in time constant voltages which are combined by the combination of the R469, R470 and R471 as D/A for obtaining 8 levels of voltage. When all of the BK1, BK2, and BK3 are low, the status if full-break-in, when more than one of the BK1, BK2, and BK3 have voltage the status is semi-break-in and the break-in time fastest when all of them have voltage. When in full-break-in, each of the BK1, BK2, and BK3, voltages are low hence the Q164 is OFF, making a very fast discharge time-constant with the 0431 alone. When either of several of the BK1, BK2, or

BK3 has voltage, the Q164 would turn ON and the C434 would be added

parallel to the C431 making the time-constant longer which determines the delay time for semi-break-in. There are 7 levels of semi-break-in voltages out of the BK1, BK2, and BK3, that Is fed to the IC119:C as comparative voltage to change the discharge time constant. Thus the time constant is the shortest if all of the BK1, BK2 ,BK3 outputs voltage. When In AUTO-break-in, the output is from BK1 only, and the comparative voltage for the IC119:C is controlled with the output voltage of the IC119:D, The keying output when in AUTO mode is output with each keying using the one-shot multi-vibrator comprising of the

IC120:A and B. Hence the average value of the IC120:A output voltage would be proportional to average speed of keying. To obtain average voltage, the

R463 and C432, etc. are used for Integrating, and the output is DC amplified by the IC119:D whose output is used as comparative voltage for keying. The D182 is for turning OFF when in AUTO mode; when AUTO is low, the voltage charging the C432 is shorted and AUTO is stopped.

The D179 and R457 help to follow speeding up the keying, while the D176 and R458 determine the discharging time constant In transmission and elongate

the time constant in reception so that it compensates the time constant

recovery during the reception. By doing this, the circuit can follow the keying

speed; transmission can continue between letters; and reception can take

place between words. The circuit is good typically between 30 characters per minute to 200 characters per minute.

h. Power Control/ALC Circuit

The forward voltage obtained in the PA unit correspondent with transmit power

is input to the IC118:A for invert amplification. At the non-inverting input there is a voltage, and the output voltage is shifted by the non-inverted input voltage. There is already about 4.0V on the ALC line which is applied to the second gate of amplification stage that is under ALC control. When a forward voltage is applied, the output voltage of the 1C118:A goes down, and when becomes

lower than about 3V, the D160 lowers the voltage of the ALC line. The VR112

is for adjusting the Tx output to 100W (High power). The VR119 is for adjusting the Tx output to 10W (Low power). The VR120 Is for adjusting the Tx output to

1W (super Low power). By I is soldering, Q166 turns ON and by having the VR114 in parallel the voltage is brought down to result in SOW. When in AM, the

R448 comes in parallel to lower the output to 40W. When in Low power, the

LOW line brings the R528 and VR119 in parallel to lower the voltage. When in super Low power, the slow line brings the R529 and VR120 in parallel to lower the voltage. The Q158 and VR113 are for making the (antenna matcher) TUNE output to 10W output. Necessary output, however, may be different depending on the automatic tuner. When the SWR Is high, reflected voltage turns on the Q158 lowering the power. The Q158 is activated from SWR 3 approximately.

I. Overcurrent Protection

The voltage difference detected in the PA unit by the final collector current us differentially amplified by the IC118:B. The output voltage lowers as current increases and at some point the ALC line is pulled down thru the D160 lowering the output power. The operating point is determined by the VR110.

j. RF meter circuit, ALC Indication

The forward voltage Is amplified by the 1C118:D for driving the meter. The

D164, R433 and C419 are for instant peak-holding to show the meter more

visible. The D163 and D136 switch to S-meter. The ALC voltage is invert amplified by the IC118:C. The output voltage is divided from 8V thereby

lowering the feedback resistance so that tolerance caused by bias-leakage is minimized; further this feedback resistor lets some current to the R423 to

obtain 4.0V to the ALC line. The output Is fed to the base of the Q150, leading to the front unit tell the CPU to switch Tx and Rx besides illuminating the Tx

LED.

2. PA Unit

a. Power Amp

The signal input is amplified by the Q803 to about 100mW. By having the idling

current of about 100mA the amplification is A-class. With the feedback the

frequency response is compensated, and with a capacitor parallel to the

emitter resistor the frequency is compensated totally. Then the signal is amplified to about 5 watt with the Q801 and Q805 (RD16HHF1) where the idling current is 800mA (adjusted with the VR804) in push-pull configuration. The D804 and D805 is thermally contacting the Q801 and Q805 to compensate Idling temperature.

b. Final Power Amp

c. Cooling Fan Control

d. Protection Circuit

There is about 1.6A of Idling current in the final amp circuit consisting of the

Q802 and Q804 (RD100HHF1). The D801 and D802 are thermally conducting with the Q802 and Q804 for temperature compensation. Feedbacks exist thru the R804 and R822 from collector side averaging the gain in a wide range. The output of 100W goes to the filter circuit. The collector current of the Q802/Q804 is detected due to the voltage drop caused by resistance of the FB803 and L801, and is output to the main unit.

The fan is controlled under the temperature of the Q802 and Q804 which is sensed by a thermistor (TH801). While transmitting, due to temperature rise, the resistance of the TH801 goes down and voltage of inverted input for the Pin No.1 of IC101 (MAIN UNIT) goes down. The IC101 (Pin No.1) input is applied a voltage corresponding to its voltage thus Is compared. When the temperature is over 50 degrees Celsius approximately, the inverted-input voltage would go down with comparative voltage, and by the comparator output voltage of the

Pin No.74 of IC101, the Q183 is turned ON and the fan starts running.

As a protection for the final power amp, power down circuits detecting SWR excessive current, and temperature rise have been installed.

3) Peri pheral Circui ts

1. Beep and Sidetone Circuit

Sidetone is output by the STON line at pin No.24 of the CPU (MAIM UNIT) in square wave. Beep Is output by the beep line at pin No.16 of the CPU (MAIN UNIT) in square wave. The sidetone frequency is swltchable in the range of 400Hz to 1kHz. The VR1 is the volume control put which leads to the AP amp.

2. Tune Circuit

At the start of the tuning, the TUNE voltage comes out by which the one-shot multi-vibrator operates and by the Q168 approximately 8V is output to command the external auto tuner as a starting signal. Separately, an output which goes low while tuning is created by the Q169 using the TUNE voltage. When the starting signal is received by the external auto tuner (e.g. EDX-2), the tuner outputs the said (low) output at TKEY terminal, The radio’s CPU monitors the TKEY terminal and while the voltage Is at low level the radio is put to the TUNE mode. If the TKEY terminal is low for more than 20 seconds, the CPU releases the TUNE mode. During the TUNE mode the radio transmits in AM mode besides microphone Is muted and the carrier is suppressed at 10W (adjustable).

3. Regulated Power Supply

The 1C115 Is a regulated power supply of 8V output. The voltage necessary for transmission, namely T8V is created by the Q149, and for reception R8V by the Q152. The IC117, Q151 and Q155 are Tx/Rx control. When PTT line is grounded at the output of the Q161 by mic’s PTT or CW keying, a High level is output from the IC117:C, and buffered by the Q150 the output is sent to the CPU in the front unit for Tx/Rx switching. The IC117:C, having delayed the rising of reception with the R413, C408, and D158, controls Q149 with Q151. When transmitting, the current flows from 13.8V thru the R410 and D156, and since the Q149's base voltage is higher by one diode difference than 8V, the emitter output will be just 8V. When transmitting, the Q151 is turned ON thus the Q149’s base voltage will be OV, resulting no output on T8V line. When

receiving, the T8V line is shorted by the D157 to discharge remaining charges in the capacitors on T8V line. The Q152 while receiving, similarly as T8V line, has currents coming thru the D167 and R432 from the 13.8V line, and since the base voltage of the Q152 is higher by one diode voltage than 8V, the base voltage of the Q152 will be 0V hence no output on R8V line. When transmitting, the R8V line is shorted by the D168 to discharge remaining charges in the capacitors on R8V line. The Input to the IC117:D, which goes low when reception Is started, Is delayed with the R421 and C412, then inverted by the

IC117:B, followed by the Q155 to control R8V. if a voltage is applied to pin No.8 of IC117:C, the output at pin No. 10 would vary with PTT going Low, hence a PTT Lock is activated.

4. Mode Voltage Functions Control, BPF/LPF Switching The CPU (MAIN UNIT) is controlling the mode voltage, preamp On/Off, Attenu

ator, Power, BPF/LPF switching, AGC, break-in, and PTT-Lock. For each mode, the Q167, Q170, Q171, Q177, Q179, Q181 and Q182 are turned on providing 8V.

5. Low Pass Fi lt er

The output from the final power amp goes through the low pass filter removing

the harmonics. The input/output for this filter is switched with a relay, and the

filters not used are shorted to ground thru relays. The LPF control utilizes the

control voltage for the BPF in the main unit. Each LPF is made of 5 pole Cheby- shev filters, attenuating the second and higher order harmonics by more than

40dB.

The transmitting signal, having removed spurious contents by the LPF goes thru the power detection circuit and

Tx/Rx switching relay.

6. Power Detection Circuit

The L901 is made by bifilar winding on a toroidal core in 10 turns. Hence the two sides will have 20 turns with a center tap. When the jumper wire goes thru the hole of the core, this itself is considered one turn having 1:20 transformer. Since there are the R902 and R904 in parallel, it effectively means 50 ohm load existing on both ends. For the jumper wire, it is equivalent to having 500/

(20*20)=0.125Q resistor existing in series. Hence when outputting 100W, the

voltage applied to ends of the said quasi-resistor is:

0.125/(50+0.125)* VO00*50) =0.176V

Since the turn ratio is 20:1, the voltage between the L901 is [0.176*20=3.52V]

The center tap of the coil has the voltage a half of the above therefore the

current will flow reversely to that in the jumper wire. A voltage divided by the TC901 and C904 is applied to the center tap, the voltage being in phase with that in the jumper wire. If the voltage is adjusted with the TC901 to be equal to the enter tap voltage, the R908 would have the voltages in phase adding each other, and the R909 would have inverted phase canceling each other. If the antenna impedance changes, there would be a differential voltage on the R909 without having cancellation due to phase or voltage difference hence having a

DC voltage after passing thru the D902. In this way, the voltage applied on the

R913 is proportional to the output power (forward voltage) and on the R914 is to the reflected power (reflected voltage). Thus the output and reflected powers are detected and in the main unit the power is controlled.

LO L1 L2 L3 7.5MHz~14.5MHz L4 L5

-2.5MHz

2.5MHz~4.0MHz

4.0MHz~7.5MHz

14.5MHz~21.5MHz BPF6

21.5MHz~30.0MHz BPF7

BPFO, BPF1 1.8MHz band BPF2 3.5MHz band BPF3 BPF4, BPF5

7MHz band 10,14MHz band 18,21 MHz band 24,28MHz band

7. Power Switch

Pressing the SW1 turns the RL801 contact ON and 13.8V is supplied. At the same time, the Q101 is turned on and 5V is supplied.

0 0

8. Power Suppl y and Resett ing

9. Dimmer

10. LCD

11. Tone

12. Electronic Keye

The IC102, resetting IC for resetting the CPU, turns on and off at 4.5V. When OFF (OV) the CPU resets. Then the IC1004’s reset signal goes Low and the CPU stops. The IC116 is the power supply for the CPU, which is made separate in order for the voltage to sustain 5V until the data is written to the

EEPROM and resetting signal is input.

A regulated power supply of 8V Is made of the IC115. The voltage of 8V Is supplied to D3, D4, D5 and D6. The CPU’s EN output Is a pulse, which current value from D3 to D6 is set. When the illumination is at the highest intensity, the EN output is constant at 5V.

The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency of 125Hz.

The CPU (IC101) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3Hz) is output from pin 45 of CPU. The output of the CPU leading to the mic amp LPF having mixed with audio signal. The tone is output only when in FM mode.

The CPU (IC101) is activated by input to pin No.68 for dots, and pin No.69 for dash. When ElecKey is ON, the electronic keyer in ON, and when Eleckey is OFF the keying is of semi-automatic (the "bug key”) operation.

13. Cloning

14. Miscellaneous

The pin 58 of CPU is clone data transmission, and the pin 57 of CPU is

receiving data. Each data is of one line, and input/output is done thru JK2 on the front unit.

The X1 is a ceramic resonator of 8MHz carefully chosen on its harmonics not interfering on amateur bands. For the front panel switches, the Y0, Y1, Y2 and Y3 with regard to the DB0~DB5 are monitored to determine which key is

pressed. On the terminals of RIT and IF-Shift pots, 5V is applied and the voltage at the input of A/D determines the positions of these pots. The Q1 is for transmit detection whose output from the main unit and illuminating the Tx

LED. For this reason it cannot be directly Input to the CPU therefore the change

is only either on or off. The 02 is the squelch output from the main unit which

illuminates the Rx LED.

4) PLL Synt hesizer ci rcui ts

1. Reference frequency oscillator circuit

The reference oscillation frequency for the PLL of the second local oscillator

reference and DDS clock, etc. is set at 16.777216M Hz. The signal is oscillated by the X601, Q609, and Q611 buffered with the Q608. It is used for the DDS clock for BFO oscillation. It is further divided 1/2064 with the IC606 to

8.128496KHZ for the second local oscillator PLL (IC606) reference frequency.

2. First Local Oscillator i

The Q605 is a Hartley oscillator with the Q605 gate grounded which works as VCO with the oscillation frequency range of 71.75 to 106.75MHz. The Q601 eliminates ripples for stabilizing the power supply, while the Q604 is a buffer circuit. The output is divided 1/8 with the IC610 and divided 1/5 with the IC611, hence 1/4 of the first local oscillator frequency (about 1.8 to 2.5MHz) is input to the phase comparator IC607. Meanwhile the DDS in the IC603 can output in

0.25Hz step, and with a D/A converter of 10bit and LPF, a sinusoidal wave that is i 1/40 of the first local frequency can be obtained. This output, with the phase comparator will control the signal. The oscillator output frequency will be 10Hz patch (0.25*40), The IC607 output goes thru a loop filter which is made of high response, low noise op-amp inside the IC601A: controlling the D602, the oscillation frequency is controlled. To widen the lock range, some voltages are supplied to cathodes of the D602. The locking voltage applicable to the anode of; the D602 is in a wide range of 2V to +6V. The IC602 and the Q603 are the necessary negative voltage, and about -6.5V is attained.

3. Second Local Oscillator

The reference oscillation frequency input to the IC606 is 8.388608MHz which is divided 1/2064 inside, and the comparison frequency is about 8.128496KHz. The Q615 is a VCO with 71.295 MHz which is buffered with Q616. The output is'amplified by the amplifier Q620, and dividing it 1/8771 in the IC606, it is fed to.a phase comparator and thru a loop fitter, the oscillation frequency is output, controlled by the D605. Also, this output is amplified by the amplifier Q614 and fed to the second mixer circuit. When transmitting FM, the anode of the D605 will be superimposed by the modulating signal from the microphone, modulat ing into FM signal. When in FM mode, the C697 is added to a loop filter by the Q618, having the time constant larger and the control under the modulation is unable, a modulated signal is created thru the VCO. The IC605 is an analog switch which enables frequency modulation on the VCO only when in FM mode.

4 .1.F. Shifting (AIF)

When in SSB or CW, by varying the first local and BFO interlocked, it is possible to change the relative receiving bandwidth without changing the receiving frequency. The range for the I.F. shifting for DX-SR8 is +/-1.5kHz in 50Hz pitch.

5) R5F2L3ACANFP#U1 (XA14 00/XA1442)

FRONT / MAIN CPU

Terminal Connection (TOP VIEW) 0

U)0SCOOtOi-N(O^iB(ONOO>O«-NcOyiAlD

0 0 0 0 0 0 0 0 0 0 ( 5 ( 5 0 0 0 0 0 0 0 0 0 0

LU LU LU LU LU LU LLJ LU LLf LLt LLf LLf 111 LU LU LU LU LU LLI LLI LLI LLI

I-'-,©. c5. CO,^¡r>5 , o. ^ S. cq ¡n. 3 £ o. S F5,5

^ £* £* S4 £* £* S1 £* & S? 5? K? 5? 5? £? rt rt '* '* '* '* '*

CWO-OLO.a-a.Q.£LtLtLlLtLlLdLlLlLIL[LILILQ.Q.Q.Q.Q.

mnmmtmmmn

<d ca

HP OO

q: a:

i s . s

222

ooo

czcccc

t t t

hi hi in

in to to

in (o,

P1_S/SEG14 P1_5/SEG13

P1_4/SEG12 P1 3/SEG11/AN15 P1~2/SEG10/AN14

P1JI/SEG9/AN13 P1_0/SEG8/AN12

PD 7/SEG7/AN11

PD_B/S EG6/A N10

P0_5/SEG5/AN9 PO 4/SEG4/AN8 PO 3/SEG3/AN7 PQ_2/SEG2/AN5 P0_1/SEG1/AN5 PO 0/SEGWAN4

P13 7/AN19/TRGCLKB

P13 6/AN18/TRGIOB

P13 5/AN17/TRGCLKA

P13_4/AN 16/TRGlOA

VL1 VL2

VL3 CL2/P12 3 CL1/P12 2

VL4

DIQIBIDIBIBIQIBISllEIIIEIEISEiiilEIEISiaiSISIS

«titttnnnt nnwi tt tt

t. o S o

Q O

t-*9 5 «

Q.£,S3

P5 0/SEG4Q P5_1/SEG41 P5~2/SEG42 P5~3/SEG43 P6-0/S EG44/TR Dl 0 AO/TR DCLK P6 1/SEG45/TRDIOBO P6~2/S EG4 6/TR Dl OCQ P6~3/S EG47/T RDI0 DO P6_4/S EG4 8/TRDIO A1 P6_S/S EG4 9/TRDI OB 1 P6 0/SEG5O/TRDIOC1 P6_7/S EG 51 /T RDIOD1 P7_0/S EG 52/CO M7 P7 1/SEG 53/CO M6 P7~2iScG54JCOM5 P7~3/SEG55/COM4 P7~4/COM3 P7- 5/COM2 P7_6fCOM1 P7_7/COMO P10 0/(TRD IOAO/TRDC LK/KTO) P10_1/(TRDIOBO/KTT) P10_2/(TRD IOCO/KI2) P10_3/(TR DI0DD/KI3) P10 4/(TRDIOA1/K!4)

FRONT CPU ( XA1400)

No.

2 3 4 P13 - 5 6 7 MODE 8 XCIN

9 10 RESET 11 12 13 XIN

14 VCC 15 P11 16 INT6 17 P11 18 INT4 19 20 P11 21 P11 22 P11 23 P11 24 KI6 25 Kl 5 26 KI4 27 28 KI2 29 30 P10 31 32 COM1 33 COM2 34 COM3 35 SEG55 36 SEG54 37 SEG53 38 SEG52 39 SEG51 40 41 42 43 SEG47 44 SEG46 45 SEG45 46 SEG44 47 SEG43 48 49

50 SEG40 51 52 SEG38 53 SEG37 54 SEG36

55 SEG35 56 SEG34

Terminal

1 P13

P13/RXD0 P13/TXD0

WKUP VREF

XCOUT XOUT

VSS

INT3

K13 DB3 KI1 COMO

SEG50 SEG49 SEG48

SEG42 SEG41

SEG39

Signal I/O Description UP RXD TXD

GND 5V 5V -

RESET I XOUT 0 GND XIN 5V EN PTT I DOWN I DOWN Key input DIAL1 I DIAL2 Y0 O Y1 Y2 Y3 DB0 I DB1 I DB2 I

DB4 I

DB5 MUTE 0 COMO 0 LCD COMO output COM1 COM2 0 COM3 0 LCD COM3 output SEG55 0 SEG54 SEG53 SEG52 0 SEG51 0 SEG50 SEG49 0 SEG48 SEG47 0 SEG46 SEG45 SEG44 0 SEG43 0

SEG42 o SEG41 0 SEG40 0 SEG39 0 SEG38 0 SEG37 0 SEG36 0 SEG35 0 SEG34 0

UP Kev inDUt

UART data reception input

UART data transmission output

GND

5V 5V

Reset input

Main clock output

CPU GND

I Main clock input

CPU power terminal LCD Dimmer

PTT input

Rotary encoder input

Key matrix input

0 0

Key matrix input

l I

Microphone mute LCD COM1 output

LCD COM2 output

0 0

0 0 0

LCD segment signal

FRONT CPU (XA1400)

No.

57 58 59 SEG31 60 SEG30 61 62 SEG28 63 SEG27

Terminal Signal I/O Description

SEG33 SEG33 O SEG32

SEG32 O SEG31 O

SEG29

SEG30 SEG29 O

SEG28 O

SEG27 O 64 SEG26 SEG26 0 65 SEG25 SEG25 O 66 SEG24

SEG24 O 67 SEG23 SEG23 O 68 SEG22

SEG22 O 69 SEG21 SEG21 0 70 SEG20 SEG20 0 71 SEG19 SEG19 0 72

SEG18 SEG18 0 73 SEG17 SEG17 74 SEG16 SEG16

LCD segment signal

O 75 SEG15 SEG15 O 76 SEG14 77

SEG13 SEG13 O

SEG14 O

78 SEG12 SEG12 0

79 SEG11 SEG11 O 80 SEG10 SEG10 O 81 SEG9 SEG9 0 82 SEG8 SEG8

0 83 SEG7 SEG7 0 84 SEG6 SEG6 0 85 SEG5 SEG5 0 86 SEG4 SEG4 0 87

SEG3 SEG3 0 88 SEG2 SEG2 0 89 SEG1 SEG1 0 90 SEGO SEGO 91 VL1 VL1 92 VL2 VL2 93 VL3 VL3

LCD power supply

94 P12 RXLED 0 RX Lamp

P12 TXLED

95 96 VL4 VL4

TX Lamp

LCD power supply 97 AN19 VOL I Volume input 98 AN18 SQL I

AN17 SHIFT I SHIFT Volume input

100 AN16

RIT I RIT Volume input

SQL Volume input

MAIN CPU ( XA1442)

1 2 3 4 5

Terminal

P13/AN3 P13/RXD0 P13/TXD0

P13/DAO

WKUPO

Siqnal I/O TEMP I

RXD I TXD SQV 0

GND - 6 VREF 5V - 7 8 9

MODE

XCIN

XCOUT

XOUT

XIN

XOUT 0

XIN I

TRBO BEEP

I NTS ULK

P11

SCL2 CLK

P10 DAT

TRDIOC1 STON 0

P10 STB P10 P10 P10 P10 PSW I P10

PON 0 Unit power ON/OFF

USB 0 USB mode setting

P7 LSB P7 P7

CWU 0 CWU mode setting

CWL 0 CWL mode setting

P7 AM o P7 FM P7 TUN

P6 NBS 0 Noise Brounker setting P6

AGCS 0 AGC setting P6 LOW 0 Tx power LOW P6 SLOW P6 MUTE

TRDIOCO

TONE

TRDIOAO

ATT P5 BK1 0 P5 BK2 0 P5 BK3 0 P4 AUTO 0 P4 PTT 0 PTT Output

PTTL P4 50W 0 Tx Power 50W

VDAT

CLK1 VCLK

Description Temperature detection of transmission AMP

UART data reception input

UART data transmission output Output of voltage for squelch GND 5V

- -

I Reset input

Main clock output

CPU GND Main clock input

CPU power terminal

I Backup signal detection input

Beep tone output

I PLL unlock signal input

5V power ON/OFF output

Serial data for EEPROM

Serial clock output for PLL

Serial clock output for EEPROM

Serial data output for PLL Side Tone Output

Strobe signal output for PLL

- -

- .

Power switch input

0 LSB mode setting

AM mode setting 0 FM mode setting 0 Output of Voltage for antenna tuner

0 Tx power SLOW 0

Microphone mute

CTCSS tone output

- -

Attenuator ON/OFF

Break-in

PTT Lock

0 0 EVR control data output

Clock output for EVR

No.

10 RESET RESET 11

12 VSS GND 13 14 VCC 5V 15 P11 BU 16 17 18 P11 5VC 0 19 20 SDA EDAT I/O

21 22 SCL ECLK

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P7 NRW 0 Narrow mode setting

39 40 41 42 43 44 45 TRDIOBO 46 47 48 49

50 51 52 53 P4 54 55 P4 56

MAIN CPU ( XA1442)

No.

57 58 TXD1 59 P3

Terminal Signal I/O

RXD1 CRX I

CTX 0

BPFO 0 60 P3 BPF1 61 P3 BPF2 62 P3 BPF3 63

P3 BPF4 0 64 P3 BPF5 0 65 P3 BPF6 0 66 P3

BPF7 0 67 P2 PRE 68 P2

DOT I 69 P2 DASH I 70 P2 CWK 71 P2

TXS I 72 P2 SQS I 73 P2 50I I 74

FAN 0 75 P1 TKEY I 76 P1 COMP 0 77 P1 78

P1 79 AN15 SRF I S-meter input/RF meter input 80 P1 81

P1 82 P1 83 P0 JP1 84

JP2 I 85 PO JP3 ] 86 PO JP4 I 87 PO JP5 I 88 PO JP6 I 89 PO JP7 I 90 PO JP8 I 91 VL1 92 VL2 93 VL3 94 P12 95

P12 96 VL4 97 P13 SCLK 0 Serial clock output for DDS 98 P13 SDAT 0 99 P13 FSY1

100 P13 FSYB 0

Description Clone data reception input Clone data transmission output

1.6MHz BAND

1.9MHz BAND

3.5MHz BAND

7MHz BAND 10MHz BAND

14MHz BAND. 18MHz BAND 21 MHz BAND. 24MHz BAND 28MHz BAND, 29MHz BAND

PRE AMP ON/OFF CWDOT inDut CW DASH input

Transmission control in CW mode

Detection of transmission squelch Open/Close Tx Power SOW settinq

Fan IVbtor control

Detection of Antenna tuner operation

- -

Band plan 1 Band plan 2 Band plan 3 Band plan 4 Band plan 5 Band plan 6 Band plan 7 Band plan 8

- -

Serial data output for DDS

0 1stLO data for DDS

BFO data for DDS

SEMICONDUCTOR DATA

1) NJM4558M (XA0097)

Operation Amplifiers

(Top View)

2) BD1754HFN (XA1403)

LED Driver Series

8 _ _ 5.

B D 1 7 5 4

o u u

l_l LJ L_1 l_J

1 4

1 2 3 ISET 4 5 L1 6 L2 7 8

3) NJM78M05DL1A (XA1118)

5V Voltage Regulator

A OUTPUT Q

A-INPUT \T_

A + INPUT [~3~

Pin Name

GND

VIN

v - Œ

§3 v+

~7l B OUTPUT ~6~| B - INPUT ~6~| B +INPUT

1.INPUT

2.GND

3.0UTPUT

4) NJM7808FA (XA1106)

8V Voltage Regulator

Pin Assignment

3 2 1

5) TC4S66F (XA0115)

Bilateral Switch

____

td td td

1. OUTPUT

2. COMMON

3. INPUT

IN/OUT

OUT/IN

Vss 3

5 Vdd

4 CONT

6) BU4052BCF (XA0236)

Analog Switch

14 8

H B R H H H B

BU4052BCF

1 T T H T H 1

1 7

INH1B1TC

AC BC

CONVERTER

LEVEL

—

BINARY TO 1 ol 4 DECODER

WITH INHIBIT

—

COMMON

-O y

yo|T -

Y2[T -

COMM ONY[3-

Y3[T -

Y1 |T-

iNH iBrr[6-

vh e [ 7 -

vss[?

■^37-

■ Y OUT/IN

■ INH

• VEE

16] VDD

-ïs]X2

- m ] x i

- i s ] COMMON X

"iUX0

-¡ T |X 3

-w]a

7) BU4001BF (XA0299)

Quad 2-input NOR GATE

8) TA75S01F (XA0332)

Single Operational Amplifiers

_ _ _

S A

p mn

14]\/0D

13] A4

12] B4

IT] 04

10] 03

T]B3

7] A3

Vcc OUT

9) LA4425A (XA0410)

5W Audio Power Amplifiers

LA4425

2 3 5

10) TC74HC74AF (XA0459)

Dual D-type Flip Flop

11) NJM3357M (XA0742)

Low Powe FM IC

1CLR 1

1D 2 1CK 3 1PR 4

1Q 5

1$ 6

GND 7

Limiter Amp

Demodulator P >

CK D

a Q

CK D

a oTJ

¡2

T=—lr

Active

Filter

Amp

|2V

] 14VCC

13 2CLR

] 12 2D

n 11 2CK

] 10 2PR

] 9 2Q

8 2G

12) NJM7805FA (XA0812)

5V Voltage Regulator

Pin Assignment

1. OUTPUT

2. COMMON

3. INPUT

13) UPC2710TB (XA0968)

Wide Band Amp

3C 2 C

1 c

□ 4 □ 5

□ 6

14) N JM2594V (XA0995)

Balanced Mixer

Pin Name

INPUT 2 GND 3 GND 4

OUTPUT 5 GND 6

Vcc

CARRIER SIGNAL

NC INPUT BYPASS INPUT

15) TC74HC390AF (XA1001)

CMOS Dual Decade Counter

1CKA 1 [

1CLR 2 [

1QA 3 [

1CKB 4 [

1QB 5 [ 1QC 6 [ 1QD 7 [

GND 8 [I

] 16 Vcc 3 15 2CKÄ

2 14 2CLR

] 13 2QA ] 12 2CKB ] 11 2QB

2 10 2QC

] 9 2QD

Vcc=16, GND=8

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