Alinco DR-03T, DR-M03R Service Manual
DR-M03RI D R- 0 3 T
S e r v i c e M a n u a l
C O N T E N T S
SPE CIFIC AT IO NS
GENERAL
TRANSMITTER
RECEIVER.............
CIRC UIT D ISC R E T ION
1) Receiver System.....
2) Transmitter System....................
3) PLL Synthesizer Circuit.
4) CPU and Peripheral Circuit.........
5) Power Supply Circuit
6) M38268MCA082GP#U0 (XA1170A)
SE M IC O ND UCTO R DATA
1) NJM7808FA(XA0102).................
2) . TC4S66F (XA0115).........................................
3) TC4W53FU (XA0348)
4) TA31136FN (XA0404).................
5) LA4425A (XA0410).....
6) BR24L32FJ (XA0604Z)....................................
7) S-80845ALMP (XA0620)
8) N JM78M05DL1A (XA0947)
9) MB15A01PFV1 (XA1010)
10) LM2904PWR (XA1103)..............
11) LM2902PWR (XA1106).............
12) TA78DS10F (XA1249).....................................
13) Transistor, Diode and LED Outline Drawing... 15
14) RD16HHF1 (XE0056)
15) LCD Connection (TTR3626UPFDHN):......... 17
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................2
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3,4
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...................5,6
........6
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7-9
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.......10
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.......14
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4,5
4
10
10
11
11
12
12
12
14
16
PARTS LIST
2
2
CPU Unit
MAIN Unit
PA Unit...
Mechanical Parts.....................................
Packing Parts
ACCESSORIES...
ACCESSORIES (SCREW SET)
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ADJUSTMENT
1) Adjustment Spot.....................................
2) VCO and RX Adjustment Specification.. 27
3) TX Adjustment Specification
4) RX Test Specification
5) TX Test Specification
...............
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PC BOARD VIEW
1) CPU Unit Side A(UP0584)
2) CPU Unit Side B (UP0584).....
3) MAIN / PA Unit Side A (UP0584)
4) MAIN / PA Unit Side B (UP0584)......... 30
.....
SCHEMATIC DIAGRAM
1) CPU Unit.......................................................31
2) MAIN Unit
...................
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BLOCK DIAGRAM
1) DR-M03R / DR-03T................................... 33
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21-24
.......24
.......
.......
......
......
.......25
.......
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21
24
....
25
25
26 *
27
28
28
29
29
30
32
EX PLO DED V IEW
1) Top.and Front View
2) Bottom View........
3) LCD Assembly
........................ .....
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..... .........
A L IN C O , Inc
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18
19
20
SPECIFICATIONS
■ General
DR-M03R DR-03T
Frequency coverage 28.000 ~ 29.700MHz ( RX, TX )
Operating mode FM 16K0F3E
Frequency resolution 5 , 8.33 , 10 , 12.5 , 15 , 20 , 25 , 30 , 50 kHz
Number of memory
Channels
Antenna impedance 50ohm unbalanced
Power requirement 13.8V DC +/-15% (11.7 - 15.8 V )
Ground method Negative ground
Current drain Receive
Transmit
Operating temperature
Frequency stability
Dimensions 142 ( w ) x 40 ( h ) x 174 ( d ) mm
Weight Approx. 1.0 Kg
0.6 A ( m ax.) 0.4 A ( Squelched )
Approx. 3.0 A max.
-10 °C - 60°C
( 142 x 40 x 188 mm for projection included )
100
+/- 7ppm
■ Transmitter
Output power Hi
Mid
Low
Modulation system Variable reactance frequency modulation
Maximum Frequency
deviation
Spurious emission -50 dB
Adjacent channel power
Noise and hum ratio -40 dB -3 4 dB
Microphone impedance 2kohm
+/- 5kHz
■ Receiver
Sensitivity
Receiver circuit
Intermediate frequency 1st 10.7 MHz 2nd 450kHz
Squelch sensitivity -16 dBu
Adjacent channel selectivity
Inter-modulation rejection
ratio
Spurious and image rejection
ratio
Audio output power
- 12 dBu for 12 dB SINAD
Double conversion super-heterodyne
2.0 W ( 8ohm , 1 0% T H D )
10 W
5 W
1 - 4 W
+/- 2.5kHz
-60 dB
-65 dB
60 dB
70 dB
! NOTE : All specifications are subject to change without notice or obligation.
2
C I R C U I T D E S C R IP T I O N
1) Receiver System
The receiver system is a double super-heterodyne system with a 10.7MHz first IF and a 450kHz
second IF.
1. Front End
2. IF Circuit
3. Demodulation Circuit
The received signal at any frequency in the 28.000MHz to 29.695MHz
range is passed through the low-pass filter (L115, L114, L113, C204,
C203, C202, C216 and C215) and tuning circuit (L105 and D105), and
amplified by the RF amplifier (Q107). The signal from Q107 is then
passed through the tuning circuit {L104, L103, L102, and variable
capacitor D104, D103, D102) and converted into 10.7MHz by the mixer
(Q106). The tuning circuit, which consists of L105, variable capacitor
D105, L104, L103, L102, variable capacitor D104, D103 and D102, is
controlled by the tracking voltage from the VCO. The local signal from the
VCO is passed through the buffer (Q145), and supplied to the source of
the mixer (Q106). The radio uses the upper side of the super-heterodyne
system. .
The mixer mixes the received signal with the local signal to obtain the sum
of and difference between them. The crystal filter (XF101A, XF101B)
selects 10.7 MHz frequency from the results and eliminates the signal of
the unwanted frequencies. The first IF amplifier (Q105) then amplifies the
signal of the selected frequency.
After the signal is amplified by the first IF amplifier (Q105), it is input to
pin16 of the demodulator IC (IC108). The second local signal of 11.15MHz
(shared with PLL IC reference oscillation), which is oscillated the external
oscillator X601, is input through pin 1 of IC108. Then, these two signals
are mixed by the internal mixer in IC108 and the result is converted into
the second IF signal with a frequency of 450kHz. The second IF signal is
output from pin 3 of IC108 to the ceramic filter (FL101), where the
unwanted frequency band of that signal is eliminated, and the resulting
signal is sent back to the IC108 through pin 5. The second IF signal input
via pin 5 is demodulated by the internal limiter amplifier and quadrature
detection circuit in IC 108, and output as an audio signal through pin 9.
4. Audio Circuit
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC120:A), and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and
amplified by the AF amplifier (IC120:B). The signal is then input to volume
(VR1). The adjusted signal is sent to the audio power amplifier (IC117)
through the pin 1 to drive the speaker.
3
5. Squelch Circuit t
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of 1C108 after it was been amplified IC120:A and it is outputted from
pin 7 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the iC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L" level, AF
control signal is begin controlled and sounds is outputted from speaker.
2) Transmitter System
1. Modulator Circuit
2. Power Amplifier Circuit
y 3. APC Circuit
The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
1C114:D and C consists of two operational amplifiers; one amplifier (pin
12,13 and 14) is composed of pre-emphasis and I DC circuit and the other
(pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency
deviation is obtained by VR107. And input to the signal switch (IC113)
(9600 bps packet signal, input switch) and input to the anode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the younger
amplifier (Q115 and Q103), and input to the final power amplifier (Q701).
The signal is then amplified by the final power amplifier (Q701) and led to
the antenna switch (D110) and low-pass filter (L113, L114, L115, C215,
C216, C202, C203 and C204), where unwanted high harmonic waves are
reduced as needed, and the resulting signal is supplied to the antenna.
Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:B), then it controls the APC voltage supplied to final power
amplifier Q701 to fix the transmission power.
3) PLL Synthesizer Circuit
1. PLL
2. Reference Frequency
Circuit
4
The dividing ratio is obtained by sending data from CPU (1C1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in 1C116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
The reference frequency appropriate for the channel steps is obtained by
dividing the 11.15 MHz reference oscillation (X601) by 4250 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel step of 5, 8.33, 10, 15, 20, 25, 30 and 50 kHz are used.
When it is 6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the 10116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which is
obtained by the internal divider in IC116.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the
reference frequency and the VCO output frequency, the charge pump
output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL loop filter and input to the input to the variable
capacitor of the VCO unit for oscillation frequency control.
5. VCO Circuit
AColpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D123). This change the
‘ oscillation frequency, which is amplified by the VCO buffer (Q134, Q145)
and output from the VCO area.
4) CPU and Peripheral Circuits
1. LCD Display Circuit
2. Reset and Backup
The CPU turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64 Hz.
When the power from the DC cable increases from Circuits 0 V to 2.5 V or
more, “H” level reset signal is output from the reset IC (IC4) to pin 33 of
the CPU (1C1), causing the CPU to reset. The reset signal , however,
waits at 100, and dose not enter the CPU until the CPU clock (X1) has
stabilized.
3. S (Signal) Meter Circuit
4. DTMF Encoder
5. Tone Encoder
6. DCS Encoder
c X601 side only.
The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from
an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
The, CPU (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is* output from pin 10, through R35, R34 and VR109 (for level
adjustment), and then through the microphone amplifier (1C114:D), and is
sent to the variable capacitor of the VCO for modulation. At the same time,
the monitoring tone passes through the AF circuit and is output from the
speaker.
The CPU (IC1 ) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor
(D123) of the VCO for modulation.
The CPU (1C1 ) is equipped with an internal DCS code encoder. The code
(023 to 754) is output from pin 9 of CPU to the variable capacitor (D601) of
the PLL reference oscillator. When DCS is ON, DCS MUTE circuit
(Q126-ON, Q133-ON, Q 132-OFF) works. The modulation activates in
5
7. CTCSS, DCS Decoder -
The voice band of the AF output signal from pin 1 of IC120:A is cut by
sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin
4 of CPU. The input signal is compared with the programmed tone
frequency code in the CPU. The squelch will open when they match.
During DCS, Q108 is ON, C419 is working and cut off frequency is
lowered.
5) Power Supply Circuit
When power supply is ON, there is a “L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to
work. Then, “H” signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch control Q8
and Q7 which turns the 5VS ON. 5VS turns ON the PLL 1C (IC116), main power supply switch Q127 and Q122,
AF POWER IC117 and the 8V of AVR (IC115). During reception, pin 29 (R5) of CPU outputs “H" level, Q124 is ON,
and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs "L” level which is
reverse by Q11 so that the output in Q128 will be “H” level, Q123 is ON, and the transmission circuit is supplied by
8 V. Or, in the case when the condition of PLL is UNLOCK, “HJ level is outputted from pin 7 of PLL IC (IC116),
UNLOCK switch Q129 is ON, transmission switch Q128 is OFF which makes the transmission to stop.
6
6) M38268MCL082GP#U0 (XA1170A)
CPU
Terminal Connection
(TOP VIEW)
O O O O r - C S ] n ^ L D t D f > C O O ) 0 ’" N C O ^ I i ) < O h '
T-T-C MCvlC NJC SJCS lNCS ICMC SlCvl COC OCOC OCO COO O
Q5 CD C5 C5 QTJ QTJ ^rj QTJ ^rj ^rj Q ^ 0 O ' C5
LU LU UJ LU LU UJ LLI LU LLl LU LU LU LU LU UJ LLl LU UJ LU UJ
O ü ^ y O O T - C M n ^ i O C O h - O ^ — CM ro in (O p> o 'I— cvj CO
UJ UJ LLl LU LU co c o e o e o c o c o o o c o o o o o o o o o '« — ••— ■•— ■»—
W W M W t O Q . Q . Q , Q . C L C L C L C L Q _ C L a . Q . Q . O . D - D _ Q . Q . C L Q .
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y i n f i n m n t m i m n
SI Él Él É] El ^1 HI SI É 1 EH Esl SI Él Él É1 111 Isl Él É l É l SI SI É l Él Él
SE612-
SEG11■
SEG10-
SEG9-
SEG8-
SEG7
SEG6-
SEG5 ■
SEG4-
SEG3-
SEG2-
SEG1 ■
SEG0-
VCC
VREF-
AVSS
COM3'
COM2-
C0M1 ■
COMO
VL3 ■
VL2-
C2
C1-
VL1-
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LO LO
IO Q. Q.
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LO
O,
No. Terminal
1 P67/AN7
2
3 P65/AN5
4 P64/AN4
5 P63/SCLK22/AN3
6 P62/SCLK21/AN2
7
8 P60/SIN2/AN0
9 P57/ADT/DA2
10 P56/DA1
11 P55/CNTR1
12
13 P53/RTP1
14 P52/RTP0
15 P51/PWM1 CLK o Serial clock output for PLL
. 16 P50/PWMO
17
18 P46/SCLK1 STB 0
19 P45/TXD
20 P44/RXD
21 P43M/TOUT
22 P42/INT2
23 P41/INT1
24 P40
25 P77
26 P76 SSTB O Security mode
27
28
29
30 P72
31 P71
32 P70/INT0
33 RESET RESET f Reset input
34 XCIN Xcin
35 XCOUT Xcout
36 XIN Xin - 7 Main clock input
37
38 VSS GND
39 P27 PSW I
40 P26 SDA O Serial data for EEPROM
41 P25 CSC o
42
43 P23 LOW o Tx low power
44 P22
45 P21
46
47
48 P16
49 P15/SEG39 SW2 I Key sw 2 (V/M)
50 P14/SEG38
P66/AN6
P61/SOUT2/AN1
P54/CNTR0 TBST o Tone burst output
P47/SRDY1 TSTB I/O Trunking board detection / Strobe signal to trunking board
P75 W/N o
P74 T5 0
P73 R5 0
XOUT Xout
P24 MID o Tx middle power
P20 SW5 I
P17 SW4 I Key sw 4 (TSQ)
Signal I/O
SMT I
SQL
BP5
TIN I
r~ b p i
BP2
DCSW
RE2
TOUT
DOUT
SCL
BP4 I/O
MUTE I/O
DATA I/O
UTX
RTX I
BEEP
SEC
RE1
PTT
SQC
BU
EXP
SW6
SW3
SW1
S-meter input
I Noise level input for squelch
I Band plan 5
CTCSS tone input / DCS code input
Band plan 1
I
Band plan 2
I
0 DCS signal mute
I Rotary encoder input
0
CTCSS tone output / DCS tone output
o DTMF output
o
Serial clock for EEPROM
Band plan 4
Microphone mute / Security alarm SW
Serial data output for PLL / PLL unlock signal input
Strobe for PLL IC
o
I/O
.. -
UART data transmission output
UART data reception output
Beep tone / Band plan 3
I
Security voltage input
I Rotary encoder input
I PTT input
Wide Narrow SW
TX power ON / OFF output
RX power ON / OFF output
0 SQL ON/OFF
I
Backup signal detection input
-
-
-
Main clock output
-
CPU GND
Power switch input
C5V power ON / OFF output
0
Trunking / Packet data SW
I
Key sw 6 (SQL)
Key sw 5 (CALL)
I
Key sw 3 (MHz)
I
Key sw 1 (FUNC)
Description
8
No. Terminal
51 P13/SEG 37 DOWN I
52
53
54 P10/SEG 34
55 P07/SEG 33
56 P06/SEG32 S32
57 P05/SEG31
58 P04/SEG 30
59 P03/SEG 29
60 P02/SEG 28
61 P01/SEG 27
62
63 P37/SEG 25
64 P36/S E G 24
65 P35/SEG 23 S23 0
66
67 P33/SE G 21
68 P32/SEG 20 S20 o
69 P31/SEG 19 S19 0
70 P30/SEG18 S18 0
71
72
73 S E G 15 S15 0
74 SEG 14
75 S E G 13 S13 o
76 S E G 12 S12 o
77
78 S E G 10 S10 0
79 SEG9
80 S E G 8
81 S E G 7
82
83 S EG 5
84 S E G 4
85 S E G 3
86 S E G 2
87
88 SEGO
89 VCC VDD
90
91 A VSS
92
93
94 COM1 COM1
95 COMO COMO
96 VL3 VL3
97
98
99 C1
100
P12/SEG 36
P11/SEG35
P00/SEG 26 S26 0
P34/SEG 22 S22
SEG17
SEG16
SEG11 S11
•SEG6
SEG 1
VREF
COM 3 C O M 3 o
COM 2
VL2
C2
VL1 VL1 I
Signal I/O Description
UP I
S33
S31 0
S30 0
S29
S28
S27
S25
S24 o
S21 0
S17
S16
S14 0
S9
S8 o
S7
S6
S5 o
S4
S3 o A
S2
S1
SO
Vref
Avss
COM 2 0
VL2
I
C1
Mic down input
Mic up input
0
o
0
o
0
o
0
o
LCD segment signal
o
o
0
o
0
o
0
o
o
-
CPU power terminal
-
AD converter power supply
-
AD converter GND
LCD C O M3 output
LCD C OM 2 output
o
o
LCD COM1 output
LCD COMO output
-
LCD power supply
-
LCD power supply
- -
-
-
LCD pow er supply
9
S E M IC O N D U C T O R D A T A
1) NJM7808FA (XA0102)
8V (1A) Voltage Regulator
1. INPUT
2. COMMON
3. OUTPUT
1 2 3
2) TC4S66F (XA0115)
Bilateral Switch
5 4
s
____
a
C9
d d d
1 2 3
1. IN/OU T
2. OUT/IN
3. VSS
4. CONT
5. VDD
5
BL f l
M
d a d
1 2 3
CONT
Function (IN-OUT)
L Disconnect (Hi Z)
H Connect (290ohm typ.)
3) TC4W53FU (XA0348)
Multiplexer / De-multiplexer
8 7 6 5
n nil a.
m i
12 3 4
1. COMMON
2. INH
3. VEE
4. VSS
5. A
6. ch 1
7. ch 0
8. VDD
Control
INH
L
L
H
Don’t care
input
A
L
H ch 1
*
ON channel
ch 0
NONE
10
4) TA31136FN (XA0404)
Narrow Band FM IF IC
16 15 14 13 12 11 10 9
flflflflyn
0
n u m i
1 2 3 4 5 6 7 8
1. OSCIN
2. OSC OUT
3. MIX OUT
4 . Vcc
5. IF IN
6. DEC
7. FIL OUT
8. FILIN
9.AF OUT
10. QUAD
11. IF OUT
12. RSSI
13. N-DET
14. N-REC
15. GND
16. MIX IN
5) LA4425A (XA0410)
5W Audio Power Amplifier
Ö .
LA4425
***
12 3 4 5
1. Input
2. Small signal GND
3. Large signal GND
4. Output
5. Vcc
Test Circuit
11
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