Alinco DJ-G1E, DJ-G1T Service Manual

DJ-G1T/E

Service Manual

CONTENTS

• SPECIFICATIONS

1) General...................................................................2

2) Transmitter

3) Receiver..................................................................2

• CIRCUIT DESCRIPTION

1) Receiver System.............................................3 _ 5

2) Transmitter System

3) PLL Circuit...............................................................6

4) VCO Circuit.......................................................6 - 7

5) DTMF Circuit...........................................................7

6) Tone Squelch Circuit..............................................7

7) Terminal Function of Microprocessor

8) Terminal Function of IC302

9) Terminal Function of IC303.................................12

• SEMICONDUCTOR DATA

1) BU4094..................................................................13

2) CM8870CFIT.........................................................14

3) M5218FP...............................................................15

4) M5237ML.............................................................. 15

5) M67748L............................................................... 16

6) MB 1505................................................................ 16

7) MX265.................................................................. 17

8) MJM386.................................................................18

9) RN5VL45C............................................................18

10) X24C08S14-3.0T.................................................18

11) TK10930VTL.........................................................19

12)Transistor, Diode and LED Outline Drawings...20

13).LCD Connection..........................................21 -22

• EXPLODED VIEW

1) Front View 1..........................................................23

2) Front View 2.........................................................24

3) Rear View

4) Charge Unit..........................................................26

5) LCD......................................................................27

.............................................................2

........................................

.................................11

............................................................25

.........

5 , 6

8-10

• PARTS LIST

RF Unit..........................................................28-30

IF Unit............................................................31 - 33

CPU Unit........................................................33 - 34

VCO Unit...............................................................35

Charge Unit...........................................................35

Key Unit..................................................................36

PTT Unit................................................................ 36

TSQ Unit................................................................36

Mechanical Parts..................................................37

Packing.................................................................. 37

• ADJUSTMENT

1) DJ-G1T Adjustment.............................................38

2) DJ-G1E Adjustment.............................................39

3) Adjustment Points................................................40

• PC BOARD VIEW

1) RF Unit Side A......................................................41

2) RF Unit Side B......................................................42

3) IF Unit Side A........................................................43

4) IF Unit Side B........................................................44

5) CPU Unit Side A................................................... 45

6) CPU Unit Side B................................................... 46

7) VCO Unit...............................................................47

8) KEY Unit................................................................48

9) Charge Unit...........................................................48

10) PTT Unit................................................................48

• CIRCUIT DIAGRAM

1) RF Unit...................................................................49

2) IF Unit....................................................................50

3) CPU Unit................................................................51

4) KEY Unit............................................................... 52

5) Charge Unit......................................................... 52

6) CTCSS Unit.........................................................52

• BLOCK DIAGRAM...........................................................53

ALIN CO EL E C TR O N IC S INC

SPECIFICATIONS

1) General

Frequency Coverage:

Modulation:

Antenna Impedance: Antenna Connector: Power Supply Voltage: TX Current @7.2VDC HI/MID/LOW:

RX Current @AF 200mW 8ÎÎ:

Squelched:

Battery Save Mode: Frequency Stability: Dimensions W x H x D:

Weight:

RX: 108.000- 173.995MHz RX:440.000 ~ 449.995MHz

TX:144.000 - 147.995MHz

RX:144.000 - 145.995MHz

RX:430.000 - 439.995MHz TX:144.000 - 145.995MHz F3E A3 (receive only) 50£2 BNC

7.2-12.0V DC max.13.8VDC approx. i 0A/0.8A/0.4A

approx. 1.6A approx. 120mA

approx. 55mA approx. 25mA ave.

5p.p.m. 50mm x 116mm x 37mm 360gr.

(T version) (T version) (T version) (E version) (E version) (E version)

2) Transmitter

Output Power HI:

MID:

LOW: Modulation: Max. Deviation: Spurious Emission: Microphone Impedance:

3) Receiver

Receiving System: IF1st/2nd:

Sensitivity (12dB SINAD):

Selectivity -6dB:

-60dB

Spurious Ratio:

Audio Output (@10% distortion):

approx. 5W (13.8VDC) 1.5W (7.2V) approx. 1W approx. 0.2W Variable Reactance +/ -5kHz not more than -60dB 2kQ

Double Conv. Super-Heterodyne

30.85MHz/455kHz TX Band Center max. -16dBp. RX Subband Center (about 440MHz) max. -10dB(i not less than 12kHz not more than 30kHz not more than -60dB min. 200mW 8ii

CIRCUIT DESCRIPTION

1 ) Receiver System

The receiver system is the double superheterodyne. The first IF is 30.85MHz and the second IF is 455kHz.

1. Front End

108.00MHz~ 173.995MHz.

The receive signal is passed through a low-pass filter (L1, L2, L4, C3, C4, C5 and C7), resonator circuit (L12, varicap D7 and D8), and input to the RF

amplifier (Q6). The signal from Q6 is passed through resonator circuit (L13, varicap D10 and D11), resonator circuit (L15, varicap D13, D14), led to the first mixer Q8 and the signal is converted into the 30.85MHz. The resonator circuit (L12, L13, L15, varicap D7, D8, D10, D11, D13 and D14) is controlled by P/D voltage. The bandwidth characteristics is obtained the frequency of

108.00MHz~173.995MHz. The diodes (D9, D12, D15 and D22) are ON at

108.00MHz~ 139.995MHz, and they are OFF at 144.00MHz~173.995MHz.

Local oscillator signal from VCO is injected to the base of mixer (Q8). The radio uses the upper side superheterodyne.

420.00MHz~ 479.995MHz

The receive signal is passed through a high-pass filter (L10, L11, C31, C32

and C33), band switch (D16B), trap circuit (L18, C57, C58 and C59) and input to the RF amplifier (Q12). The signal from Q12 is passed through resonator circuits (L19 and C60), (L20, C64 and C65), led to the first mixer Q13 and the signal converted into 30.85MHz. Local oscillator signal is passed through the buffer amplifier (Q17), and injected to the base of mixer (Q13). The radio uses the upper side superheterodyne at 420.00MHz~

429.995MHz, and uses the lower side superheterodyne at 430.00MHz-

479.995MHz.

2. IF Circuit

3. Demodulator Circuit

800.00MHz-999.99MHz (DJ-G1E only)

The receive signal is passed through a high-pass filter (L10, L11, C31, C32 and C33), (printed coil, C67 and C69) and input to the RF amplifier (Q14). The signal from Q14 is led to the first mixer Q15 and the signal converted into the 30.85MHz. Local oscillator signal is input to the doubler amplifier (Q16), and injected to the base of mixer (Q15). The radio uses the lower

side superheterodyne.

The receive signal is mixed with the local signal in the mixer to gain the difference frequency of 30.85MHz. The unwanted frequency band of the first IF signal is eliminated by the monolithic crystal filter (FL302), and led to IF amplifier Q301.

FM and AM demodulators are built in the IC301(TK 10930). The AM circuit becomes active when Pin 14 of IC301 goes low.

The IF signal is amplified by the first IF amplifier of Q301, and input to Pin24

of IC301, where it is mixed with the second local oscillator signal (30.395MHz, X303) and so is converted into the second IF signal (455kHz).

The 455kHz second IF signal is output from Pin3 of IC301, and unwanted frequency band of the second IF signal is eliminated by a ceramic filter (FL301). The resulting signal is led to the Pin5 and 7 of IC301.

Demodulator of FM

The second IF signal of Pin7 of IC301 is led to the internal limiter amplifier, quadrature detection circuit. The audio signal is output from Pin 12 of IC301.

Demodulator of AM

The second IF signal of Pin5 of IC301 is led to the internal AM amplifier, AM detection circuit. The audio signal is output from Pin 13 of IC301. The AGC circuit is used to obtain a stable audio output level even if the input level is changed. The forward AGC signal is output from Pin 18 of IC301, and input to the AGC amplifier (Q326). The gain of the first IF amplifier is controlled by the AGC signal.

4. Audio Circuit

FM Mode

The audio signal from Pin12 of IC301, which is pre-emphasized on transmit ting, is led to the emphasis circuit (R334 and C338) and compensated for the audio frequency characteristics. The audio signal is amplified by AF amplifier (Q306), led to the audio H.P.F. (Q310, C346, C347 and R346). The audio signal is input to the volume (VR311), and input to the power amplifier Pin3 of IC305, and output from Pin6 to drive the speaker.

AM Mode

When you select the AM mode, switching transistors Q324, Q308 and Q309 become ON, and then Pin14 of IC301 goes to Low (AM detection circuit is

active), Q307 is active and Q306 is not active. The audio signal from Pin13 of IC301 is amplified by AF preamplifier (Q307), led to the audio H.P.F. (Q310, C346, C347 and R346), as well as in the FM mode, then input to the volume (VR311) and the power amplifier to drive the speaker.

Note

The IC301 (TK10930) of the FM detection circuit is active even in the AM mode, FM detector circuit is active. Q306 connects the base of the FM

audio preamplifier Q309 to the ground so that the FM audio signal by the FM detection is cut.

5. Squelch Circuit

The noise in the audio signal from Pin 12 of detection IC, IC301 is passed through the squelch control variable resistor (VR311) and input to the noise filter amplifier consisting of C323, C322, C325, R317 and R316, internal noise amplifier IC301. The desired noise of the audio signal is output from Pin20 of IC301 and so amplified by noise amplifier (Q305). The amplified noise signal is rectified by D302 and then input to Pin21 of IC301. When the voltage of Pin21 is above 0.7V, Pin22 of IC301 goes to "low" (squelch circuit is active). When the voltage of Pin21 is below 0.7V, Pin22 of IC301 goes to

"High" (squelch circuit does not work). This signal "SD" is led to the CPU Pin of IC401, and then processed by CPU. When the squelch circuit is

active, Q311 and Q304 are off. When the squelch circuit does not work, Q311 and Q304 are on. In this way the audio output signal is controlled.

When the squelch circuit does not work, Q323 goes on, the squelch indicator LED (D303B) light turns on. When the squelch circuit is active, Q323 goes

off, the squelch indicator LED (D303B) light turns off.

6. Audio Power

Amplifier Circuit

7. Signal Meter

Circuit

2) Transmitter System

1. Microphone Amplifier

Modulator Circuit

When the power supply voltage of radio becomes above 6.3V in the voltage stabilizer circuit (Q302, Q303, D301 and D304). The power supply voltage of audio power amplifier IC (IC305) is controlled below 6.3V. The voltage of audio power amplifier IC (IC305) is controlled by the Q304. The Q304 is ON when the squelch is OFF, BEEP sound is outputting, and DTMF monitor (TX) is ON, then IC305 works.

The IC301 has S meter function. When the signal strength is low, voltage of

Pin 16 becomes lower, and when the signal strength is high, voltage of Pin 16 becomes higher. The S meter voltage of Pin 16 is led to the variable

resistor (VR310) and input to the Pin of IC401 (CPU). It is converted by A/D

converter built-in CPU, and S is appeared in the LCD.

After the voice is converted into the electric signal through the internal or external microphone, the signal is led to the microphone amplifier IC304.

IC304 consists of two operational amplifiers. One operational amplifier (Pin5, 6 and 7) uses pre-emphasis circuit and IDC circuit, and the other operational amplifier (Pin1, 2 and 3) uses splatter filter. The output from the microphone amplifier is passed through variable resistors VR305 for maximum deviation

adjustment to cathode of varicap (D206) diode of the VCO, controlling the VCO frequency and so producing a frequency-modulation.

2. Power Amplifier

Circuit

3. APC Circuit

The signal from VCO is amplified by RF amplifier Q4 and drives amplifier Q3, and input to the power module Pin 1 of IC1. The signal is amplified by

power module IC1, and output from Pin5 of IC1, and then led to the low- pass filter (L6, C15, C16), the antenna switch circuit D1 and the low-pass filter (L1, L2, C3, C4 and C5). The unwanted harmonics frequency signal is eliminated by the low-pass filter and input to the antenna.

Part of the transmission power is passed through the C17, C11 and detected by D3. The detected DC voltage is amplified by Q2 and drives the Q1. This

voltage is controlled by the bias voltage of Pin3 of IC1 and collector voltage of RF amplifier Q3 to stabilize the transmission power. When the transmis sion power goes higher than the settled power, detected voltage by D3 goes

higher, collector voltage of Q1 goes to low. When the transmission power

goes lower than the settled power, detected voltage by D3 goes lower,

collector voltage of Q1 goes to high. The high power setting variable resistor

VR308 and the middle power setting variable resistor VR307 located in the IF unit. The radio has no low power setting variable resistor.

3) PLL Circuit

1. Reference Freq.

Circuit

2. Phase Comparator

Circuit

Power D306A D306B

The PLL serial data (clock, data, strobe) is sent from CPU IC401. The Pin9 of IC2 is clock, Pin10 of IC2 is data, Pin 11 of IC2 is strobe. The VCO signal

is amplified by RF amplifier Q19, and input to the Pin8 of IC2. The program mable divider of IC2 is determined by frequency data, and it divides (1/N)

input signal of IC2. Resulting signal will be 5kHz or 6.25kHz.

There are 8 channel steps (5, 10, 12.5, 15, 20, 25, 30 and 50kHz) of DJ- G1T/E. The reference frequency is obtained by divided by 2560 or 2048 reference oscillator (12.8MHz). The reference frequency (5kHz) uses a channel step of 5, 10, 15, 20, 25, 30 and 50kHz. The reference frequency (6.25kHz) uses a channel step of 12.5kHz.

The reference frequency of the IC2 is 5kHz or 6.25kHz. The VCO output frequency divided by N is compared with 5kHz or 6.25kHz in the phase comparator.

High Middle

OFF ON

ON OFF

Low

OFF OFF

3. Loop Filter Circuit

4) VCO Circuit

If the phase error should occur in PLL, the charge pump (Pin5 of IC2)

outputs the pulse. This signal is converted into DC voltage by PLL loop filter

(C84, C85, C86, R70, R71, R72 and R73), and input to the varicap diode (D202, D203, D204 and D205) in the VCO unit for the frequency control.

The frequency control voltage from the PLL circuit is input to the cathode of the varicap diode D202 (VC01), D203 (VC01), D204 (VC02) and D205 (VC02). The output frequency of VCO is amplified by RF amplifier Q203, and output from VCO unit. The circuit is Colpitts oscillator. To get the wide band receive range, the radio has two VCO's. To get the wide oscillation frequency range, the fixed capacitance in the VCO is set to the smallest value.

Oscillator

VC01 Q201 VC02

Q202

Tune Varicap

D202, D203

D204, D205

Modulation

Varicap

D206 D201

Shift

Switch

Each of the oscillation frequency of VC01 and VC02 is as follows.

5) DTMF Circuit

1. Encoder Circuit

2. Decoder Circuit

6) Tone Squelch

Oscillation Frequency

VC01

(TTX) (E TX)

VC02

(E)

The CPU has the DTMF encoder. The column signal is output from Pin98, and the row signal is output from Pin99. The DTMF signal is determined corresponding to the combination of the column and row. DTMF signal is passed through variable resistor for modulation adjustment, and input to the modulation terminal of VCO unit via the splatter filter.

The detected signal from IC301 is input to the DTMF decoder Pin2 of IC402. When the tone squelch decoder decodes the input tone signal frequency as

the programmed frequency, the decoded data is output from Pinll, 12, 13 and 14 processed in the CPU IC401.

138.85MHz~170.845MHz

170.85MHz~204.845MHz

134.575MHz~169.57MHz

144.00MHZ-147.995MHz

144.00MHz-145.995MHz

450.85MHz~460.845MHz

399.15MHz~419.145MHz

419.15MHZ-449.145MHz

384.575MHz~484.57MHz

Tune Varicap

108.00MHz~ 139.995MHz

140.00MHz~173.995MHz

420.00MHz~429.995MHz

430.00MHz~449.995MHz

450.00MHz~479.995MHz

800.00MHz~999.99M Hz

Circuit

1. Encoder Circuit

2. Decoder Circuit

The 4-bit digital codes are output from Pin 34, 35, 36 and 37 of CPU and

converted into the mimic sign wave with the R437 and R440. The sign wave

is input to the low-pass filter (R435, R436 and C419), AF amp Q313, and via the active low-pass filter (Q314, R359, R360, R363 and C364), input to the modulation terminal of VCO unit. 39 selectable tone frequency waves are provided.

The tone decoder unit EJ-16u is option. The detected signal from Pin 12 of IC301 is input to the Pin15of IC701 in the EJ-16uvia CN302. When the tone

squelch decoder decodes the input tone signal frequency as the pro grammed frequency, "high" signal is output from Pin9. When the tone squelch decoder does not decode the input tone signal frequency as the

programmed frequency, "low" signal is output from Pin9, and it is input to the CPU. Consequently the audio signal is controlled by CPU.

7) Terminal Function of Microprocessor

No. Pin Name

01 AVcc Vdd

11 X1

13 GND

AN0

AN1 MRC

AN2

AN3

AVss GND /

TEST

OSC1

OSC2

RESET

X2 NC O

DO FUNC I

D1 MONI I

Signal

BP1 A/D

+BD

SMT

Vdd I Connect to Vdd

Xin

Xout

RST

Vdd

GND /

Name

I/O

AD Converter Power Supply Terminal

A/D

Microphone Remote Control Input

A/D Power Supply Voltage Detection

S-Meter Input

A/D

AD Converter Ground

Description H L Remarks

I MCU Internal Clock Input

O MCI) Internal Clock Output

MCU Reset Input

Connect to Vdd

Open

Ground Terminal

Function Key Input

Monitor Key Input

18 D4

23 D9 STB2

25 D11/INT0

26 R 00/INT 1

30 RIO/TOB BEEP

D7 SCL

DIO/STOPC TSQD

R01/INT2

R02/INT3 R02 I

R03/INT4

R11/TOC 1750

PT5

PTT2

M.MUTE

LAM PC

SDA

STB1

Bu I

SD I

R01 I

DSlD I

PTT1 I

TICD

PTT Switch Input

I TX Low Power Input

0 Microphone Mute

Lamp ON/OFF

I/O Data for EEPROM

0 Clock for EEPROM

Strobe for PLL IC

I/O CTCSS Unit Detection and Strobe

I CTCSS Tone Detection Input

Back Up Signal Detection Input

SD Signal Input

Rotary Encoder Up Input

Rotary Encoder Down Input

DTMF Signal Detection Input

Beep Tone Output

Tone Burst (1750Hz) Output

R12/TOD DPD o

DTMF ON/OFF

No.

Pin Name

Signal Name I/O

Description

H L

Remarks

33 R13/EVNB

34 R20/EVND

38 R30/SEG1

39 R31/SEG2

40 R32/SEG3 DQ3

43 R41/SEG6

44 R42/SEG7 KIN2

R21/SCK

R22/SI

R23/SO TONE3 0

R33/SEG4 DQ4

R40/SEG5

R43/SEG8

R50/SEG9 KOUTO o Key Matrix Outputl

R51/SEG10

R52/SEG11 KOUT2

DTOE 0

TONEO 0

TONE1

TONE2 0

DQ1

DQ2

KIN0 I Key Matrix Inputl

KIN1

KIN3 I

KOÜT1

DTMF Signal Input

Sub Tone Signal Output

BP2 I DTMF 4-Bit Data Input

BP3

BP4

BP5

I DTMF 4-Bit Data Input I DTMF 4-Bit Data Input

DTMF 4-Bit Data Input

I Key Matrix Input2

Key Matrix Input3

Key Matrix Input4

o Key Matrix Output2 o Key Matrix Output3

49 R53/SEG12 KOUT3 o Key Matrix Output4

50 R60/SEG13 KOÜT4

51 R61/SEG14

R62/SEG15

R63/SEG16 STB3 o Strobe for 4094

54 R70/SEG17

55 R71/SEG18

56 R72/SEG19

R73/SEG20

58 SEG21 SEG4

61 SEG24

SEG22

SEG23 SEG6

SEG25

SEG26

SEG27

CLK

DATA

SEGO o SEG1 o LCD SEG1

SEG2

SEG3 o

SEG5

SEG7

SEG8

SEG9

SEG10

o Key Matrix Output5 o

Clock Signal

0 Data Signal

LCD SEGO

o LCD SEG2

LCD SEG3

o LCD SEG4

0 LCD SEG5

o LCD SEG6 o

LCD SEG7

o LCD SEG8

LCD SEG9

0 LCD SEG10

66 SEG29

SEG28

SEG11 o

SEG12

LCD SEG11

LCD SEG12

No. Pin Name Signal

Name I/O

Description H

Remarks

67 68 SEG31

69 70

71 72 SEG35 SEG18 73 SEG36 SEG19

74 75 SEG38 SEG21 0

76 SEG39 SEG22 0 77

78 79

80 SEG43 81 82

SEG30

SEG32 SEG15 SEG33

SEG34 SEG17 0

SEG37

SEG40 SEG41 SEG24 SEG42

SEG44 SEG45 SEG28 0 LCD SEG28

SEG13 O SEG14

SEG16 0

SEG20 0

SEG23

SEG25 0 LCD SEG25 SEG26

SEG27 0 LCD SEG27

LCD SEG13 LCD SEG14

LCD SEG15

LCD SEG16

LCD SEG17

0 LCD SEG18 0 LCD SEG19

LCD SEG20 LCD SEG21

LCD SEG22 LCD SEG23

LCD SEG24

0 LCD SEG26

83 84 SEG47

85 86 87

88 SEG51 SEG34

89 SEG52 SEG35 90 COM1

91 COM2 COM1 92

94 95 96 V3

97 98 TON EC

SEG46 SEG29

SEG30 0 LCD SEG30 SEG48 SEG31 SEG49

SEG50

COM3 COM2 0 COM4

V1 V2 VL2

Vcc Vdd

SEG32 0 LCD SEG32

SEG33 0

COMO 0 LCD COMO

VL1

VL3

DTONC

LCD SEG29

0 LCD SEG31

LCD SEG33 LCD SEG34

LCD SEG35

o LCD COM1

LCD COM2

/ LCD Power Supply

LCD Power Supply

/ /

LCD Power Supply

Power Supply

0 Column Output for DTMF Signal

99 TONER

100

VTref Vdd I

DTONR

Row Output for DTMF Signal

Reference Power Supply for DTMF Output

8) Te r min a l Function of IC 3 02

BU4094BF-T1

No. Pin Name Signal Name

01 02 03 04 05 Q2 06 Q3

08 Vss

09 Qs

11 12

13 14 15

STROBE

DATA

CLOCK

Os’ IC303 (2)

Q6 Q5

OUTPUT

STB3

DATA

AFPC

R5C O Power Supply Control for RX 5V AFS

GND

T5C

SUBC 0

360C

870C 0 Power Supply Control for 870 Band ON

C5V

I/O

I I I

Power Supply Control for AF Power Amp.

AF Switch

AM Switch

0 Power Supply Control for TX 5V ON

Power Supply Control for Sub Band ON Power Supply Control for 360 Band ON

Description

H L

ON ON

Remarks

16 Vdd

C5V

9) Te r mina l Fun c t io n of IC3 03

BU4094BF-T1

No. Pin Name

01 STROBE 02

03 CLOCK 04 05 Q2 VC02C 06 07 Q4

08 09 Qs 10

11 12 13 14 15

DATA DATA I

Vss

Os' Q8

Q7 P5C Q6 Q5 HI

OUTPUT

Signal

STB3

CK I

MAINC O Power Supply Control for Main Band

VC01C O Power Supply Control for UHF VCO ON

SWC GND

MID

C5V

Name

I/O Description H L

IC302 (10)

O Power Supply Control (or VHF VCO ON

O VHF VCO Shift ON/OFF

Power Supply ON/OFF of VCO and PLL

O O TX Middle Power Control

TX High Power Control ON

ON ON

Remarks

Vdd

Power Control Table

C5V

SE MI CO ND UC TO R DA T A

1) B U40 9 4 (XA0246)

8-Stage Shift Register

STROBE HZ

Vdd

Function Table

Clock

s ~

Output enable

L X

H H

DATA \zz

CLOCK

Vss

Strobe

L X No Chg. No Chg. 0 7 No Chg.

Data

cz cz

ÜZ

r z

n z

Parallel outputs Serial outputs

Q 1

Z Z

00 c

-U 03

Qn Qs Q's

Qn-l

z □

Z J

ZZ1 Q7

10 Q's

Q7 No Chg.

No Chg.

Q7 No Chg.

Output Enable

!k -

Z=High Impedance X=Don't Care

H X X

Block Diagram

H H

Q1 PARALLEL Q8

No Chg. No Chg. No Chg.

OUTPUT

Qn-1

Q7 No Chg.

2) CM8870CFIT (XA0231)

CTCSS Encoder/Decoder

Function Table

Name Description IN+ Inverting Input

IN- GS Gain Selection

Vref Reference Voltage Output INH PD Power Down Control OSC1

OSC 2

Vss

TOE Q1

Q2 Q3 Q4

StD ESt

St/GT Steering Input/Guard Time Output Vdd Positive Power Supply

Noninverting Input

Clock Input Clock Output

Negative Power Supply

Three State Output Enable

Three State Output (RX Data Output)

Delay Steering Output First Steering Output

IN+

IN-

Vref

cz=

INH

cz:

OSC1

OSC2

Vss cz

3 16

Decode Ta

F high Key TOE

F low

697 1209 697 1336 697 1477 770 1209 4 H 0 770

1336 5 H 0 1 0 1

770 1477

1209 7 H 0

852

1336 8 H 1 0

852

1477

852 641 1336 941 1209 941 1477

697

1633 770 1633 B H 1 1 852 1633 C H 1 1 1 941

1633

L: Logic Low, H: Logic High, Z=High Impedance.

Vdd

St/Gt

ESt

ZD IZ)

StD

ZZ 0 4

ZZl 03

ZZI

TOE

ble

H 0 0

9 0 H

# H 1 1 0 0

A H

ANY

. 0

H 1 0

L z

0 1

1 1

0 0

0 0 0

02 Q1

0 1 1 0 1

0 0

1 0 0 1 1 1

0 1

3 ) M 5 218FP (X A00 68)

Dual Low Noise

Operational Amplifiers

Inverting Input 1 2 [

Noninverting Input 1 3 [

Power Supply Minus 4 I

4 ) M5237ML (X A02 1 7 )

Voltage Regulator

Test Circuit

Vi Vo

Output 1 1 I

I e Power Supply Plus

| 7 Output 2

| 6 Inverting Input 2

I 5 Noninverting Input 2

M5237ML

5) M67748L (XA0148) 135~150MHz 7W RF Power Module

6) MB1505 (XA0240) PLL Frequency Synthsizer

OSCin

CZZ

Fin(Ground)

OSC o u tIZ Z

czz

Vcc

czz

CZ Z

GND

c z

fin

czz

_ l

o cn

Function Table

No.

Name I/O

OSCin I

OSCout o Reference oscillator output terminal

2 3 Vp 4

Vcc 5 6

7 8 fin 9

10 Data I Serial data input terminal 11 LE 12 FC I Phase switch input terminal 13 BiSW 0 Analogue switch output terminal 14

15 0 P o Phase detector output terminal for external charge pump

16 oR o

Do 0 Internal charge pump output terminal

GND

Clock I Clock input terminal

tout o

Reference oscillator input terminal

Charge pump output terminal Power supply terminal

Ground terminal

Phase detector output terminal Locked: H

Prescaler input terminal

Load enable signal input terminal

Phase detector input monitor terminal H: (r, L: fp

Phase detector output terminal for external charge pump

Function

zn z□

ZD FC

ZZ3

= □

(out

BiSW

Data

Clock

7) MX265 (XA0241 )

CTCSS Encoder/Decoder

6Bp

a <5

'p L iZ l

MX265DW

XTAL/CLOCK Vdd

XTAL TONE IN

LOAD/LATCH

SERIAL ENABLE RttTX

SERIAL DATA TONE OUT

SERIAL CLOCK RX DETECT

NC DECODE COMP. IN

VSS

J T

BIAS

RX DECODE

0.1MF

HI—

O.IijF

-«—II

----

O.lnF

-----II---

0.1MF

560K

-vw—

- 4 - » -

X°.,mf

Xtal/Clock: Input to the on-chip inverter used with a

1 MHz Xtal or external clock source.

Xtal: Output of the on-chip inverter (clock output).

Load/Latch: Controls 8 on-chip latches and is used to

latch RX/TX, PTL, and D0-D5. This pin is internally pulled to Vdd. A logic "1" applied to this input puts the 8

latches in "transparent" mode. A logic “0" applied to this

input puts the 8 latches in the "latched" mode. Data is

loaded and latched by a 0-1 -0 strobe pulse on this pin.

Serial Enable: A logic "0" applied to this input will enable serial programming. This pin is internally pulled to Vdd.

Serial Data Input: This is the serial data input. Data is

loaded in the following order: D5, D4, D3, D2, D1, DO, RX/TX and PTL. This pin is internally pulled to Vdd.

Serial Clock Input: Data is clocked on the positive going edge. This pin is internally pulled to Vdd.

Decode Comparator Input: This is the inverting input of the decode comparator. This pin is normally connected to the integrated output of the RX Tone

Detect line.

Rx Tone Detect: In Rx mode this pin will go to logic "1" during a successful decode. It must be externally integrated to control response and deresponse times.

Tx Tone Out: The CTCSS sinewave output appears on

this pin under the control of the RX/TX pin. This pin,

when not transmitting a tone, may be biased to Vdd -

0.7V or O/C.

Rx/Tx: This input selects Rx or Tx modes . This

function may be selected by this pin, or It may be serially loaded. This pin is internally pulled to Vdd via a 1 MC2

resistor.

Bias: This pin is the output of an internally generated Vdd/2 bias level and would normally be externally

decoupled to Vss via capacitor C6.

Vss: Negative supply.

RX Tone Decode Out: This is the gated output of the

decode comparator. This output is used to gate the RX Audio path. A logic "0" on this pin indicates a successful

decode and that the Decode Comparator Input pin is more positive than the Decode Comparator Ref. input.

Tone Input: This is the input to the CTCSS tone detector. It is internally biased to Vdd/2.

Vdd: Positive Supply.

8) NJM386 (XA0061) Power Amplifiers

V+=9V RL=16fi Po=500mW

9) RN5VL45C (XA0232) Voltage Detector

Equivalent Circuit

Gain

-Input

+tnput

GND

n z

c =

c_ 5

0 0

CT>

Gain

Bypass

Vout

10) X24C08S14-3.0T (XA0226)

EEPROM 256 x 8Bit

NC IZ Z

AO d

A1 [ZZ

NC C Z

A2 C Z

Vss IZ Z

NC C Z

ro « h

0 0

6 9

7 8

Z Z NC

ZZ1 Vcc

IZ I TEST

Z Z I NC

Z Z SCL

IZ I SDA

Z ZI NC

Out Vdd Vss

Pin Names

Symbol Description

A0-A2

SDA Serial Data SCL Serial Clock

TEST

Vss Ground Vcc

NC No Connect

Adress Inputs

Supply Voltage

Hold at Vss

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