AES 7880 Users Manual

HEC

.

L9N-7880

DATA TRANSCEIVERS

PLL SYNTHESIZED

Service Manual

UHF

HERMES ELECTRONICS CO., LTD.

1. SPECIFICATION

GENERAL SPECIFICATIONS

POWER SOURCE ………………………………………+5VD.C.
TEMPERATURE RANGE
STORAGE ……………………………………….80℃ maximum -40℃ min.
25℃ nominal
OPERATING …………………………………….60℃ maximum -20℃ min.
ANTENNA IMPEDANCE ………………………………...50Ω
FREQUENCY CONTROL …………………………………...PLL SYNTHESISER
FREQUENCIES OF OPERATION ………………………..402MHZ-470MHZ
FREQUENCY TOLERANCE AND STABILITY …………±2.5PPM
HIGH HUMIDITY ………………………………………….90﹪
CHANNEL CAPABILITY ………………………………….1
NOMINAL DIMENSIONS ………………………………….40 ㎜(L)X30 ㎜(W)X20 ㎜(H)
WEIGHT ……………………………………………………….16g

RADIO DATA TRANSCEIVER NOMINAL PERFORMANCE

PERFORMANCE SPECIFICATIONS ………………………...FCC part 90
RF OUTPUT POWER ……………………………………..0.7w
MODULATION TYPE ……………………………………….FM
INTERMEDIATE FREQUENICES ………………………….307.2 khz

CHANNEL SPACING ………………………………………..25KHZ
TRANSMIT ATTACK TIME …………………………＜25 mS
CURRENT CONSUMPTION
TRANSMIT ……………………………….520mA@0.7W
RECEIVE ………………………………..2.5mA

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14.7456 MHz VCTCXO

An external clock signal from VCTCXO X1 is connect to CC1020 XOSC_Q1 , This VCTCXO is only
5x3.2x1.4(H) mm, and is manufactured with a ceramic base and metal lid to assure very good aging
characteristics and reliability. This device offers an in ±2.5PPM over -30 to +75 Celsius. The VR1 is used
to adjust the frequency is as close as possible to the exact required transmit frequency. Ideally it should be
within 100 Hz at room temperature.

PA module

The U2 is a power amplifier IC as the final RF amplifier in the 400MHz to 480MHz band.

Low pass filter

The amplifier RF signal is through the harmonic low pass filter, comprising L63 to L65 and C62-C66 and
then to the antenna connector J1.

Antenna switch

When transmitting, the diode D61 and D60 are forward biased, allowing the RF to pass to the antenna. D60
is shorted to ground which makes L61 look open circuit (1/4 wave tuned stub ). This prevents the TX signal
from passing to the receiver stage.

Microcontroller interface

Used in a typical system, CC1020 will interface to a microcontroller. This microcontroller must be able to:

. Program CC1020 into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK,

and PSEL)

. Interface to the bi-directional synchronous data signal interface (DIO and DCLK)
. Optionally, the microcontroller can do data encoding / decoding
. Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status,

or other status information

. Optionally, the microcontroller can read back digital RSSI value and other status information via 4-wire

serial interface

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DI, PDO and PCLK are high impedance inputs as long as PSEL is not

Configuration interface

The microcontroller interface is shown in figure 5. The microcontroller uses 3 or 4 I/O pins for the

configuration interface(PDI, PDO, PCLK and PSEL). PDO should be connected to an input at the
microcontroller. PDI, PCLK and PSEL muse be microcontroller outputs. One I/O pin can be saved if PDI
and PDO are connected together and a bi-directional pin is used at the microcontroller.

The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the

configuration interface is not used. P
activated (active low).

PSEL has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a

high level during power down mode in order to prevent a trickle current flowing in the pull-up.

Signal interface

A bi-directional pin is used for data (DIO) to be transmitted and data received. DCLK providing the data

timing should be connected to a microcontroller input.

As an optional, the data output in receive mode can be made available on a separate pin.

PLL lock signal

Optionally, one microcontroller pin can be used to monitor the lock signal. This signal is at low logic level

when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test signals.

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