AEROFLEX ACT5271 Service Manual

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ACT5271

64-Bit Superscaler Microprocessor

Features

Full militarized QED RM5271 microprocessor

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Dual Issue superscalar microprocessor - can issue one

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integer and one floating-point instruction per cyc le

150, 200, 250 MHz operating frequencies – Consult Factory for

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lates t speeds

345 Dhrystone2.1 MIPS maximum

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SPECInt95 7.3, SPECfp95 8.3 maximum

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High performance system interfa ce com patible with RM7000,

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RM5270, RM5260, RM5261, R4600, R4700 and R5000

Up to 125MHz memory bus operation for a 1000MBps bandwidth

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from CPU to L2 cache and main memory

64-bitmultiplexed system address/data bus for optimum price/

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performanc e with high performance writ e protocols t o maximize
uncached write ba ndw idth

Suppor ts 1/2 c lock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)

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IEEE 1149.1 JTA G boundary scan

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Integrated on-c hip caches

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32KB/32KB inst ruction /data -both 2 way set associative

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Virtually indexed, physically tagged

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Write-back and write-through on per page basis

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Pipeline restart on first double for data cache misses

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Integrated secondary cache controller (R5000 compatible)

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Supports 512K or 2MByte block write-through secondary

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Integrated memory management unit

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Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pa ges

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Variable page size (4KB to 16MB in 4x increments)

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High-performance floating point unit - up to 532 MFLOPS

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Single cycle repeat rate for common single precision operations

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and some double precision operations

Two cycle repeat rate for double precision multiply and double

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precision combined multiply-add operations

Single cycle repeat rate for single precision combined multiply-

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add operation

MIPS IV instructi on set

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Floating point multiply-add instruction increases performance in

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signal processing and graphics applications

Conditional moves to reduce branch frequency

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Index address modes (register + register)

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Embedded application enhancements

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Specialized DSP integer Multiply-Accumulate instruction and 3

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operand multiply instruction

I and D cache locking by set

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Optional dedicated exception vector for interrupts

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Fully static CMOS design with power down logic

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Standby reduced power mode with WAIT instruction

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4.2 Watts typical power @ 200MHz

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2.5V core with 3.3V IO’s

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208-lead CQFP, cavity-up package (F17)

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208-lead CQFP, inverted footprint (F24), Intended to duplicate

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the commercial QED footprint
179-pin PGA package (

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Future Product)

(P10)

BLOCK DIAGRAM

Preliminary

eroflex Circuit

Technology

– RISC TurboEngines For The Future © SCD5271 REV 1 12/22/98

DESCRIPTION

The Aeroflex ACT5271 is a highly integrated
superscalar microprocessor that implements a
superset of the MIPS IV Instruction Set
Architect ure(I SA). It has a hig h pe rform an ce 64 -bit
integer unit, a high throughput, fully pipelined 64-bit
floating point unit, an operating system friendly
memory management unit with a 48-entry fully
associative TLB, a 32 KByte 2-way set associative
instruction cac he, a 32 KByte 2 -way set assoc iative
data cache, and a high-performance 64-bit system
interface with support for an optional external
secondary cache. The ACT5271 can issue both an
integer an d a float ing point instruc tion in the s ame
cycle.

The ACT5271 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.The ACT5271 is also applicable to the
low end workstation market where its balanced
integer and floating-point performance and direct
support for a large secondary cache (up to 2MB)
provide outstanding price/performance

HARDWARE OVERVIEW

The ACT527 1 offers a high-level of int egration
targeted at high-performance embedded
applications. The key elements of the ACT5271
are briefly des c ribed below.

Superscalar Dispatch

The ACT5271 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer ins t ruction an d a floating- point comput at ion
instruction simultaneously. With respect to
superscal ar issue, i nteger ins tructions in clude alu ,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-a dd, conver ts, etc. In c ombinatio n with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT527 1 pro vide s un pa rallele d p rice /perfo rman ce
in computationally intensive embedded
applications.

addition to this standard pipeline, the ACT5271
uses an extended seven stage pipeline for
floating-point operations. Like the ACT5270 and
R5000, the ACT5271 does virtual to physical
transla ti on in parallel wit h c ac he access.

Integer Unit

Like the other members of the ACT52xx family
and R5000, the ACT5271 implements the MIPS IV
Instruction Set Architecture, and is therefore fully
upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the
ACT5271 includes two implementation specific
instruct ions no t found in t he base line MIPS IV ISA
but tha t are u seful in t he em bedded marke t place.
Described in detail in the QED R M 5271 datas heet,
these instructions are integer multipl y-accumulate
and 3-operand integer multiply.

The ACT5271 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer m ultiply/divid e operations , a nd t he program
counte r(PC).

Register File

The ACT5271 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.

ALU

The ACT5271 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perf orm all ti o ns
in a single processor c y cl e.

CPU Registers

Like all MIPS ISA processors, the ACT5271 CPU
has a simple, clean user visible state consisting of
32 gene ral purpo se regi sters, two sp ecial pu rpose
registers for integer multiplication and division, a
program c ounter, and n o c ondition code bit s .

Pipeline

For integ er operations, loa ds, stores, and oth er
non-floating-point operations, the ACT5271 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In

Aeroflex Circuit Technology SCD5271 REV 1 12/22/98 Plainview NY [phone]

For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark ACT5271, 64-Bit Superscalar
Microprocessor see the latest QED datasheet
(Revision 1.0 July 1998).

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