ACT ACT-SF512K32N-39P1T, ACT-SF512K32N-39P1Q, ACT-SF512K32N-39P1M, ACT-SF512K32N-39P1I, ACT-SF512K32N-39P1C Datasheet

ACT-SF512K32 High Speed

512Kx32 SRAM / 512Kx32 Flash

Multichip Module

FEATURES

■4 – 512K x 8 SRAMs & 4 – 512K x 8 Flash Die in One MCM

■Access Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash)

■Organized as 512K x 32 of SRAM and 512K x 32 of Flash Memory with Common Data Bus

■Low Power CMOS

■Input and Output TTL Compatible Design

■MIL-PRF-38534 Compliant MCMs Available

■Decoupling Capacitors and Multiple Grounds for Low Noise

■Commercial, Industrial and Military Temperature Ranges

■Industry Standard Pinouts

■TTL Compatible Inputs and Outputs

■Packaging – Hermetic Ceramic

●66–Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)"

●68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x

.20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)

CIRCUIT TECHNOLOGY

www.aeroflex.com

FLASH MEMORY FEATURES

■Sector Architecture (Each Die)

●8 Equal Sectors of 64K bytes each

●Any combination of sectors can be erased with one

command sequence

■+5V Programing, +5V Supply

■Embedded Erase and Program Algorithms

■Hardware and Software Write Protection

■Page Program Operation and Internal Program Control Time.

■10,000 Erase/Program Cycles

			E		X	L	A
		L
	O	F					B
								S
R			ISO
									C
A
E									I
									N
			9001
									.
C								D
		E	R			I
				T I F			E

Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2)

FWE1 SWE1

FWE

2

SWE

2

FWE3 SWE3

FWE4 SWE4

PIN DESCRIPTION

I/O0-31

Data I/O

OE

A0–A18

A0–18

Address Inputs

SCE

FWE

1-4

Flash Write Enables

FCS

SWE

1-4

SRAM Write Enables

Flash Chip Enable

FCE

512K X 8 FLASH

512K X 8 FLASH

512K X 8 FLASH

512K X 8 FLASH

SRAM Chip Enable

512K X 8 SRAM

512K X 8 SRAM

512K X 8 SRAM

512K X 8 SRAM

SCE

Output Enable

OE

NC

Not Connected

VCC

Power Supply

GND

Ground

I/O0-7

I/O8-15

I/O16-23

I/O24-31

eroflex Circuit Technology - Advanced Multichip Modules © SCD3852 REV A 5/20/98

Absolute Maximum Ratings

Symbol

Rating

Range

Units

TC

Operating Temperature

-55 to +125

°C

TSTG

Storage Temperature

-65 to +150

°C

VG

Maximum Signal Voltage to Ground

-0.5 to +7

V

TL

Maximum Lead Temperature (10 seconds)

300

°C

Parameter

Flash Data Retention

10 Years

Flash Endurance (Write/Erase Cycles)

10,000

Normal Operating Conditions

Symbol

Parameter

Minimum

Maximum

Units

VCC

Power Supply Voltage

+4.5

+5.5

V

VIH

Input High Voltage

+2.2

VCC + 0.3

V

VIL

Input Low Voltage

-0.5

+0.8

V

Capacitance

(VIN = 0V, f = 1MHz, TC = 25°C)

Symbol

Parameter

Maximum

Units

CAD

A0 – A18 Capacitance

80

pF

COE

Capacitance

80

pF

OE

CWE1-4

F/S Write Enable Capacitance

30

pF

CCE

F/S Chip Enable Capacitance

50

pF

CI/O

I/O0 – I/O31 Capacitance

30

pF

This parameter is guaranteed by design but not tested

DC Characteristics

(VCC = 5.0V, VSS = 0V, TC = -55°C to +125°C)

Parameter

Sym

Conditions

Min

Max

Units

Input Leakage Current

ILI

VCC = Max, VIN = 0 to VCC

10

µA

=

= VIH,

= VIH,

Output Leakage Current

ILO

FCE

SCE

OE

10

µA

VOUT = 0 to VCC

SRAM Operating Supply Current x 32

= VIL

= VIH, f = 5MHz, VCC =

ICCx32

SCE

, OE

550

mA

Mode

Max, FCE = VIH

=

= VIH,

= VIH, f = 5MHz,

Standby Current

ISB

FCE

SCE

OE

80

mA

VCC = Max

SRAM Output Low Voltage

VOL

IOL = 8 mA, VCC = Min,

= VIH

0.4

V

FCE

SRAM Output High Voltage

VOH

I = -4.0 mA, , V

= Min,

= V

2.4

V

CC

FCE

IH

OH

Flash Vcc Active Current for Read (1)

ICC1

= VIL,

= VIH,

= VIH

260

mA

FCE

OE

SCE

Flash Vcc Active Current for Program

ICC2

300

mA

FCE = VIL, OE = VIH, SCE = VIH

or Erase (2)

Flash Output Low Voltage

VOL

IOL = 12 mA, VCC = Min,

= VIH

0.45

V

SCE

Flash Output High Voltage

VOH1

= VIH

0.85 x VCC

V

IOH = -2.5 mA, , VCC = Min, SCE

Flash Low Vcc Lock Out Voltage

VLKO

3.2

4.2

V

Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The

frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

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SRAM AC Characteristics

(VCC = 5.0V, VSS= 0V, Tc= -55°C to +125°C)

Read Cycle

	Parameter	Symbol	–025		–035		Units
			Min Max		Min Max
	Read Cycle Time	tRC	25		35		ns
	Address Access Time	tAA		25		35	ns
	Chip Select Access Time	tACE		25		35	ns
	Output Hold from Address Change	tOH	0		0		ns
	Output Enable to Output Valid	tOE		12		25	ns
	Chip Select to Output in Low Z *	tCLZ	2		4		ns
	Output Enable to Output in Low Z *	tOLZ	0		0		ns
	Chip Deselect to Output in High Z *	tCHZ		12		15	ns
	Output Disable to Output in High Z *	tOHZ		12		15	ns
	* Parameters guaranteed by design but not tested

Write Cycle

Parameter		Symbol	–025		–035		Units
			Min Max		Min Max
Write Cycle Time		tWC	25		35		ns
Chip Select to End of Write		tCW	17		25		ns
Address Valid to End of Write		tAW	17		25		ns
Data Valid to End of Write		tDW	13		20		ns
Write Pulse Width		tWP	17		25		ns
Address Setup Time		tAS	2		2		ns
Output Active from End of Write *		tOW	4		4		ns
Write to Output in High Z *		tWHZ		13		15	ns
Data Hold from Write Time		tDH	0		0		ns
Address Hold Time		tAH	0		0		ns
* Parameters guaranteed by design but not tested

Truth Table

Mode		SCE			OE			SWE		Data I/O	Power
Standby		H			X			X		High Z	Standby
Read		L			L			H		Data Out	Active
Output Disable		L			H			H		High Z	Active
Write		L			X			L		Data In	Active

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Timing Diagrams — SRAM

Read Cycle Timing Diagrams

Read Cycle 1 (SCE = OE = VIL, SWE = VIH)

tRC

A0-18

tAA

tOH

DI/O	Previous Data Valid	Data Valid

Read Cycle 2 (SWE = VIH)
	tRC
A0-18
	tAA
SCE	tACE
		tCHZ
	tCLZ	SEE NOTE
OE	SEE NOTE
	tOE	tOHZ
		SEE NOTE
	tOLZ
	SEE NOTE
DI/O	High Z	Data Valid
	UNDEFINED	DON’T CARE

	Write Cycle Timing Diagrams
	Write Cycle (SWE Controlled, OE = VIH)
	tWC
	A0-18
	tAW		tAH
	tCW
	SCE
	tAS	tWP
	SWE
	tWHZ		tOW
		tDW	tDH
	SEE NOTE

DI/O				Data Valid

Write Cycle (SCE Controlled, OE = VIH )

	tWC
A0-18
	tAW	tAH
tAS	tCW
SCE
	tWP
SWE
	tDW	tDH

DI/O		Data Valid

Note: Guaranteed by design, but not tested.

AC Test Circuit

Current Source

IOL

AC Test Conditions

Parameter

Typical

Units

To Device Under Test

VZ ~ 1.5 V (Bipolar Supply)

Input Pulse Level

0 – 3.0

V

Input Rise and Fall

5

ns

CL = 50 pF

IOH

Input and Output Timing Reference Level

1.5

V

Current Source

Notes:

1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance

ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.

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