Acer X3 Service Guide

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X3 System
Service Guide
PART NO.: 49.59902.001 DOC. NO.: SG255-9801A PRINTED IN TAIWAN
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Copyright

Copyright 1998 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written permission of Acer Incorporated.
Disclaimer
Acer Incorporated makes no representations or warranties, either expressed or implied, with respect to the contents hereof and specifically disclaims any warranties of merchantability or fitness for any particular purpose. Any Acer Incorporated software described in this manual is sold or licensed "as is". Should the programs prove defective following their purchase, the buyer (and not Acer Incorporated, its distributor, or its dealer) assumes the entire cost of all necessary servicing, repair, and any incidental or consequential damages resulting from any defect in the software. Further, Acer Incorporated reserves the right to revise this publication and to make changes from time to time in the contents hereof without obligation of Acer Incorporated to notify any person of such revision or changes.
All brand and product names mentioned in this manual are trademarks and/or registered trademarks of their respective companies.
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About this Manual

Purpose
This service guide aims to furnish technical information to the service engineers and advanced users when upgrading, configuring, or repairing the X3 system.
Manual Structure
This service guide contains technical information about the X3 system. It consists of three chapters and five appendices.
Chapter 1 System Introduction
This chapter describes the system features and major components. It contains the X3 system board layout, block diagrams, cache and memory configurations, power management and mechanical specifications, and operation theory.
Chapter 2 Major Chipsets
This chapter describes the features and functions of the major chipsets used in the system board, including the Pentium Pro processor. It also includes chipset block diagrams, pin diagrams, and pin descriptions.
Chapter 3 BIOS Setup Utility
This chapter describes the parameters in the BIOS Utility screens.
Appendix A Model Definition
This appendix shows the different configuration options for the X3 system.
Appendix B Spare Parts List
This appendix lists the spare parts for the X3 system with their part numbers and other information.
Appendix C Schematics
This appendix contains the schematic diagrams for the system board.
Appendix D Silk Screen
This appendix illustrates the system board silk screen.
Appendix E BIOS POST Check Points
This appendix lists and describes the BIOS POST check points.
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Conventions

The following are the conventions used in this manual:
Text entered by user Represents text input by the user.
Screen messages
, , , etc. Represent the actual keys that you have to press on the
Denotes actual messages that appear onscreen.
keyboard.
NOTE
Gives bits and pieces of additional information related to the current topic.
WARNING
Alerts you to any damage that might result from doing or not doing specific actions.
CAUTION
Gives precautionary measures to avoid possible hardware or software problems.
IMPORTANT
Reminds you to do specific actions relevant to the accomplishment of procedures.
TIP
Tells how to accomplish a procedure with minimum steps through little shortcuts.
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Table of Contents

Chapter 1 System Introduction
1.1 Configuration Overview....................................................................................... 1-1
1.1.1 Front Panel........................................................................................... 1-1
1.1.2 Rear Panel............................................................................................ 1-6
1.2 Features.............................................................................................................. 1-7
1.2.1 Intel Pentium Pro Microprocessor.......................................................... 1-7
1.2.2 System Architecture.............................................................................. 1-8
1.2.3 SCSI Disk Array.................................................................................... 1-9
1.2.4 Server Management.............................................................................1-10
1.2.5 Redundant Power Supply Subsystem ...................................................1-10
1.2.6 Security................................................................................................1-10
1.2.7 Memory Board .....................................................................................1-10
1.2.8 Major Components...............................................................................1-11
1.3 Board Layouts.....................................................................................................1-12
1.3.1 System Board ......................................................................................1-12
1.3.2 Memory Board .....................................................................................1-13
1.3.3 SCSI Disk Array Backplane Board........................................................1-13
1.3.4 RDM Module........................................................................................1-14
1.4 Jumpers and Connectors....................................................................................1-15
1.4.1 Jumper Settings...................................................................................1-16
1.4.2 Connector List......................................................................................1-18
1.5 System Board Specifications ..............................................................................1-20
1.6 Hardware Configurations.....................................................................................1-21
1.6.1 Memory Configurations........................................................................1-21
1.6.2 Video Memory Specification.................................................................1-23
1.6.3 Video Display Modes and Refresh Rates..............................................1-23
1.6.4 Parallel Port Configurations..................................................................1-24
1.6.5 Serial Port Configurations ....................................................................1-24
1.6.6 Memory Address Map ..........................................................................1-24
1.6.7 Interrupt Channels Map........................................................................1-25
1.6.8 I/O Address Map..................................................................................1-26
1.7 Block Diagrams...................................................................................................1-27
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1.7.1 System Block Diagram......................................................................... 1-27
1.7.2 Memory Controller Block Diagram........................................................1-28
1.7.3 Memory Interleaving Block Diagram ....................................................1-29
1.7.4 System Clock Diagram.........................................................................1-30
1.7.5 Interrupt Distribution Logic Diagram.....................................................1-31
1.7.6 Dual-processor Operation Diagram......................................................1-32
1.8 Power Requirements...........................................................................................1-33
1.8.1 400W Power Supply for IDX-2..............................................................1-33
1.9 Mechanical Specifications...................................................................................1-35
1.9.1 IDX-2 Housing...................................................................................... 1-35
1.10 Shipping Configuration........................................................................................1-37
1.11 Cable Connections..............................................................................................1-38
Chapter 2 Major Chipsets
2.1 Pentium Pro processor (P6) ..................................................................................2-1
2.1.1 Features.................................................................................................2-1
2.1.2 Pin Diagram...........................................................................................2-4
2.1.3 CPU ID ..................................................................................................2-5
2.1.4 Signal Types..........................................................................................2-6
2.1.5 Signal Descriptions ................................................................................2-8
2.2 Memory Interface Component (S82451GX).......................................................2-33
2.2.1 Features...............................................................................................2-33
2.2.2 S82451GX Pin Diagram.......................................................................2-34
2.2.3 S82451GX Signal Descriptions ............................................................2-35
2.3 Data Path Chipset (S82452GX) .........................................................................2-36
2.3.1 Features...............................................................................................2-36
2.3.2 S82452GX Pin Diagram.......................................................................2-38
2.3.3 S82452GX Signal Descriptions ............................................................2-39
2.4 DRAM Control Chipset (S82453GX) ..................................................................2-41
2.4.1 S82453GX Pin Diagram.......................................................................2-41
2.4.2 S82453GX Signal Descriptions ............................................................2-42
2.5 PCI Bridge (S82454GX).....................................................................................2-44
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2.5.1 Features...............................................................................................2-44
2.5.2 S82454GX Block Diagram ...................................................................2-46
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2.5.3 S82454GX Pin Diagram.......................................................................2-47
2.5.4 S82454GX Signal Descriptions.............................................................2-48
2.6 SIO (82379AB)..................................................................................................2-51
2.6.1 Features...............................................................................................2-51
2.6.2 82379AB Block Diagram......................................................................2-53
2.6.3 82379AB Pin Diagram..........................................................................2-54
2.6.4 82379AB Signal Descriptions...............................................................2-55
2.7 EISA System Component (82374SB).................................................................2-64
2.7.1 Features...............................................................................................2-64
2.7.2 Block Diagram .....................................................................................2-66
2.7.3 Pin Diagram.........................................................................................2-67
2.7.4 Signal Descriptions ..............................................................................2-68
2.8 PCI-EISA Bridge (82375SB)...............................................................................2-92
2.8.1 Features...............................................................................................2-92
2.8.2 Block Diagram .....................................................................................2-94
2.8.3 Pin Diagram.........................................................................................2-95
2.8.4 Signal Descriptions ..............................................................................2-96
2.9 SCSI Controller (AIC 7880)............................................................................... 2-111
2.9.1 Features.............................................................................................2-111
2.9.2 Block Diagram ...................................................................................2-114
2.9.3 Pin Diagram.......................................................................................2-115
2.9.4 Signal Descriptions ............................................................................2-116
2.10 ATI 264VT ........................................................................................................2-127
2.10.1 Features.............................................................................................2-127
2.10.2 Block Diagram ...................................................................................2-128
2.10.3 Pin Diagram.......................................................................................2-129
2.10.4 Signal Descriptions ............................................................................2-130
2.10.5 Display Modes....................................................................................2-135
2.11 Super I/O Controller (SMC 37C935)................................................................. 2-136
2.11.1 Features.............................................................................................2-136
2.11.2 Block Diagram ...................................................................................2-138
2.11.3 Pin Diagram.......................................................................................2-139
2.11.4 Signal Descriptions ............................................................................2-140
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Chapter 3 BIOS Setup Utility
3.1 Entering Setup......................................................................................................3-1
3.2 System Information...............................................................................................3-2
3.2.1 Processor...............................................................................................3-3
3.2.2 Processor Speed....................................................................................3-3
3.2.3 Bus Frequency.......................................................................................3-3
3.2.4 Internal Cache........................................................................................3-3
3.2.5 External Cache ......................................................................................3-3
3.2.6 Floppy Drive A.......................................................................................3-3
3.2.7 Floppy Drive B.......................................................................................3-3
3.2.8 IDE Primary Channel Master..................................................................3-4
3.2.9 IDE Primary Channel Slave ...................................................................3-4
3.2.10 Total Memory.........................................................................................3-4
3.2.11 Serial Port 1...........................................................................................3-4
3.2.12 Serial Port 2...........................................................................................3-4
3.2.13 Parallel Port...........................................................................................3-4
3.2.14 Pointing Device......................................................................................3-4
3.3 Product Information..............................................................................................3-5
3.3.1 Product Name........................................................................................3-5
3.3.2 Main Board ID........................................................................................3-5
3.3.3 Main Board S/N......................................................................................3-5
3.3.4 System BIOS Version ............................................................................3-5
3.3.5 System BIOS ID.....................................................................................3-6
3.3.6 BIOS Release Date ................................................................................3-6
3.4 Disk Drives...........................................................................................................3-6
3.4.1 Floppy Drives.........................................................................................3-7
3.4.2 IDE Drives .............................................................................................3-8
3.5 Startup Configuration.......................................................................................... 3-10
3.5.1 System POST Mode ............................................................................3-10
3.5.2 Silent Boot...........................................................................................3-10
3.5.3 Num Lock After Boot ............................................................................3-11
3.5.4 Memory Test ........................................................................................3-11
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3.5.5 Initialize SCSI Before IDE.................................................................... 3-11
3.5.6 Boot from IDE CD-ROM....................................................................... 3-11
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3.5.7 System Boot Drive...............................................................................3-11
3.5.8 MP Compliant Revision........................................................................3-11
3.6 Advanced Configuration......................................................................................3-12
3.6.1 Onboard Devices Configuration ...........................................................3-13
3.6.2 PnP/PCI System Configuration ............................................................3-17
3.6.3 Memory/Cache Configuration ...............................................................3-19
3.6.4 Non-PnP ISA Device Configuration......................................................3-20
3.6.5 Chipset Configuration...........................................................................3-23
3.7 System Security Setup........................................................................................3-25
3.7.1 IDE Disk Drive Control.........................................................................3-25
3.7.2 Setup Password...................................................................................3-26
3.7.3 Power-on Password..............................................................................3-28
3.8 Date and Time....................................................................................................3-29
3.8.1 Date.....................................................................................................3-29
3.8.2 Time ....................................................................................................3-29
3.9 Remote Diagnostic Configuration........................................................................3-29
3.10 Load Default Settings..........................................................................................3-30
3.11 Abort Settings Change........................................................................................3-30
3.12 Reset Non-PnP ISA Device Setting.....................................................................3-31
3.13 Leaving Setup.....................................................................................................3-31
Appendices Appendix A Model Definition Appendix B Spare Parts List Appendix C Schematics Appendix D Silk Screens Appendix E BIOS POST Check Points
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List of Figures
1- 1 Front Panel...........................................................................................................1-1
1- 2 Front Panel Features............................................................................................1-2
1- 3 RDM LED .............................................................................................................1-5
1- 4 Rear Panel............................................................................................................1-6
1- 5 Pentium Pro CPU Architecture..............................................................................1-8
1- 6 System Architecture..............................................................................................1-8
1- 7 Memory Board Layout.........................................................................................1-13
1- 8 SCSI Disk Array Backplane Board......................................................................1-13
1- 9 RDM Module Layout...........................................................................................1-14
1- 10 System Board Jumper and Connector Locations .................................................1-15
1- 11 System Block Diagram .......................................................................................1-27
1- 12 Memory Controller Block Diagram ......................................................................1-28
1- 13 Memory Interleaving Block Diagram...................................................................1-29
1- 14 System Clock Diagram .......................................................................................1-30
1- 15 Interrupt Distribution Logic Diagram....................................................................1-31
1- 16 Dual-processor Operation Logic Diagram............................................................1-32
1- 17 IDX-2 Housing ....................................................................................................1-36
1- 18 Basic Model Configuration..................................................................................1-37
1- 19 System Board Power Cable Connections............................................................1-38
1- 20 System Boards and Power Subsystem Interconnections.....................................1-39
1- 21 Door Switches Circuit..........................................................................................1-39
1- 22 Cable 1 Definition for Power Subsystem J11.......................................................1-40
1- 23 Cable 2 Definition for Power Subsystem J2 ........................................................1-40
1- 24 Cable 3 Definition for Power Subsystem J3 ........................................................1-41
1- 25 Cable 4 Definition for Power Subsystem J4 ........................................................1-41
1- 26 Cable 5 Definition for Power Subsystem J5 ........................................................1-42
1- 27 Cable 6 Definition for Power Subsystem J6 ........................................................1-42
1- 28 Cable 7 Definition for Power Subsystem J7 ........................................................1-43
1- 29 Cable 9 Definition for Power Subsystem J10.......................................................1-43
1- 30 Cable 10 Definition for Power Subsystem J14.....................................................1-44
1- 31 Cable 11 Definition for the Front Panel Board.....................................................1-44
1- 32 Cable 12 Definition for the Wide SCSI Connectors .............................................1-45
1- 33 Cables 14 and 15 Definition for the SCSI Backplane Board ................................ 1-45
1- 34 Cables 16 and 17 Definition for Diskette and IDE Drives..................................... 1-46
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1- 35 Cable 18 Definition for Power Subsystem J7.......................................................1-46
1- 36 Cable 19 Definition for the Narrow SCSI Connector............................................1-47
2- 1 P6 Processor Pin Diagram................................................................................... 2-4
2- 2 Pentium Pro CPU Identification Markings ............................................................ 2-5
2- 3 GTL+ Bus Topology............................................................................................. 2-7
2- 4 S82451GX Pin Diagram ......................................................................................2-34
2- 5 S82452GX Pin Diagram ......................................................................................2-38
2- 6 S82453GX Pin Diagram ......................................................................................2-41
2- 7 S82454GX Block Diagram ..................................................................................2-46
2- 8 S82454GX Pin Diagram ......................................................................................2-47
2- 9 82379AB Block Diagram.....................................................................................2-53
2- 10 82379AB Pin Diagram ........................................................................................2-54
2- 11 ESC (82374SB) Block Diagram ..........................................................................2-66
2- 12 ESC (82374SB) Pin Diagram..............................................................................2-67
2- 13 PCEB (82375SB) Block Diagram........................................................................2-94
2- 14 PCEB (82375SB) Pin Diagram............................................................................2-95
2- 15 AIC 7880 Block Diagram................................................................................... 2-114
2- 16 AIC 7880 Pin Diagram......................................................................................2-115
2- 17 ATI 264VT Block Diagram ................................................................................2-128
2- 18 ATI 264VT Pin Diagram....................................................................................2-129
2- 19 37C935 Block Diagram.....................................................................................2-138
2- 20 37C935 Pin Diagram.........................................................................................2-139
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List of Tables
1- 1 LED Indicator Description .....................................................................................1-3
1- 2 LCD Messages .....................................................................................................1-4
1- 3 System Board Specifications .............................................................................. 1-20
1- 4 Memory Configurations .......................................................................................1-21
1- 5 Video memory Specification ...............................................................................1-23
1- 6 Display Modes and Refresh Rates for EDO DRAM .............................................1-23
1- 7 Parallel Port Operation Mode Settings................................................................1-24
1- 8 Memory Address Map.........................................................................................1-24
1- 9 Interrupt Channels Map.......................................................................................1-25
1- 10 I/O Address Map.................................................................................................1-26
1- 11 400W SPS Output Rating...................................................................................1-33
1- 12 IDX-2 Housing Specifications ..............................................................................1-35
2- 1 GTL+ Bus Termination Voltage Specifications......................................................2-6
2- 2 P6 Processor Signal Descriptions .........................................................................2-8
2- 3 S82451GX Signal Descriptions...........................................................................2-35
2- 4 S82452GX Signal Descriptions...........................................................................2-39
2- 5 S82453GX Signal Descriptions...........................................................................2-42
2- 6 S82454GX Signal Descriptions...........................................................................2-48
2- 7 82379AB Signal Descriptions..............................................................................2-55
2- 8 ESC (82374SB) Signal Abbreviations.................................................................2-68
2- 9 ESC (82374SB) Signal Descriptions ................................................................... 2-69
2- 10 PCEB (82375SB) Signal Descriptions................................................................. 2-96
2- 11 AIC 7880 I/O Type Descriptions........................................................................2-116
2- 12 AIC 7880 Signal Descriptions............................................................................ 2-116
2- 13 ATI 264VT Signal Descriptions .........................................................................2-130
2- 14 Display Modes for DRAM (45ns) or EDO DRAM (60ns) ....................................2-135
2- 15 Display Modes for Synchronous DRAM or EDO DRAM with Burst CAS ............ 2-135
2- 16 37C935 Buffer Type Descriptions......................................................................2-140
2- 17 37C935 Signal Descriptions..............................................................................2-140
3- 1 Parallel Port Operation Mode Settings................................................................3-15
3- 2 Drive Control Settings .........................................................................................3-25
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C h a p t e r 1C h a p t e r 1

System Introduction

1.1 Configuration Overview
1.1.1 Front Panel
The system front panel is divided into two sections. The upper front panel consists of the diskette/CD-ROM/tape drive bays, keylock, power switch, LED indicators, LCD display screen, and an embedded reset switch.
The lower part contains the externally accessible hard disk drive bays with 14 drive trays for narrow or wide SCSI drives.
Figure 1- 1 Front Panel
One pair of system keys and one pair of power switch keylock are hung inside the upper front door. Additional duplicate keys can be found at the back of the system.
System Introduction 1-1
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1.1.1.1 Front Panel Features
Drive Bays
Figure 1-2 gives a closer look of the upper front panel features.
LED Indicators
5.25-inch
CD-ROM Drive
3.5-inch Keylock
LCD Display Screen
Figure 1- 2 Front Panel Features
1.1.1.2 CD-ROM Drive
The basic system comes with a SCSI CD-ROM drive already installed.
1.1.1.3 3.5-inch Diskette Drive
Power Switch
Reset Switch (embedded)
A 3.5-inch diskette drive also comes with the basic system.
1.1.1.4 5.25-inch Drive Bays
Two empty 5.25-inch drive bays allow installation of additional devices.
1.1.1.5 Power Switch
The power switch allows you to turn the system power on or off.
1.1.1.6 Reset Switch
Pressing the reset switch generates a hardware reset pulse that restarts the system initializing all the registers, buffers, and memory subsystems.
1.1.1.7 Keylock
The keylock gives security to the system against unauthorized users. Turning the keylock to the unlocked position enables the power and reset switches. Turning the keylock to the locked position disables both switches whether the system is on or off. Supposing the system is on and you intend to reset or turn it off, make sure that the keylock is unlocked. Otherwise, the switches do not respond.
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1.1.1.8 LED Indicators
Table 1- 1 LED Indicator Description
LED Icons Description
Power Status Green Indicates that power is on. This color also denotes that the system
is running on a good supply of AC power.
Red Indicates that power is on. The AC power supply fails and the
system is running on battery power.
Battery Status
UPS
Hard Disk Busy Green Indicates that at least one of the hard disks is currently accessing.
Green Indicates that a battery is present and in good condition. The
battery LED shows this color during normal system operation, during which the battery automatically charges.
When the power status LED is red, a green battery LED also indicates that the system is running on battery power. When this happens, shutdown the system immediately because the battery keeps a fully-configured system running only for about eight minutes.
Red Normally, this color indicates that the battery is bad. However,
there are times when the battery LED turns red for a few seconds due to other factors and NOT because the battery is bad. See below.
Hard Disk Failure
Green Indicates that all the hard disks installed on the backplane board
are in good condition.
Red Indicates that one of the hard disks installed on the backplane
board is bad.
In these instances, the battery LED may turn red for a few seconds but DOES NOT necessarily indicate that the battery is bad.
System Startup
At system power on, the battery LED shows red light when the system performs initialization and self-tests. The red light should remain for only a few seconds and eventually turn to green.
Resumption of AC power supply while the system is running on battery power.
When AC power is cut-off, the battery automatically supplies the system power. The sudden return of AC power at this time when the system is running on battery may cause the battery LED to change to red. Simultaneously, the message “Battery Fails !” may appear on the LCD screen. When this happens, allow the battery to recover for a while. Wait for the battery LED to return to green and the LCD message to disappear.
If the battery LED remains red for several seconds and the message “Battery Fails !” still shows on the LCD screen, change the battery or call your dealer or a technician for assistance.
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1.1.1.9 LCD Display Screen
The LCD display is a two-line by 16-character screen that indicates the boot status as well as any BIOS check point errors encountered upon system initialization. Normally, the system BIOS and the microcontroller firmware send the LCD display messages that appear on the screen. However, if you hooked up a special purpose driver to control the LCD module, this driver define the messages. See the driver manual for more information.
Table 1-2 lists the LCD messages from the system BIOS and the microcontroller at power on.
Table 1- 2 LCD Messages
Message Description
Hello! Welcome !
POST Checkpoints
Power #1 Fails !
Power #2 Fails !
Power #3 Fails !
Battery Fails !
Power Fan Fails ! This message indicates that one or more fans on the power
AC Power Fails ! This message indicates that there is no power coming from the AC
The system is running well !
This is the first message that appears on the LCD screen. This message indicates that the microcontroller works fine.
During the system power-on self-tests (POST), the LCD screen shows which POST check-point is currently being tested.
After POST, the microcontroller checks the power subsystem status. If it detects that power supply module 1 is bad, this message appears on the LCD screen.
If the microcontroller detects that power supply module 2 is bad, this message appears on the LCD screen.
If the microcontroller detects that power supply module 3 is bad, this message appears on the LCD screen.
Normally, this message indicates that the battery is bad and must be replaced with a new one.
There are times when this message appears for a few seconds but do not necessarily mean that the battery is bad. Refer to the previous page for these instances.
subsystem failed.
line and the system is currently running only on battery power. This message appears after POST and other tests. It shows that
the system has passed all the tests and is running fine.
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1.1.1.10 RDM LED
The RDM LED located on the lower right panel enables the remote diagnostic management feature. Refer to the RDM User’s Guide for information on the RDM feature.
RDM Icon
RDM LED
Figure 1- 3 RDM LED
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1.1.2 Rear Panel
The rear panel includes the connectors for the keyboard, mouse, VGA monitor, printer, and serial devices. Below the connectors are the slot openings for expansion boards. On the lower left is the socket for the system power cable. A standby current adapter socket is located on the lower right corner.
Keyboard Port
Mouse Port
Serial Port 1
Video Port
Parallel Port
Serial Port 2
Narrow SCSI Knockout
Figure 1- 4 Rear Panel
Expansion Slot Brackets
Power Socket
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1.2 Features
The AcerAltos 19000Pro4 is a powerful 64-bit quad-processor system loaded with a host of new and innovative features. The system offers a new standard for flexible productivity ideal for local area networks and multiuser server environments.
1.2.1 Intel Pentium Pro Microprocessor
The Intel Pentium Pro CPU is the heart of the AcerAltos 19000Pro4 system. Designed to work with the Orion chipset composed of a PCI bridge and memory controller, the Pentium Pro running at 200 MHz carries a new generation of power not present in its predecessors.
The system board has four CPU sockets to accommodate up to four Intel Pentium Pro CPUs for a multiprocessor configuration. This configuration doubles efficiency and reliability thereby upgrading overall system performance. The Pentium Pro supports a wide range of applications running under SMP network operating systems such as WindowsNT, UNIX, NetWare, etc.
The CPU also incorporates the first-level (L1) and second-level (L2) caches, the advanced peripheral interrupt controller (APIC), and the system bus controller. Figure 1-5 shows the CPU architecture.
1.2.1.1 First-level and Second-level Cache
The Pentium Pro has a 16-KB first-level and 256/512/1024-KB second-level cache. These caches produce a high hit rate that reduces the processor’s external memory bandwidth requirements.
1.2.1.2 Advanced Peripheral Interrupt Controller (APIC)
The APIC unit inside the CPU along with the I/O APIC unit facilitate multiprocessor interrupt management. The APIC works with multiple I/O subsystems where each subsystem have its own interrupts that help minimize centralized system overhead.
1.2.1.3 Bus Controller
The bus controller integrated in the Pentium Pro CPU controls the system bus to make it perform its functions efficiently. It ensures that the bus serves as a reliable interconnection between one or two CPUs, I/O bridge, and memory controllers.
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1.2.1.4 Pentium Pro CPU Architecture
Figure 1- 5 Pentium Pro CPU Architecture
1.2.2 System Architecture
The system bus, PCI buses, EISA bus, Orion PCI bridge (OPB), Orion memory controller (OMC), PCI/EISA Bridge (PCEB), and EISA system controller (ESC) comprise the basic system architecture.
Figure 1- 6 System Architecture
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1.2.2.1 System Bus
The system bus is the CPU’s major connection to all the system devices, primarily the PCI and EISA bridges, and the memory controllers. It can handle as many as eight outstanding transactions at a time through the transaction pipelining feature in which consecutive tasks from the CPU are queued in and transported to the designated devices on a first-in first-out basis. Pipelining allows for transaction overlapping in different phases as the CPU does not have to wait for each transaction to complete before it issues the next transaction. This produces significant improvement on overall system performance.
The bus architecture supports a number of features that ensure high reliability. It has an 8-bit error correction code (ECC) that protects the data lines and a 2-bit parity code that protects the address lines.
The bus uses the gunning transceiver logic (GTL+), a synchronous latched bus protocol that simplifies timing constraints. This protocol supports higher frequency system designs but requires a low voltage that reduces electromagnetic interference (EMI) resulting to a lower power consumption.
1.2.2.2 PCI and EISA Buses
The system supports two PCI buses created by the two PCI bridge chipsets (OPB). The PCI buses serve as the links between the PCI bridges and the PCI devices onboard. The presence of two buses instead of one reduces the I/O bottleneck and matches the higher bandwidth of the CPU for faster data transfers.
The EISA bus connects the EISA devices to the other system devices through the PCI/EISA bridge (PCEB) and the EISA system controller (ESC). The use of the PCEB and ESC maintains compatibility with the EISA environment.
1.2.2.3 Orion PCI Bridge
The Orion PCI bridge (OPB) is a low-cost I/O subsystem solution for high-performance systems. The OPB translates transactions between the system bus and the PCI buses using 32-byte buffers for inbound and outbound postings. The use of two OPBs in the system creates an architecture that allows faster data transfers.
1.2.2.4 Orion Memory Controller
The Orion memory controller (OMC) acts as an interface between the system bus and the system memory. It consists of the DRAM control (DC) chip and the data path (DP) chip. The OMC relates to the DRAM array through four memory interface controller (MIC) chips. The OMC supports 256-bit 4-way memory interleaving resulting to a more efficient memory traffic management.
1.2.3 SCSI Disk Array
The system supports an array of 14 hot-swappable disk drive trays through two 7-slot SCSI backplane boards (Acer BP-W7). The trays accommodate wide and narrow SCSI hard disks. With the AIC-7880 SCSI controller onboard, the transfer rate reaches up to 40 MB per second for ultra-wide SCSI.
System Introduction 1-9
Page 22
1.2.4 Server Management
The system comes with the ASM Pro feature that allows voltage stability and CPU thermal monitoring, prevents data loss by prompt ECC memory error reporting, maximizes system resources by indicating the PCI bus utilization, and promotes efficiency by minimizing system downtime.
A related feature of ASM is the remote diagnostic management (RDM) that permits system diagnosis from a remote site through a modem. The RDM facilitate the fixing of detected problems, changing system configurations or rebooting in the event of system failure.
1.2.5 Redundant Power Supply Subsystem
The system comes with a power backplane that holds up to three 400-watt power supply modules. The power subsystem supports a redundant configuration such that even if one power supply fails, the remaining two continues to work together to supply the 800-watt requirement for a fully­configured system.
Two important segments of the power subsystem configuration are the charger board and battery box. Together, these two components function like an uninterruptible power supply (UPS). Providing an additional support to the three 400-watt power supply modules, the battery automatically charges whenever the system is on. The battery gives a fully-configured system the ability to run continuously through short interruptions in wall power or for a maximum of six minutes in the event of total AC power shutdown.
1.2.6 Security
The system housing comes with mechanical security locks on both the front panel and the side panel preventing unauthorized access to the internal components and system use.
The system BIOS secures the CMOS data and other system software with power-on password, keyboard password, setup control, disk drive control, and monitor control.
1.2.7 Memory Board
The memory board comes already installed with the basic system. A total of 16 168-pin DIMM sockets reside on the board. The sockets accept 32-MB, 64-MB, and 128-MB DIMMs for a maximum of 2 GB memory configuration.
1-10 Service Guide
Page 23
1.2.8 Major Components
The main board contains the following features:
Four ZIF-type socket 8 for Intel Pentium Pro CPU
Four VRM8 sockets for voltage regulator modules
Seven PCI, three EISA expansion slots
Intel Orion chip set and Intel EISA bridge
Two Adaptec 7880 PCI fast/wide SCSI controller
ATI 264VT/GT PCI VGA chip plus 1M/2M byte DRAM
SMC FDC37C935 super IO chip
Acer server management hardware module
Remote diagnostic module
128-byte CMOS NVRAM as system clock/calendar storage plus 8K-byte extended NVRAM
for EISA configuration storage
256K-byte Flash ROM containing system, onboard SCSI, and on-board VGA BIOS
PS/2 keyboard and mouse interface
Front panel interface including power and hard disk LEDs
System Introduction 1-11
Page 24
1.3 Board Layouts
1.3.1 System Board
4
3
2
1
32
31
30
29
28
27
26
25
1. VRM connector 1
2. Pentium Pro CPU socket 1
3. VRM connector 3
4. Pentium Pro CPU socket 3
5. BIOS
6. Battery
7. +12V, +5V downside power connector
8. Buzzer
9. Narrow SCSI interface
10. Wide SCSI interface 1
11. Wide SCSI interface 2
12. PCI slots
13. EISA slots
14. Keyboard controller
15. Pentium Pro CPU socket 4
16. Parallel port
24
22
8
9
10
11
19
20
21
7
6
5
23
17. Video port
18. Serial port 1
19. Serial port 2
20. Mouse port
21. Keyboard port
22. VRM connector 4
23. VRM connector 2
24. RDM connectors
25. Pentium Pro CPU socket 2
26. ±12V, ±5V power connector
27. +12V, +5V power connector
28. VCC3 power connector
29. Memory board slot
30. IDE connector
31. Front Panel Connector
32. Diskette drive connector
12
13
14
15
16
17
18
1-12 Service Guide
Page 25
1.3.2 Memory Board
Connectors
Memory Banks
Figure 1- 7 Memory Board Layout
1.3.3 SCSI Disk Array Backplane Board
Memory Interface Components (82451)
Status Signal
Connector
Jumper J4
SCSI Channel 1
Channel Configuration
Switches
SCSI Channel 2
SCSI Channel Out
Jumper J3
Power
SCSI Drive Slot
SCSI Drive Switch
Terminators
RA4, RA5, RA6
Terminators
RA1, RA2, RA3
Figure 1- 8 SCSI Disk Array Backplane Board
System Introduction 1-13
Page 26
1.3.4 RDM Module
1 23-pin connector 2 RDM controller 3 RDM LED connector 4 23-pin connector
Figure 1- 9 RDM Module Layout
1-14 Service Guide
Page 27
1.4 Jumpers and Connectors
Figure 1- 10 System Board Jumper and Connector Locations
The blackened pin of a jumper or connector represents pin 1.
System Introduction 1-15
Page 28
1.4.1 Jumper Settings
Table 3-2 Jumper Settings
Jumper Setting Function
JP1 Reserved JP2 Reserved
JP10 Reserved
JP11 1-2
JP12 Reserved
JP13 1-2*
JP14 Reserved
JP15 1-2
JPX1 Reserved JPX2 Reserved JPX3 Reserved
*
2-3
2-3
2-3* Open
Password Security
Check password Bypass password
Onboard VGA
Enabled Disabled
CPU Bus Frequency
60 MHz 66 MHz 50 MHz
The following sections describe and illustrate the jumpers that are not listed in the above table.
*
Default setting
1-16 Service Guide
Page 29
1.4.1.1 CPU Activation Jumpers
Jumpers JP4, JP5, JP6, JP7, JP8,and JP9 allow you to select the CPU to activate at a time. Table 3-3 lists the settings and the corresponding functions of these jumpers.
Table 3-3 CPU Activation Jumpers
Group 1 CPUs (CPU1 and CPU3)
JP6 JP7 Function
2-3 Open CPU1 only 1-2 1-2 CPU3 only 1-2 2-3 CPU1 and CPU3
Group 2 CPUs (CPU2 and CPU4)
JP4 JP5 Function
2-3 Open CPU2 only 1-2 1-2 CPU4 only 1-2 2-3 CPU2 and CPU4
Groups 1 and 2 CPUs
JP8 JP9 Function
2-3 1-2 Group 1 only 1-2 2-3 Group 2 only 2-3 2-3 Group 1 and Group 2
1.4.1.2 CPU Frequency Jumper
Table 3-4 lists the CPU frequency ratios depending on JP3 settings.
Table 3-4 CPU Frequency Ratios (JP3)
JP3 Settings
1-2 3-4 5-6 7-8
C C C C 2 C C O C 3 C C C O 4 C C O O 5 O C C C 2.5 O C O C 3.5
C = Closed (Processor pin connected to Vss) O = Open
Core/Bus
DO NOT change jp3 settings unless you are qualified to do so. Ask a technician if you need help when configuring the jumper.
System Introduction 1-17
Page 30
1.4.2 Connector List
Table 3-5 Connector Functions
Connector Function
CN1 Power connector for ±12V, ±5V CN2 Power connector for ±12V, ±5V CN3 Power connector for VCC3 CN4 Power switch connector CN5 Front panel connector CN6 Power connector for ±12V, ±5V CN7 System fan connector CN8 System fan connector CN9 System fan connector CN10 System fan connector CN11 Diskette drive connector CN12 RDM LED connector CN13 RDM connector (to FP11 on the front panel board) CN14 RDM connector (to FP11 on the front panel board) CN15 IDE connector CN16 CPU2 fan connector CN17 CPU1 fan connector CN18 CPU2 temp. connector CN19 CPU1 temp. connector CN20 Voltage regulator module 2 (VRM2) CN21 Voltage regulator module 1 (VRM1) CN22 Keyboard/mouse connector CN23 Serial ports 1 and 2 CN24 Video port/Parallel port CN25 Voltage regulator module 4 (VRM4) CN26 Voltage regulator module 3 (VRM3) CN27 CPU4 temp. connector CN28 CPU4 fan connector CN29 CPU3 fan connector CN30 CPU3 temp. connector CN31 ITP connector CN32 System fan connector CN33 System fan connector CN34 System fan connector
1-18 Service Guide
Page 31
Table 3-5 Connector Functions (continued)
Connector Function
CN35 HDD LED connector CN36 Extended controller connector CN37 Redundant power signal connector CN38 Intel feature connector CN40 Narrow SCSI connector CN42 Wide SCSI connector 2 CN43 Wide SCSI connector 1 CN44 Down-side power connector for +12V, +5V
System Introduction 1-19
Page 32
1.5 System Board Specifications

Table 1- 3 System Board Specifications

Item Description
PCB Size 410mm x 360mm Processor I/O Integrated Quad PPro CPUs & VRM on-board;
(200MHz/512KB, 200MHz/1MB)
Memory ECC Memory card-
16 DIMM slots, up to 2GB (4GB in the future)
1/2/4-way interleaving access Slots 6 PCI, 2 EISA, plus one PCI/EISA shared slot RDM Module Remote Diagnostic Module H/W & F/W built in Server Management ASM Pro Server Management H/W & S/W included VGA and DRAM PCI VGA, 1MB DRAM on-board, expandable to 2MB PCI-SCSI Two Adaptec 7880 Ultra/Fast, Wide/Narrow SCSI on-board I/O Integrated Super I/O SMC935- FDC, AT-IDE, ECP/EPP, 16550 * 2
1-20 Service Guide
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1.6 Hardware Configurations
1.6.1 Memory Configurations
The memory board comes already installed with the basic system. A total of 16 168-pin DIMM sockets reside on the board. The sockets accept 32-MB, 64-MB, and 128-MB DIMMs for a maximum of 2 GB memory configuration.
1.6.1.1 Important points to configure memory
The above table must be followed when upgrading memory
All DIMMs in each of slot0-3, 4-7, 8-11, 12-15 must be populated with
identical ones
Banks should be populated in the order from Bank 0 to Bank 15
Install DIMMs in slot0-3, (and 4-7, and 8-11, and 12-15) makes 4-way
interleaving
Table 1- 4 Memory Configurations
Total
Bank 0 Bank 1 Bank 2-3 Bank 4-7 Bank 8-11 Bank 12-15
32MB * 1 32MB 32MB * 1 32MB * 1 64MB 32MB * 1 32MB * 1 32MB * 2 128MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 256MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 32MB * 4 384MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 32MB * 4 32MB * 4 512MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 64MB * 4 512MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 64MB * 4 64MB * 4 768MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 128MB * 4 768MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 128MB * 4 128MB * 4 1280MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 256MB * 4 1280MB 32MB * 1 32MB * 1 32MB * 2 32MB * 4 256MB * 4 256MB * 4 2304MB 64MB * 1 64MB 64MB * 1 64MB * 1 128MB 64MB * 1 64MB * 1 64MB * 2 256MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 512MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 32MB * 4 640MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 32MB * 4 32MB * 4 768MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 64MB * 4 768MB
Memory
System Introduction 1-21
Page 34
Table 3-6 Memory Configurations (continued)
Bank 0 Bank 1 Bank 2-3 Bank 4-7 Bank 8-11 Bank 12-15
64MB * 1 64MB * 1 64MB * 2 64MB * 4 64MB * 4 64MB * 4 1024MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 128MB * 4 1024MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 128MB * 4 128MB * 4 1536MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 256MB * 4 1536MB 64MB * 1 64MB * 1 64MB * 2 64MB * 4 256MB * 4 256MB * 4 2560MB 128MB * 1 128MB 128MB * 1 128MB * 1 256MB 128MB * 1 128MB * 1 128MB * 2 512MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 1024MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 32MB * 4 1152MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 32MB * 4 32MB * 4 1280MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 64MB * 4 1280MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 64MB * 4 64MB * 4 1536MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 128MB * 4 1536MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 128MB * 4 128MB * 4 2048MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 256MB * 4 2048MB 128MB * 1 128MB * 1 128MB * 2 128MB * 4 256MB * 4 256MB * 4 3072MB 256MB * 1 256MB 256MB * 1 256MB * 1 512MB 256MB * 1 256MB * 1 256MB * 2 1024MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 2048MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 32MB * 4 2176MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 32MB * 4 32MB * 4 2304MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 64MB * 4 2304MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 64MB * 4 64MB * 4 2560MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 128MB * 4 2560MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 128MB * 4 128MB * 4 3072MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 256MB * 4 3072MB 256MB * 1 256MB * 1 256MB * 2 256MB * 4 256MB * 4 256MB * 4 4096MB
Memory
Total
1-22 Service Guide
Page 35
1.6.2 Video Memory Specification
Table 1- 5 Video memory Specification
Item Specification
Memory size 1MB 2MB Memory type EDO RAM Memory configuration 256K*16 x 2 256K*16 x 4 Fixed or upgradeable 1st MB is fixed onboard, 2nd MB is upgradeable Memory speed 60ns Memory voltage 5V Memory package SOJ 40-pin
1.6.3 Video Display Modes and Refresh Rates
Table 1- 6 Display Modes and Refresh Rates for EDO DRAM
256 colors 64K colors 16.7M colors
Resolution 1 MB 2 MB 1 MB 2 MB 1 MB 2 MB
640 x 480 100 100 100 100 90 100 800 x 600 100 100 90 100 100 1024 x 768 100 100 100 — 1152 x 864 80 80 80 — 1280 x 1024 * 75
* - 1280 x 1024 @ 16 colors is available at 75 Hz.
System Introduction 1-23
Page 36
1.6.4 Parallel Port Configurations
The onboard parallel port interface supports a 25-pin D-type connector. The port functions in different operation modes and is adjustable to select LPT1, LPT2, and LPT3 by changing the CMOS settings in the BIOS Utility.
Table 1-7 lists the operation mode settings and their corresponding functions.
Table 1- 7 Parallel Port Operation Mode Settings
Setting Function
Standard Parallel Port (SPP) Allows normal speed operation but in
one direction only
Enhanced Parallel Port (EPP 1.7/1.9) Allows bidirectional parallel port
operation at maximum speed
Extended Capabilities Port (ECP) Allows parallel port to operate in
bidirectional mode and at a speed higher than the maximum data transfer rate
Standard and Bidirectional Allows normal speed operation in a
two-way mode
1.6.5 Serial Port Configurations
The system board has two high-speed 9-pin D-type serial ports. These ports are NS16C550­compatible UARTs with 16-byte FIFO send/receive capability. The port functions are software adjustable to select COM1, COM2, COM3, and COM4.
1.6.6 Memory Address Map
Table 1- 8 Memory Address Map
Address Name Function
00000000 ~ 0009FFFF 640 KB system memory Main Memory 000A0000 ~ 000BFFFF 128 KB video RAM Graphics display buffer 000C0000 ~ 000C7FFF 32 KB I/O expansion ROM Video BIOS 000C8000 ~ 000CFFFF 32 KB I/O expansion ROM Reserved for ROM on I/O adapters 000D0000 ~ 000DFFFF 64 KB I/O expansion ROM Reserved for ROM on I/O adapters 000E0000 ~ 000E7FFF 32 KB System extended BIOS (SCSI BIOS) 000E8000 ~ 000EFFFF 32 KB Reserved for system extended BIOS 000F0000 ~ 000FFFFF 64 KB System BIOS 00100000 ~ FFFFFFFF System memory System Memory
1-24 Service Guide
Page 37
1.6.7 Interrupt Channels Map
Table 1- 9 Interrupt Channels Map
IRQ System Device
IRQ0 Timer output 0 IRQ1 Keyboard IRQ2 Reserved IRQ3 Serial port 2 IRQ4 Serial port 1 IRQ5 Reserved IRQ6 Diskette drive IRQ7 Parallel port IRQ8 Real-time clock IRQ9 Reserved IRQ10 Reserved IRQ11 Reserved IRQ12 PS/2 mouse IRQ13 Numeric processor IRQ14 IDE primary channel IRQ15 IDE secondary channel
System Introduction 1-25
Page 38
1.6.8 I/O Address Map
Table 1- 10 I/O Address Map
Hex Range Device
000 ~ 00F DMA controller-1 020 ~ 021 Interrupt controller-1 022 ~ 023 ESC (82374) configuration 040 ~ 043 System timer-1 048 ~ 04B System timer-2 061 NMI status and control 070 NMI mask 080 ~ 08F DMA page register 092 System control port 0A0 ~ 0A1 Interrupt controller-2 0B2 ~ 0B3 Advanced power management 0C0 ~ 0DE DMA controller-2 0F0 Reset IRQ 13 1F0 ~ 1F7 Hard disk 278 ~ 27F Parallel port 2 2F8 ~ 2FF Serial port 2 378 ~ 37F Parallel port 1 3B0 ~ 3BF Monochrome display 3C0 ~ 3CF EGA, VGA, SVGA 3D0 ~ 3DF CGA, VGA, SVGA 3F0 ~ 3F7 Diskette drive controller 3F8 ~ 3FF Serial port 1 *4A0 On board peripherals control *4A1-4A3 ASM control and status(1) *4A4 Redundant power supply status *4A5 ASM control and status(2) *4A6 RDM control and status *4A7 Backplane board status *4A8-4AF ASM control and status(3) CF8 PCI configuration address regulation CFC PCI configuration data regulation
1-26 Service Guide
Page 39
1.7 Block Diagrams
1.7.1 System Block Diagram
System Architecture
PPro-CPU1 & 512K/1M Cache
EISA Slot *3
Orion DC/DP
533MB/s
MIC * 4
1
3
2
9
10
1/2/4 Way Interleave ECC Memory
IMM * 16: IMM 1 for Bank 0
for Bank 4
5
4
11
12
6
13
14
PPro-CPU1 & 512K/1M Cache
64bit @ 66MHz GTL+ PPro-MPBus 533MB/s
7
8
15
16
X3 Block Diagram
PPro-CPU2 & 512K/!M Cache
P6-MPBus/PCI Bridge
OPB
PCI Bus 133MB/s
PCI/EISA Bridge
PCEB ESC
VGA
EISA Bus 33MB/s
1
2
S I/O
3
1
2
A.S.M. R.D.M.
PPro-CPU1 & 512K/1M Cache
P6-MPBus/PCI Bridge
OPB
PCI Bus 133MB/s
PCI Slot * 3PCI Slot *
1
3
4
2
3
Dual SCSI-
Figure 1- 11 System Block Diagram
System Introduction 1-27
Page 40
1.7.2 Memory Controller Block Diagram
Two-bank, N : 1 - way Interleaved Memory Data Connections
To Memory Controller
72
82451 x 4
Register Register Register Register
Multiplexer
Row 1
72
36 36 36 36 36 36 36 36
BANK 1 BANK 3BANK 2 BANK4BANK 5 BANK 6 BANK 7 BANK 8
BANK 9 BANK 10 BANK 11 BANK 15 BANK 12 BANK 16BANK 13 BANK 14
WAY 1 WAY 4WAY 2 WAY 3
1 : 1
72
Figure 1- 12 Memory Controller Block Diagram
2 : 1
72
72
Row 2
4 : 1
1-28 Service Guide
Page 41
1.7.3 Memory Interleaving Block Diagram
SLOT 15
SLOT 13
SLOT 11
SLOT 9
SLOT 7
SLOT 5
SLOT 3
SLOT 16
SLOT 14
SLOT 12
SLOT 10
SLOT 8
SLOT 6
SLOT 4
4 : 1 Interleaved
4 : 1 Interleaved
4 : 1 Interleaved
SLOT 1
SLOT 2
2 : 1 Interleaved
X3 Memory Board
DIMMs Population Rules of X3 Memory Board
Figure 1- 13 Memory Interleaving Block Diagram
Remark
1. Please follow Table 1-4(page 1-21 and 1-22) for the memory configurations.
2. Every 4 consecutive DIMMs are set as a group.(e.g. Group 1 means slot 1~4, Group 2 means slot 5~8, Group 3 means slot 9~12, Group 4 means slot 13~16)
3. Except for group 1, memory upgrade should be performed at least one group(4 DIMMs) at a time.
4. All DIMMs in a group should be of the same DIMM size.
5. Adding 1 DIMM, 2 DIMMs or 4 DIMMs is allowed in group 1, but not in group 2, 3 and 4.
6. Please follow the DIMM QVL of this product when you select DIMM for upgrade. Using DIMM out of the QVL is not quality assured.
System Introduction 1-29
Page 42
1.7.4 System Clock Diagram
P6-1
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
CPUCLK4
X1
VDD
+5V
P6-3
P6-2
CPUCLK5
CPUCLK6
CPUCLK7
X2
SEL1
SEL0
P6-4
CPUCLK10
CPUCLK8
CPUCLK9
VSS
82454GX-1
CPUCLK11
82454GX-2
82453GX
82452GX
82451GX-1
82451GX-2
82451GX-3
82451GX-4
XTPIN1
XTPIN2
System Clock Diagram
Figure 1- 14 System Clock Diagram
FREQS1
FREQS0
SMC935
CLK_24M
CLKA
24.0MHz
CPUCLK
14.318MHz
32.768KZHz
S0S1S2
5V 5V
JP15
CLKB
CLKC
CLKD
1-30 Service Guide
Page 43
1.7.5 Interrupt Distribution Logic Diagram
AIC 7880
PCIINT4#
Interrupt Distribution Logic
Interrupt Distribution Logic
INTA# INTB# INTC# INTD#
INTA# INTB# INTC# INTD#
INTA# INTB# INTC# INTD#
AIC 7880
PCIINT5#
INTA# INTB# INTC# INTD#
IRQ3, 4, 9, 10, 11, 12, 14, 15
B2IRQ3, 4, 9, 10, 11, 12, 14, 15
INTA# INTB# INTC# INTD#
INTA# INTB# INTC# INTD#
B2INTA# B2INTB# B2INTC# B2INTD#
B2INTE#
PCIINT1# PCIINT2# PCIINT3#
PCIINT4#
IRQ Mapper
82374EB
PLSI
P6INT
P6
CPU
Figure 1- 15 Interrupt Distribution Logic Diagram
System Introduction 1-31
Page 44
1.7.6 Quad-processor Operation Diagram
Dual-processor Operation Logic
INIT
NMI
LINTIN1 LINTIN0
RESET
ICC BUS
PCIINT[1:4]# IRQ 3,4,9:12,14,15
Quad-processor Operation Logic
P6
Local
APIC
8259A
P6
Local
APIC
INTR
P6
Local
APIC
I/O
P6
Local
APIC
VCC3
APIC
Figure 1- 16 Dual-processor Operation Logic Diagram
1-32 Service Guide
Page 45
1.8 Power Requirements
The specific housing configuration of the X3 system determines the total power consumption required by the system.
1.8.1 400W Power Supply for IDX-2
X3 systems with IDX-2 housing require two to three units of 400-watt power supply modules. The following specifications are for a single 400-watt module.
1.8.1.1 Output Requirements
Table 1- 11 400W SPS Output Rating
Output Nominal Output Power Ripple and Noise Minimum Maximum
1 +5.1V 204 W 50 mV 5A 40A 2 5V 5 W 50 mV 0 1A 3 3.3V 89 W 33 mV 0 27A 4 +12V 168 W 120 mV 1A 14A 5 -12V 36 W 120 mV 0 3A 6 5V 0.5 W 50 mV 0 0.1A 7 56.5V 56.5 W 800 mV 0 1A
Ripple and noise bandwidth from 10 Hz to 20 MHz.
When AC power is on, +12V should provide 10A surge current. This regulation should be within -6% and +7%.
Regulation: The total voltage regulation for each level is calculated in terms of the hand of
voltage defined by the maximum positive and negative excursions (from nominal) that occur.
System Introduction 1-33
Page 46
1.8.1.2 Installation Requirements
Installing or removing power supply modules, battery, or charger while the AC power cord is plugged-in may damage the whole power subsystem. Adhere to the standard procedure when installing or removing power supply modules, battery, or charger.
Failure to follow the standard safety procedure when installing or removing power modules may result to a fatal system damage.
Follow these steps to install or remove power supply modules, battery, or charger:
1. If the system is on, press the power switch to turn off the power.
2. Unplug the AC power cord from the power outlet.
3. Open the right panel of the system housing.
4. Remove or install power modules.
5. Close the housing then apply AC power.
1-34 Service Guide
Page 47
1.9 Mechanical Specifications
1.9.1 IDX-2 Housing
Table 1- 12 IDX-2 Housing Specifications
Item Description
Dimensions Spacing between adapter cards Weight
Basic Model
Full-load Opening for expansion slots Drive Bays
Major subassembly support
Circuit card support
Metal finish
Color/Paint
Case finish
740 mm (d) x 435 mm (w) x 700 mm (h)
0.8 inch
58 kg 82 kg (maximum)
12 One 3.5-inch external bays
Three 5.25-inch external bays 14 SCSI disk array drive bays
Major subassemblies are rigidly held in place by frame components. Adequate clearances are provided so that cards can be installed and removed without bending or forcing. All other components such as SPS and FDD can be assembled easily.
Circuit cards plugged into the system board are supported by a card edge connector, the card end bracket, and by a card edge guide supporting the card edge from the farthest end bracket (if the card conforms to the full length).
All metal surfaces are plated or equivalent treatment Lower case: metal
Left cover: metal Frame: metal Right cover: metal
Units delivered in specified MCS colors. Paint samples supplied to the vendor as required.
All surfaces are textured or equivalent treatment
Figure 1-17 shows the IDX-2 housing.
System Introduction 1-35
Page 48
Figure 1- 17 IDX-2 Housing
1-36 Service Guide
Page 49
1.10 Shipping Configuration
Figure 1-18 shows the basic model configuration for an X3 system with IDX-2 housing (AcerAltos 19000Pro4).
400W S.P.S.
400W S.P.S.
400W S.P.S.
Battery Box
Figure 1- 18 Basic Model Configuration
P6
P6
OPB
OPB
P6
P6
System Introduction 1-37
Page 50
1.11 Cable Connections
The following figures illustrate the cable connections for the different system components.
System Board Power Connections
Figure 1- 19 System Board Power Cable Connections
1-38 Service Guide
Page 51
Figure 1- 20 System Boards and Power Subsystem Interconnections
Door Switches Circuit
Door Switchs Circuit
CN4 PS_SW
PS_ONPS_ON
1
+5V STABY+5V STABY
2
PS_ONPS_ON
3
X3 Mother BD
1 2 3 4 5 : : 34
CN5
5VSTABY5VSTABY PS_ONPS_ON
Figure 1- 21 Door Switches Circuit
Cable 9
Cable 11
1 2 3 4 5.......34
CN6
Front Panel BD
Right Door S.W.
Cable 10
Left Door S.W.
Power Subsystem
J10J10
4 GND4 GND 3 +5V Sdaby3 +5V Sdaby 2 Remot.on/off2 Remot.on/off 1 NC1 NC
J14J14
11 22
System Introduction 1-39
Page 52
Cable 1 - Power Subsystem J11
14P
Part Number:
50.59903.021 Fm Power
Subs. J11 “ C1/J11
AC Fail Bat. OK Bat. Fit. GND Fan Fail PS3 Fail PS2 Fail PS1 Fail PS3 Pres. PS2 Pres. PS1 Pres.
* Key --
N.C.
* Key --
N.C.
* Key --
N.C.
length: 65 cm
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 1- 22 Cable 1 Definition for Power Subsystem J11
Cable 2 - Power Subsystem J2
Part Number:
50.59910.011 16P
Fm Power Subs. J2
C2/J2
p1~p6
40 cm
14P
To Front Panel BD CN5
AC Fail Bat. OK(BatLow) Bat. Fit.(BatPres) GND Fan Fail PS3 Fail PS2 Fail PS1 Fail PS3 Pres. PS2 Pres. PS1 Pres. N.C. N.C. N.C.
* The pin 12~14 of this end don’t need keys!
p7~p12
40 cm
6P To M.B. CN8
6P To M.B. CN8
DC P.G. +5V +12V
-12V GND GND GND GND
-5V +5V +5V +5V p13~ p16: NC
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
DC P.G. +5V +12V
-12V GND GND GND GND
-5V +5V +5V +5V
-- Key
-- Key
Figure 1- 23 Cable 2 Definition for Power Subsystem J2
1-40 Service Guide
Page 53
Cable 3 - Power Subsystem J3
Fm Power Subs. J3
Part Number:
50.59903.031
14P
C3/J3
Remote Ret. +3.3V +3.3V +3.3V GND GND GND Remote +3.3V +3.3V +3.3V GND GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
p1~p14
length: 42 cm
Figure 1- 24 Cable 3 Definition for Power Subsystem J3
Cable 4 - Power Subsystem J4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GND GND GND GND GND GND GND +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V
14P To M.B. CN4
* This end must add a yellow caution label!
Part Number:
50.59914.001 10P
Fm Power Subs. J4
C4/J4
GND GND GND +5V +5V +12V GND GND +5V +5V
1 2 3 4 5 6 7 8 9 10
37 cm
Figure 1- 25 Cable 4 Definition for Power Subsystem J4
1 2 3 4 5 6 7 8 9 10
+5V +5V +5V +5V +12V GND GND GND GND GND
10P To M.B. CN3
* This end must add a yellow caution label!
System Introduction 1-41
Page 54
Cable 5 - Power Subsystem J5
Part Number:
50.59908.021 12P
Fm Power Subs. J5
C5/J5
1
+5V
2
GND
3
+12V
4
GND
5
GND
6
+5V
7
GND
8
+12V
9
+12V
10
GND
11
GND
12
+5V
Figure 1- 26 Cable 5 Definition for Power Subsystem J5
p1~p4
p9~p12
48cm
p5~p8
44 cm 1
+12V
2
GND
3
GND
4
+5V
1
+12V
2
GND
3
GND
4
+5V
1
+12V
2
GND
3
GND
4
+5V
46 cm
4P To SCSI BP-W7(L) P1
4P To SCSI BP-W7(L) P2
4P To SCSI BP-W7(L) P3
Cable 6 - Power Subsystem J6
Part Number:
50.59908.001 12P
Fm Power Subs. J6
C6/J6
1
+5V
2
GND
3
+12V
4
GND
5
GND
6
+5V
7
GND
8
+12V
9
+12V
10
GND
11
GND
12
+5V
Figure 1- 27 Cable 6 Definition for Power Subsystem J6
p1~p4
p9~p12
46 cm
p5~p8
42cm
1 2 3 4 1 2 3 4 1 2 3 4
+12V GND GND +5V +12V GND GND +5V +12V GND GND +5V
44cm
4P To SCSI BP-W7(R) P1
4P To SCSI BP-W7(R) P2
4P To SCSI BP-W7 (R) P3
1-42 Service Guide
Page 55
Cable 7 - J12 for FDD/HDD/...
Part Number:
50.59901.011
Fm Power Subs. J12
C7/J12
p1~p4
8P
p5~p8
+12V GND GND +5V +12V GND GND +5V
50 cm
55 cm
1 2 3 4 5 6 7 8
Figure 1- 28 Cable 7 Definition for Power Subsystem J7
Cable 9 - Power Subsystem J10
Part Number:
50.59912.011
PS_ON 5VSTNDBY PS_ON
3P
Fm M.B. CN1
1 2 3
p1 : NC
p2
p3
46 cm
15 cm
4P To FDD/HDD/ Tape/CD-ROM/...
15 cm
1
+12V
2
GND
3
GND
4
+5V
1
+12V
2
GND
3
GND
4
+5V
4P To Power Subs. J10
p2
4 3 2
p3
1
4P
4P
GND +5V Standby Remote On/Off N.C.
p1, p4: NC “ C9/J10
Figure 1- 29 Cable 9 Definition for Power Subsystem J10
System Introduction 1-43
Page 56
Cable 10 - Power Subsystem J14
Part Number:
50.59911.021 39 cm
2P
Fm Power Subs. J14
28 cm
* Cable: 22 AWG, Black
82 cm
43 cm
Figure 1- 30 Cable 10 Definition for Power Subsystem J14
Cable 11 - Front Panel BD
Part Number:
50.59904.021 34P
R.D. S.W.
L.D. S.W.
Fm M.B. F.P. Connector CN9
P16 - Key
CABLE 11
length: 70 cm
Figure 1- 31 Cable 11 Definition for the Front Panel Board
34P
To Front Panel BD CN6
P16 - Key
1-44 Service Guide
Page 57
Cable 12 - Wide SCSI Cables
Part Number:
50.59906.001
68P Wide-SCSI Connector
Fm M.B. SCSI Connector J20
length: 75 cm
Figure 1- 32 Cable 12 Definition for the Wide SCSI Connectors
Cable 14 & 15 - SCSI B.P. BD
Part Number:
50.59903.041
14P
Fm F.P. BD CN3 Connector
CABLE 14
length: 68 cm
68P Wide-SCSI Connector
To SCSI BP-W7 (L) Channel-0/ Channel-1
14P
To SCSI BP-W7 (L) P4
Part Number:
50.59903.001
14P
Fm F.P. BD CN4 Connector
CABLE 15
14P
length: 52 cm
To SCSI BP-W7 (R) P4
Figure 1- 33 Cables 14 and 15 Definition for the SCSI Backplane Board
System Introduction 1-45
Page 58
Cable 16 & 17 - Floppy & IDE
Part Number:
50.59904.031
Part Number:
50.59905.011
Fm M.B. IDE Connector CN12
CABLE 17
34P
Fm M.B. Floppy Connector CN10
Pin-5 : Key
CABLE 16
40P
length: 47cm
* Note: Pin10 ~ Pin 16 must be inverted for 3.25” FDD.
40P
length: 47 cm
To HDD
Figure 1- 34 Cables 16 and 17 Definition for Diskette and IDE Drives
Cable 18 - Power Subsystem J7
34P
To FDD
40P
To HDD
Part Number:
50.59914.011 10P
Fm Power Subs. J7
C18/J7
GND GND GND +5V +5V +12V GND GND +5V +5V
1 2 3 4 5 6 7 8 9 10
28 cm
Figure 1- 35 Cable 18 Definition for Power Subsystem J7
1 2 3 4 5 6 7 8 9 10
+5V +5V +5V +5V +12V GND GND GND GND GND
10P To M.B. CN2
* This end must add a yellow caution label!
1-46 Service Guide
Page 59
Cable 19 - Narrow SCSI Cable
Part Number:
50.58607.001 50P
Fm M.B. N-SCSI Connector J17
C19/J17
length: 75 cm
Figure 1- 36 Cable 19 Definition for the Narrow SCSI Connector
50P
len.: 15 cm
50P
50P
To HDDs
len.: 15 cm
System Introduction 1-47
Page 60
C h a p t e r 2C h a p t e r 2

Major Chipsets

This chapter describes the major chipsets used in the X3 system board and memory board. It includes the chipset features, block diagram, and signal descriptions.
2.1 Pentium Pro processor (P6)
2.1.1 Features
The Pentium microprocessors. The P6 processor maintains binary compatibility with the 8086/88, 80286, Intel386, Intel486, and Pentium processors. It integrates the second-level cache, APIC, and memory bus controller found in previous Intel processors as a single component.
The P6 processor provides significant performance improvements using the following internal architectural improvements:
TM
Pro (P6) CPU is the next generation in the Intel386TM/lntel486TM family of
Super-scalar model
Super-pipelined model
Register renaming
Out-of-order execution
Speculative execution
The expected P6 processor performance gains, over a Pentium processor using the same process technology, are 1.5X (lnteger Specmark), 2.0X (Floating-point Specmark), and 1.75X (Aggregate Specmark).
Increasing clock frequencies and processor performance can complicate system designs. To counter this trend, a primary design goal of the P6 processor bus is to simplify system design as much as possible while still providing advanced features and high performance. The P6 processor provides all of the debug hooks on previous generation processors, and has increased the debug information available directly from the bus. In addition, the P6 processor integrates several system components and has a configurable bus frequency.
The external P6 bus design enables it to be multiprocessor ready. It integrates bus arbitration and control, cache coherency circuitry, an MP interrupt controller, and other system-level functions into the bus interface.
Major Chipsets 2-1
Page 61
To relax timing constraints, the P6 implements a synchronous latched bus protocol to enable a full clock cycle for signal transmission and a full-clock cycle for signal interpretation and generation. This latched protocol simplifies interconnect timing requirements and supports higher frequency system designs using inexpensive ASIC interconnect technology. The P6 bus uses low-voltage swing gunning transceiver logic (GTL) I/O buffers, making high-frequency signal communication easier.
The P6 processor component contains a processor core and a large second-level (L2) cache. The high internal cache hit rate satisfies most of the CPU core's bandwidth and latency requirements. The L2 cache reduces the P6 processor's external memory bandwidth requirement and makes the processor's performance less sensitive to bus access latency. Eliminating external caches removes some complexities in P6 processor system design.
The processor handles most of the P6 processor cache protocol complexity. A non-caching I/O bridge on the P6 bus does not need to comprehend the cache protocol and does not need snoop logic. The I/O bridge can issue standard memory accesses on the P6 bus, which are transparently snooped by all P6 bus agents. If data is modified in a P6 processor cache, the processor transparently provides data on the bus, instead of the memory controller. This functionality eliminates the need for a back-off capability that existing I/O bridges require to enable cache write­back cycles. The memory controller must observe snoop response signals driven by the P6 bus agents, absorb write-back data on a modified hit, and merge any write data.
The P6 processor integrates memory type range registers (MTRRs) that can replace the external address decode logic used to decode cacheability attributes.
The P6 bus protocol enables a near linear increase in system performance with an increase in the number of processors. The P6 processor interfaces to a multiprocessor system without any support logic. This “glueless” interface enables a desktop P6 processor system to be built with an upgrade socket for another P6 processor. The key design challenge in a P6 processor chipset is to take advantage of the P6 bus protocol and adapt to the higher bandwidth requirements of multiple processors.
The external P6 bus and P6 processor use a ratio clock design that provides modularity and upgradability. The processor's internal clock frequency is a multiple of the bus clock frequency, where the multiple is 2, 3, or 4. Only certain bus and processor frequency combinations are supported. This specification reserves additional combinations to provide future upgrade paths.
The ratio clock approach reduces the tight coupling between the processor clock and the external bus clock. For a fixed system-bus clock frequency, P6 processors introduced later with higher processor clock frequencies can use the same support chipset at the same bus frequency. Faster and slower P6 processors can co-exist in the same system. A customer's investment in a P6 processor chipset is protected for a longer time and for a greater range of processor frequencies. The ratio clock approach also preserves system modularity, allowing a system's electrical topology to determine the system bus clock frequency while process technology can determine the processor clock frequency.
The P6 bus architecture provides a number of features to support high reliability and high availability designs. Most of these additional features can be disabled, if necessary. For example, the bus architecture allows the data bus to be unprotected with parity, or protected with an error correcting code (ECC). Error detection and limited recovery are built into the bus protocol.
A P6 processor-based cluster can contain up to four P6 processors, and a combination of four other loads consisting primarily of memory controllers, I/O bridges, and custom attachments.
2-2 Service Guide
Page 62
In a four-processor system, the data bus is the most critical resource. To account for this situation the P6 bus implements several features to maximize available bus bandwidth. These features allow for pipelined transactions in which bus transactions in different phases overlap an increase in transaction pipeline depth over previous generations, and support for deferring a transaction for later completion.
A P6 processor system for the high-end server market can contain four-processor clusters, each behind a level 2 (L2) cache controller. The P6 processor cache protocol provides flexibility in the L2 cache design, enabling high-end servers to use their L2 cache design for a key difference in performance. Non-latency L2 misses can be supported in a deferred reply mode without preventing further transactions from being issued and completed.
The P6 bus architecture is therefore adaptable to various classes of systems. In desktop multiprocessor systems, a subset of the bus features can be used. In the low-end server market, the P6 bus provides an easier entry into low-end multiprocessing with linear increases in performance as CPUs are added. Finally, the P6 bus meets the demands of the high-end server marketplace, allowing P6 processor systems to be considered for applications currently being downsized.
Major Chipsets 2-3
Page 63
2.1.2 Pin Diagram
Figure 2- 1 P6 Processor Pin Diagram
2-4 Service Guide
Page 64
2.1.3 CPU ID
Top Markings Bottom Markings
ZZZ = Speed (MHz)
LLL = L2 Cache Size (Kbyte)
KB8Ø521EXZZZ QYYYY LLLK
intel
PENTIUM PRO
FFFFFFFF-XXXX
FFFFFFFF = FPO Lot #
‘94 ‘95INTEL
CM
R
R
XXXX = Serial Number
XXXXXXXXAA YYYYYYYYAA MALAY K
KB8Ø521EXZZZ SYYYY LLLK
ZZZ = Speed (MHz)
LLL = L2 Cache Size (Kbyte)
SYYYY = S-Spec Number
CPU Alternative Identification Number
Country of origin, product designator
Figure 2- 2 Pentium Pro CPU Identification Markings
Source: Intel Pentium Pro Processor Specification Update released on May 15, 1996.
Major Chipsets 2-5
Page 65
2.1.4 Signal Types
The P6 processor has following signal types.
3.3V Tolerant Type (TTL-compatible)
5V Tolerant Type (TTL-compatible)
GTL+ Type
JTAG Type
2.1.4.1 GTL+ Type
Most of the P6 processor signals use a variation of the low-voltage Gunning Transceiver Logic (GTL) signaling technology. The P6 processor bus specification is similar to the GTL specification plus enhancements to provide larger noise margins and reduced ringing. This is accomplished by increasing the termination voltage level and controlling the edge rates. Since this specification is different from the standard GTL specification, it is referred to as GTL+ in this document.
The GTL+ signals are open-drain and require external termination to a supply that provides the high-signal level. The GTL+ inputs use differential receivers that require a reference signal (V Termination, usually a resistor on each end of the signal trace, is used to pull the bus up to the high-voltage level and to control reflections on the stub-free transmission line. The receivers use V
to determine if a signal is a logical 0 or a logical 1.
REF
REF
).
Table 2-1 lists the bus termination voltage specifications for GTL+.
Table 2- 1 GTL+ Bus Termination Voltage Specifications
Symbol Parameter Voltage (V)
V
TT
V
REF
Bus Termination Voltage Input Reference Voltage
V
should be created from VTT by a voltage divider of 1%
REF
1.5±10%
2/3 VTT±2%
resistors.
2-6 Service Guide
Page 66
There are eight V
pins on the P6 processor to ensure that internal noise does not affect the
REF
performance of the I/O buffers. Pins A1, C7, S7 and Y7 (V pins A47, U41, AE47 and AG45 (V
[7:4]) must be tied together. The two groups may also be
REF
tied to each other if desired.
CPU ASICCPU ASIC
Figure 2- 3 GTL+ Bus Topology
2.1.4.2 JTAG
[3:0]) must be tied together while
REF
1.5V1.5V
JTAG stands for Joint Test Action Group. This signal type is tolerant to 3.3V and especially used for testing and debugging.
Major Chipsets 2-7
Page 67
2.1.5 Signal Descriptions
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
A[35:32]# A[31:28]# A[27:24]# A[23:20]# A[19:16]# A[15:12]# A[11:08]# A[07:03]#
C1, E9, E7, E5 G9, E3, E1, J9 G5, G7, L9, G3 J7, G1, J3, J5 J1, L7, N9, L3 L5, N3, N7, N1 N5, Q9, Q1, Q7 Q3, S1, Q5, S3 S5
I/O, GTL+ The A[35:3]# signals are the address signals.
They are driven during the two-clock request phase by the request initiator. The signals in the two clocks are referenced Aa[35:3]# and Ab[35:3]#. During both clocks, A[35:24]# signals are protected with the AP1# parity signal, and A[23:3]# signals are protected with the APO# parity signal.
The Aa[35:3]# signals are interpreted based on information carried during the first request phase clock on the REQa[4:0]# signals.
For memory transactions as defined by REQa[4:0]# = {XX01X,XX10X,XX11X}, the Aa[35:3]# signals define a 236-byte physical memory address space. The cacheable agents in the system observe the Aa[35:3]# signals and begin an internal snoop. The memory agents in the system observe the Aa[35:3]# signals and begin address decode to determine if they are responsible for the transaction completion. Aa[4:3]# signals define the critical word, the first data chunk to be transferred on the data bus.
For P6.0 DX IO transactions as defined by REQa[4:0]# = 1000X, the signals Aa[16:3]# define a 64K+3 byte physical IO space. The IO agents in the system observe the signals and begin address decode to determine if they are responsible for the transaction completion. Aa[35:17]# are always zero. Aa[16:3]# is zero unless the IO space being accessed is the first three bytes of a 64KB address range.
For deferred reply transactions as defined by REQa[4:0]# = 00000, Aa[23:16]# carry the deferred ID. This signal is the same deferred ID supplied by the request initiator of the original transaction on Ab[23:16]#/DID[7:0]# signals. P6 bus agents that support deferred replies sample the deferred ID and perform an internal match against any outstanding transactions waiting for deferred replies. During a deferred reply, Aa[35:24]# and Aa[15:3]# are reserved.
For the branch-trace message transaction as defined by REQa[4:0]# = 01001 and for special and interrupt acknowledge transactions, as defined by REQa[4:0]# = 01000, the Aa[35:3]# signals are reserved and undefined.
2-8 Service Guide
Page 68
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
A[35:32]# A[31:28]# A[27:24]# A[23:20]# A[19:16]# A[15:12]# A[11:08]# A[07:03]# (continued)
A20M# A11 I, 3.3V The A20M# signal is the address-20 mask signal
C1, E9, E7, E5 G9, E3, E1, J9 G5, G7, L9, G3 J7, G1, J3, J5 J1, L7, N9, L3 L5, N3, N7, N1 N5, Q9, Q1, Q7 Q3, S1, Q5, S3 S5
I/O, GTL+ During the second clock of the request phase,
Ab[35:3]# signals perform identical signal functions for all transactions. For ease of description, these functions are described using new signal names. Ab[31:24]# are renamed the attribute signals ATTR[7:01#. Ab[23:16]# are renamed the Deferred ID signals DID[7:0]#. Ab[15: 8]# are renamed the eight-byte enable signals BE[7:0]. Ab[7:3]# are renamed the extended function signals EXF[4:0].
On the active-to-inactive transition of RESET#, each P6 bus agent samples A[35:3]# signals to determine its power-on configuration. Two clocks after RESET# is sampled deasserted, these signals begin normal operation.
in the PC Compatibility group. If the A20M# input signal is asserted, the P6 processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the one MB boundary. Only assert A20M# when the processor is in real mode. The effect of asserting A20M# in protected mode is undefined and may be implemented differently in future processors.
Snoop requests and cache-line write-back transactions are unaffected by A20M# input. Address 20 is not masked when the processor samples external addresses to perform internal snooping.
A20M# is an asynchronous input. However, to guarantee recognition of this signal that follows an I/O write instruction, A20M# must be valid with active RS[2:0]# signals of the corresponding I/O write bus transaction. In FRC mode, A20M# must be synchronous to BCLK.
During active RESET#, the P6 processor begins sampling the A20M# and IGNNE# values to determine the ratio of core-clock frequency to bus-clock frequency.
Major Chipsets 2-9
Page 69
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
A20M# continued
ADS# AE3 I/O, GTL+ The ADS# signal is the address strobe signal. It is
A11 I, 3.3V The following table shows the bus frequency to
core frequency ratio configuration:
Ratio of Core Clock to Bus Clock LINT[1] LINT[0]# IGNNE#S A20M#
2 0 0 0 0 3 0 0 1 0 4 0 0 0 1 5 0 0 1 1 5/2 0 1 0 0 7/2 0 1 1 0 9/2 0 1 0 1 11/2 0 1 1 1
(All other combinations are reserved.)
asserted by the current bus owner for one clock to indicate a new request phase. A new request phase can only begin if the in-order queue has less than the maximum number of entries defined by the power-on configuration (1 or 8), the request phase is not being stalled by an active BNR# sequence and the ADS# associated with the previous request phase is sampled inactive. Along with the ADS#, the request initiator drives A[35:3]#, REQ[4:0]#, AP[I:0]#, and RP# signals for two clocks. During the second request phase clock, ADS# must be inactive. RP# provides parity protection for REQ[4:0]# and ADS# signals during both clocks. If the transaction is part of a bus locked operation, LOCK# must be active with ADS#.
If the request initiator continues to own the bus after the first request phase, it can issue a new request every three clocks. If the request initiator needs to release the bus ownership after the request phase, it can deactivate its BREQn#/BPRI# arbitration signal as early as with the activation of ADS#.
All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. On sampling the asserted ADS#, all agents load the new transaction in the in-order queue and update internal counters. The error, snoop, response, and data phase of the transaction are defined with respect to ADS# assertion.
2-10 Service Guide
Page 70
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
AERR# AE9 I/O, GTL+ The AERR# signal is the address parity error
signal. Assuming the AERR# driver is enabled during the power-on configuration, a bus agent can drive AERR# active for exactly one clock during the error phase of a transaction. AERR# must be inactive for a minimum of two clocks. The error phase is always three clocks from the beginning of the request phase.
On observing active ADS#, all agents begin parity and protocol checks for the signals valid in the two request phase clocks. Parity is checked on AP[1:0]# and RP# signals. AP1# protects A[35:24]#, AP0# protects A[23:3]# and RP# protects REQ[4:0]#. A parity error without a protocol violation is signaled by AERR# assertion.
If AERR# observation is enabled during a power­on configuration, AERR# assertion in a valid error phase aborts the transaction. All bus agents remove the transaction from the in-order queue and update internal counters. The snoop phase, response phase, and data phase of the transaction are aborted. Specifically if the snoop phase associated with the aborted transaction is driven in the next clock, the snoop results, including a STALL condition (HIT# and HITM# asserted for one clock), are ignored. All bus agents must also begin an arbitration reset sequence and deassert BREQn#/BPRI# arbitration signals on sampling AERR# active. A current bus owner in the middle of a bus lock operation must keep LOCK# asserted and assert its arbitration request BPRI#/BREQn# after keeping it inactive for two clocks to retain its bus ownership and guarantee lock atomicity. All other agents, including the current bus owner not in the middle of a bus lock operation, must wait at least 4 clocks before asserting BPRI#/BREQn# and beginning a new arbitration.
If AERR# observation is enabled, the request initiator can retry the transaction up to n times until it reaches the retry limit defined by its implementation. After n retries, the request initiator treats the error as a hard error. The request initiator asserts BERR# or enters the machine check exception handler, as defined by the system configuration.
If AERR# observation is disabled during a power­on configuration, AERR# assertion is ignored by all bus agents except a central agent. Based on the system machine check architecture, the central agent can ignore AERR#, assert NMI to execute NMI handler, or assert BINIT# to reset
Major Chipsets 2-11
Page 71
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
the bus units of all agents and execute an MCE handler.
AP[1:0]# S9, U1 I/O, GTL+ The AP[1:0]# signals are the address parity
signals. They are driven by the request initiator during the two request phase clocks along with ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This rule allows parity to be high when all the covered signals are high.
Provided "AERR# drive" is enabled during the power-on configuration, all bus agents begin parity checking on observing active ADS# and determine if there is a parity error. On observing a parity error on any one of the two request phase clocks, the bus agent asserts AEPR# during the error phase of the transaction.
BCLK A19 I, 3.3V The BCLK (clock) signal is the execution control
group input signal. It determines the bus frequency. All agents drive their outputs and latch their inputs on the BCLK rising edge.
The BCLK signal indirectly determines the P6 processor's internal clock frequency. Each P6 processor derives its internal clock from BCLK by multiplying the BCLK frequency by 2, 3, or 4 as defined and allowed by the power-on configuration.
All external timing parameters are specified with respect to the BCLK signal.
BERR# C5 I/O, GTL+ The BERR# signal is the error group bus error
signal. It indicates an unrecoverable error without a bus protocol violation if asserted.
The BERR# protocol is as follows: If an agent detects an unrecoverable error for which BERR# is a valid error response and BERR# is sampled inactive, it asserts BERR# for three clocks. An agent can assert BERR# only after observing that the signal is inactive. An agent asserting BERR# must deassert the signal in two clocks if it observes that another agent began asserting BERR# in the previous clock.
BERR# assertion conditions are defined by the system configuration. Configuration options enable the BERR# driver as follows:
enabled or disabled asserted optionally for internal errors along with IERR# optionally asserted by the request initiator of a bus transaction after it observed an error
asserted by any bus agent when it observes an error
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
in a bus transaction
BERR# continued
BINIT# AC43 I/O, GTL+ The BINIT# signal is the bus initialization signal.
BNR# U7 I/O, GTL+ The BNR# signal is the block next request signal
C5 I/O, GTL+ BERR# sampling conditions are also defined by
the system configuration. Configuration options enable the BERR# receiver to be enabled or disabled. When the bus agent samples an active BERR# signal and if MCE is enabled, the P6 processor enters the machine check handler. If MCE is disabled, typically the central agent forwards BERR# as an NMI to one of the processors.
If the BINIT# driver is enabled during the power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information.
The BINIT# protocol is as follows: If an agent detects an error for which BINIT# is a valid error response, and BINIT# is sampled inactive, it asserts BINIT# for three clocks. An agent can assert BINIT# only after observing that the signal is inactive. An agent asserting BINIT# must deassert the signal in two clocks if it observes that another agent began asserting BINIT# in the previous clock.
If BINIT# observation is enabled during a power­on configuration, and BINIT# is sampled asserted, all bus state machines are reset. All agents reset their rotating ID for bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches are not affected.
If BINIT# observation is disabled during power-on configuration, BINIT# is ignored by all bus agents except a central agent that must handle the error in a manner appropriate to the system architecture.
in the arbitration group. The BNR# signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions to avoid an internal transaction queue overflow. During a bus stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
BNR# continued
BP[3:2]# AC39, AE43 I/O, GTL+ The BP[3:2]# signals are the system support
BPM[1:0]# AA39, AC41 I/O, GTL+ The BPM[1:0]# signals are more system support
U7 I/O, GTL+ A valid bus stall involves assertion of BNR# for
one clock on a well-defined clock edge (T1), followed by de-assertion of BNR# for one clock on the next clock edge (T1+1). BNR# can first be sampled on the second clock edge (T1+1) and must always be ignored on the third clock edge (T1+2). An extension of a bus stall requires one clock active (T1+2), one clock inactive (T1+3) BNR# sequence with BNR# sampling points every two clocks (T1+1, T1+3,...).
After the RESET# active-to-inactive transition, bus agents might need to perform hardware initialization of their bus unit logic. Bus agents intending to create a request stall must assert BNR# in the clock after RESET# is sampled inactive.
After BINIT# assertion, all bus agents go through a similar hardware initialization and can create a request stall by asserting BNR# four clocks after BINIT# assertion is sampled.
On the first BNR# sampling clock that BNR# is sampled inactive, the current bus owner is allowed to issue one new request. Any bus agent can immediately reassert BNR# (four clocks from the previous assertion or two clocks from the previous de-assertion) to create a new bus stall. This throttling mechanism enables independent control on every new request generation.
If BNR# is deasserted on two consecutive sampling points, new requests can be freely generated on the bus. After receiving a new transaction, a bus agent can require an address stall due to an anticipated transaction-queue overflow condition. In response, the bus agent can assert BNR#, three clocks from active ADS# assertion and create a bus stall. Once a bus stall is created, the bus remains stalled until BNR# is sampled asserted on subsequent sampling points.
group breakpoint signals. They are outputs from the PE processor that indicates the status of breakpoints.
group breakpoint and performance monitor signals. They are outputs from the P6 processor that indicates the status of breakpoints and programmable counters used for monitoring P6 performance.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
BPRI# U5 I, GTL+ The BPRI# is the priority-agent bus request
signal. The priority agent arbitrates for the bus by asserting BPRI#. The priority agent is always the next bus owner. Observing BPRI# active causes the current symmetric owner to stop issuing new requests unless the requests are part of an ongoing locked operation.
If LOCK# is sampled inactive two clocks from BPRI# driven asserted, the priority agent can issue a new request within four clocks of asserting BPRI#. The priority agent can further reduce its arbitration latency to two clocks if it samples active ADS# and inactive LOCK# on the clock in which BPRI# was driven active. It can reduce its arbitration latency to three clocks if it samples active ADS# and inactive LOCK# on the clock in which BPRI# was sampled active. If LOCK# is sampled active, the priority agent must wait for LOCK# to be sampled deasserted to gain bus ownership in two clocks. The priority agent can keep BPRI# asserted until all of its requests are completed and can release the bus by deasserting BPRI# at the same clock edge on which it issued the last request.
On observation of active AERR#, RESET#, or BINIT#. BPRI# must be deasserted in the next clock. BPRI# can be reasserted in the clock after sampling the RESET# active-to-inactive transition or three clocks after sampling BINIT# active and RESET# inactive. On AERR# assertion, if the priority agent is in the middle of a bus-locked operation, BPRI# must be reasserted after two clocks, otherwise BPRI# must stay inactive for at least 4 clocks.
After the RESET# inactive transition, P6 bus agents begin BPRI# and BNR# sampling on BNR# sample points. If both BNR# and BPRI# are observed inactive on BNR# sampling points, the P6 APIC units on a common APIC bus are synchronized. In a system with multiple P6 bus clusters sharing a common APIC bus, BPRI# signals of all clusters must be asserted after RESET# until BNR# is observed inactive on a BNR# sampling point. The BPRI# signal on all P6 buses must then be deasserted within 100ns of each other to accomplish APIC bus synchronization across all processors.
CPUPRES# B2 Other CPUPRES# is a ground pin that allows a
designer to detect the presence of a processor in a socket.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
BR0# BR[3:1]#
D[63:60]# D[59:56]# D[55:52]# D[51:48]# D[47:44]# D[43:40]# D[39:36]# D[35:32]# D[31:28]# D[27:24]# D[23:20]# D[19:16]# D[15:12]# D[11:08]# D[07:04]# D[03:00]#
AC5 U9, AA1, W3
W43, Y47, W45, U43 S39, W47, S41, U45 U47, S43, S45, Q41 Q39, S47, Q43, Q45 N43, Q47, N41, N39 L43, N45, N47, L41 L47, J43, L39, L45 J41, J47, J45, J39 G47, G43, G41, G45 G39, E47, E43, E45 E41, E39, C47, C41 C45, C43, C39, A45 C37, A37, A43, C35 A41, A39, A35, A33 C33, C31, A31, C29 A29, C27, A27, C25
I/O, GTL+
I, GTL+
I/O, GTL+ The D[63:0]# signals are the data signals. They
The BR[3:0]# pins are the physical bus request pins that drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. Below are the rotating interconnections between the processor and bus signals.
Bus Pins
Signal Agent 0 Agent 1 Agent 2 Agent 3
BREQ0# BR0# BR3# BR2# BR1# BREQ1# BR1# BR0# BR3# BR2# BREQ2# BR1# BR0# BR3# BR3# BREQ3# BRS# BR2# BR1# BR0#
During a power-up configuration, the central agent must assert the BR0# bus signal. All symmetric agents sample their BR[3:0]# pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. All agents then configure their pins to match the appropriate bus signal protocol, as shown in below:
Pin sampled active on RESET# Agent ID
BR0# 0 BR3# 1 BR2# 2 BR1# 3
are driven during the data phase by the agent responsible for driving the data. These signals provide a 64-bit data path between various P6 bus agents. The 32-byte line transfers require four data transfer clocks with valid data on all eight bytes. Partial transfers require one data transfer clock with valid data on the byte(s) indicated by active byte enables BE[7:0]#. Data signals not valid for a particular transfer must still have correct ECC (if data bus ECC is selected). If BE0# is asserted, D[7:03]# transfers the least significant byte. If BE7# is asserted. D[63:56]# transfers the most significant byte.
The data driver asserts DRDY# to indicate a valid data transfer. If the data phase involves more than one clock the data driver also asserts DBSY# at the beginning of the data phase and deasserts DBSY# on the same clock that it performs the last data transfer.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
DBSY# AA5 I/O, GTL+ The DBSY# signal is the data-bus busy signal. It
indicates that the data bus is busy. It is asserted by the agent responsible for driving the data during the data phase, provided the data phase involves more than one clock. DBSY# is asserted at the beginning of the data phase and is deasserted on the same clock on which the last data is driven.
When normal read data is being returned, the data phase begins with the response phase. Thus the agent returning read data can assert DBSY# when the transaction reaches the top of the in­order queue and it is ready to return response on RS[2:0]# signals. In response to a write request, the agent driving the write data must drive DBSY# active after the write transaction reaches the top of the in-order queue and it sees active TRDY# with inactive DBSY# indicating that the target is ready to receive data. For an implicit write-back response, the snoop agent must assert DBSY# active after the target memory agent of the implicit write-back asserts TRDY#. Implicit write-back TRDY# assertion begins after the transaction reaches the top of the in-order queue, and TRDY# de-assertion associated with the write portion of the transaction, if any, is completed. In this case, the memory agent guarantees assertion of implicit write-back response in the same clock in which the snooping agent asserts DBSY#.
DEFER# Y5 I, GTL+ The DEFER# signal is the defer signal. It is
asserted by an agent during the snoop phase to indicate that the transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory: agent or I/O agent. For systems that involve resources on a system bus other than the P6 bus, a bridge agent can accept the DEFER# assertion responsibility on behalf of the addressed agent.
DEFER# can only be asserted if DEN# is active during the request phase. When HITM# and DEFER# are both active during the snoop phase, HITM# is given priority and the transaction must be completed with implicit write-back response. If HITM# is inactive, and DEFER# active, the agent asserting DEFER# must complete the transaction with a deferred or retry response.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
DEFER# Y5 I, GTL+ If DEFER# is inactive, or HITM# is active, then
the transaction is committed for in-order completion and snoop ownership is transferred normally between the requesting agent, the snooping agents, and the response agent.
If DEFER# is active with HITM# inactive, the transaction commitment is deferred. If the defer agent completes the transaction with a retry response, the requesting agent must retry the transaction. If the defer agent returns a deferred response, the requesting agent must freeze snoop state transitions associated with the deferred transaction and issues of new order­dependent transactions until the corresponding deferred reply transaction. In the meantime, the ownership of the deferred address is transferred to the defer agent and it must guarantee management of conflicting transactions issued to the same address.
If DEFER# is active in response to a newly issued bus-lock transaction, the entire bus-locked operation is re-initiated regardless of HITM#. This feature is useful for a bridge agent in response to a split bus-locked operation. It is recommended that the bridge agent extend the snoop phase of the first transaction in a split locked operation until it can either guarantee ownership of all system resources to enable successful completion of the split sequence or assert DEFER# followed by a retry response to abort the split sequence.
DEP[7:0]# U39, Y45, AA47,
W41, A47, W39, Y43, AC45
I/O, GTL+ The DEP[7:0]# signals are the data bus
ECC/parity signals. They are driven during the data phase by the agent responsible for driving D[63:0]#. The DEP[7:0]# signals provide optional ECC protection for the data bus. During power-on configuration, DEP[7:0]# signals can be enabled for either ECC checking or no checking.
The ECC error correcting code can detect and correct single-bit errors and detect double-bit or nibble errors.
DEP[7:0]# provide valid ECC for the entire data bus on each data clock, regardless of which bytes are valid If checking is enabled, receiving agents check the ECC signals for all 64 data signals.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
DRDY# AA3 I/O, GTL+ The DRDY# signal is the data phase data-ready
signal. The data driver asserts DRDY# on each data transfer. indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks in the data phase. During a line transfer, DRDY# is active for four clocks. During a partial 1-to-8 byte transfer. DRDY# is active for one clock. Except for the last data clock during a data phase, DRDY# and DBSY# must both be active together. If a data transfer is exactly one clock, then the entire data phase consists of one clock active DRDY# and inactive DBSY#.
FERR# C17 O, 3.3V The FERR# signal is the PC compatibility group
floating-point error signal. The P6 processor asserts FERR# when it detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel387 coprocessor. FERR# is included for compatibility with systems using DOS-type floating-point error reporting.
FLUSH# A15 I, 3.3V When the FLUSH# input signal is asserted, the
P6 bus agent writes back all internal cache lines in the modified state and invalidates all internal cache lines. At the completion of a flush operation, the P6 processor issues a flush acknowledge transaction to indicate that the cache flush operation is complete. The P6 processor stops caching any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous input. However, to guarantee recognition of this signal following an I/O write instruction, FLUSH# must be valid along with RS[2:0]# in the response phase of the corresponding l/O Write bus transaction. In FRC mode, FLUSH# must be synchronous to BCLK.
On active-to-inactive transition of RESET#, each P6 bus agent samples FLUSH# signals to determine its power-on configuration. Two clocks after RESET# is sampled deasserted, these signals begin normal operation.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
FRCERR C9 I/O, GTL+ The FRCERR signal is the error group 7
functional-redundancy-check error signal. If two P6 processors are configured in an FRC pair, as a single "logical" processor, then the checker processor asserts FRCERR if it detects a mismatch between its internally sampled outputs and the master processor's outputs. The checker's FRCERR output pin is connected to the master's FRCERR input pin.
For point-to-point connections, the checker always compares against the master's outputs. For bussed single-driver signals, the checker compares against the signal when the master is the only allowed driver. For bussed multiple-driver wire-OR signals, the checker compares against the signal only if the master is expected to drive the signal low.
FRCERR is also toggled during the P6 processor's reset action. A P6 processor asserts FRCERR for approximately 1 second after RESET's active-to-inactive transition if it executes its built-in self-test (BIST). When BIST execution completes, the P6 processor de-asserts FRCERR if BIST completed successfully and continues to assert FRCERR if BIST fails. If the P6 processor does not execute the BIST action, then it keeps FRCERR asserted for approximately 20 clocks and then deasserts it.
HIT# HITM#
AC3 AA7
I/O, GTL+ I/O, GTL+
The HIT# and HITM# signals are snoop-hit and hit-modified signals. They are snoop results asserted by any P6 bus agent in the snoop phase.
Any bus agent can assert both HIT# and HITM# together for one clock in the snoop phase to indicate that it requires a snoop stall. When a stall condition is sampled, all bus agents extend the snoop phase by two clocks The stall can be continued by reasserting HIT# and HITM# together every other clock for one clock.
A caching agent must assert HITM# for one clock in the snoop phase if the transaction hits a modified line, and the snooping agent must perform an implicit write-back to update main memory. The snooping agent with the modified line makes a transition to shared state if the original transaction is read line or read partial, otherwise it transitions to invalid state. A deferred reply transaction may have HITM# asserted to indicate the return of unexpected data.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
HIT# HITM# continued
IERR# C3 O, 3.3V The IERR# is the error group internal error signal.
IGNNE# A9 I, 3.3V The IGNNE# signal is the PC Compatibility group
AC3 AA7
I/O, GTL+ I/O, GTL+
A snooping agent must assert HIT# for one clock during the snoop phase if the line does not hit a modified line in its write-back cache and if at the end of the transaction its plans to keep the line in shared state. Multiple caching agents can assert HIT# in the same snoop phase. If the requesting agent observes HIT# active during the snoop phase it can not cache the line in exclusive or modified state.
On observing a snoop stall, the agents asserting HIT# and HlTM# independently reassert the signal after one inactive clock so that the correct snoop result is available, in case the snoop phase terminates after the two clock extension.
A P6 processor asserts IERR# when it observes an internal error. It keeps IERR# asserted until it is turned off as part of the machine check error or the NMI handler in software, or with RESET#, BINIT#, and INIT# assertion.
An internal error can be handled in several ways inside the processor based on its power-on configuration. If MCE is enabled, IERR# causes an MCE entry. IERR# can also be directed on the BERR# pin to indicate an error. Usually BERR# is sampled back by all processors to enter MCE or it can be redirected as an NMI by the central agent.
Ignore numeric error signal. If IGNNE# is asserted, the P6 processor ignores a numeric error and continues to execute non-control floating-point instructions. If IGNNE# is deasserted, the P6 processor freezes on a non­control floating-point instruction if previous instruction caused an error.
IGNNE# has no effect when the NE bit in control register o is set. IGNNE# is an asynchronous input. However, to guarantee recognition of thus signal following an I/O write instruction, IGNNE# must be valid along with RS[2:0]# in the response phase of the corresponding I/O Write bus transaction. In FRC mode, IGNNE# must be synchronous to BCLK. During active RESET#, the P6 processor begins sampling the A20M# and IGNNE# values to determine the ratio of core­clock frequency to bus-clock frequency. (See A20M# signal description for details).
After the PLL-lock time, the core clock is stabilized and locked to the external bus clock. On the active-to-inactive transition of RESET#, the P6 processor latches A20M# and IGNNE# and freezes the frequency ratio internally. Normal operation on the two signals continues two clocks
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
after sampling RESET# inactive.
INIT# C11 I, 3.3V The INIT# signal is the execution control group
initialization signal. Active INIT# input resets integer registers inside all P6 processors without affecting their internal (L1 or L2) caches or their floating-point registers. Each P6 processor begins execution at the power-on reset vector configured during power-on configuration regardless of whether INIT# has gone inactive. The processor continues to handle snoop requests during INIT# assertion.
INIT# can be used to help performance of DOS extenders written for the Intel 80286 processor. INIT# provides a method to switch from protected mode to real mode while maintaining the contents of the internal caches and floating-point state. INIT# can not be used in lieu of RESET# after power-up.
On active-to-inactive transition of RESET#, each P6 bus agent samples INIT# signals to determine its power-on configuration. Two clocks after RESET# is sampled deasserted these signals begin normal operation.
INIT# is an asynchronous input. In FRC mode, INIT# must be synchronous to BCLK.
INTR AG43 I, 3.3V The INTR signal is the interrupt request signal. It
is the power-on default state of the LINT0 signal in the APIC group. The INTR input indicates that an external interrupt has been generated. The interrupt is maskable using the IF bit in the EFLAGS register. If the IF bit is set, the P6 processor vectors to the interrupt handler after the current instruction execution is completed. Upon recognizing the interrupt request, the P6 processor issues a single interrupt acknowledge (INTA) bus transaction. INTK must remain active until the INTA bus transaction to guarantee its recognition.
INTR is sampled on every rising BCLK edge. INTR is an asynchronous input but recognition of INTR is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times. INTR must also be deasserted for a minimum of two clocks to guarantee its inactive recognition. In FRC mode, INTR must be synchronous to BCLK.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
LlNT[1:0] AG41, AG43 I, 3.3V The LINT[1:0] signals are the execution control
group local interrupt signals. When APIC is disabled, LINT0 signal defaults to the maskable interrupt request signal INTR and LINT1 to a non­maskable interrupt (NMI). INTR and NMl are backward compatible with the same signals in the Pentium processor. Both signals are asynchronous inputs. In FRC mode, LINT[1:0] must be synchronous to BCLK. LINT[1:0] signals need to be programmed when APIC is enabled.
During active RESET#, P6 begins sampling the A20M# and IGNNE# values to determine the ratio of core-clock frequency to bus-clock frequency. After the PLL-lock time, the core clock is stabilized and locked to the external bus clock. On the active-to-inactive transition of RESET#, P6 latches A20M# and IGNNE#, and internally freezes the frequency ratio. Normal operation on the two signals continues two clocks after sampling RESET# inactive.
LINT[1:0]# is used for core-to-bus frequency ratio extensions of future processors. Use the pins in the power-on configuration logic similar to the A20M# and IGNNE# pins.
LOCK# AA9 I/O, GTL+ The LOCK# signal is the arbitration group bus
lock signal. For a locked transaction sequence, LOCK# is asserted from the first transaction's request phase through the last transaction's response phase. A locked operation can be prematurely aborted (and LOCK# deasserted) if AERR# or DEFER# is asserted during the first bus transaction of the sequence. The sequence can also be prematurely aborted if a hard error (such as a hard failure response or AERR# assertion be beyond the retry limit) occurs on any one of the transactions during the locked operation.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes LOCK# deasserted. This enables symmetric agents to retain bus ownership throughout the bus locked operation and guarantee the atomicity of lock. If AERR# is asserted up to the retry limit during an ongoing locked operation, the arbitration protocol ensures that the lock owner receives the bus ownership after arbitration logic is reset. This is accomplished by requiring the lock owner to reactivate its arbitration request one clock ahead of other agents' arbitration request. LOCK# is kept asserted throughout the arbitration reset sequence.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
NMI AG41 I, 3.3V The NMI signal is the non-maskable interrupt
signal. It is the default state of the LINT1 signal. Asserting NMI causes an interrupt with an internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized after the IREI is executed by the NMI service routine. At most, one assertion of NMI is held pending.
NMI is rising-edge sensitive. Recognition of NMI is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times. If asserted asynchronously, active and inactive pulse widths must be a minimum of two clocks. In FRC mode, NMI must be synchronous to BCLK.
PICCLK AA43 I, 5V The PICCLK signal is the execution control group
APIC Clock signal. It is an input clock to the P6 processor for synchronous operation of the APIC bus. PICCLK must be synchronous to BCLK in FR7 mode.
PICD[1:0] AE21, AA41 I/O, 5V The PICD[1:0] signals are the execution control
group APIC Data signals. They are used for bidirectional serial message passing on the APIC bus.
PLL[2:1] C23, C19 Others Isolated analog decoupling is required for the
internal phase lock loop (PLL). This should be equivalent to 0.1uF of ceramic capacitance across the PLL1 and PLLw pins.
PRDY# Y39 O, GTL+ The PRDY# signal is the system support group
probe ready signal. A P6 processor asserts PRDY to indicate that it has entered probe mode and that its test access port (TAP) is ready to accept a boundary scan or probe mode command.
PREQ# AA45 I, 3.3V The PREQ# signal is the system support group
probe request signal. Asserting PREQ# stops normal P6 processor execution and places the P6 processor in probe mode,: where it is capable of executing probe instructions. Probe mode is similar to ICE mode (in-circuit emulator mode) on other Intel processors.
PWRGOOD AG7 I, 3.3V PWRGOOD is a 3.3V tolerant input. This signal
is a clean indication that clocks and the system
3.3V, 5V and VCCP supplies are stable and within
their specifications. PWRGOOD can be driven inactive at any time but power and clocks must be stable before the rising edge of PWRGOOD.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
REQ[4:0]# W5, Y1, Y3, W7,W9I/O, GTL+ The REQ[4:0]# signals are request command
signals. They are asserted by the current bus owner in both clocks of the request phase. In the first clock, the REQa[4:0]# signals define the transaction type to a level sufficient to begin a snoop request. In the second clock, REQb[4:0]# signals carry additional information to define the complete transaction type. REQb[4:2]# is reserved. REQb[1:0]# signals transmit LEN[1:0]# (the data transfer length information). In both clocks, REQ[4:0]# and ADS# are protected by parity RP#.
All receiving agents observe the REQ[4:0]# signals to determine the transaction type and participate in the transaction as necessary, as shown in below:
Transaction REQa[4:0]# REQb[4:0]#
Deferred Reply 00000 XXXXX Rsvd (Ignore) 00001 XXXXX Interrupt Acknowledge 01000 DSZ[1:0]#,000 Special Transactions 01000 DSZ[1:0]#,001 Rsvd (Central agent response) 01000 DSZ[1:0]#,01X Rsvd (Central agent response) 01000 DSZ[1:0]#,1XX Branch Trace Message 01001 DSZ[1:0]#,000 Rsvd (Central agent response) 01001 DSZ[1:0]#,001 Rsvd (Central agent response) 01001 DSZ[1:0]#,01X Rsvd (Central agent response) 01001 DSZ[1:0]#,1XX I/O Read 10000 DSZ[1:0]#, rsvd,
I/O Write 10001 DSZ[1:0]#, rsvd, Rsvd (Ignore) 1100X DSZ[1:0]#,XXX
Memory Read & Invalidate ASZ[1:0]#, DSZ[1:0]#, rsvd,
010 LEN[1:0]#
Rsvd (Memory Write) ASZ[1:0]#, DSZ[1:0]#, rsvd,
011 LEN[1:0]#
Memory Read ASZ[1:0]#, 1, DSZ[1:0]#, rsvd,
D/C#, 0 LEN[1:0]#
Memory Write ASZ[1:0]#, 1, DSZ[1:0]#, rsvd,
W/WB#, 0 LEN[1:0]#
RESET# Y41 I, GTL+ The RESET# signal is the execution control group
reset signal. Asserting RESET# resets all P6 processors to known states and invalidates their L1 and L2 caches without writing back modified (M state) lines. RESET# must remain active for one microsecond for a "warm" reset. For a power­on type reset, RESET# must stay active for at least one millisecond after VCC and CLK have reached their proper DC and AC specifications. On observing active RESET#, all bus agents must deassert their outputs within two clocks.
LEN[1:0]# LEN[1:0]#
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
RESET# continued
RP# AC7 I/O, GTL+ The RP# signal is the request parity signal. The
RS[2:0]# AE7,AE5,AC9 I, GTL+ The RS[2:0]# signals are the response status
Y41 I, GTL+ A number of bus signals are sampled at the
active-to-inactive transition of RESET# for the power-on configuration.
Unless its outputs are tristated during power-on configuration, after active-to-inactive transition of RESET#, the P6 processor optionally executes its built-in self-test (BIST) and begins program execution at reset-vector 00_000F_FFF0H or 00_FFFF FFF0H.
request initiator drives it in both clocks of the request phase. RP# provides parity protection on ADS# and REQ[4:0]#. When a P6 bus agent observes an RP# parity error on any one of the two request phase clocks, it must assert AERR# in the error phase, provided "AERR# drive" is enabled during the power-on configuration. A correct parity signal is high if an even number of covered signals are low. It is low if an odd number of covered signals are low. Parity are high when all covered signals are high.
signals. They are driven by the response agent (the agent responsible for completion of the transaction at the top of the in-order queue). Assertion of RS[2.0]# to a non-zero value for one clock completes the response phase for a transaction. The response encodings are shown in below. Only certain response combinations are valid, based on the snoop result signaled during the transaction's snoop phase.
RS[2:0]# HITM# DEFER# Description
000 NA NA Idle state. 001 0 0 Retry Response.
010 0 1 Defer Response.
011 0 1 Reserved 100 X X Hard Failure.
101 0 0 Normal without data 110 1 X Implicit write-back
111 0 0 Normal with data.
The transaction is canceled and must be retried by the initiator.
The transaction is suspended. The defer agent completes it with a defer reply
The transaction received a hard error. Exception handling is required.
response. Snooping agent transfers the modified cache line on be data bus.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
RS[2:0]# continued
AE7, AE5, AC9 I, GTL+ The RS[2:0]# assertion for a transaction is
initiated when all of the following conditions are met:
All bus agents have observed the snoop phase completion of the transaction.
The transaction is at the top of in-order queue.
RS[2:0]# are sampled in the idle state
The response driven depends on the following transactions:
The response agent returns a hard-failure response for any transaction in which the response agent observes a hard error.
The response agent returns a normal with data response for a read; transaction with HITM# and DEFER# deasserted in the snoop phase, when the addressed agent is ready to return data and samples inactive DBSY#.
The response agent returns a normal without data response for a write transaction with HITM# and DEFER# deasserted in the snoop phase, when the addressed agent samples TRDY# active and DBSY# inactive, and it is ready to complete the transaction.
The response agent must return an implicit write-back response in the next clock for a read transaction with HITM# asserted in the snoop phase, when the addressed agent samples TRDY# active and DBSY# inactive.
The addressed agent must return an implicit write-back response in the clock after the following sequence is sampled for a write transaction with HITM# asserted:
TRDY# active and DBSY# inactive
followed by TRDY# inactive
followed by TRDY# active and DBSY# inactive
The defer agent can return a deferred, retry, or split response anytime for a read transaction with STM# deasserted and DEFER# asserted.
The defer agent returns deferred, retry, or split response when it samples TRDY# active and DBSY# inactive for a write transaction with HITM# deasserted and DEFER# asserted.
Major Chipsets 2-27
Page 87
Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
SMI# W1 I, 3.3V The SMI# is the response system management
interrupt (SMI) signal. It is asserted by the response agent in the response phase. The addressed I/O agent asserts SMI# to signal a synchronous I/O restart SMI in response to an I/O transaction initiated by the processor to a powered-down I/O device. In observing an active RSMI# during the response phase, the P6 processor saves the current state and enters SMM mode. It issues an SMI acknowledge bus transaction then begins program execution from the SMM handler. It is not protected under parity and is an optional signal if the system does not support any synchronous I/O restart capability.
RSP# U3 I, GTL+ The RSP# is the response parity signal. It is
driven by the response agent during the assertion of RS[2:0]#. RSP# provides parity protection for RS[2:0]#.
A correct parity signal is high if an even number of covered signals are low. It is if an odd number of covered signals are low. During idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high since it is not driven by any agent guaranteeing correct parity.
P6 bus agents check RSP# at all times and if a parity error is observed, treat it as a protocol violation error. If the BINIT# driver is enabled during configuration, the agent observing RSP# parity error asserts BTNIT#.
STPCLK# A3 I, 3.3V The STPCLK# is the stop clock signal. When
asserted, P6 enters a low power stop-clock state. The processor issues a stop clock acknowledge special transaction and stops sending internal clock signals to all units except the bus unit and the APIC unit. P6 continues to snoop bus transactions and service interrupts in the stop clock state. When STPCLK# is deasserted, P6 restarts its internal lock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock. STPCLK# is an asynchronous input. In FRC mode, STPCLK# must be synchronous to BCLK.
TCK A5 I, JTAG The TCK is the system support group test clock
signal. TCK provides the clock input for the test bus (also known as the test access port). TCK must be connected to a clock to ensure initialization of the JTAG support.
TDI A13 I, JTAG The TDI is the system support group test-data-in
signal. TDI transfers serial test data into the P6 processor. TDI provides the serial input needed for JTAG support.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
TDO C13 O, JTAG The TDO is the system support group test-data-
out signal. TDO transfers serial test data out from the P6 processor. TDO provides the serial output needed for JTAG support.
TESTHI A23, A25, AE39 Other TESTHI pins should be tied to VCCP. A 10K pull-
up resistor may be used.
TESTLO
THERMTRIP# A17 O, 3.3V The P6 processor protects itself from catastrophic
TMS C15 I, JTAG The TMS is an additional system support group
TRDY# Y9 I, GTL+ The TRDY# is the target ready signal. It is
C21, AS39, AS41, AS43, AS45, BA13, BA15, BA33, BA37, BC13, BC15, BC33, BC37
Other TESTLO pins should be tied to VSS. A 1K pull-
down resistor may be used.
overheating through an internal thermal sensor. This sensor is set way above the normal operating temperature to ensure that there are no false trips. The P6 stops all executions when the junction temperature exceeds 135°C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched and P6 stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. As long as the temperature drops below the trip level, a RESET# pulse resets P6 and the execution continues. If the temperature has not dropped beyond the trip level, P6 continues to drive THERMTRIP# and remain in inactivity.
JTAG-support signal.
asserted by the target in the response phase to indicate that the target is ready to receive write or implicit write-back data transfer. This enables the request initiator or the snooping agent to begin the appropriate data transfer. There is no data transfer after a TRDY# assertion if a write has zero length in the request phase. The data transfer is optional if an implicit write-back occurs for a transaction that writes a full cache line (P6.0 DX performs the implicit write-back). For a write transaction, TRDY# is driven by the addressed agent when:
the transaction has a write or write-back data transfer
it has a free buffer available to receive the write data
there is a minimum of 3 clocks after ADS# for the
transaction
the transaction reaches the top of the in-order queue
there is a minimum of 1 clock after RS[2:0]# active
assertion for transaction "n-1” (after the transaction reaches the top of in-order queue).
TRDY# continued
Y9 I, GTL+ For an implicit write-back, TRDY# is driven by the
addressed agent when:
Major Chipsets 2-29
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
transaction has an implicit write-back data transfer indicated in the Snoop Result Phase.
it has a free cache line buffer to receive the cache line write-back if the transaction also has a request initiated transfer, that the request initiated TRDY# was asserted and then deasserted (EDY# must be deasserted for at least one clock between the TRDY# for the write and the TRDY# for the implicit write­back),
a minimum of I clock after RS[2:0]# active assertion for transaction "n-1". (After the transaction reaches the top of in-order queue).
TRDY# for a write or an implicit write-back may be deasserted when:
inactive DBSY# and active TRDY# are observed
DBSY# is observed inactive on the clock TRDY# is
asserted.
a minimum of 3 clocks are guaranteed between two TRDY# active-to-inactive transitions
the response is driven on RS[2:0]#
inactive DBSY# and active TRDY# are observed for a
write, and TRDY# is required for an implicit write­back
TRST# A7 I, JTAG The TRST# is an additional system support group
JTAG-support signal.
UP# AG3 Other The upgrade present signal is an open in the P6
processor and tied to VSS in the OverDrive processor. This prevents the operation of voltage regulators that cause a potentially harmful voltage to the OverDrive processor. It also prevents a contention between onboard regulator and OverDrive processor VRM.
VCC5 Power VCC5 is used by the OverDrive processor for
fan/heatsink power.
VCCP
B4, B8, B16, B24, B32, B40, B44, F2, F6, F42, F46, K4, K44, P2, P6, P42, P46, T4, T44, X6, X42, AB4, AB44, AJ3, AJ7, AJ41, AJ45, AL1, AL5, AL39, AL43, AL47, AN3, AN7, AN41, AN45, AQ1, AQ5, AQ9, AQ39, AQ43, AQ47, BA17, BA21, BA25, BA29
Power VCCP the primary power supply.
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
VCCS
VID[3:0] AS1, AS3, AS5,
V
[7:0] AG45, U41,
REF
AU1, AU5, AU9, AU39, AU43, AU47, AW3, AW7, AW41, AW45, AY1, AY3, AY5, AY7, AY9, AY39, AY41, AY43, AY45, AY47, BA3, BA7, BA41, BA45, BC19, BC23, BC27, BC31
AS7
AE47, A47, Y7, S7, C7, A1
Power VCCS is the secondary power supply used by
Power V
some second level cache versions.
VID[3:0] are 4-voltage identification pins on the P6. These pins support automatic selection of power supply voltage. These pins are not signals but are either an open circuit in the processor or a short circuit to Vss.
The open and short circuits define the voltage required by P6. This has been added to cleanly support voltage specification variations on future P6 processors. The following are the voltage definition of these pins:
VID[3:0] Voltage Setting VID[3:0] Voltage Setting
0000 3.5 1000 2.7 0001 3.4 1001 2.6 0010 3.3 1010 2.5 0011 3.2 1011 2.4 0100 3.1 1100 2.3 0101 3.0 1101 2.2 0110 2.9 1110 2.1 0111 2.8 1111 No CPU
[7:0] are the reference voltage pins for the
REF
GTL+ buffers.
Major Chipsets 2-31
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Table 2- 2 P6 Processor Signal Descriptions
Signal Pin Type Description
V
SS
B6, B12, B20, B28, B36, B42, B46, F4, F8, F40, F44, K2, K6, K8, K40, K42, K46, P4, P8, P40, P44, T2, T6, T8, T40, T42, T46, X3, X4, X8, X40, X44, X46, AB2, AB6, AB8, AB40, AB42, AB46, AF2, AF4, AF6, AF8, AF40, AF42, AF44, AF46, AJ1, AJ5, AJ9, AJ39, AJ43, AJ47, AL3, AL7, AL41, AL45, AN1, AN5, AN9, AN39, AN43, AN47, AQ3, AQ7, AQ41, AQ45, AU3, AU7, AU41, AU45, AW1, AW5, AW9, AW39, AW43, AW47, BA1, BA5, BA9, BA19, BA23, BA27, BA31, BA39, BA43, BA47, BC1, BC3, BC5, BC7, BC9, BC17, BC21, BC25, BC29, BC39, BC41, BC43, BC45, BC47
Power Ground
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2.2 Memory Interface Component (S82451GX)
The Memory Interface Component (MIC) provides part of a high-performance. low-cost memory subsystem solution for P6.0 based systems by combining high-integration, high-performance technology with an architecture that is capable of low-latency response and high throughput.
The MIC can connect directly to a Memory Controller with no external glue components. A typical P6.0 system may be composed of one to four P6.0 processors and a PCI bridge. The system bus is designed to support eight physical loads at 66.67 MHz so it may need an additional bridge, memory controller, or other custom attachments. These may be connected to the system bus. Additional loads may be supported at a lower bus frequency.
The four Memory Interface Component are used to interface the Memory Controller data path with the Memory sub-system. Four MIC's handle one quad-word of data between the Memory Controller and Memory. Three basic types of memory system are supported: a 4 way interleaved DRAM system, a two-way interleaved DRAM system, and a one-way non-interleaved DRAM system.
A rich set of features are provided by the MIC to meet the requirements of "state-of-the-art" high­integration desktop and server systems. In addition to the memory configurations described above, the MIC handles data that includes ECC, two back-to-back cache line writes are supported for slow DIMMs, and 3V/5V DIMMs are supported. Some power management features are included that allow some I/O drivers to be put in standby when not in use.
2.2.1 Features
Memory support
Support for 4-way interleaved conventional DRAM
Support for 2-way inlerleaved conventional DRAM
Support for 1-way non-interleaved conventional DRAM
Support for partial reads and partial writes
Support for part line read and writes
Any one of 4 interleaves can be populated
Read rate programmable
Volt and 5 Volt DIMMs are supported
Standard 36 bit DIMMs are supported
Device features
144-pin PQFP
0.5 um, 3.3 V CMOS gate array
Maximum power dissipation of tbd (< 1.5 W)
On-chip PLL
JTAG support
Major Chipsets 2-33
Page 93
2.2.2 S82451GX Pin Diagram
Figure 2- 4 S82451GX Pin Diagram
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2.2.3 S82451GX Signal Descriptions
Table 2- 3 S82451GX Signal Descriptions
Signal Pin Type Description
MIC Control Interface Signals
MICCMD#[6:0] 03-09 I
MICMWC# 10 I
MIC Data Path Interface Signals
MDE[17:10] MDE[09-02] MDE[01:00]
MD_RDY# 11 I
Memory Interface Signals
I0_D[17:16] I0_D[15-11] I0_D[10-07] I0_D[06-01]
I1_D[17:13] I1_D[12-07] I1_D[06-03] I1_D[02-00]
I2_D[17:13] I2_D[12-07] I2_D[06-01] I2_D[00]
I3_D[17:12] I3_D[11-06] I3_D[05-00]
12-19 22-29 32-33
114,115 117-121 124-127 129-134
90-94 96-101 104-107 111-113
66-70 74-79 81-86 89
43-48 51-56 58-63
I/O
I/O
I/O
I/O
I/O
MIC Command. Used to receive a command from the 82453GX to read data or write data, or to write MIC configuration data.
MIC Write Command. Command from the 82453GX to write data held in the MIC to memory.
Memory Data and ECC. ECC is computer over 64-bit data words. MDE[17:0] is one fourth of a Quad-Word.
Memory Data Ready. Asserted when input data on the memory data bus is valid.
Memory Data ECC. ECC is computed over 64-bit data words. I0_D[17:0] is one fourth of a Quad-Word that is connected to interleave zero of the memory.
Memory Data and ECC. ECC is computed over 64-bit data words. I1_D[17:0] is one fourth of a Quad-Word that is connected to interleave one of the memory.
Memory Data and ECC. ECC is computed over 64-bit data words. I2_D[17:0] is one fourth of a Quad-Word that is connected to interleave two of the memory.
Memory Data and ECC. ECC is computed over 64-bit data words. I3_D[17:0] is one fourth of a Quad-Word that is connected to interleave three of the memory.
Clock Support Signals
BCLK 39 I
System Support Signals
MI_RST# 2 I System Reset Control.
Test Interface
TCLK 142 I JTAG Test Clock. TDI 137 I JTAG Test Data In. TDO 139 O JTAG Test Data Out. TMS 135 I JTAG Test Mode Select. TRST# 141 I JTAG Test Reset.
PLL Reference Clock. This is the input to the device.
Major Chipsets 2-35
Page 95
2.3 Data Path Chipset (S82452GX)
The S82452GX, together with S82453GX, provides a high-performance, low-cost memory subsystem solution for P6.0-based systems by combining high-integration, high-performance technology with an architecture that is capable of low-latency response and high throughput.
The S82452GX can connect directly to a P6.0 system bus with no external glue components. A typical P6.0 system may be composed of one to four P6.0 processors and a PCI bridge. The system bus is designed to support eight physical loads at 66.67 MHz so the system bus may need an additional bridge, memory controller, or other custom attachments. Additional loads may be supported at lower bus frequencies.
The S82452GX and S82453GX act as interface between the P6.0 bus and the system memory. The system supports three basic types of memory: a 4:1 interleaved DRAM system, a 2:1 interleaved DRAM system, and a non-interleaved DRAM system. The 4:1 interleaved DRAM system supports a maximum memory size of 4 MB using 64-Mbit technology. For the 2:1 interleaved and non-interleaved DRAM system, the maximum memory sizes are 2 GB and 1 Byte, respectively.
The S82452GX and S82453GX also have data integrity features that include ECC in the memory array, support for memory scrubbing, and parity (control) and ECC (data) on the system bus. These features, as well as a set of error reporting mechanisms, can be selected by configuring the S82452GX and S82453GX.
2.3.1 Features
Processor support
Full support for the 64 bit P6.0 bus operating at 50.0 to 66.67 MHz (15ns).
ECC protection for the P6.0 data bus.
Parity protection for the P6.0 control bus.
Support for 36 bit addresses.
8 or 1 deep in-order queue; 4 deep request queue.
Four cache line read buffer, 4 cache line write buffer.
Multiprocessor support (snarfing).
Support for third party defer of transactions.
GTL+ bus driver technology.
Memory support
Support for up to 4 GB of 4-way interleaved conventional DRAM, per controller, using 64
Mbit technology DRAMs.
Support for 2-way interleaved and non-interleaved conventional DRAM.
Support for 4 Mbit, 16 Mbit, and 64 Mbit devices.
Supports permuting memory address bits to obtain alternate row selection bits.
Mixed memory sizes allowed (when address bit permuting is not used).
Staggered CAS-before-RAS Refresh
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Single error correction, double and nibble error detection.
Support for memory scrubbing.
Power management of the memory array.
Support for shadowing in the 640K to 1 MB address range.
Remapping of addresses above 1 MB to recover memory ranges mapped to other P6.0
devices.
Expandable to four memory controllers.
LVTTL interface to memory interface components (MlCs).
Device features
Two packages: a 208 pin PQFP controller and a 240 pin PQFP or 256 pin BGA data
path.
0.5 um, 3.3 V CMOS gate array.
On-chip Digital PLL.
JTAG Boundary Scan support.
Major Chipsets 2-37
Page 97
2.3.2 S82452GX Pin Diagram
Figure 2- 5 S82452GX Pin Diagram
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2.3.3 S82452GX Signal Descriptions
Table 2- 4 S82452GX Signal Descriptions
Signal Pin Type Description
P6.0 Bus Interface
D#[63:60] D#[59:56] D#[55:52] D#[51:48] D#[47:44] D#[43:40] D#[39:36] D#[35:32] D#[31:28] D#[27:24] D#[23:20] D#[19:16] D#[15:12] D#[11:08] D#[07:04] D#[03:00]
DEP#[7:0] 227, 233, 235, 230,
DRDY# 226 I/O
105, 109, 106, 99, 92, 108, 93, 102, 103, 95, 96, 86, 84, 98, 87, 89, 79, 90, 77, 76, 71, 82, 83, 70, 74, 64, 68, 73, 63, 67, 65, 58, 57, 54, 53, 56, 51, 50, 47, 48, 45, 44, 42, 37, 39, 38, 35, 34, 29, 26, 32, 23, 31, 28, 25, 22, 19, 16, 18, 13, 15, 10, 12, 09
237, 229, 232, 236
I/O Data.
I/O
Data ECC/Parity. ECC computed over the 64 data bits. Parity is not generated or checked.
Data Ready. Asserted for each cycle that data is transferred.
Data Path Reset Signal
MI-RST# 238 I
S82451GX Data Path Interface
MDE[71:64] MDE[63:56] MDE[55:48] MDE[47:40] MDE[39:31] MDE[30:23] MDE[22:16] MDE[15:08] MDE[07:00]
MDRDY0# MDRDY1#
S82453GX / S82452GX Interchip
MEMCMD#[7:0] MEMERR#[1:0]
SYSCMD#[4:0]
SYSERR# 216
SYSDEN# 224
198-191, 189-182, 178-171, 169-162, 59-151, 148-141, 138-132, 130-123, 119-112
111, 150 O
213-206 I/O 215,214
223, 222, 219, 218, 217
DPDC
DCDP
DPDC
DCDP
I/O
Reset. This signal is driven by MI_RST# signal from the S82452GX.
Memory Data and ECC. ECC is computed over 64-bit data words. Parity is computed as byte-parity over a 64-bit word.
Memory Data Ready. Asserted when write data on the memory data bus is valid. Two copies are provided to support external loading.
Memory side command.
Indicates memory error conditions detected in the S82452GX.
System side command.
Indicates system error conditions detected in the S82452GX.
System side data enable.
Major Chipsets 2-39
Page 99
Table 2- 4 S82452GX Signal Descriptions
Signal Pin Type Description
Support Signals
GTL_REFV 239 I GTL Reference Voltage. BCLK 204 I PLL Reference Clock.
Test
TCK 3 I Test Clock. TDI 6 I Test Data In. TDO 7 O Test Data Out. TMS 5 I Test Mode Select. TRST# 8 I
Test Reset. For normal operation, TRST# must be asserted low after PWR_GD is asserted.
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2.4 DRAM Control Chipset (S82453GX)
2.4.1 S82453GX Pin Diagram
Figure 2- 6 S82453GX Pin Diagram
Major Chipsets 2-41
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