Acer CHROMEBOOK 14 CP5-471 Schematics
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TABLE OF CONTENT
PAGE
D D
03
04
05
06
07
08
09
10
C C
B B
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TITLE
BLOCK DIAGRAM02
SKL ULT SYSTEM CTL
SKL ULT - DEBUG
SKL ULT - DDR3L CH A
SKL ULT - DDR3L CH B
SKL ULT - PCIE/SATA/USB/DSI
SKL ULT - I2S/DMIC/SD/UFS
SKL ULT - SPI/LPC/SMB/ISH
SKL ULT - XDP/SERVO
SKL ULT - CORE POWER
SKL ULT - GT POWER
SKL ULT - IO/MEM/SA POWER
SKL ULT - RESERVED
SKL ULT - GND
SPI TPM & BIOS SPI
LPDDR3 CH A
LPDDR3 CH B
EMMC
LED/TEMP SENSORS
EDP PANEL
USB3.0
USBPD EC
USBC PORT
HDMI
PAGE
30
31
32
33
34
35
36
37
38
39
40
41
42
TITLE
MEC1322
Thermal Protect
USBPD
BATT CHARGER
PMIC-1
PMIC-2
POWER GATES 1
POWER GATES 2
IMVP8
IMVP8 CORE
IMVP8 GT/SA
Power Tree
Change List
26
27
28
29
A A
NGFF-WIFI/BT/DB
TP & KB CONN
NAU88L25/MAX98357
NFC
Notes:
Part Value Prefix : "*" means no stuff
Net Value suffix : "*" means Low Active
Part : "*" means NO STUFF
5
4
3
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
1
ZDA
ZDA
ZDA
143Monday, April 04, 2016
143Monday, April 04, 2016
143Monday, April 04, 2016
of
of
of
8A
8A
8A
5
www.schematic-x.blogspot.com
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1
ZDA SKL ULT SYSTEM BLOCK DIAGRAM
D D
Memory Down
02
Dual Channel LPDDR III
IMC
SKY LAKE ULT
MCP
EDP
USB3
USB2
USB TYPE C
EMMC
USB TYPE C MUX
EMMC
USB3.0
Integrated PCH
DDIDP*4
eDP
DP
CONN.
C C
Cardreader CONN.
USB TYPE C
CHARGER
GL823
USB3.0/2.0
(cardreader)
USB2.0
PCI-E x1
CCD(Camera)
I/O board
USB2.0
I/O Board Conn.USB2 IO*1
eDP Conn.
HDMI Conn.
USB3 CONN.
NGFF
WLAN+BT
Blue Tooth
B B
D-MIC
Int. D-MIC
I2S
LPC
CLK
I2C_0
SPI
SPI ROM
128M
NAU88L25
AUDIO CODEC
MAX98357AETE+T*
A A
5
AUDIO JACK
4
Speaker
LED
3
K/B Con.
EC
MEC1322
Touch PAD
HALL
SENSOR
2
Fan Driver
(Fan signal)
TPM(option)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZDA
ZDA
ZDA
243Monday, Ap ril 04, 2 016
243Monday, Ap ril 04, 2 016
243Monday, Ap ril 04, 2 016
1
8A
8A
8A
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of
of
5
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SKL ULT - SYSTEM CTL
PCIe Clock ASSIGNMENT
WIFI1
D D
C C
BUF_PCH_PLT_RST*[19,26,30]
B B
A A
+V3P3A
R1113
100K_2
4
RAP3047
*100K_2
RAP3048 *0_4
PCH_SYSRST*[10,30]
PCH_RSMRST*[10,30]
ROP_VCCST_PWRGD[10,34]
ROP_SYS_PWROK[10,34]
PCH_PWROK[34,38]
ROP_DSW_PWROK[34,35]
PCIE_WAKE*[26]
EC_PCH_WAKE*[30]
TRACKPAD_INT*[4,27,30]
WIFI_PCIE_CLK_DN[26]
WIFI_PCIE_CLK_DP[26]
WIFI_CLK_REQ*[26]
AUDIO_INT_WAK*[9]
+V3P3A+V3P3S
RAP3046
*0_4
53
1
2
U135
SN74AHC1G08DCKR
TP105
TP103
TP104
RAP3045
0_4
CPM4431
0.1U/16V_4
+V3P3S
RAP1003
10K_2
RAP1067
1M_2
RAP1004
100K_2
R3587
100K_2
CLKOUT_SRC_N_0
D42
CLKOUT_SRC_P_0
C42
GPP_B_5_SRCCLKREQB_0
AR10
CLKOUT_SRC_N_1
B42
CLKOUT_SRC_P_1
A42
GPP_B_6_SRCCLKREQB_1
AT7
CLKOUT_SRC_N_2
D41
CLKOUT_SRC_P_2
C41
GPP_B_7_SRCCLKREQB_2
AT8
CLKOUT_SRC_N_3
D40
CLKOUT_SRC_P_3
C40
GPP_B_8_SRCCLKREQB_3
AT10
CLKOUT_SRC_N_4
B40
CLKOUT_SRC_P_4
A40
GPP_B_9_SRCCLKREQB_4
AU8
CLKOUT_SRC_N_5
E40
CLKOUT_SRC_P_5
E38
GPP_B_10_SRCCLKREQB_5
AU7
REV = 1
SRTC REST_N
0 - SAVE ME RTC REGISTER WHEN BATTERY IS REMOVED
1 - CLEAR ME RTC REGISTER
RTESTB
1 - SAVE REGISTER BIT IN RTC WELL (DEFAULT)
0 - RESETS THER REGISTER BITS IN THE RTC WELL
+V3P3A_DSW
RAP1061
RAP1005
10K_2
RAP1011
10K_2
100K_2
CAP14472
*0.1u/10V_ 2
U80J
SKYLAKE_ULT
CLOCK SIGNALS
10 OF 20
+V1P00S_VCCST
RAP1008
100K_2
+V3P3A
RAP1062
1K_2
RAP1459 *SHORT_2
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
TPM_PLTRST#[16]
RAP1002
*10K_2
RAP1064 60.4_4
TP17
TP18
GPD_8_SUSCLK
XTAL_IN
XTAL_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRSTB
RTESTB
+V3P3A +V1P8S
RAP3049
10K_2
3
RAP3051 *0_2
PCH_PLT_RST*
PM_CPUPWRGD
VCCST_PWRGD_MCP
PCH_SUSPWRACK*
PCH_SUSACK*
PM_LANPHY_ENABLE
USB_WAKEOUT_INTRUDET*
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
AT11
AP15
BA16
PCH_SLP_S5*
AY16
AN15
PCH_SLP_LAN*
AW15
PCH_SLP_WLAN*
BB17
PCH_SLP_SA*
AN16
BA15
AY15
PCH_BATLOW*
AU13
EC_HID_INT*
AU11
SM_INTRUDER*
AP16
MPHY_EXT_PWR_G ATE*
AM10
AM11
XTAL24_IN_R
XTAL24_OUT_R
RAP1088
10M_4
C186 33P/50V_4
4
3
1
2
C187 33P/50V_4
+VCCF24NS_1P0
Trace length < 1000 mils
RTC_X1
RTC_X2
TP100
TP101
TP102
TP75
TP79TP39
TP20
TP78
TP21
X5
24MHz,30ppm
C291 15P/50V_4
12
X6
32.768KHz,20ppm
C289 15P/50V_4
RAP3020
1M_2
TP22
+V3P3A_DSW
RAP1081
RAP1077
*100K_2
10K_2
RAP1458 *0_2
RAP1457 *SHORT_2
R5150 100K/F_4
+V3P3A_RTC
RAP1075
1M_4
PM_SLP_S0* [30,34]
PM_SLP_S3* [30,34,36,37]
PM_SLP_S4* [30,34,35,36]
PCH_EC_SLP_SUS* [30]
ROP_PCH_PWRBTN* [34]
EC_PCH_PWRBTN* [10,30]
EC_PCH_ACPRESENT [30]
HSJ_MIC_DET [28]
RAP1089 *SHORT_4
RAP1087
1M_4
CLKOUT_XDP_DN* [10]
TP120
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTCRST*
RTC_RST*
QPM3390
2
PJA138K
1
GPP_B_13_PLTRSTB
AN10
SYS_RESETB
B5
RSMRSTB
AY17
CPUPWRGD
A68
VCCST_PWRGD
B65
SYS_PWROK
B6
PCH_PWROK
BA20
DSW_PWROK
BB20
GPP_A_13_SUSWARNB_SUSPWRDNACK
AR13
GPP_A_15_SUSACKB
AP11
WAKEB
BB15
GPD_2_LAN_WAKEB
AM15
GPD_11_LANPHYPC
AW17
GPD_7_USB2_WAKEOUTB
AT15
REV = 1
CLKOUT_XDP_DP [10]
SUS_CLK [26]
RAP1091 2.7K/F_4
RAP1072
20K_4
CAP1073
1U/6.3V_4
RAP3052 *0_2
+V3P3A_RTC+V3P3A_RTC
RAP1078
20K_4
CAP1079
1U/6.3V_4
U80K
SKYLAKE_ULT
SYSTEM POWER MANAGEMENT
11 OF 20
GPP_B_11_EXT_PWR_GATEB
RAP1090 *SHORT_4
GPP_B_12_SLP_S0B
GPD_4_SLP_S3B
GPD_5_SLP_S4B
GPD_10_SLP_S5B
SLP_SUSB
SLP_LANB
GPD_9_SLP_WLANB
GPD_6_SLP_AB
GPD_3_PWRBTNB
GPD_1_ACPRESENT
GPD_0_BATLOWB
GPP_A_11_PMEB
INTRUDERB
GPP_B_2_VRALERTB
SRTCRST* [30]
RTC_RST* [30]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :
SKL ULT SYSTEM CTL
SKL ULT SYSTEM CTL
SKL ULT SYSTEM CTL
ZDA
ZDA
ZDA
8A
8A
8A
of
of
of
343Monday, Ap ril 04, 2016
343Monday, Ap ril 04, 2016
1
343Monday, Ap ril 04, 2016
5
4
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SKL ULT - DEBUG
D D
+V1P00S_VCCSTG
R66
1K/F_4
+V3P3A
C C
B B
RAP1452
100K_2
SOC_PROCHOT*[30]
TRACKPAD_INT*[3,27,30]
PECI[30]
TP119 TP96
XDP_BPM<0>[10]
XDP_BPM<1>[10]
R45
49.9_4
R46
49.9_4
+V1P00S_VCCST
R88
1K_2
TP97
R1180 499/F_4
TP98
TP23
TP24
TP242
R47
49.9_4
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
R48
49.9_4
R49
*49.9_4
SOC_CATERR*
PECI
SOC_THRMTRIP*
XDP_BPM<2>
XDP_BPM<3>
R5037 365/F_4
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
CATERR_N
PECI
PROCHOT_N
THRMTRIPB
SKTOCC_N
MBP_N[0]
MBP_N[1]
MBP_N[2]
MBP_N[3]
GPP_E_3_CPU_GP_0
GPP_E_7_CPU_GP_1
GPP_B_3_CPU_GP_2
GPP_B_4_CPU_GP_3
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
CPU_EOPIO_RCOMP
REV = 1
U80D
SKYLAKE_ULT
4 OF 20
JTAGCPU MISC
CPU_JTAG_TCK
CPU_JTAG_TDI
CPU_JTAG_TDO
CPU_JTAG_TMS
CPU_JTAG_TRST_N
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRSTB
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
R129
*49.9_4
R130
*49.9_4
R136
49.9_4
R131
*49.9_4
R138
49.9_4
R132
49.9_4
+V1P00S_VCCSTG
R133
R134
49.9_4
49.9_4
CPU_JTAG_TCLK [10]
CPU_JTAG_TDI [10]
CPU_JTAG_TDO [10]
CPU_JTAG_TMS [10]
XDP_JTAG_TRST* [10]
PCH_JTAG_TCLK [10]
PCH_JTAG_TDI [10]
PCH_JTAG_TDO [10]
PCH_JTAG_TMS [10]
XDP_TCLK_JTAGX [10]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
SKL ULT - DEBUG
SKL ULT - DEBUG
SKL ULT - DEBUG
Size Document Number Rev
PROJECT :
Size Document Number Rev
ZDA
ZDA
ZDA
443Monda y, Ap ril 04, 20 16
443Monda y, Ap ril 04, 20 16
443Monda y, Ap ril 04, 20 16
1
8A
8A
8A
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of
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5
4
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1
SKL ULT - DDR CHANNEL A
D D
U80B
SKYLAKE_ULT
DDRDQ_IL00_NIL00[0]
M_A_DQ<0 >[17] M_A_CLK_ DDR_DN*<0 > [17]
M_A_DQ<1 >[17]
M_A_DQ<2 >[17]
M_A_DQ<3 >[17]
M_A_DQ<4 >[17]
M_A_DQ<5 >[17]
M_A_DQ<6 >[17]
M_A_DQ<7 >[17]
M_A_DQ<8 >[17]
M_A_DQ<9 >[17]
M_A_DQ<1 0>[17]
M_A_DQ<1 1>[17]
M_A_DQ<1 2>[17]
M_A_DQ<1 3>[17]
M_A_DQ<1 4>[17]
M_A_DQ<1 5>[17]
M_A_DQ<1 6>[17]
M_A_DQ<1 7>[17]
M_A_DQ<1 8>[17]
M_A_DQ<1 9>[17]
M_A_DQ<2 0>[17]
C C
B B
M_A_DQ<2 1>[17]
M_A_DQ<2 2>[17]
M_A_DQ<2 3>[17]
M_A_DQ<2 4>[17]
M_A_DQ<2 5>[17]
M_A_DQ<2 6>[17]
M_A_DQ<2 7>[17]
M_A_DQ<2 8>[17]
M_A_DQ<2 9>[17]
M_A_DQ<3 0>[17]
M_A_DQ<3 1>[17]
M_A_DQ<3 2>[17]
M_A_DQ<3 3>[17]
M_A_DQ<3 4>[17]
M_A_DQ<3 5>[17]
M_A_DQ<3 6>[17]
M_A_DQ<3 7>[17]
M_A_DQ<3 8>[17]
M_A_DQ<3 9>[17]
M_A_DQ<4 0>[17]
M_A_DQ<4 1>[17]
M_A_DQ<4 2>[17]
M_A_DQ<4 3>[17]
M_A_DQ<4 4>[17]
M_A_DQ<4 5>[17]
M_A_DQ<4 6>[17]
M_A_DQ<4 7>[17]
M_A_DQ<4 8>[17]
M_A_DQ<4 9>[17]
M_A_DQ<5 0>[17]
M_A_DQ<5 1>[17]
M_A_DQ<5 2>[17]
M_A_DQ<5 3>[17]
M_A_DQ<5 4>[17]
M_A_DQ<5 5>[17]
M_A_DQ<5 6>[17]
M_A_DQ<5 7>[17]
M_A_DQ<5 8>[17]
M_A_DQ<5 9>[17]
M_A_DQ<6 0>[17]
M_A_DQ<6 1>[17]
M_A_DQ<6 2>[17]
M_A_DQ<6 3>[17]
AL71
DDRDQ_IL00_NIL00[1]
AL68
DDRDQ_IL00_NIL00[2]
AN68
DDRDQ_IL00_NIL00[3]
AN69
DDRDQ_IL00_NIL00[4]
AL70
DDRDQ_IL00_NIL00[5]
AL69
DDRDQ_IL00_NIL00[6]
AN70
DDRDQ_IL00_NIL00[7]
AN71
DDRDQ_IL01_NIL01[0]
AR70
DDRDQ_IL01_NIL01[1]
AR68
DDRDQ_IL01_NIL01[2]
AU71
DDRDQ_IL01_NIL01[3]
AU68
DDRDQ_IL01_NIL01[4]
AR71
DDRDQ_IL01_NIL01[5]
AR69
DDRDQ_IL01_NIL01[6]
AU70
DDRDQ_IL01_NIL01[7]
AU69
DDRDQ_IL10_NIL02[0]
AF65
DDRDQ_IL10_NIL02[1]
AF64
DDRDQ_IL10_NIL02[2]
AK65
DDRDQ_IL10_NIL02[3]
AK64
DDRDQ_IL10_NIL02[4]
AF66
DDRDQ_IL10_NIL02[5]
AF67
DDRDQ_IL10_NIL02[6]
AK67
DDRDQ_IL10_NIL02[7]
AK66
DDRDQ_IL11_NIL03[0]
AF70
DDRDQ_IL11_NIL03[1]
AF68
DDRDQ_IL11_NIL03[2]
AH71
DDRDQ_IL11_NIL03[3]
AH68
DDRDQ_IL11_NIL03[4]
AF71
DDRDQ_IL11_NIL03[5]
AF69
DDRDQ_IL11_NIL03[6]
AH70
DDRDQ_IL11_NIL03[7]
AH69
DDRDQ_IL02_NIL04[0]
BB65
DDRDQ_IL02_NIL04[1]
AW65
DDRDQ_IL02_NIL04[2]
AW63
DDRDQ_IL02_NIL04[3]
AY63
DDRDQ_IL02_NIL04[4]
BA65
DDRDQ_IL02_NIL04[5]
AY65
DDRDQ_IL02_NIL04[6]
BA63
DDRDQ_IL02_NIL04[7]
BB63
DDRDQ_IL03_NIL05[0]
BA61
DDRDQ_IL03_NIL05[1]
AW61
DDRDQ_IL03_NIL05[2]
BB59
DDRDQ_IL03_NIL05[3]
AW59
DDRDQ_IL03_NIL05[4]
BB61
DDRDQ_IL03_NIL05[5]
AY61
DDRDQ_IL03_NIL05[6]
BA59
DDRDQ_IL03_NIL05[7]
AY59
DDRDQ_IL12_NIL06[0]
AT66
DDRDQ_IL12_NIL06[1]
AU66
DDRDQ_IL12_NIL06[2]
AP65
DDRDQ_IL12_NIL06[3]
AN65
DDRDQ_IL12_NIL06[4]
AN66
DDRDQ_IL12_NIL06[5]
AP66
DDRDQ_IL12_NIL06[6]
AT65
DDRDQ_IL12_NIL06[7]
AU65
DDRDQ_IL13_NIL07[0]
AT61
DDRDQ_IL13_NIL07[1]
AU61
DDRDQ_IL13_NIL07[2]
AP60
DDRDQ_IL13_NIL07[3]
AN60
DDRDQ_IL13_NIL07[4]
AN61
DDRDQ_IL13_NIL07[5]
AP61
DDRDQ_IL13_NIL07[6]
AT60
DDRDQ_IL13_NIL07[7]
AU60
REV = 1
DDR CH - A
2 OF 20
DDR0_CLK_N[0]
DDR0_CLK_P[0]
DDR0_CLK_N[1]
DDR0_CLK_P[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS_N[0]
DDR0_CS_N[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[5]_CAA0
DDR0_MA[9]_CAA1
DDR0_MA[6]_CAA2
DDR0_MA[8]_CAA3
DDR0_MA[7]_CAA4
DDR0_BA[2]_CAA5_BG0
DDR0_MA[12]_CAA6
DDR0_MA[11]_CAA7
DDR0_MA[15]_CAA8_ACT_N
DDR0_MA[14]_CAA9_BG1
DDR0_MA[13]_CAB0
DDR0_CAS_N_CAB1_MA15
DDR0_WE_N_CAB2_MA14
DDR0_RAS_N_CAB3_MA16
DDR0_BA[0]_CAB4
DDR0_MA[2]_CAB5
DDR0_BA[1]_CAB6
DDR0_MA[10]_CAB7
DDR0_MA[1]_CAB8
DDR0_MA[0]_CAB9
DDR0_MA[3]
DDR0_MA[4]
DDRDQSN_IL00_NIL00
DDRDQSP_IL00_NIL00
DDRDQSN_IL01_NIL01
DDRDQSP_IL01_NIL01
DDRDQSN_IL10_NIL02
DDRDQSP_IL10_NIL02
DDRDQSN_IL11_NIL03
DDRDQSP_IL11_NIL03
DDRDQSN_IL02_NIL04
DDRDQSP_IL02_NIL04
DDRDQSN_IL03_NIL05
DDRDQSP_IL03_NIL05
DDRDQSN_IL12_NIL06
DDRDQSP_IL12_NIL06
DDRDQSN_IL13_NIL07
DDRDQSP_IL13_NIL07
DDR0_ALERT_N
DDR0_PARITY
DDR_VREF_CA
DDR_VREF_DQ[0]
DDR_VREF_DQ[1]
DDR_VTT_CNTL
8/19 Modify Follow PD7H
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
TP_M_A_A<3>
TP_M_A_A<4>
TP_DDR0_ALERT*
DDR_CA_VREF
DDR_VREFDQ_CHA
DDR_VREFDQ_CHB
DDR_VTT_CTRL [35]
R1115 *SHORT_2
R1116 *SHORT_2
R1117 *0_2
TP238
CAP1020
22nF/16V_4
RAP1021
24.9_4
M_A_CLK_ DDR_DP<0> [17 ]
M_A_CLK_ DDR_DN*<1 > [17]
M_A_CLK_ DDR_DP<1> [17 ]
M_A_CKE< 0> [17]
M_A_CKE< 1> [17]
M_A_CKE< 2> [17]
M_A_CKE< 3> [17]
M_A_CS*< 0> [17]
M_A_CS*< 1> [17]
M_A_ODT<0 > [17]
M_A_CA_A<0 > [17]
M_A_CA_A<1 > [17]
M_A_CA_A<2 > [17]
M_A_CA_A<3 > [17]
M_A_CA_A<4 > [17]
M_A_CA_A<5 > [17]
M_A_CA_A<6 > [17]
M_A_CA_A<7 > [17]
M_A_CA_A<8 > [17]
M_A_CA_A<9 > [17]
M_A_CA_B< 0> [17]
M_A_CA_B< 1> [17]
M_A_CA_B< 2> [17]
M_A_CA_B< 3> [17]
M_A_CA_B< 4> [17]
M_A_CA_B< 5> [17]
M_A_CA_B< 6> [17]
M_A_CA_B< 7> [17]
M_A_CA_B< 8> [17]
M_A_CA_B< 9> [17]
M_A_DQS_ DN*<0> [1 7]
M_A_DQS_ DP<0> [17 ]
M_A_DQS_ DN*<1> [1 7]
M_A_DQS_ DP<1> [17 ]
M_A_DQS_ DN*<2> [1 7]
M_A_DQS_ DP<2> [17 ]
M_A_DQS_ DN*<3> [1 7]
M_A_DQS_ DP<3> [17 ]
M_A_DQS_ DN*<4> [1 7]
M_A_DQS_ DP<4> [17 ]
M_A_DQS_ DN*<5> [1 7]
M_A_DQS_ DP<5> [17 ]
M_A_DQS_ DN*<6> [1 7]
M_A_DQS_ DP<6> [17 ]
M_A_DQS_ DN*<7> [1 7]
M_A_DQS_ DP<7> [17 ]
RAP1026 5.11_4
RAP1027 10/F_4
RAP1028 10/F_4
CAP1022
22nF/16V_4
RAP1023
24.9_4
CAP1024
22nF/16V_4
RAP1025
24.9_4
+VDDQ_MEM
RAP1029
8.2K/F_4
RAP1030
8.2K/F_4
RAP1031
8.2K/F_4
RAP1032
8.2K/F_4
RAP1033
8.2K/F_4
RAP1034
8.2K/F_4
CA_VREF [17,18]
VREFDQ_CHA [17]
VREFDQ_CHB [18]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :
SKL ULT - DDR3L CH A
SKL ULT - DDR3L CH A
SKL ULT - DDR3L CH A
ZDA
ZDA
ZDA
8A
8A
8A
of
of
of
543Monday, Apr il 04, 201 6
543Monday, Apr il 04, 201 6
543Monday, Apr il 04, 201 6
1
5
4
3
2
1
SKL ULT - DDR CHANNEL B
D D
DDRDQ_IL04_NIL10[0]
M_B_DQ<0 >[18]
M_B_DQ<1 >[18]
M_B_DQ<2 >[18]
M_B_DQ<3 >[18]
M_B_DQ<4 >[18]
M_B_DQ<5 >[18]
M_B_DQ<6 >[18]
M_B_DQ<7 >[18]
M_B_DQ<8 >[18]
M_B_DQ<9 >[18]
M_B_DQ<1 0>[18]
M_B_DQ<1 1>[18]
M_B_DQ<1 2>[18]
M_B_DQ<1 3>[18]
M_B_DQ<1 4>[18]
M_B_DQ<1 5>[18]
M_B_DQ<1 6>[18]
M_B_DQ<1 7>[18]
M_B_DQ<1 8>[18]
C C
B B
M_B_DQ<1 9>[18]
M_B_DQ<2 0>[18]
M_B_DQ<2 1>[18]
M_B_DQ<2 2>[18]
M_B_DQ<2 3>[18]
M_B_DQ<2 4>[18]
M_B_DQ<2 5>[18]
M_B_DQ<2 6>[18]
M_B_DQ<2 7>[18]
M_B_DQ<2 8>[18]
M_B_DQ<2 9>[18]
M_B_DQ<3 0>[18]
M_B_DQ<3 1>[18]
M_B_DQ<3 2>[18]
M_B_DQ<3 3>[18]
M_B_DQ<3 4>[18]
M_B_DQ<3 5>[18]
M_B_DQ<3 6>[18]
M_B_DQ<3 7>[18]
M_B_DQ<3 8>[18]
M_B_DQ<3 9>[18]
M_B_DQ<4 0>[18]
M_B_DQ<4 1>[18]
M_B_DQ<4 2>[18]
M_B_DQ<4 3>[18]
M_B_DQ<4 4>[18]
M_B_DQ<4 5>[18]
M_B_DQ<4 6>[18]
M_B_DQ<4 7>[18]
M_B_DQ<4 8>[18]
M_B_DQ<4 9>[18]
M_B_DQ<5 0>[18]
M_B_DQ<5 1>[18]
M_B_DQ<5 2>[18]
M_B_DQ<5 3>[18]
M_B_DQ<5 4>[18]
M_B_DQ<5 5>[18]
M_B_DQ<5 6>[18]
M_B_DQ<5 7>[18]
M_B_DQ<5 8>[18]
M_B_DQ<5 9>[18]
M_B_DQ<6 0>[18]
M_B_DQ<6 1>[18]
M_B_DQ<6 2>[18]
M_B_DQ<6 3>[18]
AY39
DDRDQ_IL04_NIL10[1]
AW39
DDRDQ_IL04_NIL10[2]
AY37
DDRDQ_IL04_NIL10[3]
AW37
DDRDQ_IL04_NIL10[4]
BB39
DDRDQ_IL04_NIL10[5]
BA39
DDRDQ_IL04_NIL10[6]
BA37
DDRDQ_IL04_NIL10[7]
BB37
DDRDQ_IL05_NIL11[0]
AY35
DDRDQ_IL05_NIL11[1]
AW35
DDRDQ_IL05_NIL11[2]
AY33
DDRDQ_IL05_NIL11[3]
AW33
DDRDQ_IL05_NIL11[4]
BB35
DDRDQ_IL05_NIL11[5]
BA35
DDRDQ_IL05_NIL11[6]
BA33
DDRDQ_IL05_NIL11[7]
BB33
DDRDQ_IL14_NIL12[0]
AU40
DDRDQ_IL14_NIL12[1]
AT40
DDRDQ_IL14_NIL12[2]
AT37
DDRDQ_IL14_NIL12[3]
AU37
DDRDQ_IL14_NIL12[4]
AR40
DDRDQ_IL14_NIL12[5]
AP40
DDRDQ_IL14_NIL12[6]
AP37
DDRDQ_IL14_NIL12[7]
AR37
DDRDQ_IL15_NIL13[0]
AT33
DDRDQ_IL15_NIL13[1]
AU33
DDRDQ_IL15_NIL13[2]
AU30
DDRDQ_IL15_NIL13[3]
AT30
DDRDQ_IL15_NIL13[4]
AR33
DDRDQ_IL15_NIL13[5]
AP33
DDRDQ_IL15_NIL13[6]
AR30
DDRDQ_IL15_NIL13[7]
AP30
DDRDQ_IL06_NIL14[0]
AY31
DDRDQ_IL06_NIL14[1]
AW31
DDRDQ_IL06_NIL14[2]
AY29
DDRDQ_IL06_NIL14[3]
AW29
DDRDQ_IL06_NIL14[4]
BB31
DDRDQ_IL06_NIL14[5]
BA31
DDRDQ_IL06_NIL14[6]
BA29
DDRDQ_IL06_NIL14[7]
BB29
DDRDQ_IL07_NIL15[0]
AY27
DDRDQ_IL07_NIL15[1]
AW27
DDRDQ_IL07_NIL15[2]
AY25
DDRDQ_IL07_NIL15[3]
AW25
DDRDQ_IL07_NIL15[4]
BB27
DDRDQ_IL07_NIL15[5]
BA27
DDRDQ_IL07_NIL15[6]
BA25
DDRDQ_IL07_NIL15[7]
BB25
DDRDQ_IL16_NIL16[0]
AU27
DDRDQ_IL16_NIL16[1]
AT27
DDRDQ_IL16_NIL16[2]
AT25
DDRDQ_IL16_NIL16[3]
AU25
DDRDQ_IL16_NIL16[4]
AP27
DDRDQ_IL16_NIL16[5]
AN27
DDRDQ_IL16_NIL16[6]
AN25
DDRDQ_IL16_NIL16[7]
AP25
DDRDQ_IL17_NIL17[0]
AT22
DDRDQ_IL17_NIL17[1]
AU22
DDRDQ_IL17_NIL17[2]
AU21
DDRDQ_IL17_NIL17[3]
AT21
DDRDQ_IL17_NIL17[4]
AN22
DDRDQ_IL17_NIL17[5]
AP22
DDRDQ_IL17_NIL17[6]
AP21
DDRDQ_IL17_NIL17[7]
AN21
REV = 1
U80C
SKYLAKE_ULT
DDR CH - B
3 OF 20
DDR1_CLK_N[0]
DDR1_CLK_N[1]
DDR1_CLK_P[0]
DDR1_CLK_P[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS_N[0]
DDR1_CS_N[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[5]_CAA0
DDR1_MA[9]_CAA1
DDR1_MA[6]_CAA2
DDR1_MA[8]_CAA3
DDR1_MA[7]_CAA4
DDR1_BA[2]_CAA5_BG0
DDR1_MA[12]_CAA6
DDR1_MA[11]_CAA7
DDR1_MA[15]_CAA8_ACT_N
DDR1_MA[14]_CAA9_BG1
DDR1_MA[13]_CAB0
DDR1_CAS_N_CAB1_MA15
DDR1_WE_N_CAB2_MA14
DDR1_RAS_N_CAB3_MA16
DDR1_BA[0]_CAB4
DDR1_MA[2]_CAB5
DDR1_BA[1]_CAB6
DDR1_MA[10]_CAB7
DDR1_MA[1]_CAB8
DDR1_MA[0]_CAB9
DDR1_MA[3]
DDR1_MA[4]
DDRDQSN_IL04_NIL10
DDRDQSP_IL04_NIL10
DDRDQSN_IL05_NIL11
DDRDQSP_IL05_NIL11
DDRDQSN_IL14_NIL12
DDRDQSP_IL14_NIL12
DDRDQSN_IL15_NIL13
DDRDQSP_IL15_NIL13
DDRDQSN_IL06_NIL14
DDRDQSP_IL06_NIL14
DDRDQSN_IL07_NIL15
DDRDQSP_IL07_NIL15
DDRDQSN_IL16_NIL16
DDRDQSP_IL16_NIL16
DDRDQSN_IL17_NIL17
DDRDQSP_IL17_NIL17
DDR1_ALERT_N
DDR1_PARITY
DRAM_RESETB
DDR_COMP[0]
DDR_COMP[1]
DDR_COMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
TP_M_B_A<3>
TP_M_B_A<4>
TP_DDR1_ALERT*
TP_DDR1_PARITY
TP_DDR3_DRAMRST*
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
R1118 *SHORT_2
R1119 *SHORT_2
R1120 *0_2
TP33
TP34
RAP1017
162_4
RAP1018
80.6_4
M_B_CLK _DDR_DN*<0> [18]
M_B_CLK _DDR_DN*<1> [18]
M_B_CLK _DDR_DP<0> [18 ]
M_B_CLK _DDR_DP<1> [18 ]
M_B_CKE <0> [18]
M_B_CKE <1> [18]
M_B_CKE <2> [18]
M_B_CKE <3> [18]
M_B_CS* <0> [18]
M_B_CS* <1> [18]
M_B_ODT<0 > [18]
M_B_CA_ A<0> [18]
M_B_CA_ A<1> [18]
M_B_CA_ A<2> [18]
M_B_CA_ A<3> [18]
M_B_CA_ A<4> [18]
M_B_CA_ A<5> [18]
M_B_CA_ A<6> [18]
M_B_CA_ A<7> [18]
M_B_CA_ A<8> [18]
M_B_CA_ A<9> [18]
M_B_CA_ B<0> [18]
M_B_CA_ B<1> [18]
M_B_CA_ B<2> [18]
M_B_CA_ B<3> [18]
M_B_CA_ B<4> [18]
M_B_CA_ B<5> [18]
M_B_CA_ B<6> [18]
M_B_CA_ B<7> [18]
M_B_CA_ B<8> [18]
M_B_CA_ B<9> [18]
M_B_DQS_ DN*<0> [1 8]
M_B_DQS_ DP<0> [1 8]
M_B_DQS_ DN*<1> [1 8]
M_B_DQS_ DP<1> [1 8]
M_B_DQS_ DN*<2> [1 8]
M_B_DQS_ DP<2> [1 8]
M_B_DQS_ DN*<3> [1 8]
M_B_DQS_ DP<3> [1 8]
M_B_DQS_ DN*<4> [1 8]
M_B_DQS_ DP<4> [1 8]
M_B_DQS_ DN*<5> [1 8]
M_B_DQS_ DP<5> [1 8]
M_B_DQS_ DN*<6> [1 8]
M_B_DQS_ DP<6> [1 8]
M_B_DQS_ DN*<7> [1 8]
M_B_DQS_ DP<7> [1 8]
RAP1019
200_4
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
SKL ULT - DDR3L CH B
SKL ULT - DDR3L CH B
SKL ULT - DDR3L CH B
Size Document Number Rev
PROJECT :
Size Document Number Rev
1
ZDA
ZDA
ZDA
643Monday, April 04, 2 016
643Monday, April 04, 2 016
643Monday, April 04, 2 016
8A
8A
8A
of
of
of
5
4
3
2
1
SKL ULT - PCIE/SATA/USB/SSIC/DSI/CSI
U80A
SKYLAKE_ULT
DDI1_TXN[0]
DDI1_LANE_DN*<0>[24]
DDI1_LANE_DP<0>[24]
R879
2.2K_4
DDI1_LANE_DN*<1>[24]
DDI1_LANE_DP<1>[24]
DDI1_LANE_DN*<2>[24]
DDI1_LANE_DP<2>[24]
DDI1_LANE_DN*<3>[24]
DDI1_LANE_DP<3>[24]
DDI2_LANE_DN*<0>[25]
DDI2_LANE_DP<0>[25]
DDI2_LANE_DN*<1>[25]
DDI2_LANE_DP<1>[25]
DDI2_LANE_DN*<2>[25]
DDI2_LANE_DP<2>[25]
DDI2_LANE_DN*<3>[25]
DDI2_LANE_DP<3>[25]
DDI1_CTRL_DATA
DDI2_CTRL_CLK
DDI2_CTRL_DATA
D D
+V3P3S
PORT C DETECT
1 = DETECT
0 = NOT DETECTED 0 = NOT DETECTED
INTERNAL PD
R877
2.2K_4
PORT B DETECT
1 = DETECT
INTERNAL PD
+V1P00S_VCCSTG
DDI2_CTRL_CLK[25]
RAP1013
24.9_4
DDI2_CTRL_DATA[25]
EDP_COMP
C C
U80H
SKYLAKE_ULT
E55
DDI1_TXP[0]
F55
DDI1_TXN[1]
E58
F58
DDI1_TXP[1]
DDI1_TXN[2]
F53
DDI1_TXP[2]
G53
DDI1_TXN[3]
F56
DDI1_TXP[3]
G56
DDI2_TXN[0]
C50
DDI2_TXP[0]
D50
DDI2_TXN[1]
C52
DDI2_TXP[1]
D52
A50
DDI2_TXN[2]
DDI2_TXP[2]
B50
DDI2_TXN[3]
D51
DDI2_TXP[3]
C51
GPP_E_18_DDPB_CTRLCLK
L13
GPP_E_19_DDPB_CTRLDATA
L12
N7
GPP_E_20_DDPC_CTRLCLK
GPP_E_21_DDPC_CTRLDATA
N8
GPP_E_22_DDPD_CTRLCLK
N11
GPP_E_23_DDPD_CTRLDATA
N12
DP_COMP
E52
REV = 1
DDI
DISPLAY SIDEBANDS
1 OF 20
EDP
SSIC / USB3PCIE/USB3/SATA
USB3_1_RXN
H8
USB3_1_RXP
PCIE_1_USB3_5_RXN
PCIE_RX_DN*<1>[26]
PCIE_RX_DP<1>[26]
PCIE_TX_DN*<1>[26]
PCIE_TX_DP<1>[26]
C827 0.1U/16V_4
C828 0.1U/16V_4
PCIE_TX_C_DN*<1>
PCIE_TX_C_DP<1>
PCIe SATA ASSIGNMENT
WIFI1--
B B
PCIE_RCOMPN
RAP1053 100/F_4
XDP_PRDY*[10]
A A
XDP_PREQ*[10]
5
R5107 0_2
SD_CDZ[8,10,22]
PCIE_RCOMPP
H13
PCIE_1_USB3_5_RXP
G13
B17
PCIE_1_USB3_5_TXN
PCIE_1_USB3_5_TXP
A17
PCIE_2_UFS_0A_USB3_6_RXN
G11
PCIE_2_UFS_0A_USB3_6_RXP
F11
D16
PCIE_2_UFS_0A_USB3_6_TXN
PCIE_2_UFS_0A_USB3_6_TXP
C16
PCIE_3_UFS_0B_LAN_0A_RXN
H16
PCIE_3_UFS_0B_LAN_0A_RXP
G16
D17
PCIE_3_UFS_0B_LAN_0A_TXN
PCIE_3_UFS_0B_LAN_0A_TXP
C17
PCIE_4_LAN_0B_RXN
G15
PCIE_4_LAN_0B_RXP
F15
B19
PCIE_4_LAN_0B_TXN
PCIE_4_LAN_0B_TXP
A19
PCIE_5_LAN_0C_RXN
F16
PCIE_5_LAN_0C_RXP
E16
C19
PCIE_5_LAN_0C_TXN
PCIE_5_LAN_0C_TXP
D19
PCIE_6_RXN
G18
PCIE_6_RXP
F18
D20
PCIE_6_TXN
PCIE_6_TXP
C20
PCIE_7_SATA_0_RXN
F20
PCIE_7_SATA_0_RXP
E20
B21
PCIE_7_SATA_0_TXN
PCIE_7_SATA_0_TXP
A21
PCIE_8_SATA_1A_RXN
G21
PCIE_8_SATA_1A_RXP
F21
D21
PCIE_8_SATA_1A_TXN
PCIE_8_SATA_1A_TXP
C21
PCIE_9_LAN_0D_RXN
E22
PCIE_9_LAN_0D_RXP
E23
B23
PCIE_9_LAN_0D_TXN
PCIE_9_LAN_0D_TXP
A23
PCIE_10_LAN_0E_RXN
F25
PCIE_10_LAN_0E_RXP
E25
D23
PCIE_10_LAN_0E_TXN
PCIE_10_LAN_0E_TXP
C23
PCIE_RCOMPN
F5
PCIE_RCOMPP
E5
PRDY_N
D56
PREQ_N
D61
GPP_A_7_PIRQAB
BB11
E28
PCIE_11_SATA_1B_RXN
PCIE_11_SATA_1B_RXP
E27
PCIE_11_SATA_1B_TXN
D24
PCIE_11_SATA_1B_TXP
C24
PCIE_12_SATA_2_RXN
E30
F30
PCIE_12_SATA_2_RXP
PCIE_12_SATA_2_TXN
A25
PCIE_12_SATA_2_TXP
B25
REV = 1
USB3_2_SSIC_1_RXN
USB3_2_SSIC_1_RXP
USB3_2_SSIC_1_TXN
USB3_2_SSIC_1_TXP
USB3_3_SSIC_2_RXN
USB3_3_SSIC_2_RXP
USB3_3_SSIC_2_TXN
USB3_3_SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E_9_USB2_OCB_0
GPP_E_10_USB2_OCB_1
GPP_E_11_USB2_OCB_2
GPP_E_12_USB2_OCB_3
GPP_E_4_SATA_DEVSLP_0
GPP_E_5_SATA_DEVSLP_1
GPP_E_6_SATA_DEVSLP_2
GPP_E_0_SATAXPCIE_0_SATAGP_0
GPP_E_1_SATAXPCIE_1_SATAGP_1
GPP_E_2_SATAXPCIE_2_SATAGP_2
8 OF 20
4
GPP_E_8_SATA_LEDB
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
3
USB2_OC*<1>
USB2_OC*<2>
USB3_RX_DN*<1> [24]
USB3_RX_DP<1> [24]
USB3_TX_DN*<1> [24]
USB3_TX_DP<1> [24]
USB3_RX_DN*<2> [22]
USB3_RX_DP<2> [22]
USB3_TX_DN*<2> [22]
USB3_TX_DP<2> [22]
USB3_RX_DN*<3> [22]
USB3_RX_DP<3> [22]
USB3_TX_DN*<3> [22]
USB3_TX_DP<3> [22]
USB3_RX_DN*<4> [22]
USB3_RX_DP<4> [22]
USB3_TX_DN*<4> [22]
USB3_TX_DP<4> [22]
USB2_DN*<1> [24]
USB2_DP<1> [24]
USB2_DN*<2> [21]
USB2_DP<2> [21]
USB2_DN*<3> [26]
USB2_DP<3> [26]
USB2_DN*<5> [22]
USB2_DP<5> [22]
USB2_DN*<6> [22]
USB2_DP<6> [22]
USB2_DN*<9> [22]
USB2_DP<9> [22]
USB2_COMP
USB2_OTG_ID [30]
USB2_OTG_VBUS_SNS [30]
USB2_OC*<0> [32]
USB2_OC*<2> [22]
USB2_OC*<3> [22]
R1056 113/F_4
TP253
SPI_TPM_IRQ* [16]
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E_13_DDSP_HPD_0
GPP_E_14_DDSP_HPD_1
GPP_E_15_DDSP_HPD_2
GPP_E_16_DDSP_HPD_3
GPP_E_17_EDP_HPD
L_BKLTEN
L_BKLTCTL
L_VDDEN
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
TP148
EDP_TX_DN*<0> [21]
EDP_TX_DP<0> [21]
EDP_TX_DN*<1> [21]
EDP_TX_DP<1> [21]
EDP_TX_DN*<2> [21]
EDP_TX_DP<2> [21]
EDP_TX_DN*<3> [21]
EDP_TX_DP<3> [21]
EDP_AUX_DN* [21]
EDP_AUX_DP [21]
DDI1_AUX_DN* [24]
DDI1_AUX_DP [24]
TP230
TP231
DDI1_HPD [30]
DDI2_HPD [25]
EC_SMI* [30]
EC_SCI* [30]
EDP_HPD [21]
L_BKLT_EN [21]
L_BRIGHTNESS [21]
L_VDD_EN [21]
6/9 Remove R1135
+V3P3A
R1134
*100K_2
+V3P3A
RAP1016
RAP1455
100K_2
100K_2
RAP1014
100K_2
USB3 PORT USB2 PORT ASSIGNMENT
USBC CONN1
--
--
4
3
1
2
3
9
5
CCD
BLUETOOTH
USB-A CONN
USB 3.0 Conn.
Card reader62
+V3P3A
RING OSC BYPASS
RAP1434
1 = BYPASS MODE ENABLE
20K_2
0 = RING OSC
USB2_OC*<0>
+V3P3A
USB2_OC*<1>
+V3P3A
USB2_OC*<2>
+V3P3A
USB2_OC*<3>
2
QUALIFIED BY DFXTESTMODE
XTAL INPUT FREQ[1:0]
00 = 24 MHZ
01 = 25 MHZ
10 = 250 MHZ
RAP1438
11 = 100 MHZ
20K_2
QUALIFIED BY DFXTESTMODE
HVM ONLY REMOVED IN SPT
XTAL INPUT FREQ[1:0]
00 = 24 MHZ
01 = 25 MHZ
RAP1436
10 = 250 MHZ
20K_2
11 = 100 MHZ
QUALIFIED BY DFXTESTMODE
HVM ONLY REMOVED IN SPT
XTAL INPUT MODE (HVM ONLY)
RAP1440
1 = INPUT DIFFERENTIAL
20K_2
0 = INPUT SINGLE-ENDED
QUALIFIED BY DFXTESTMODE
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
SKL ULT - PCIE/SATA/USB/DSI
SKL ULT - PCIE/SATA/USB/DSI
SKL ULT - PCIE/SATA/USB/DSI
ZDA
ZDA
ZDA
743Monday, April 04, 2016
743Monday, April 04, 2016
743Monday, April 04, 2016
of
of
1
of
8A
8A
8A
5
+V1P8A
4
3
2
1
SKL ULT - I2S/DMIC/SDIO/UFS
C1109
0.1U/16V_4
U138
14
VCC
1
1OE
4
2OE
10
3OE
13
4OE
SN74LVC125APWR
MERGE_I2 S_SFRM[28]
MERGE_I2 S_SCL[28]
TP247
R5146
10K_4
BOOT_BEEP
MERGE_I2 S_PCHTXD_AU DRXD[28]
D D
SECURITY MEASURES STRAP OPTION
1 = FLASH DESCRIPTOR IS OVERRIDE
C C
+V1P8A
DMIC_DATA0_L[21]
GND
DMIC_CLK0_L[21]
1A
1Y
2A
2Y
3A
3Y
4A
4Y
2
3
5
6
9
8
12
11
7
0 = DEFAULT
+V3P3S
RAP1046
*20K_2
R5137 0_4
R5138 0_4
R3499 33/F_2
R5139 0_4
R5139 put close to Pin 12 of U136.
I2S1_PCH RXD_NAUTXD[28]
I2S1_PCH TXD_NAURXD[28]
MERGE_I2 S_PCHRXD_A UDTXD
I2S0_SFR M
MERGE_I2 S_SFRM
I2S0_SCL K
MERGE_I2 S_SCL
I2S0_TXD
MERGE_I2 S_PCHTXD_AU DRXD
MERGE_I2 S_PCHRXD_A UDTXD
I2S0_RXD
R5057 33_4
R5058 33_4
I2S1_SCL[28]
I2S_MCLK[28]
I2S1_SFR M[28]
R5142 0_4
R5143 0_4
R5140 *0_4
R5141 *0_4
R1106 33_4
R5059 33_4
R5060 33_4
R3501 *SHORT_2
R3502 *SHORT_2
R3503 33/F_2
R3504 *SHORT_2
R899 33_4
R900 33_4
R5147
*0_4
I2S0_SFR M
I2S0_SCL K
I2S0_TXD
I2S0_RXD
I2S1_PCH RXD_NAUTXD_C
I2S1_SCL K_C
I2S_MCLK_ C
I2S1_SFR M_C
I2S1_PCH TXD_NAURXD_C
I2S2_SFR M
I2S2_SCL K
I2S2_TXD
I2S2_RXD
DMIC_CLK0_R
PCH_BUZZER
+VCCPAZIO
1
3
RAP1431
100K_2
+V3P3A_EC
2
Q105
AO3413
RAP1430
100K_2
AZA_SYNC_SSP0_SFRM
BA22
AZA_BCLK_SSP0_SCLK
AY22
AZA_SDO_SSP0_TXD
BB22
AZA_SDI_0_SSP0_RXD
BA21
AZA_SDI_1_SSP1_RXD
AY21
AZA_RSTB_SSP1_SCLK
AW22
GPP_D_23_SSP_MCLK
J5
SSP1_SFRM
AY20
SSP1_TXD
AW20
GPP_F_1_SSP2_SFRM
AK7
GPP_F_0_SSP2_SCLK
AK6
GPP_F_2_SSP2_TXD
AK9
GPP_F_3_SSP2_RXD
AK10
GPP_D_19_DMIC_CLK_0
H5
GPP_D_20_DMIC_DATA_0
D7
GPP_D_17_DMIC_CLK_1
D8
GPP_D_18_DMIC_DATA_1
C8
GPP_B_14_SPKR
AW5
FLASH_DSC_OVERRIDE* [30]
FROM EC - ACTIVE LOW
REV = 1
U80G
SKYLAKE_ULT
7 OF 20
SDIO/SDXCAUDIO
GPP_G_0_SD_CMD
GPP_G_1_SD_DATA0
GPP_G_2_SD_DATA1
GPP_G_3_SD_DATA2
GPP_G_4_SD_DATA3
GPP_G_5_SD_CDB
GPP_G_6_SD_CLK
GPP_A_17_SD_PWR_EN_B_ISH_GP_7
GPP_G_7_SD_WP
GPP_A_16_SD_1P8_SEL
SD_RCOMP
GPP_F_23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
SD_RCOMP
BOOT_BEEP
R5009 *0_2
RAP1050 200_4
+V3P3A
R4434
100K_2
SD_CDZ [7,10,22]
TOP SWAP STRAP
1 = TOP SWAP ENABLE
U80I
CSI-2
EMMC
9 OF 20
0 = TOP SWAP DISABLE
INTERNAL PD
CSI2_CLKN_0
CSI2_CLKP_0
CSI2_CLKN_1
CSI2_CLKP_1
CSI2_CLKN_2
CSI2_CLKP_2
CSI2_CLKN_3
CSI2_CLKP_3
CSI2_COMP
GPP_D_4_FLASHTRIG
GPP_F_13_EMMC_DATA0
GPP_F_14_EMMC_DATA1
GPP_F_15_EMMC_DATA2
GPP_F_16_EMMC_DATA3
GPP_F_17_EMMC_DATA4
GPP_F_18_EMMC_DATA5
GPP_F_19_EMMC_DATA6
GPP_F_20_EMMC_DATA7
GPP_F_21_EMMC_RCLK
GPP_F_22_EMMC_CLK
GPP_F_12_EMMC_CMD
EMMC_RCOMP
3
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
CSI2_COMP
EMMC_RCOMP
EMMC_D<0> [19]
EMMC_D<1> [19]
EMMC_D<2> [19]
EMMC_D<3> [19]
EMMC_D<4> [19]
EMMC_D<5> [19]
EMMC_D<6> [19]
EMMC_D<7> [19]
EMMC_RCLK [19]
EMMC_CLK [19]
EMMC_CMD [19]
RAP1054
200_4
RAP1055
100/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT :
SKL ULT - I2S/DMIC/SD/UFS
SKL ULT - I2S/DMIC/SD/UFS
SKL ULT - I2S/DMIC/SD/UFS
ZDA
ZDA
ZDA
8A
8A
8A
of
843Monday, Ap ril 04, 2 016
of
843Monday, Ap ril 04, 2 016
of
843Monday, Ap ril 04, 2 016
1
RAP1433
*20K_2
B B
CSI2_DN_0
A36
CSI2_DP_0
B36
CSI2_DN_1
C38
CSI2_DP_1
D38
CSI2_DN_2
C36
CSI2_DP_2
D36
CSI2_DN_3
A38
CSI2_DP_3
B38
CSI2_DN_4
C31
CSI2_DP_4
D31
CSI2_DN_5
C33
CSI2_DP_5
D33
CSI2_DN_6
A31
CSI2_DP_6
B31
CSI2_DN_7
A33
CSI2_DP_7
B33
CSI2_DN_8
A29
CSI2_DP_8
B29
CSI2_DN_9
C28
CSI2_DP_9
D28
CSI2_DN_10
A A
5
4
A27
B27
C27
D27
CSI2_DP_10
CSI2_DN_11
CSI2_DP_11
REV = 1
SKYLAKE_ULT
5
4
3
2
1
SKL ULT - SPI/LPC/SMB/ISH
+V3P3A
R891 *249K_4
D D
SPI0_MOSI_IO_0
BOOT HALT
1 = DISABLE
0 = ENABLE
INTERNAL PU
SPI0_IO_2
CONSENT STRAP
1 = DISABLE
0 = ENABLE
INTERNAL PU
C C
NO REBOOT STRAP
1 = NO REBOOT
0 = REBOOT
INTERNAL PD
6/9 1. RAP1035 Un-stuff
2. NFC_RST move to GPP_C_10
BOOT BIOS STRAP
RAP1009
4.7K_2
1 = LPC
0 = SPI
INTERNAL PD
RAP1010
4.7K_2
B B
RAP1049
2.2K_4
RAP3043
*4.7K_4
+V3P3_TP_OUT
+V1P8S
+V1P8A
RAP1047
2.2K_4
RAP3044
*4.7K_4
SPI0_MISO_IO_1
JTAG ODT
1 = DISABLE
0 = ENABLE
INTERNAL PU
SPI0_IO_3
PERSONALITY STRAP
1 = DISABLE
0 = ENABLE
INTERNAL PU
+V3P3S
RAP1432
*20K_2
RAP1035
*20K_2
I2C4_SDA[28]
I2C4_SCL[28]
XDP_SPI0_MOSI[10]
XDP_SPI0_IO2[10]
FLASH_SPI_CL K[16]
FLASH_SPI_MISO[16]
FLASH_SPI_MOSI[16]
TP183
TP184
FLASH_SPI_CS*[16]
TPM_SPI_CS*[16]
EC_PCH_RCIN*[30]
LPC_SERIRQ[30]
WLAN_PCIE_WAKE*[26]
TP177
TP178 TP182
TP179
TP180
NFC_DWL_REQ[29 ]
NFC_IRQ*[29]
NFC_RST[29]
TP191
PCHRXD_SERVOTXD[10]
PCHTXD_SERVORXD[10]
SCREW_SPI_WP_STATUS[16]
TP233
I2C1_SDA[27]
I2C1_SCL[27]
C1138
33P/50V_4
I2C PORT ASSIGNMENT0LEVEL
A A
RESERVED
TRACKPAD
1
NFC
2
RESERVED
3
AUDIO CODEC
4
ISHISH 0
+3.3V
+3.3V
+1.8V
+1.8V
+1.8V
+1.8V
(2GB, 1866Mbps)K4E6E304EB-EGCF
R217 *1K_2
RAP1043 1K_2
RAP1044 1K_2
TP137
TP138
TP139
TP140
TP141
TP142
+V3P3A
+V3P3A_WIFI
C1139
33P/50V_4
ITCH_SPI_CLK
ITCH_SPI_MISO
ITCH_SPI_MOSI
ITCH_SPI_IO2
ITCH_SPI_IO3
ITCH_SPI_CS*
RAP1000 1 00K_2
R894 10K_2
R1144
100K_2
I2C2_SDA[29]
I2C2_SCL[29]
Memory straps pin
0
1
2
3
4
5
60110
0000
0001
0010
0011
0100
0101
SPI0_CLK
AV2
SPI0_MISO_IO_1
AW3
SPI0_MOSI_IO_0
AV3
SPI0_IO_2
AW2
SPI0_IO_3
AU4
SPI0_FLASH_0_CSB
AU3
SPI0_FLASH_1_CSB
AU2
SPI0_TPM_CSB
AU1
GPP_D_1_SPI1_CLK
M2
GPP_D_2_SPI1_MISO_IO_1
M3
GPP_D_3_SPI1_MOSI_IO_0
J4
GPP_D_21_SPI1_IO_2
V1
GPP_D_22_SPI1_IO_3
V2
GPP_D_0_SPI1_CSB
M1
MLK_CLK
G3
MLK_DATA
G2
MLK_RSTB
G1
GPP_A_0_RCINB
AW13
GPP_A_6_SERIRQ
AY11
REV = 1
GPP_B_15_GSPI0_CSB
AN8
GPP_B_16_GSPI0_CLK
AP7
GPP_B_17_GSPI0_MISO
AP8
GPP_B_18_GSPI0_MOSI
AR7
GPP_B_19_GSPI1_CSB
AM5
GPP_B_20_GSPI1_CLK
AN7
GPP_B_21_GSPI1_MISO
AP5
GPP_B_22_GSPI1_MOSI
AN5
GPP_C_8_UART0_RXD
AB1
GPP_C_9_UART0_TXD
AB2
GPP_C_10_UART0_RTSB
W4
GPP_C_11_UART0_CTSB
AB3
GPP_C_20_UART2_RXD
AD1
GPP_C_21_UART2_TXD
AD2
GPP_C_22_UART2_RTSB
AD3
GPP_C_23_UART2_CTSB
AD4
GPP_C_16_I2C0_SDA
U7
GPP_C_17_I2C0_SCL
U6
GPP_C_18_I2C1_SDA
U8
GPP_C_19_I2C1_SCL
U9
GPP_F_4_I2C2_SDA
AH9
GPP_F_5_I2C2_SCL
AH10
GPP_F_6_I2C3_SDA
AH11
GPP_F_7_I2C3_SCL
AH12
GPP_F_8_I2C4_SDA
AF11
GPP_F_9_I2C4_SCL
AF12
REV = 1
MEMORY PNPCH_MEM_CFG[3:0]
H9CCNNNBLTBLAR-NUD
K4E8E324EB-EGCF
K4E8E324EB-EGCF
H9CCNNNBLTBLAR-NUD
K4E6E304EB-EGCF
H9CCNNN8JTBLAR-NUD (HYX ,DUAL CHANNEL (4PCS) ,4GB, 1866Mbps) 31x80 ,
U80E
SKYLAKE_ULT
SMBUS, SMLINKSPI - FLASH
GPP_C_2_SMBALERTB
GPP_C_4_SML0DATA
GPP_C_5_SML0ALERTB
SPI - TOUCH
C LINK
LPC
5 OF 20
U80F
SKYLAKE_ULT
6 OF 20
ISHLPSS
GPP_C_7_SML1DATA
GPP_B_23_SML1ALERTB_PCHHOTB
GPP_A_1_LAD_0_ESPI_IO_0
GPP_A_2_LAD_1_ESPI_IO_1
GPP_A_3_LAD_2_ESPI_IO_2
GPP_A_4_LAD_3_ESPI_IO_3
GPP_A_5_LFRAMEB_ESPI_CSB
GPP_A_14_SUS_STATB_ESPI_RESETB
GPP_A_9_CLKOUT_LPC_0_ESPI_CLK
GPP_A_10_CLKOUT_LPC_1
GPP_F_10_I2C5_SDA_ISH_I2C2_SDA
GPP_F_11_I2C5_SCL_ISH_I2C2_SCL
GPP_D_13_ISH_UART0_RXD_SML0BDATA
GPP_D_14_ISH_UART0_TXD_SML0BCLK
GPP_D_16_ISH_UART0_CTSB_SML0BALERTB
GPP_C_12_UART1_RXD_ISH_UART1_RXD
GPP_C_13_UART1_TXD_ISH_UART1_TXD
GPP_C_14_UART1_RTSB_ISH_UART1_RTSB
GPP_C_15_UART1_CTSB_ISH_UART1_CTSB
GPP_A_12_BM_BUSYB_ISH_GP_6
Specification
(HYX ,SINGLE CHANNEL (2PCS), 2GB, 1866Mbps)H9CCNNN8JTBLAR-NUD
(HYX , DUAL CHANNEL (4PCS) ,8GB, 1866Mbps)
(SAM , DUAL CHANNEL (4PCS) ,4GB, 1866Mbps)
(SAM ,SINGLE CHANNEL (2PCS), 2GB, 1866Mbps)
(HYX ,SINGLE CHANNEL (2PCS), 4GB, 1866Mbps)
(SAM , DUAL CHANNEL (4PCS) ,8GB, 1866Mbps)
GPP_C_0_SMBCLK
GPP_C_1_SMBDATA
GPP_C_3_SML0CLK
GPP_C_6_SML1CLK
GPP_A_8_CLKRUNB
GPP_D_9_ISH_SPI_CSB
GPP_D_10_ISH_SPI_CLK
GPP_D_11_ISH_SPI_MISO
GPP_D_12_ISH_SPI_MOSI
GPP_D_5_ISH_I2C0_SDA
GPP_D_6_ISH_I2C0_SCL
GPP_D_7_ISH_I2C1_SDA
GPP_D_8_ISH_I2C1_SCL
GPP_D_15_ISH_UART0_RTSB
GPP_A_18_ISH_GP_0
GPP_A_19_ISH_GP_1
GPP_A_20_ISH_GP_2
GPP_A_21_ISH_GP_3
GPP_A_22_ISH_GP_4
GPP_A_23_ISH_GP_5
EDF8132A3MA-JD-F (1GB, 1866Mbps)
5
4
3
+V3P3A
R7
R8
TLS_CONFIDENTI ALITY
R10
R9
W2
W1
W3
V3
EXT_BOOT_STALL_STRAP
AM7
AY13
BA13
BB13
AY12
BA12
PM_SUS_STAT*
BA11
EC_LPC_CLK_R
AW9
PCH_LPC_CLK1
AY9
AW11
RAP1001 10K_2
P2
P3
P4
P1
I2C0_SDA
M4
I2C0_SCL
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
PCBA
31x00
31x20
31x10 ,
31x70
31x30
31x40
31x50
31x90
RAP1051
RAP1052
10K_2
10K_2
10/5 Modify
RPM3429 22_2
R1141 *100K_2
R1142 *100K_2
EN_PP1800_DX_AUDIO
Stuff
R1044,R1045,R1046
R1040,R1045,R1046
R1044,R1041,R1046
R1040,R1041,R1046
R1044,R1045,R1042
R1040,R1045,R1042
R1044,R1041,R1042
2
TP80
TP77
TP131
+V3P3A
R1143 *100K_2
PCH_MEM_CFG0
PCH_MEM_CFG1
PCH_MEM_CFG2
PCH_MEM_CFG3
SMB_CLK [10]
SMB_DATA [10]
EC_IN_RW [27]
LPC_LAD<0> [30]
LPC_LAD<1> [30]
LPC_LAD<2> [30]
LPC_LAD<3> [30]
LPC_FRAME* [30]
EC_LPC_CLK [ 30]
LPC_CLKRUN* [30]
USB_A0_ILIM_SEL [22]
USB_A1_ILIM_SEL [22]
PLACEHOLDER
TP181
TP213
TP212
AUDIO_IRQ* [28]
TP254
TP221
TP222
TP223
TP224
TP225
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R1040
SP@100K_2
R1044
SP@100K_2
+V3P3A
R5088
10K_4
1
R1041
SP@100K_2
R1045
SP@100K_2
GPP_C_2_SMBALERTB
TLS CONFIDENTIALITY
1 = ENABLE
0 = DISABLE
INTERNAL PD
R892
*10K_4
GPP_C_5_SML0ALERTB
ESPI/LPC EC
1 = ESPI
0 = LPC
INTERNAL PD
R1097
GPP_B_23_SMLALERTB_PCHHOTB
*4.7K/J_4
EXT BOOT STALL BYPASS
1 = ENABLE
0 = DISABLE
INTERNAL PD
+V1P8A
+V3P3A+V1P8A
R1131
3
QPM3388
FDV301N
R1042
SP@100K_2
R1046
SP@100K_2
100K_2
1
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SKL ULT - SPI/LPC/SMB/ISH
SKL ULT - SPI/LPC/SMB/ISH
SKL ULT - SPI/LPC/SMB/ISH
AUDIO_INT_WAK* [3]
+V3P3A
R1043
*100K_2
R1047
100K_2
ZDA
ZDA
ZDA
of
of
of
943Monday, Ap ril 04, 2016
943Monday, Ap ril 04, 2016
943Monday, Ap ril 04, 2016
8A
8A
8A
5
4
3
2
1
SKL ULT - XDP/CHROME SERVO
For Production systems unstuff ITP header and RAP1348. For ITP to function these 2 components need to be stuffed.
D D
XDP_PREQ*[7]
CFG<0>[14]
+V1P00S_VCCSTG
RAP1344
RAP1343
150/F_4
C C
B B
CAD NOTE:
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<0>
1K/F_4
+V1P00A
XDP_PRDY*[7]
CFG<1>[14]
CFG<2>[14]
CFG<3>[14]
XDP_BPM<0>[4]
XDP_BPM<1>[4]
CFG<4>[14]
CFG<5>[14]
CFG<6>[14]
CFG<7>[14]
SWAPPABLE OPTION
RAP1345 *SHORT_4
RAP1346 *SHORT_4
RAP1354 1K/F_4
RAP1355 *1K/F_4
RAP1356 *SHORT_4
RAP1348 *1.5K/F_4
RAP1357 *SHORT_4
RAP1358 *0_4
5/22 DNS
RAP1349 *SHORT_4
RAP1353 *0_4
RAP1350 *0_4
RAP1351 *SHORT_4
RAP1352 *SHORT_4
SMB_DATA[9]
SMB_CLK[9]
PCH_RSMRST*[3,30]
ROP_VCCST_PWRGD[3,34]
EC_PCH_PWRBTN*[3,30]
+V3P3A
XDP_SPI0_MOSI[9]
ROP_SYS_PWROK[3,34]
PCH_JTAG_TCLK[4]
CPU_JTAG_TCLK[4]
XDP_TCLK_JTAGX[4]
+V1P00A
RAP1365
*49.9_4
RAP1368
*0_4
RAP1369
1K/F_4
XDP_PRSNT_PIN1
PM_RSMRST_PWRGD_XDP
EAR_N
SPI0_MOSI_SYS_PWROK_XDP
SMB_DATA_R
SMB_CLK_R
XDP_TCLK1
XDP_TCLK0
CAD NOTE:
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<3>
SOC XDP
CN35
2
112
4
334
6
556
8
778
10
9910
12
111112
14
131314
16
151516
18
171718
20
191920
22
212122
24
232324
26
252526
28
272728
30
292930
32
313132
34
333334
36
353536
38
373738
40
393940
42
414142
44
434344
46
454546
48
474748
50
494950
52
515152
54
535354
56
555556
58
575758
60
595960
*BSH-030-01-L-D-A-TR
ITP_PMOD E_R
XDP_DBRESET_N
XDP_TDO
XDP_TDI
XDP_TMS
RAP1374 *SHORT_4
RAP1375 *SHORT_4
RAP1376 *SHORT_4
RAP1377 *SHORT_4
RAP1381 *SHORT_4
RAP1382 *SHORT_4
RAP1383 *SHORT_4
RAP1384 *SHORT_4
RAP1387 100K/F_4
RAP1385 *SHORT_4
RAP1386 *SHORT_4
STBP_0 [14]
STBN_0 [14]
CFG<8> [14]
CFG<9> [14]
CFG<10> [14]
CFG<11> [14]
STBP_1 [14]
STBN_1 [14]
CFG<12> [14]
CFG<13> [14]
CFG<14> [14]
CFG<15> [14]
CLKOUT_XDP_DP [3]
CLKOUT_XDP_DN* [3]
ITP_PMOD E [14]
PCH_SYSRST* [3,10,30]
CPU_JTAG_TDO [4]
PCH_JTAG_TDO [4]
XDP_JTAG_TRST* [4]
CPU_JTAG_TDI [4]
PCH_JTAG_TDI [4]
CPU_JTAG_TMS [4]
PCH_JTAG_TMS [4]
+V3P3A
XDP_SPI0_IO2 [9]
XDP_OVERRIDE* [36]
+V1P00A
R137
*49.9_4
GOOGLE CHROME SERVO SOCKET CONNECTOR
CN17
SERVO_PCH_SPI_CS*[16]
SERVO_PCH_SPI_MISO[16]
+V3P3A_EC_SPI_SERVO
+V3P3DSW_EC
+V3P3_INA
A A
5
SERVO_PCH_SPI_HOLD*[16]
SERVO_EC_SPI_CLK[30]
SERVO_EC_SPI_MOSI[30]
PCHTXD_SERVORXD[9]
USBPDRXD_SERVOTXD[23]
USBPDTXD_SERVORXD[23]
ECTXD_SERVORXD[30]
DEVICE_PROCHOT*[20,30,33,34,38]
USBPD_BOOT0[23] LID_OPEN [21,30]
EC_USBPD_RST*[23,30]
4
SD_CDZ[7,8,22]
RAP1360 *SHORT_2
RAP1428 *SHORT_2
RAP1364 *SHORT_2
SD_CD*_R_R
TP81
TP82
+V3P3_INA
TP83
TP84
TP85 TP86
*AXK750147G
3
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SERVO_EC_RST*
TP91
TP90
TP89
I2C_SCL_IN A_R I2C_SCL_IN AI2C_SDA_IN A I2C_SDA_IN A_R
TP88
TP87
CR15 RB500V-40
RAP1429 *SHORT_2
I2C_SCL_IN A
I2C_SDA_IN A
RPM3576 4.7K_4
RPM3577 4.7K_4
SERVO_PCH_SPI_CLK [16]
SERVO_PCH_SPI_MOSI [16]
SERVO_EC_SPI_CS* [30]
SERVO_EC_SPI_MISO [30]
V3P3DSW_ENA [27,30,31,35]
PCHRXD_SERVOTXD [9]
MECH_PWRBTN* [27,30,34]
PCH_SYSRST* [3,10,30]
ECRXD_SERVOTXD [30]
SERVO_SPI_WP* [ 16]
+V3P3_INA
2
+V3P3_BIOS_SPI_SERVO
+V3P3A
+V3P3A_EC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
PROJECT :
SKL ULT - XDP/SERVO
SKL ULT - XDP/SERVO
SKL ULT - XDP/SERVO
ZDA
ZDA
ZDA
1
8A
8A
8A
of
10 43Monday, April 04, 2016
10 43Monday, April 04, 2016
10 43Monday, April 04, 2016
5
4
3
2
1
SKL ULT - POWER CORE
U80L
D D
C C
EDRAM ONLY REQUIRED FOR 2+3E SKU
+VCCCORE +VCCCORE
VCCCORE
A30
VCCCORE
A34
VCCCORE
A39
VCCCORE
A44
VCCCORE
AK33
VCCCORE
AK35
VCCCORE
AK37
VCCCORE
AK38
VCCCORE
AK40
VCCCORE
AL33
VCCCORE
AL37
VCCCORE
AL40
VCCCORE
AM32
VCCCORE
AM33
VCCCORE
AM35
VCCCORE
AM37
VCCCORE
AM38
VCCCORE
G30
VCCCOREG0
K32
VCCCOREG1
AK32
VCCEDRAM
AB62
VCCEDRAM
P62
VCCEDRAM
V62
VCC_EDRAM_1P8
H63
VCC_EDRAM_FUSEPRG
G61
VCCEDRAM_SENSE
AC63
VSSEDRAM_SENSE
AE63
VCCEOPIO
AE62
VCCEOPIO
AG62
VCCEOPIO_SENSE
AL63
VSSEOPIO_SENSE
AJ62
REV = 1
SKYLAKE_ULT
CPU POWER 1 OF 4
12 OF 20
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE_SENSE
VSSCORE_SENSE
VIDALERT_N
VIDSCK
VIDSOUT
VCCFUSEPRG
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
CPU_SVIDALRT*_R
B63
A63
D64
G20
RPM3558 220_4
+V1P00S_VCCSTG
RAP1450
100/F_4
VCCCORE_SENSE [38]
VSSCORE_SENSE [38]
CPU_SVIDALRT* [38]
RAP1451
+V1P00S_VCCST
56_4
CPU_SVIDCLK [38]
CPU_SVIDDAT [38]
CORE
+VCCCORE
CAPS PLACE CLOSE TO SOC ON SAME SIDE
CAP1201
CAP1208
CAP1215
CAP1171
CAP1181
CAP1191
22u/6.3V_6
CAP1203
22u/6.3V_6
CAP1206
1U/6.3V_2
CAP1431
1U/6.3V_2
CAP14476
22u/6.3V_6
4
22u/6.3V_6
CAP1210
22u/6.3V_6
CAP1213
1U/6.3V_2
CAP1433
1U/6.3V_2
CAP14477
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
22u/6.3V_6
B B
CAPS PLACE ON OPPOSITE SIDE OF SOC
CAP1193
CAP1183
CAP1173
22u/6.3V_6
CAP1176
1U/6.3V_2
CAP1425
1U/6.3V_2
A A
5
CAPS PLACE CLOSE TO SOC ON SAME SIDE
CAP14473
22u/6.3V_6
22u/6.3V_6
CAP1186
1U/6.3V_2
CAP1427
1U/6.3V_2
CAP14474
22u/6.3V_6
22u/6.3V_6
CAP1196
1U/6.3V_2
CAP1428
1U/6.3V_2
CAP14475
22u/6.3V_6
22u/6.3V_6
CAP1217
22u/6.3V_6
CAP1220
1U/6.3V_2
CAP1435
1U/6.3V_2
CAP14478
22u/6.3V_6
CAP1172
22u/6.3V_6
CAP1223
22u/6.3V_6
CAP1226
1U/6.3V_2
CAP1437
1U/6.3V_2
CAP14479
22u/6.3V_6
CAP1192
22u/6.3V_6
CAP1229
22u/6.3V_6
CAP1231
1U/6.3V_2
CAP1439
1U/6.3V_2
CAP14480
22u/6.3V_6
CAP1174
10u/6.3V_4
CAP1234
22u/6.3V_6
CAP1235
1U/6.3V_2
CAP1441
1U/6.3V_2
CAP1184
10u/6.3V_4
CAP1443
10u/6.3V_4
CAP1177
1U/6.3V_2
CAP1424
1U/6.3V_2
3
CAP1194
10u/6.3V_4
CAP1444
10u/6.3V_4
CAP1187
1U/6.3V_2
CAP1426
1U/6.3V_2
CAP1204
10u/6.3V_4
CAP1445
10u/6.3V_4
CAP1197
1U/6.3V_2
CAP1429
1U/6.3V_2
CAP1211
10u/6.3V_4
CAP1446
10u/6.3V_4
CAP1207
1U/6.3V_2
CAP1430
1U/6.3V_2
CAP1218
10u/6.3V_4
CAP1447
10u/6.3V_4
CAP1214
1U/6.3V_2
CAP1432
1U/6.3V_2
CAP1224
10u/6.3V_4
CAP1448
10u/6.3V_4
CAP1221
1U/6.3V_2
CAP1434
1U/6.3V_2
CAP1442
10u/6.3V_4
CAP1449
10u/6.3V_4
CAP1227
1U/6.3V_2
CAP1436
1U/6.3V_2
2
CAP1232
1U/6.3V_2
CAP1438
1U/6.3V_2
CAP1236
1U/6.3V_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
SKL ULT - CORE POWER
SKL ULT - CORE POWER
SKL ULT - CORE POWER
1
ZDA
ZDA
ZDA
8A
8A
11 43Monday, April 04, 2016
11 43Monday, April 04, 2016
11 43Monday, April 04, 2016
8A
of
of
of
5
4
3
2
1
SKL ULT - POWER GRAPHICS
D D
+VCCGT
VCCGT
A48
VCCGT
A53
VCCGT
A58
VCCGT
A62
VCCGT
A66
VCCGT
AA63
VCCGT
AA64
VCCGT
AA66
VCCGT
AA67
VCCGT
AA69
VCCGT
AA70
VCCGT
AA71
VCCGT
AC64
VCCGT
AC65
VCCGT
AC66
VCCGT
AC67
VCCGT
AC68
VCCGT
AC69
VCCGT
AC70
VCCGT
AC71
VCCGT
K48
K50
K52
K53
K55
K56
K58
K60
M62
N63
N64
N66
N67
N69
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
REV = 1
C C
B B
VCCGT_SENSE[38]
VSSGT_SENSE[38]
U80M
SKYLAKE_ULT
CPU POWER 2 OF 4
SLICED GT
UNSLICED GT
VCCGTU_SENSE
VSSGTU_SENSE
13 OF 20
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
VCCGTU
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
CAPS PLACE CLOSE TO SOC ON SAME SIDE
C51
22u/6.3V_6
CAPS PLACE ON OPPOSITE SIDE OF SOC
CAP1156
10u/6.3V_4
CAP1102
1U/6.3V_2
C1029
22u/6.3V_6
+VCCGT
CAPS PLACE CLOSE TO SOC ON SAME SIDE
CAP1101
*10u/6.3V _4
CAPS PLACE ON OPPOSITE SIDE OF SOC
CAP1456
*10u/6.3V _4
CAP14466
*10u/6.3V _4
C62
22u/6.3V_6
CAP1157
10u/6.3V_4
CAP1109
1U/6.3V_2
C1030
22u/6.3V_6
CAP1108
*10u/6.3V _4
CAP1457
*10u/6.3V _4
CAP1467
*10u/6.3V _4
C63
22u/6.3V_6
CAP1162
10u/6.3V_4
CAP1116
1U/6.3V_2
C1031
22u/6.3V_6
CAP1115
*10u/6.3V _4
CAP1458
*10u/6.3V _4
CAP1468
*10u/6.3V _4
C64
22u/6.3V_6
CAP1165
10u/6.3V_4
CAP1123
1U/6.3V_2
C1032
22u/6.3V_6
CAP1122
*10u/6.3V _4
CAP1459
*10u/6.3V _4
CAP1469
*10u/6.3V _4
C65
22u/6.3V_6
CAP1167
10u/6.3V_4
CAP1130
1U/6.3V_2
C1033
22u/6.3V_6
CAP1129
*10u/6.3V _4
CAP1460
*10u/6.3V _4
CAP1470
*10u/6.3V _4
CAP1155
22u/6.3V_6
CAP1169
10u/6.3V_4
CAP1137
1U/6.3V_2
CAP1136
*10u/6.3V _4
CAP1461
*10u/6.3V _4
CAP1471
*10u/6.3V _4
CAP1159
22u/6.3V_6
CAP1179
10u/6.3V_4
CAP1142
1U/6.3V_2
CAP1141
*10u/6.3V _4
CAP1462
*10u/6.3V _4
CAP1472
*10u/6.3V _4
CAP1161
22u/6.3V_6
CAP1189
10u/6.3V_4
CAP1148
1U/6.3V_2
CAP1147
*10u/6.3V _4
CAP1463
*10u/6.3V _4
CAP1473
*10u/6.3V _4
CAP1164
22u/6.3V_6
CAP1199
10u/6.3V_4
CAP1103
1U/6.3V_2
CAP1150
*10u/6.3V _4
CAP1464
*10u/6.3V _4
CAP1474
*10u/6.3V _4
CAP1166
22u/6.3V_6
CAP1450
10u/6.3V_4
CAP1110
1U/6.3V_2
CAP1152
*10u/6.3V _4
CAP1465
*10u/6.3V _4
CAP1475
*10u/6.3V _4
CAP1168
22u/6.3V_6
CAP1451
10u/6.3V_4
CAP1117
1U/6.3V_2
CAP1178
22u/6.3V_6
CAP1452
10u/6.3V_4
CAP1124
1U/6.3V_2
CAP1131
1U/6.3V_2
CAP1138
1U/6.3V_2
CAP1476
*1U/6.3V_ 2
A A
5
4
CAP1486
*1U/6.3V_ 2
CAP1477
*1U/6.3V_ 2
CAP1487
*1U/6.3V_ 2
CAP1478
*1U/6.3V_ 2
CAP1488
*1U/6.3V_ 2
3
CAP1479
*1U/6.3V_ 2
CAP1489
*1U/6.3V_ 2
CAP1480
*1U/6.3V_ 2
CAP1490
*1U/6.3V_ 2
CAP1481
*1U/6.3V_ 2
CAP1491
*1U/6.3V_ 2
CAP1482
*1U/6.3V_ 2
CAP1492
*1U/6.3V_ 2
CAP1483
*1U/6.3V_ 2
CAP1493
*1U/6.3V_ 2
CAP1484
*1U/6.3V_ 2
CAP1494
*1U/6.3V_ 2
2
CAP1485
*1U/6.3V_ 2
CAP1495
*1U/6.3V_ 2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
SKL ULT - GT POWER
SKL ULT - GT POWER
SKL ULT - GT POWER
1
ZDA
ZDA
ZDA
8A
8A
8A
12 43Monday, April 04, 2016
12 43Monday, April 04, 2016
12 43Monday, April 04, 2016
of
of
of
+V1P8A
RPM3305 *SHORT_4
RPM3309 *SHORT_4
+V3P3A
RPM3310 *0.01/F_4
RPM3314 *SHORT_4
D D
C C
B B
A A
RPM3315 *SHORT_4
RPM3316 *SHORT_4
+V3P3A_DSW
RPM3312 *SHORT_4
+V3P3A_RTC
RPM3317 *SHORT_4
RPM3326 *SHORT_4
RPM3327 *SHORT_4
RPM3328 *SHORT_4
RPM3329 *SHORT_4
RPM3323 *0.01/F_4
+V1P8A
RPM3324 *SHORT_4
RPM3331 *SHORT_4
+V3P3A +VCCPGPPG
RPM3333 *SHORT_4
+V1P00A +VCCDUSB_1P0
RPM3282 *SHORT_6
+V1P00A +VCCPRIM_1P0
RPM3283 *SHORT_8
RPM3284 *SHORT_6
RPM3285 *SHORT_4
RPM3286 *SHORT_8
RPM3288 *SHORT_4
RPM3289 *SHORT_8
RPM3290 *SHORT_4
RPM3291 *SHORT_4
RPM3292 *SHORT_4
RPM3293 *SHORT_4
RPM3294 *SHORT_4
RPM3295 *SHORT_4
RPM3296 *SHORT_4
RPM3297 *SHORT_4
RPM3298 *SHORT_4
RPM3287 *SHORT_4
5
+VCCATS
+VCCPAZIO
+VCCPSPI
+VCCPRIM_3P3
+VCCPRTCPRIM_3P3
+VCCPDSW_3P3
+VCCPRTC_3P3
+VCCPGPPA+V3P3A
+VCCPGPPB
+VCCPGPPC
+VCCPGPPE
+VCCPGPPD
+VCCPGPPF
+VCCPRIM_CORE
+VCCMPHYAON_1P0
+VCCMPHYGTAON_1P0
+VCCAPLL_1P0
+VCCSRAM_1P0
+VCCFHV
+VCCAPLLEBB_1P0
+VCCDTS_1P0
+VCC19P2_1P0
+VCCF100_1P0
+VCCF135_1P0
+VCCF100OC_1P0
+VCCF24NS_1P0
+VCC24TBT_1P0
+VCCAMPHYPLL_1P0_R
5
+VDDQ_MEM
R3571 *SHORT_8
+VCCMPHYGTAON_1P0
L15 2.2uH/0.12A_6
CAPS PLACE CLOSE TO SOC ON SAME SIDE
CAP1264
CAP1270
22u/6.3V_6
22u/6.3V_6
CAPS PLACE ON OPPOSITE SIDE OF SOC
+VCCMPHYAON_1P0
C1102
22u/6.3V_6
CAP1245
22u/6.3V_6
C1103
22u/6.3V_6
+VCCDUSB_1P0
CAP1252
22u/6.3V_6
+VCCSRAM_1P0
CAP1256
*1u/6.3V_4
+VCCAMPHYPLL_1P0
C1087
22u/6.3V_6
CAP1244
1u/6.3V_4
+VCCPDSW_3P3
CPM4429
*0.22u/10V_4
CAP1253
*10u/6.3V_4
CAP14493
10u/10V_4
C1088
22u/6.3V_6
4
CAP1247
10u/6.3V_4
+V1P00S_VCCST
+VCCSFR_OC
CAP1262
1u/6.3V_4
+VCCAPLL_1P0
CAP14482
1u/6.3V_4
CAP14481
1u/6.3V_4
4
CAP1274
22u/6.3V_6
CAP1242
*10u/6.3V_4
CAP1249
1u/6.3V_4
CAP1250
1U/6.3V_2
+VCCPSPI
+VCCFHV
CAP1267
1u/6.3V_4
3
SKL ULT - IO/SA/MEM POWER
+VDDQ_MEM_SOC
CAP1241
CAP1265
10u/6.3V_4
CAP1243
*1U/6.3V_2
+VDDQ_MEM_SOC
CAP1259
1U/6.3V_2
+V1P00S_VCCSTG
CAP1260
1u/6.3V_4
+V1P00S_VCCST
C1140
10u/10V_4
+VCCPRIM_CORE
CAP1272
*1u/6.3V_4
+VCCAMPHYPLL_1P0
+VCCPAZIO
+VCCPRIM_3P3
+VCCAPLLEBB_1P0
CAP1271
1u/6.3V_4
10u/6.3V_4
CAP1248
*1U/6.3V_2
PRIM CAPSSEC CAPS
CAP1240
10u/6.3V_4
C1141
10u/10V_4
+VCCPRIM_1P0
+VCCDSW_1P0
CAP1257
10u/6.3V_4
CAP1254
*1U/6.3V_2
CAP1276
*1u/6.3V_4
CAP1261
1u/6.3V_4
CAP1258
*1U/6.3V_2
CAP14483
1u/6.3V_4
AB19
AB20
P18
AF18
AF19
V20
V21
AL1
K17
N15
N16
N17
P15
P16
K15
L15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
T19
T20
AJ21
AK20
N18
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
L1
VCCMPHYGTAON_1P0
VCCMPHYGTAON_1P0
VCCMPHYGTAON_1P0
VCCMPHYGTAON_1P0
VCCMPHYGTAON_1P0
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCDUSB_1P0
VCCDUSB_1P0
VCCPDSW_3P3
VCCPDSW_3P3
VCCPDSW_3P3
VCCPAZIO
VCCPSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPFUSE_3P3
VCCFHV_2P8
VCCAPLLEBB
REV = 1
AU23
VCCDU
VCCDU
AU28
AU35
VCCDU
AU42
VCCDU
BB23
VCCDU
BB32
VCCDU
VCCDU
BB41
BB47
VCCDU
BB51
VCCDU
VCCDDQ_CLK
AM40
A18
VCCST
A22
VCCSTG
AL23
VCCSFR_OC
K20
VCCSFR
K21
VCCSFR
REV = 1
CPU POWER 4 OF 4
3
CPU POWER 3 OF 4
U80O
SKYLAKE_ULT
15 OF 20
SKYLAKE_ULT
14 OF 20
U80N
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPHVC_3P3
VCCDTS_1P0
VCCATS
VCCPRTCPRIM_3P3
VCCPRTC_3P3
VCCPRTC_3P3
VCCRTCEXT
VCC19P2_1P0
VCCF100_1P0
VCCF135_1P0
VCCF100OC_1P0
VCCF24NS_1P0
VCC24TBT_1P0
GPP_B_0_CORE_VID_0
GPP_B_1_CORE_VID_1
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+VCCPGPPG
2
+V1P00S_VCCSTG
CAPS PLACE CLOSE TO SOC ON SAME SIDE CAPS PLACE ON OPPOSITE SIDE OF SOC
CAP1278
VCCRT CEXT
C1C7
10u/10V_4
CAP1277
1U/6.3V_2
+VCCSA
TP48
TP49
VSSSA_SE NSE [38]
VCCSA_S ENSE [ 38]
CAP1282 0.1U/16V_4
TP51
TP52
CAP1255
*47u/10V_8
1U/6.3V_2
CAPS PLACE CLOSE TO SOC ON SAME SIDE
+VCCPGPPC +VCCPGPPE+VCCPGPPA
CAP1279
*1u/6.3V_4
+VCCPAZIO+VCCAPLL_1P0
2
CAP1283
CAP1280
1U/6.3V_2
1U/6.3V_2
CAP1284
CAP1281
10u/6.3V_4
10u/6.3V_4
CAPS PLACE ON OPPOSITE SIDE OF SOC
CAP1285
10u/6.3V_4
CAP1286
1U/6.3V_2
+VCCPGPPD +VCCPGPPF+VCCPGPPB
CAP1287
*1u/6.3V_4
DESIGN NOTE:
CAP ON VCCRTCEXT MUST BE LOW LEAKAGE
CAP1297
*1u/6.3V_4
+VCCPRIM_3P3
CAP1268
*1u/6.3V_4
+VCCF24NS_1P0+VCC24TBT_1P0
CAP1289
10u/6.3V_4
CAP1290
10u/6.3V_4
CAP1291
1U/6.3V_2
CAP1296
*1u/6.3V_4
CAP1306
*47u/10V_8
CAP1275
*1u/6.3V_4
CAP1288
*1U/6.3V_2
CAP1293
10u/6.3V_4
CAP1294
10u/6.3V_4
CAP1295
1U/6.3V_2
+VCCPGPPF
+VCCPGPPG
+VCCF100OC_1P0
1
CAP1292
CAP1298
*1U/6.3V_2
*1U/6.3V_2
CAP1299
CAP1303
10u/6.3V_4
10u/6.3V_4
CAP1304
CAP1300
10u/6.3V_4
10u/6.3V_4
CAP1305
CAP1301
1U/6.3V_2
1U/6.3V_2
please put C2 close to SOC ball AF16
C2
0.1U/16V_4
+VCCPRIM_3P3
+VCCDTS_1P0
+VCCATS
CAP1311
1u/6.3V_4
CAP1312
*47u/10V_8
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
SKL ULT - IO/MEM/SA POWER
SKL ULT - IO/MEM/SA POWER
SKL ULT - IO/MEM/SA POWER
CAP1307
*10u/6.3V_4
CAP1317
1u/6.3V_4
CAP1318
1u/6.3V_4
CAP1313
*10u/6.3V_4
CAP1316
1U/6.3V_2
CAP1319
0.1U/16V_4
+VCC19P2_1P0
ZDA
ZDA
ZDA
+VCCF100_1P0
CAP1321
*47u/10V_8
+VCCF135_1P0
of
13 43Monday, April 04, 2016
13 43Monday, April 04, 2016
13 43Monday, April 04, 2016
CAP1302
*1U/6.3V_2
CAP1308
22u/6.3V_6
CAP1309
10u/6.3V_4
CAP1310
1U/6.3V_2
+VCCPRTCPRIM_3P3
+VCCPRTC_3P3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
CAP1320
0.1U/16V_4
8A
8A
8A
5
4
3
2
1
SKL ULT - RESERVED
D D
CFG<0>
RAP1328
*1K_2
U80S
SKYLAKE_ULT
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG0
1:(DEFAULT) NORMAL OPERATION; NO STALL
0:STALL
AW69
AW68
AU56
AW48
C7
U12
U11
H11
RESERVED SIGNALS
19 OF 20
SPARE_1
SPARE_2
SPARE_3
SPARE_4
SPARE_5
SPARE_6
SPARE_7
SPARE_8
REV = 1
U80T
SKYLAKE_ULT
SPARE
20 OF 20
4
DDR_VIEW[0]
DDR_VIEW[1]
PEG_VIEW[2]
PEG_VIEW[3]
CPU_POPIO_VIEW[0]
CPU_POPIO_VIEW[1]
POPIICCCTL
POPIICCOBS
PCIE2_PLLOBSN
PCIE2_PLLOBSP
PCIE3_PLLOBSN
PCIE3_PLLOBSP
SATA_PLLOBSN
SATA_PLLOBSP
USB2_PLLMON
MIPI_PLLOBSN
MIPI_PLLOBSP
AZA_PLLMON_N
AZA_PLLMON_P
XCKPLL_MON_N
XCKPLL_MON_P
PGDMON
CPU_EDM[0]
CPU_EDM[1]
PCH_EDM
FIVR_PROBE_ANA[0]
FIVR_PROBE_ANA[1]
FIVR_PROBE_DIG[0]
FIVR_PROBE_DIG[1]
FPF_MON
FPF_VREF
EDRAM_EDM
ZVM_N
EDRAM_VIEW[0]
EDRAM_VIEW[1]
MSM_N
SKL_CNL_N
SPARE_9
F6
SPARE_10
E3
SPARE_11
C11
SPARE_12
B11
SPARE_13
A11
SPARE_14
D12
SPARE_15
C12
SPARE_16
F52
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
TP76
PCH_EDM
EDRAM_EDM
SKL_CNL*
PGDMON
DFXTESTMODE
1 = DISABLE
ENABLE
INTERNAL PU
RAP1326
*SHORT_2
RAP1325
*SHORT_2
RAP1324 *100K_2
3
+V1P00S_VCCST
JUST A PLACEHOLDER - NO PEG FOR ULX/ULT
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG2
1: (DEFAULT)NORMAL OPERATION;
0: LANE REVERSAL
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG3
0 : ENABLED
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
DISPLAY PORT PRESENCE STRAP
CFG4
0: ENABLED
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE
EMBEDDED DISPLAY PORT
1: DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO
EMBEDDED DISPLAY PORT
CFG<5> CFG<6>
JUST A PLACEHOLDER.
NOT NEEDED FOR ULX-ULT
PCIE PORT BIFURCATION STRAPS
CFG[6:5]
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNCTION1 ENABLED DEVICE1 FUNCTION 2 DISABLED
01: DEVICE 1 FUNCTION 1 DISABLED, DEVICE 1 FUNCTION 2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
Reserve
1: DISABLED(DEFAULT)
CFG8
RAP1327
*1K_2
JUST A PLACEHOLDER.
NOT NEEDED FOR ULX-ULT
0: ENABLED; WILL BE
NO SVID PROTOCOL CAPABLE VR CONNECTED
CFG9
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
0:NO VR SUPPORTING SVID
IS PRESENT. THE CHIP WILL NOT
GENERATE (OR RESPOND TO) SVID ACTIVITY
SAFE MODE BOOT
CFG10
1: POWER FEATURES ACTIVATED DURING RESET
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
2
CFG<2>
RAP1330
*1K_2
CFG<3>
RAP1331
*1K_2
CFG<4>
RAP1332
1K_2
RAP1333
*1K_2
CFG<8>
RAP1335
*1K_2
CFG<9>
RAP1336
*1K_2
CFG<10>
RAP1337
*1K_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
SKL ULT - RESERVED
SKL ULT - RESERVED
SKL ULT - RESERVED
ZDA
ZDA
ZDA
of
of
of
14 43Monday, April 04, 2016
14 43Monday, April 04, 2016
1
14 43Monday, April 04, 2016
8A
8A
8A
N[0]
CFG<0>[10]
CFG<1>[10]
CFG<2>[10]
CFG<3>[10]
CFG<4>[10]
CFG<5>[10]
CFG<6>[10]
CFG<7>[10]
CFG<8>[10]
CFG<9>[10]
CFG<10>[10]
CFG<11>[10]
CFG<12>[10]
CFG<13>[10]
CFG<14>[10]
CFG<15>[10]
C C
RAP1323
49.9_4
STBN_0[10]
STBP_0[10]
STBN_1[10]
STBP_1[10]
RCOMP
ITP_PMOD E[10]
+V1P00A
RAP1322
1.5K/F_4
B B
E68
N[1]
B67
N[2]
D65
N[3]
D67
N[4]
E70
N[5]
C68
N[6]
D68
N[7]
C67
N[8]
F71
N[9]
G69
N[10]
F70
N[11]
G68
N[12]
H70
N[13]
G71
N[14]
H69
N[15]
G70
STBN[0]
E63
STBP[0]
F63
STBN[1]
E66
STBP[1]
F66
RCOMP
E60
ITP_PMODE
E8
TD_ANODE
AY2
TD_CATHODE
AY1
TD_DFTANATP0
D1
TD_DFTANATP1
D3
THERMDA1
K46
THERMDC1
K45
THERMDA2
AL25
THERMDC2
AL27
HVM_CLK_N
C71
HVM_CLK_P
B70
LGC_SPARE[0]
F60
EXTBGREF
A52
CPU_EOPIO_VIEW[0]
BA70
CPU_EOPIO_VIEW[1]
BA68
EANALOGVP[0]
J71
EANALOGVP[1]
J68
EDRAM_THERMDA
F65
EDRAM_THERMDC
G65
LGC_SPARE[1]
F61
LGC_SPARE[2]
E61
REV = 1
A A
5
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