Acer CHROMEBOOK 13 Schematics

A

ompal Confidential

C

M

odel Name : Z3ENN

File Name : LA-B551PR10

OM P/N : 4319TUBOL01~10

B

1

2

AX

D

DA@

P

CB

DAZ17600100

DAZ17600100 P

P

CB Z3ENN LA-B551P LS-B551P

B

C

D

Compal Confidential

NIKE MB LA-B551P

E

1

2

Nvidia LOGAN Processor

2014-05-28

3

REV: 1.0

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

Z3ENN M/B LA-B551P

E

of

1 42Thursday, June 19, 2014

of

1 42Thursday, June 19, 2014

of

1 42Thursday, June 19, 2014

4

1.0

A

ompal Confidential

C

odel Name : LOGAN Block Diagram

M

D

MIC * 1

1

S

peaker * 2

(2W)

Audio JACK HP + MIC

P.23

2

HEADSET SW TS3A225E

PWR_ON

P.23

B

DDR3L 256/512Mb*16

D

DR3L

256/512Mb*16

P

.04

C

DDR3L Bus

D

DDR3L 256/512Mb*16

P.05

DDR3L 256/512Mb*16

E

P.04 P.05

1

Audio Codec MAX9809X

P.22

G

EN1_I2C

CH0 DDR CH1

VDDIO_DDR (1.35V)

DAP2 VDDIO_AUDIO (1.8V)

SDMMC4 VDDIO_SDMMC4 (1.8V)

SDMMC3 VDDIO_SDMMC3 (1.8V & 3.3V)

8 bits

eMMC 16G/32G

P.25

SD Card4 bits

P.27

PMU_32K_IN

PMIC AS3722

32KHz

AS3728

SYS_RESET#

CORE_PWR_REQ

CPU_PWR_REQ

PWR_I2C

VDDIO_SYS (1.8V)

Nvidia

Logan

SDMMC1 VDDIO_SDMMC1 (1.8V)

LVDS/DP

AVDD_LVDS0_IO (1.05V) AVDD_PLL_UD2DPD (1.05V) AVDD_LVDS0_PLL

12MHz

BT/WLAN Antenna

WIFI/BT AW-CM389NF FOXCONN T77H526.01

P.20

13.3" LCD Panel 1366*768 eDP I/F

P.14

2

GEN1_I2C

HDMI

3

HDMI CONN.

HDMI & DDC

P.16

Charger BQ24735

BATT CONN.

P.31

CHARGER_I2C

EC STM32L100

P.29

AVDD_HDMI (3.3V)

AVDD_HDMI_PLL (1.05V)

SPI VDDIO_BB (1.8V)

USB2.0

AVDD_USB (3.3V)

USB3.0

P.31

THEM Sensor G781

P.29

LID SW IC

P.24

SPI ROM

4

W25Q32DW

P.18

SPI VDDIO_GMI (1.8V)

USB3.0

USB3.0 * 2 Port

Camera Module

VDDIO_UART (1.8V)

GEN2_I2C VDDIO_HV (3.3V)

CAM_I2C VDDIO_CAM (1.8V)

USB2.0

THEM Sensor TMP451

TPM SLB9645TT1.2 (FW:133.32Goog)

P.21

P.27

3

Touch ScreenTouch PAD

Design reserve

P.28

4

www.schematic-x.blogspot.com

P.17 P.14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet

SYSTEM BLOCK

Z3ENN M/B LA-B551P

E

of

2 42Thursday, June 1 9, 2014

of

2 42Thursday, June 1 9, 2014

of

2 42Thursday, June 1 9, 2014

0.1

A

V

oltage Rails

Power Plane Description

VIN

BATT+ Battery power supply

B+

VDD_5V0_SYS For All Device standby mode

VDD_3V3_SYS For All Device standby mode

VDD_1V8_PMU

1

V_RTC_1V8

+VDD_1V35_MEM

VDD_0V675_DDR3_VREF For DDR VREFDQ & VREF CA

VDD_1V2_CORE_AP

VDD_1V0_CPU For TEGRA CPU VDD

VDD_1V05_PLL_AP

VDD_1V8_PMU For TEGRA AVDD_OSC, VDDIO_SYS

VDD_1V05_PLL_AP For TEGRA VDDIO_DDR_HS

VDD_1V8_PMU For TEGRA VDDIO_GMI,

VDD_1V05_PLL_AP

V_USB_3V3

VDD_1V8_PMU

2

VDD_3V3_HV_AP For TEGRA VDDIO_HV

VDD_1V05_PLL_AP For TEGRA AVDD_HDMI_PLL

VDD_1V05_PLL_AP

VDD_1V8_PMU For TEGRA VDDIO_BB

VDD_1V8_PMU

VDD_1V8_PMU For eMMC VCCQ Power rail

VDD_2V85_EMMC For eMMC Power rail

VDD_5V0_SYS For CODEC AMP Power

+MICBIAS For MIC signal

VDD_1V8_PMU For CODEC Power

V_MIPI_1V2 For eDP bridge Power

VDDC_1V8_EDP For eDP bridge Power

3

VDD_3V3_SYS For Cap sensor Power rail

BL_12V For LCD backlight Power rail

VDD_3V3_LCM For LCD Power rail

VDD_3V3_LCM For Touch Control Power rail

V_SENSOR_2V85 For GYRO & COMPASS rail

VDD_3V3_SYS For Wireless KB Power rail

V_CAM_2V8

VDD_1V8_PMU

V_VCM_2V8

VDD_3V3_SYS

VDD_1V8_PMU

VDD_3V3_SYS For NFC VBAT Power rail

VDD_1V8_PMU For NFC PVDD Power rail

VDD_3V3_SYS For GPS VDD Power rail

VDD_1V8_PMU

+GPS_AUX_OUT

VDD_3V3_SBY_EC(EC_AVCC) For MCU Power

4

Adapter power supply (12V)

AC or battery power rail for power circuit.

For All Device standby mode

PMU RTC power rail

DDR3L power rail & TEGRA DDR power rail

For TEGRA core logic

AVDD_PLL_P_C, AVDD_PLL_X, AVDD_PLL_M, AVDD_PLL_U, AVDD_PLL_E

For TEGRA AVDDIO_USB3, AVDD_USB3_PLL

For TEGRA AVDD_USB, HVDD_USB3

For TEGRA VDDIO_CAM, VDDIO_SDMMC4, AVDD_USB_PLL

For TEGRA AVDD_HDMIAVDD_3V3_HDMI_TEGRA_S

For TEGRA AVDD_DSI_CSI_PLL

For TEGRA AVDD_DSI_CSIV_MIPI_1V2

For SD card PowerVDD_3V3_SD_CARD

For TEGRA VDDIO_SDMMC3V_MICROSD_IO

For TEGRA VDDIO_Audio,VDDIO_SDMMC1, VDDIO_UART

For eMMC VCC Power railVDD_2V85_EMMC

For 2M Front Camera & ALS Power railVDD_3V3_SYS

For 8M Rear CAMERA AVDD

For 8M Rear CAMERA VDDIO

For 8M Rear CAMERA VCM_VDD

For WIFI VBAT Power rail

For WIFI VIO Power rail

For GPS VDDIO Power rail

For GPS LNA Power

A

CTIVE SUSPEND

B

DEEP SLEEP OFF

C

OM Config

B

on-Touch

N

4

319TUBOL01 (SMT MB AB551 Z3ENN HYN 2G KIN 16G HDMI)

EMI@/DA@/HYN2G@/HYN16G@/AZURE@

4

319TUBOL02 (SMT MB AB551 Z3ENN T50 2G/16G HDMI)

EMI@/DA@/HYN2G@/HYN16G@/AZURE@

4319TUBOL03 (SMT MB AB551 Z3ENN T50 4G/32G HDMI) EMI@/DA@/HYN4G@/HYN32G@/AZURE@

4319TUBOL04 (SMT MB AB551 Z3ENN T50 2G/32G HDMI) EMI@/DA@/HYN2G@/HYN32G@/AZURE@

4319TUBOL05 (SMT MB AB551 Z3ENN T50 4G/16G HDMI) EMI@/DA@/HYN4G@/HYN16G@/AZURE@

4319TUBOL06 (SMT MB AB551 Z3ENN HYN 2G KIN 16G P2 HDMI) EMI@/DA@/HYN2G@/KIN16G@/AZURE@

Touch

4319TUBOL07 (SMT MB AB551 Z3ENN T50 2G/16G T HDMI) TS@/EMI@/DA@/HYN2G@/KIN16GA@/AZURE@

4319TUBOL08 (SMT MB AB551 Z3ENN T50 4G/32G T HDMI) TS@/EMI@/DA@/HYN4G@/HYN32G@/FOXCO@

4319TUBOL09 (SMT MB AB551 Z3ENN T50 2G/32G T HDMI) TS@/EMI@/DA@/HYN2G@/HYN32G@/FOXCO@

4319TUBOL10 (SMT MB AB551 Z3ENN T50 4G/16G T HDMI) TS@/EMI@/DA@/HYN4G@/KIN16G@/FOXCO@

@EMI@

DA@PCB

@

KIN16G@ HYN16G@ KIN32G@ HYN32G@ KIN16GA@

HYN2G@ HYN4G@ KIN2G@ AZURE@ FOXCO@

E

1

2

3

4

D

B

TO Option Table

B

TO Item BOM Structure

EMI Part EMI@ EMI Reserve Part ESD Reserve Part @ESD@

Connector CONN@ UN-MOUNT

eMMC

DDR3L

WIFI/BT

Touch Screen TS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet

Notes List

Z3ENN M/B LA-B551P

E

of

3 42Thursday, June 1 9, 2014

of

3 42Thursday, June 1 9, 2014

of

3 42Thursday, June 1 9, 2014

0.1

A

D580M: CH0 MEMORY I/F

C

1

DDR_DQ[0..31](6)

BYTE 0

BYTE 2

2

BYTE 1

BYTE 3

DDR_DQS0P(6)

3

DDR_DQS0N(6)

DDR_DM0(6)

DDR_DQS2P(6) DDR_DQS2N(6)

DDR_DM2(6)

DDR_DQS1P(6) DDR_DQS1N(6)

DDR_DM1(6)

DDR_DQS3P(6) DDR_DQS3N(6)

DDR_DM3(6)

DDR_DQS0P

DDR_DQS0N

DDR_DQS2P

DDR_DQS2N

DDR_DQS1P

DDR_DQS1N

DDR_DQS3P

DDR_DQS3N

DDR_DQ0

DDR_DQ1

DDR_DQ2 DDR_DQ3

DDR_DQ4

DDR_DQ5

DDR_DQ6

DDR_DQ7

DDR_DQ16

DDR_DQ17

DDR_DQ18

DDR_DQ19 DDR_DQ20

DDR_DQ21

DDR_DQ22

DDR_DQ23

DDR_DQ8

DDR_DQ9 DDR_DQ10

DDR_DQ11 DDR_DQ12

DDR_DQ13 DDR_DQ14

DDR_DQ15

DDR_DQ24

DDR_DQ25

DDR_DQ26

DDR_DQ27 DDR_DQ28

DDR_DQ29 DDR_DQ30

DDR_DQ31

DDR_DM0

DDR_DM2

DDR_DM1

DDR_DM3

B

U1E

BGA

SEC 5 OF 8

B5

DDR_DQ0

B2

DDR_DQ1

A5

DDR_DQ2

C2

DDR_DQ3

B3

DDR_DQ4

C3

DDR_DQ5

A4

DDR_DQ6

A3

DDR_DQ7

E9

DDR_DQ8

A9

DDR_DQ9

G8

DDR_DQ10

C9

DDR_DQ11

E8

DDR_DQ12

F9

DDR_DQ13

F8

DDR_DQ14

D9

DDR_DQ15

B8

DDR_DQ16

C6

DDR_DQ17

A8

DDR_DQ18

A6

DDR_DQ19

F6

DDR_DQ20

D6

DDR_DQ21

A7

DDR_DQ22

E6

DDR_DQ23

D11

DDR_DQ24

A11

DDR_DQ25

E11

DDR_DQ26

B11

DDR_DQ27

F11

DDR_DQ28

G12

DDR_DQ29

A10

DDR_DQ30

H12

DDR_DQ31

C5

DDR_DQS0P

D5

DDR_DQS0N

C1

DDR_DM0

G9

DDR_DQS1P

H9

DDR_DQS1N

B9

DDR_DM1

C8

DDR_DQS2P

D8

DDR_DQS2N

B6

DDR_DM2

H11

DDR_DQS3P

G11

DDR_DQS3N

C11

DDR_DM3

SA00007KT00 S IC CD580M-R-A1 FCBGA 813P GPU

SEC 5 OF 8

CD580M

DDR_CLK

DDR_CLK_N

DDR_CLKB

DDR_CLKB_N

DDR_A0 DDR_A1

DDR_A2 DDR_A3

DDR_A4 DDR_A5

DDR_A6 DDR_A7

DDR_A8 DDR_A9

DDR_A10 DDR_A11

DDR_A12 DDR_A13

DDR_A14 DDR_A15

DDR_A_B3 DDR_A_B4

DDR_A_B5

DDR_BA0

DDR_BA1 DDR_BA2

DDR_CAS_N DDR_RAS_N

DDR_WE_N

DDR_RESET_N

DDR_CS0_N DDR_CS1_N

DDR_CS_B0_N DDR_CS_B1_N

DDR_CKE0 DDR_CKE1

DDR_CKE_B0 DDR_CKE_B1

DDR_ODT0 DDR_ODT1

DDR_ODT_B0 DDR_ODT_B1

C

Capacitor need close to SOC < 100mil.

1

C1 2.2P_0402_50V

G14 H14

H18 G18

C14 D12

E14 G15

E12 D14

B12 F14

C12 F12

H15 D20

F18 D18

C20 A16

G17 E20

H17

E17

E18 F17

C15 D15

E15

F15

A12 B14

A19 A18

A13 A14

A20 B20

A15 B15

C18 B18

2

DDR0_CLKP

DDR0_CLKN

DDR1_CLKP

DDR1_CLKN

DDR_A0 DDR_A1

DDR_A2

DDR0_A3 DDR0_A4

DDR0_A5 DDR_A6

DDR_A7 DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12 DDR_A13

DDR_A14

DDR_A15

DDR1_A3 DDR1_A4

DDR1_A5

DDR_BA0

DDR_BA1 DDR_BA2

DDR_CAS# DDR_RAS#

DDR_WE#

DDR_RESET#

DDR0_CS0#

DDR0_CS1#

DDR1_CS0#

DDR1_CS1#

DDR0_CKE0

DDR0_CKE1

DDR1_CKE0

DDR1_CKE1

DDR0_ODT0

DDR0_ODT1

DDR1_ODT0

DDR1_ODT1

C2 2.2P_0402_50V

2

DDR_CAS# (6,7) DDR_RAS# (6,7)

DDR_WE# (6,7)

DDR_RESET# (6,7)

DDR0_CS0# (6) DDR0_CS1# (6)

DDR1_CS0# (7) DDR1_CS1# (7)

DDR0_CKE0 (6) DDR0_CKE1 (6)

DDR1_CKE0 (7) DDR1_CKE1 (7)

DDR0_ODT0 (6) DDR0_ODT1 (6)

DDR1_ODT0 (7) DDR1_ODT1 (7)

D

DDR_BA0 (6,7)

DDR_BA1 (6,7) DDR_BA2 (6,7)

DDR0_CLKP (6) DDR0_CLKN (6)

DDR1_CLKP (7) DDR1_CLKN (7)

DDR_A[0..2] (6,7)

DDR0_A[5..3] (6)

DDR_A[6..15] (6,7)

DDR1_A[5..3] (7)

E

N

ote:Place at the T-point

DDR0_CLKN

R1

45.3_0402_1%

1

45.3_0402_1%

2

DDR0_CLK_TERM

R2

DDR0_CLKP

1

2

1

C3

0.01U_0402_16V7K

2

DDR1_CLKN

R3

45.3_0402_1%

1

45.3_0402_1%

2

DDR1_CLK_TERM

R4

DDR1_CLKP

1

2

1

C4

0.01U_0402_16V7K

2

1

2

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDR3L (Channel 0)

Z3ENN M/B LA-B551P

E

of

4 42Thursday, June 19, 2014

of

4 42Thursday, June 19, 2014

of

4 42Thursday, June 19, 2014

4

0.1

A

D580M: CH1 MEMORY I/F

C

B

C

D

E

1

C13

4.7U_0402_6.3V6M

+1.05V_RUN_AVDD

1

C14

4.7U_0402_6.3V6M

2

Change R5 to 0.01 ohm, follow nV comment, 12/23

R5

1

0.01_1206_ 1%

1

47P_0402_50V8J

2

C326

1

C342

4.7U_0402_6.3V6M

2

1

2

+1.35V_LP0

2

C347

33P_0402_50V8K

5/04 EMI ADD

Add C347 33P to +1.35V_LP0 for EMI, 05/22

U1F

BGA

DDR_DQ[32..63](7)

E21

B21 G21

A21 G20

D21 F20

C21

B26

C24 A26

A24 E26

D24 E27

A25

B23

G23 A23

H23 C23

F24 A22

E24

C31

C27 C30

A27 C29

D27 A29

A28

H21

H20 F21

C26 D26

B24

E23

D23 F23

B30 B29

B27

C17

D17

DDR_DQ32 DDR_DQ33

DDR_DQ34 DDR_DQ35

DDR_DQ36 DDR_DQ37

DDR_DQ38 DDR_DQ39

DDR_DQ40 DDR_DQ41

DDR_DQ42 DDR_DQ43

DDR_DQ44 DDR_DQ45

DDR_DQ46 DDR_DQ47

DDR_DQ48 DDR_DQ49

DDR_DQ50 DDR_DQ51

DDR_DQ52 DDR_DQ53

DDR_DQ54 DDR_DQ55

DDR_DQ56 DDR_DQ57

DDR_DQ58 DDR_DQ59

DDR_DQ60 DDR_DQ61

DDR_DQ62 DDR_DQ63

DDR_DQS4P DDR_DQS4N

DDR_DM4

DDR_DQS5P

DDR_DQS5N DDR_DM5

DDR_DQS6P DDR_DQS6N

DDR_DM6

DDR_DQS7P

DDR_DQS7N DDR_DM7

DDR_COMP_PU DDR_COMP_PD

1

DDR_DM4

DDR_DM6

DDR_DM5

DDR_DM7

R634_0402_1%

R734_0402_1%

DDR_DQ32

DDR_DQ33

DDR_DQ34

DDR_DQ35

DDR_DQ36 DDR_DQ37

DDR_DQ38

DDR_DQ39

DDR_DQ48

DDR_DQ49

DDR_DQ50

DDR_DQ51 DDR_DQ52

DDR_DQ53 DDR_DQ54

DDR_DQ55

DDR_DQ40 DDR_DQ41

DDR_DQ42 DDR_DQ43

DDR_DQ44

DDR_DQ45

DDR_DQ46 DDR_DQ47

DDR_DQ56

DDR_DQ57 DDR_DQ58

DDR_DQ59

DDR_DQ60

DDR_DQ61

DDR_DQ62

DDR_DQ63

DDR_COMP_PU

DDR_COMP_PD

BYTE 4

BYTE 6

2

BYTE 5

BYTE 7

DDR_DQS4P(7 ) DDR_DQS4N(7)

DDR_DM4(7)

3

+1.35V_LP0_ VDDIO_DDR

DDR_DQS6P(7 )

DDR_DQS6N(7)

DDR_DM6(7)

DDR_DQS5P(7 ) DDR_DQS5N(7)

DDR_DM5(7)

DDR_DQS7P(7 )

DDR_DQS7N(7)

DDR_DM7(7)

DDR_DQS4P

DDR_DQS4N

DDR_DQS6P

DDR_DQS6N

DDR_DQS5P

DDR_DQS5N

DDR_DQS7P

DDR_DQS7N

2

CD580M

SEC 6 OF 8

(1.05V)

AVDD_PLL_APC2C3

VDDIO_DDR_HS

(1.2 - 1.5V)

VDDIO_DDR 10

VDDIO_DDR_MCLK

AVDD_PLL_M

VDDIO_DDR 1

VDDIO_DDR 2 VDDIO_DDR 3

VDDIO_DDR 4 VDDIO_DDR 5

VDDIO_DDR 6 VDDIO_DDR 7

VDDIO_DDR 8 VDDIO_DDR 9

C5

0.1U_0402_1 0V6K

K16

B17

A17

J9 J12

J14 J11

J17 J18

J20 J21

K10 K11

J15

Add C346 33P to +1.35V_LP0_VDDIO_DDR for EMI, 05/22

C346

33P_0402_50V8K

1

C9

0.47U_0402_16V4Z

2

1/18 follow nvidia suggestion for PDN

C7

0.1U_0402_1 0V6K

1

C10

0.47U_0402_16V4Z

2

1

C6

2.2U_0402_6 .3V6M

2

1

C8

2.2U_0402_6 .3V6M

2

+1.35V_LP0_ VDDIO_DDR

1

C11

4.7U_0402_6.3V6M

2

1

2

1

2

1

C12

4.7U_0402_6.3V6M

2

Add C326 4.7uF, follow nV comment, 01/13

1

2

1

2

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDR3L (Channel 1)

Z3ENN M/B LA-B551P

E

of

5 42Thursday, June 19, 201 4

of

5 42Thursday, June 19, 201 4

of

5 42Thursday, June 19, 201 4

4

0.1

1

2

3

4

MEM_0_VREFCA(6)

MEM_0_VREFDQ(6)

+VDDIO_DRAM

1

R12

5.49K_0402_ 1%

2

1

R15

5.49K_0402_ 1%

2

A

2

56Mx16 DDR3 *4==>2048MB

512Mx16 DDR3 *4==>4096MB

DR_DQ[0..31](4)

D

DR_A[0..2](4,7)

D

DR0_A[5..3](4)

D

DR_A[6..15](4,7)

D

M8

H1

N3 P7

P3

N2 P8

P2 R8

R2 T8

R3

L7

R7

N7

T3 T7

M7

M2

N8

M3

J7

K7

K9

K1

L2

J3

K3

L3

F3

C7

E7 D3

G3

B7

T2

2

L8

J1

L1

J9

L9

2

C15

DDR_BA0(4,7)

DDR_BA1(4,7) DDR_BA2(4,7)

DDR0_CLKP(4) DDR0_CLKN(4)

DDR0_CKE0(4)

DDR0_ODT0(4)

DDR0_CS0#(4)

DDR_RAS#(4,7)

DDR_CAS#(4,7) DDR_WE#(4,7)

DDR_DQS0P(4)

DDR_DQS2P(4)

DDR_DM0(4 )

DDR_DM2(4 )

DDR_DQS0N(4)

DDR_DQS2N(4)

DDR_RESET#(4,6,7)

DDR0_ODT1(4,6)

DDR0_CS1#(4,6) DDR0_CKE1(4,6)

1

R13

5.49K_0402_ 1%

2

1

R16

5.49K_0402_ 1%

2

A

1

0.1U_0402_10V6K

C16

2

DDR_A0 DDR_A1

DDR_A2

DDR0_A3

DDR0_A4 DDR0_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9 DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_A14

DDR_A15

DDR_BA0

DDR_BA1

DDR_BA2

DDR0_CLKP

DDR0_CLKN DDR0_CKE0

DDR0_ODT0

DDR0_CS0#

DDR_RAS#

DDR_CAS# DDR_WE#

DDR_DQS0P DDR_DQS2P

DDR_DM0 DDR_DM2

DDR_DQS0N DDR_DQS2N

DDR_RESET#

1

R8

240_0402_1 %

DDR0_ODT1

DDR0_CS1#

DDR0_CKE1

1

R10

240_0402_1 %

MEM_0_VREFCA (6)

MEM_0_VREFDQ (6)

U

19

VREFCA

VREFDQ

A0 A1

A2

A3 A4

A5 A6

A7 A8

A9 A10/AP

A11

A12

A13 A14

A15/BA3

BA0

BA1

BA2

CK CK

CKE/CKE0

ODT/ODT0

CS/CS0

RAS

CAS

WE

DQSL

DQSU

DML DMU

DQSL

DQSU

RESET

ZQ/ZQ0

NC/ODT1

NC/CS1

NC/CE1

NCZQ1

96-BALL

SDRAM DDR3

H5TC4G63MFR-PBA 9 6P

SA00005AV50

+VDDIO_DRAM

@

5/04 EMI ADD

B

DQL0

DQL1 DQL2

DQL3 DQL4

DQL5 DQL6

DQL7

DQU0

DQU1 DQU2

DQU3 DQU4

DQU5 DQU6

DQU7

VDD VDD

VDD

VDD VDD

VDDQ VDDQ

VDDQ

VSS

VSS VSS

VSS

VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ

B

C340

47P_0402_50V8J

C

19

U

19

E3

F7 F2

F8 H3

H8 G2

H7

D7

C3 C8

C2 A7

A2 B8

A3

B2 D9

G7

K2

K8

N1 N9

R1 R9

A1 A8

C1 C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8 M1

M9 P1

P9 T1

T9

B1 B9

D1

D8 E2

E8

F9

G1

G9

1

2

YN2G@

H

S

A00005AV50

S

IC D3 256M16/1600 H5TC4G6 3AFR-PBA ABO!

H

YN4G@

S

A00006WZ40

S

IC D3 512M16/1600 H5TC8G6 3AMR-PBA ABO!

DDR_DQ0

DDR_DQ1

DDR_DQ2

DDR_DQ3

DDR_DQ4

DDR_DQ5

DDR_DQ6

DDR_DQ7

DDR_DQ16

DDR_DQ17

DDR_DQ18

DDR_DQ19 DDR_DQ20

DDR_DQ21 DDR_DQ22

DDR_DQ23

+VDDIO_DRAM

MEM_0_VREFCA( 6)

MEM_0_VREFDQ(6)

205mA 205mA

0.1U_0402_10V6K

4.7U_0603_6.3V6M

C19

C29

4.7U_0603_6.3V6M

1

2

4.7U_0603_6.3V6M

1

2

1

C341

47P_0402_50V8J

2

0.1U_0402_10V6K

1

C20

C30

1/18 follow nvidia suggestion for PDN

C21

2

+VDDIO_DRAM

0.1U_0402_10V6K

1

C31

2

C331

+VDDIO_DRAM

820mA

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_10V6K

1

2

0.47U_0402_16V4Z

1

C32

2

0.47U_0402_16V4Z

1

2

0.1U_0402_10V6K

1

C22

2

0.1U_0402_10V6K

1

C33

2

R14

1

2

0.01_0805_ 1%

0612 modified.

C23

0.1U_0402_10V6K

1

2

+1.35V_LP0

2013/11/20 2014/11/09

C

20

U

20

1

0.1U_0402_10V6K

C18

2

0.1U_0402_10V6K

1

2

DDR_DQS1P(4 )

DDR_DQS3P(4 )

DDR_DM1(4)

DDR_DM3(4)

DDR_DQS1N(4)

DDR_DQS3N(4)

DDR_RESET#(4,6,7)

DDR0_ODT1(4,6) DDR0_CS1#(4,6)

DDR0_CKE1(4,6)

Compal Secret Data

YN2G@

H

S

A00005AV50

S

IC D3 256M16/1600 H5TC4G6 3AFR-PBA ABO!

H

YN4G@

S

A00006WZ40

S

IC D3 512M16/1600 H5TC8G6 3AMR-PBA ABO!

1

C17

2

Deciphered Date

0.1U_0402_10V6K

DDR0_A3

DDR0_A4 DDR0_A5

DDR_BA0

DDR_BA1

DDR_BA2

DDR0_CLKP DDR0_CLKN

DDR0_CKE0

DDR0_ODT0 DDR0_CS0#

DDR_RAS# DDR_CAS#

DDR_WE#

DDR_DQS1P DDR_DQS3P

DDR_DM1 DDR_DM3

DDR_DQS1N DDR_DQS3N

DDR_RESET#

1

R9

240_0402_1 %

DDR0_ODT1

DDR0_CS1#

DDR0_CKE1

1

R11

240_0402_1 %

DDR_A0 DDR_A1

DDR_A2

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12 DDR_A13

DDR_A14

DDR_A15

2

D

U

20

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC4G63MFR-PBA 9 6P

SA00005AV50

@

D

DQL0

DQL1 DQL2

DQL3 DQL4

DQL5 DQL6

DQL7

DQU0

DQU1 DQU2

DQU3 DQU4

DQU5 DQU6

DQU7

VDD VDD

VDD

VDD VDD

VDDQ VDDQ

VDDQ

VSS

VSS VSS

VSS

VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ

E

19

U

20

E3

DDR_DQ8

F7

DDR_DQ9

F2

DDR_DQ10

F8

DDR_DQ11

H3

DDR_DQ12

H8

DDR_DQ13

G2

DDR_DQ14

H7

DDR_DQ15

D7

DDR_DQ24

C3

DDR_DQ25

C8

DDR_DQ26

C2

DDR_DQ27

A7

DDR_DQ28

A2

DDR_DQ29

B8

DDR_DQ30

A3

DDR_DQ31

B2 D9

G7

K2

K8

N1 N9

R1 R9

A1 A8

C1 C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8 M1

M9 P1

P9 T1

T9

B1 B9

D1

D8 E2

E8

F9

G1

G9

Title

Size Doc ument Number Rev

Custom

Date: Sheet

C24

C34

Compal Electronics, Inc.

Z3ENN M/B LA-B551P

IN2G@

K

S

A00007X410

S

IC D3 256M16/1600 D25 16EC4BXGGB ABO!

K

IN2G@

S

A00007X410

S

IC D3 256M16/1600 D25 16EC4BXGGB ABO!

+VDDIO_DRAM

4.7U_0603_6.3V6M

0.1U_0402_10V6K

1

2

1

2

0.1U_0402_10V6K

1

C25

2

4.7U_0603_6.3V6M

1

C35

2

DDR3L CH0

1

C26

2

+VDDIO_DRAM

0.1U_0402_10V6K

1

C36

2

E

0.1U_0402_10V6K

1

C27

2

0.1U_0402_10V6K

1

C37

2

6 42Thursday, June 19, 201 4

C38

of

0.1U_0402_10V6K

C28

1

2

1

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

3

4

0.1

1

2

3

+VDDIO_DRAM

4

MEM_1_VREFCA(7) MEM_1_VREFDQ(7)

DDR1_ODT1(4,7)

DDR1_CS1#(4,7) DDR1_CKE1(4,7)

1

R21

5.49K_0402_1%

2

1

R23

5.49K_0402_1%

2

A

2

56Mx16 DDR3 *4==>2048MB

512Mx16 DDR3 *4==>4096MB

D

DR_DQ[32..63](5)

D

DR_A[0..2](4,6)

DR1_A[5..3](4)

D

DDR_RESET#(4,6,7)

C39

DDR_BA0(4,6) DDR_BA1(4,6)

DDR_BA2(4,6)

DDR1_CLKP(4)

DDR1_CLKN(4) DDR1_CKE0(4)

DDR_DQS6P(5)

DDR_DQS4P(5)

DDR_DM6(5)

DDR_DM4(5)

DDR_DQS6N(5)

DDR_DQS4N(5)

1

C40

0

0 .1U_0402_10V6K

.1U_0402_10V6K

2

DDR1_ODT0(4) DDR1_CS0#(4)

DDR_RAS#(4,6) DDR_CAS#(4,6)

DDR_WE#(4,6)

1

R22

5.49K_0402_1%

2

1

R24

5.49K_0402_1%

2

A

DR_A[6..15](4,6)

1

0.1U_0402_10V6K

2

DDR_A0

DDR_A1

DDR_A2

DDR1_A3 DDR1_A4

DDR1_A5

DDR_A6

DDR_A7 DDR_A8

DDR_A9

DDR_A10 DDR_A11

DDR_A12 DDR_A13

DDR_A14 DDR_A15

DDR_BA0 DDR_BA1

DDR_BA2

DDR1_CLKP

DDR1_CLKN DDR1_CKE0

DDR1_ODT0 DDR1_CS0#

DDR_RAS#

DDR_CAS# DDR_WE#

DDR_DQS6P DDR_DQS4P

DDR_DM6 DDR_DM4

DDR_DQS6N DDR_DQS4N

DDR_RESET#

1

2

R17

240_0402_1%

DDR1_ODT1

DDR1_CS1#

DDR1_CKE1

1

2

R19

240_0402_1%

MEM_1_VREFCA (7)

MEM_1_VREFDQ (7)

U

22

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC4G63MFR-PBA 96P

SA00005AV50

@

DQL0

DQL1 DQL2

DQL3 DQL4

DQL5 DQL6

DQL7

DQU0

DQU1 DQU2

DQU3 DQU4

DQU5 DQU6

DQU7

VDD VDD

VDD

VDD VDD

VDDQ VDDQ

VDDQ

VSS

VSS VSS

VSS

VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ

+VDDIO_DRAM

0.1U_0402_10V6K

1

C50

2

+VDDIO_DRAM

0.1U_0402_10V6K

1

C60

2

E

1

2

0.1U_0402_10V6K

1

C51

2

0.1U_0402_10V6K

1

C61

2

7 42Thursday, June 19, 2014

E

1

C52

2

0.1U_0402_10V6K

1

C62

2

3

4

0.1

of

B

U

22

U

22

E3

DDR_DQ48

F7

DDR_DQ49

F2

DDR_DQ50

F8

DDR_DQ51

H3

DDR_DQ52

H8

DDR_DQ53

G2

DDR_DQ54

H7

DDR_DQ55

D7

DDR_DQ32

C3

DDR_DQ33

C8

DDR_DQ34

C2

DDR_DQ35

A7

DDR_DQ36

A2

DDR_DQ37

B8

DDR_DQ38

A3

DDR_DQ39

205mA 205mA

B2 D9

G7

K2

K8

C43

N1 N9

R1 R9

A1 A8

C1 C9

D2

E9

C53

F1

H2

H9

A9

B3

E1

G8

J2

J8 M1

M9 P1

P9 T1

T9

B1 B9

D1

D8 E2

E8

F9

G1

G9

B

YN2G@

H

S

A00005AV50

S

IC D3 256M16/1600 H5TC4G63AFR-PBA ABO!

H

YN4G@

A00006WZ40

S

IC D3 512M16/1600 H5TC8G63AMR-PBA ABO!

+VDDIO_DRAM

0.1U_0402_10V6K

4.7U_0603_6.3V6M

1

C44

2

4.7U_0603_6.3V6M

1

C54

2

1

C45

2

+VDDIO_DRAM

0.1U_0402_10V6K

1

C55

2

0.1U_0402_10V6K

C46

0.1U_0402_10V6K

C56

EMI, close to C50/C57/C28

+VDDIO_DRAM

1

C343

2

Add C343/C344/C345 33P to +VDDIO_DRAM for EMI, 05/22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

33P_0402_50V8K

C344

2

C

U

21

U

21

MEM_1_VREFCA(7) MEM_1_VREFDQ(7)

0.1U_0402_10V6K

C47

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

1

2

1

33P_0402_50V8K

2

C

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

1

C57

2

33P_0402_50V8K

C345

2013/11/20 2014/11/09

1

0.1U_0402_10V6K

C42

C41

2

DDR_DQS7P(5) DDR_DQS5P(5)

DDR_DM7(5) DDR_DM5(5)

DDR_DQS7N(5) DDR_DQS5N(5)

DDR_RESET#(4,6,7)

DDR1_ODT1(4,7)

DDR1_CS1#(4,7) DDR1_CKE1(4,7)

Compal Secret Data

Deciphered Date

YN2G@

H

S

A00005AV50

S

IC D3 256M16/1600 H5TC4G63AFR-PBA ABO!

H

YN4G@

A00006WZ40

S

IC D3 512M16/1600 H5TC8G63AMR-PBA ABO!

0.1U_0402_10V6K

DDR1_A3 DDR1_A4

DDR1_A5

DDR_DQS7P DDR_DQS5P

DDR_DM7 DDR_DM5

DDR_DQS7N DDR_DQS5N

DDR_RESET#

1

R18

240_0402_1%

DDR1_ODT1

DDR1_CS1#

DDR1_CKE1

1

R20

240_0402_1%

DDR_A0

DDR_A1

DDR_A2

DDR_A6

DDR_A7

DDR_A8

DDR_A9 DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_A14 DDR_A15

DDR_BA0

DDR_BA1

DDR_BA2

DDR1_CLKP

DDR1_CLKN

DDR1_CKE0

DDR1_ODT0

DDR1_CS0#

DDR_RAS#

DDR_CAS#

DDR_WE#

2

1

2

D

U

21

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

H5TC4G63MFR-PBA 96P

SA00005AV50

@

D

U

22

U

21

E3

DQL0

DQL1 DQL2

DQL3 DQL4

DQL5 DQL6

DQL7

DQU0

DQU1 DQU2

DQU3 DQU4

DQU5 DQU6

DQU7

VDD VDD

VDD

VDD VDD

VDDQ VDDQ

VDDQ

VSS

VSS VSS

VSS

VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ

Title

Size Doc ument Number Rev

Custom

Date: Sheet

DDR_DQ56

F7

DDR_DQ57

F2

DDR_DQ58

F8

DDR_DQ59

H3

DDR_DQ60

H8

DDR_DQ61

G2

DDR_DQ62

H7

DDR_DQ63

D7

DDR_DQ40

C3

DDR_DQ41

C8

DDR_DQ42

C2

DDR_DQ43

A7

DDR_DQ44

A2

DDR_DQ45

B8

DDR_DQ46

A3

DDR_DQ47

B2 D9

G7

K2

K8

N1 N9

R1 R9

A1 A8

C1 C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8 M1

M9 P1

P9 T1

T9

B1 B9

D1

D8 E2

E8

F9

G1

G9

Compal Electronics, Inc.

Z3ENN M/B LA-B551P

IN2G@

K

S

A00007X410

S

IC D3 256M16/1600 D2516EC4BXGGB ABO!

K

IN2G@

A00007X410

S

IC D3 256M16/1600 D2516EC4BXGGB ABO!

4.7U_0603_6.3V6M

1

C49

C48

2

4.7U_0603_6.3V6M

1

C58

C59

2

DDR3L CH1

1

0.1U_0402_10V6K

SDMMC3_CLK(27)

1

2

+VDDIO_SDMMC3

0.1U_0402_10V6K

+1.8V_VDDIO_CPU

+VDDIO_SDMMC3

+1.8V_VDDIO_CPU

2

C327 22P_0402_50V8 J

3

4

@

Add C327@ 22P, follow RF request, 01/14

A

1

C70

4.7U_0402_6.3V6M

2

1

C72

2

1

C75

2

SDMMC3_CLK_LB_IN_R

+

1.8V_VDDIO_CPU

1

C63

0.1U_0402_10V6K

2

KBC_SPI_MOSI(29)

KBC_SPI_MISO(29)

KBC_SPI_SCK(29) KBC_SPI_CS(29)

EN_VDD_BL(15)

1

C71

2

SDMMC1_DAT[3..0](20)

SDMMC1_CLK(20)

SDMMC1_CMD(20 )

R29 33.2_0402_1%

1

R31 33.2_0402_1%

1

R43 49.9_0402_1%

R44 49.9_0402_1%

2

1

2

1

C73 4.7U_0603 _6.3V6M

2

R367

0_0402_5%

R34 33.2_0402_1%

R35 33.2_0402_1%

C76

1

SDMMC3_DAT[3..0](27)

2

SDMMC3_CMD(27 )

SDMMC3_CD(24,27)

1

2

1

2

Change R34/R35 from 49.9 to 33.2ohm, follow nV comment, 04/08

4.7U_0603_6.3V6M

1

2

SDMMC4_DAT[7..0](25)

SDMMC4_CLK(25)

SDMMC4_CMD(25 )

2

R120 0_0402_5%

1

2

R119 0_0402_5%

1

2

1

C66

4.7U_0402_6.3V6M

2

Delete 3G interface, 12/19

SDMMC1_COMP_PU

SDMMC1_COMP_PD

SDMMC3_CLK_LB_OUT

SDMMC3_CLK_LB_IN

SDMMC3_COMP_PU SDMMC3_COMP_PD

SDMMC4_COMP_PU SDMMC4_COMP_PD

SDMMC1_DAT0 SDMMC1_DAT1

SDMMC1_DAT2 SDMMC1_DAT3

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2

SDMMC3_DAT3

SDMMC4_DAT0

SDMMC4_DAT1 SDMMC4_DAT2 SDMMC4_DAT3

SDMMC4_DAT4 SDMMC4_DAT5 SDMMC4_DAT6

SDMMC4_DAT7

2

R75

R75 0_0402_5%

0_0402_5%

@

1

B

D580M_SDMMC_ULPI_JTAG

C

1A

U

BGA

AC14

AF15

AH15 AD17

AJ15

AJ18 AH17 AK18

AL17

AK17

AL18

AG15

AL16

AF17

AE17 AE15

AJ17

AG17 AD15

P9

L2 L3 L1

J8 L7 L8

L5

J7 L6

K1 L4

E1

H2 H1 F1

G1 F5 F2

V24

F4 F3

E2 E5

F31

F29 F30 E28

H31 D31 E30

E29 F28 G31

E31

H30 H29

BGA

(1.8V-3.3V)

VDDIO_BB

ULPI_DATA0

ULPI_DATA1 ULPI_DATA2 ULPI_DATA3

ULPI_DATA4 ULPI_DATA5 ULPI_DATA6

ULPI_DATA7

ULPI_CLK

ULPI_DIR

ULPI_NXT ULPI_STP

DAP3_DIN

DAP3_DOUT DAP3_FS

DAP3_SCLK

GPIO_PV0 GPIO_PV1

(1.8V-3.3V)

VDDIO_SDMMC1

SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2

SDMMC1_DAT3

SDMMC1_CLK

SDMMC1_CMD

SDMMC1_WP_N

SDMMC1_COMP_PU SDMMC1_COMP_PD

CLK2_OUT CLK2_REQ

(1.8V-3.3V)

VDDIO_SDMMC3

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2

SDMMC3_DAT3

SDMMC3_CLK

SDMMC3_CMD

SDMMC3_CD_N SDMMC3_CLK_LB_OUT SDMMC3_CLK_LB_IN

SDMMC3_COMP_PU SDMMC3_COMP_PD

(1.2V-1.8V)

VDDIO_SDMMC4

SDMMC4_DAT0 SDMMC4_DAT1 SDMMC4_DAT2

SDMMC4_DAT3 SDMMC4_DAT4 SDMMC4_DAT5

SDMMC4_DAT6 SDMMC4_DAT7

SDMMC4_CLK

SDMMC4_CMD

SDMMC4_COMP_PU SDMMC4_COMP_PD

SDMMC3_CLK_LB_OUT

CD580M

SEC 1 OF 8

SDMMC3_CLK_LB_IN

(1.8V-3.3V)

VDDIO_SYS

VDDIO_SYS_2

(0.9-1.1V)

PWR_I2C_SCL

PWR_I2C_SDA

CORE_PWR_REQ

CPU_PWR_REQ

CLK_32K_IN

CLK_32K_OUT

PWR_INT_N

SYS_RESET_N

RESET_OUT_N

THERM_DP THERM_DN

(1.8V)

JTAG_RTCK

JTAG_TRST_N

TEST_MODE_EN

(1.8V - 3.3V)

KB_COL0

KB_COL1 KB_COL2 KB_COL3

KB_COL4 KB_COL5 KB_COL6

KB_COL7

KB_ROW0 KB_ROW1

KB_ROW2 KB_ROW3 KB_ROW4

KB_ROW5 KB_ROW6 KB_ROW7

KB_ROW8 KB_ROW9

KB_ROW10

KB_ROW11 KB_ROW12 KB_ROW13

KB_ROW14 KB_ROW15 KB_ROW16

KB_ROW17

VDD_RTC

OWR

VPP_FUSE

JTAG_TCK

JTAG_TDI

JTAG_TDO JTAG_TMS

AVDD_OSC

XTAL_IN

XTAL_OUT

V23 L10

AD30

AC28 AD28 AD31

AF28 AA27 AD29

AA25

W31 Y26

AF30 AC31 Y29

Y31 AB31 Y30

AA29 AA28 AA31

V28 Y27 AF29

AC30 Y25 AA26

AC29

AB12

J4

J3

Y28 V25

H3

J6

V30

AA30

Y24

AA7

U28 U29

R10

J2 H6 H5

J1 J5 H4

H7

D1 E3

E4

Delete 3G interface, 12/19Delete 3G interface, 12/19

JTAG_TCK_R

JTAG_TMS_R JTAG_TRST#_R

TEST_MODE_EN

C

LID_CLOSED#

XTAL_IN

XTAL_OUT

ONKEY# (26) HOLD_R (29) SERVO_DBG_GPIO (24)

BD_ID_STRAP0 (26)

SDMMC3_WP# (27)

GOOG_DEV_MODE (24) GOOG_RECOVERY_MODE (24)

EN_VDD_SD ( 27) AP_WP# (18)

1

2

D1RB751V-40_SOD323-2

BR_UART1_TXD (24)

BR_UART1_RXD (24)

IGPU_PWRGD (36)

BD_ID_STRAP1 ( 26)

CORE_PWR_REQ (24,29,33 ,36)

CPU_PWR_REQ (24,33)

CLK_32KHZ_PMU (36)

CPU_OC_INT (36)

PMU_INT_L (36)

SYS_RESET# (21,24,25,3 0,36)

THERMD_P (21)

THERMD_N (21)

JTAG_RTCK (24)

JTAG_TDI (2 4)

JTAG_TDO (24)

1

2M_0402_5%

2

1

R45

4

Change C78/C79 to 8.2P, follow vendor suggestion, 04/09

R37 0_0402_5%

R38 10K_0402_5%

R39 0_0402_5%

R40 0_0402_5%@

R41 100K_0402_5%

R42 0_0402_5%

C78

8.2P_0402_50V8D

1

2

Y1

Y1 12MHZ_7PF_FL120 0105

12MHZ_7PF_FL120 0105

3

C79

1

2

8.2P_0402_50V8D

1

2

1

LID_OPEN (24,29)

MIC_PRSNT# (23)

2

R28 100K_0402_5%@

R30 100K_0402_5%@

2

1

2

D

1

C64

0.1U_0402_10V6K

2

1

C67

0.1U_0402_10V6K

2

1

+1.8V_VDDIO_CPU

C65

C68

1

R32

R32 100K_0402_5%@

100K_0402_5%@

2

R33 0_0402_5%@

JTAG_TCK (24,29 )

JTAG_TMS (24,29) JTAG_TRST# (24)

4.7U_0603_6.3V6M

1

2

1

4.7U_0603_6.3V6M

2

+1.8V_VDDIO_CPU

R26

1K_0402_5%

1

2

+

1.8V_VDDIO_CPU

1

R27

R27 1K_0402_5%

1K_0402_5%

2

1

C74

0.1U_0402_10V6K

2

1

C77

4.7U_0402_6.3V6M

2

+1.00V_LP0_VDD_RTC

1

C69

0.1U_0402_10V6K

2

PWR_I2C_SCL (36)

PWR_I2C_SDA (36)

PMIC_WARM_RESET# (10,29,30)

+1.8V_RUN_VPP_FUSE

2

R36

R36 10K_0402_5%

10K_0402_5%

1

+1.8V_VDDIO_CPU

2

L1BLM15AX300SN1D_2P

E

1

2

3

4

1.8V/ PU /ext PH 10K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SDMMC_ULPI_JTAG

Z3ENN M/B LA-B551P

E

0.1

of

8 42Thursday, June 19, 2014

of

8 42Thursday, June 19, 2014

of

8 42Thursday, June 19, 2014

1

2

3

+1.05V_RUN_AVDD_HDMI_PLL

SI2305CDS-T1-GE3_SOT23-3

Change Q2 P/N to SB923050030, 01/07

4

A

+

1.8V_VDDIO

+1.05V_RUN

+3.3V_RUN

+3.3V_LP0

4.7U_0402_6.3V6M

Remove C96/C97 and put one test point, 12/23

+

1.8V_VDDIO_CPU

R

358

1

2

0_0805_5%

R

410

1

2

0_0805_5%

0612 modified.

+1.05V_RUN_CPU

R359

1

2

0_0805_5%

R411

1

2

0_0805_5%

0612 modified.

+3.3V_RUN_CPU

R360

1

2

0_0603_5%

+3.3V_LP0_CPU

R361

1

2

0.01_0603_1%

0612 modified.

+1.8V_VDDIO_CPU

1

C90

0.1U_0402_10V6K

2

TPM_I2C_SCL(21)

TPM_I2C_SDA(21)

R52 change to @, follow nV comment, 12/25

P-MOSFET TO POWER GATE AVDD_HDMI_PLL

1

D

Q2

A

2

G

2

1

D

Q4

@

DMG6968U-7_SOT23-3

S

3

S

1

R57

R57 1M_0402_5%

1M_0402_5%

2

R61 0_0402_5%@

2

G

SB00000Q800

VGTH(MAX)=0.9V

R61 0_0402_5%@

1

R55 0_0402_5%@

SB923050030

Change Q4@ to VGTH=0.9V, 01/08

1

C91

2

T15 PAD @

Delete 3G interface, 12/19

1K_0402_1%

+1.05V_RUN_CPU

1

2

B

A

K14

A

L13

A

L14

K9

A

L9

A

E9 D9

A

E11

A

D11

AK8

AL8

AJ9

AH9

AJ8

AH8

AF9

AG9

AK11

AL11

AD14 AE14

AL15

AK15

AG14 AF14

AJ14

AH14

AH12

AJ12 AE12 AD12

AL12 AK12 AF12 AG12

AJ11 AH11

AL10 AF11

AG11

AC11

AJ6 AL7

AK5 AK6 AH6 AH5

AL6 AJ5

AF8

AG8

AL5

AC15

AF18 AE18

AH18

AG18 AD18

HSIC_REXT

2

R52

@

1

R60 0_0402_5%

2

EN_VDD_HDMI (10,16,9)

B

1B

U

BGA

(1.2V)

VDD_DSI_CSI 1

A

VDD_DSI_CSI 2

A A

VDD_DSI_CSI 3

SI_A_D0_N

C

SI_A_D0_P

C

SI_A_D1_N SI_A_D1_P

C

SI_A_CLK_N

C

SI_A_CLK_P

CSI_B_D0_N

CSI_B_D0_P CSI_B_D1_N CSI_B_D1_P

CSI_E_CLK_N

CSI_E_CLK_P CSI_E_D0_N

CSI_E_D0_P

DSI_A_D0_N DSI_A_D0_P

DSI_A_D1_N DSI_A_D1_P DSI_A_D2_N

DSI_A_D2_P DSI_A_D3_N DSI_A_D3_P

DSI_A_CLK_N

DSI_A_CLK_P

DSI_B_D0_N

DSI_B_D0_P DSI_B_D1_N DSI_B_D1_P

DSI_B_D2_N DSI_B_D2_P DSI_B_D3_N

DSI_B_D3_P

DSI_B_CLK_N

DSI_B_CLK_P

CSI_DSI_TEST_OUT CSI_DSI_RUP CSI_DSI_RDN

(1.8V - 3.3V)

VDDIO_CAM

GPIO_PCC1 GPIO_PCC2

GPIO_PBB0 GPIO_PBB3 GPIO_PBB4

GPIO_PBB5 GPIO_PBB6 GPIO_PBB7

CAM_I2C_SCL CAM_I2C_SDA

CAM_MCLK

(1.2V)

VDDIO_HSIC

HSIC1_DATA HSIC_STROBE

HSIC_REXT

HSIC2_DATA HSIC2_STROBE

+3.3V_AVDD_HDMI

GPIO_PH7 (10)

C

D580M

S

EC 2 OF 8

1

R56

R56 1M_0402_5%

1M_0402_5%

2

(3.3V)

A

VDD_HDMI

A

VDD_HDMI

A

(1.05V.. 1.2V?)

VDD_HDMI_PLL

A

HDMI_TXD0N

HDMI_TXD1N

HDMI_TXD2N

HDMI_PROBE

(1.05V)

AVDD_LVDS0_IO

(1.05V)

AVDD_PLL_UD2DPD

(1.8V)

AVDD_LVDS0_PLL

LVDS0_TXD0N

LVDS0_TXD0P

LVDS0_TXD1N

LVDS0_TXD1P

LVDS0_TXD2N

LVDS0_TXD2P

LVDS0_TXD3N

LVDS0_TXD3P

LVDS0_TXD4N

LVDS0_TXD4P

LVDS0_PROBE

DP_AUX_CH0_P

DP_AUX_CH0_N

(1.8V)

AVDD_PLL_UTMIP

(3.3V)

USB_VBUS_EN0 USB_VBUS_EN1

AO3419L_SOT23-3

SB000006R10

S

3

Q1

HDMI_TXD0P

HDMI_TXD1P

HDMI_TXD2P

HDMI_TXCN

HDMI_TXCP

HDMI_CEC

HDMI_INT

HDMI_RSET

DDC_SCL

DDC_SDA

DP_HPD

LVDS0_RSET

AVDD_USB

USB0_DN

USB0_DP

USB1_DN

USB1_DP

USB2_DN

USB2_DP

USB0_VBUS

USB0_ID

USB_REXT

D

G

A

AD5

AD6 AD4 AD3

AD2 AD1 AF5 AF6

AD7 AC3 AF2 AE1

AC7 AC8

AJ1

AL4

AF1

AJ2 AJ3 AG3

AG4 AG5 AG6 AG1

AG2 AF3 AF4

AC2

AK3 AL3

AC6 AC5

AB15

AC12

AH20 AJ20

AF20 AG20 AE20 AD20

AB1 AC1

AL20 AK20

AL19

1

P-MOSFET TO PREVENT BACKDRIVE ON AVDD_HDMI

2

1

D

Q3

2

G

DMG6968U-7_SOT23-3

S

3

SB00000Q800

VGTH(MAX)=0.9V

Change Q3 to VGTH=0.9V, 01/08

C

3.3V_AVDD_HDMI

+

1

C

80

0.1U_0402_10V6K

A9

A10

H1

HDMI_RSET

DDC_SCL DDC_SDA

LVDS_RSET

USB0_VBUS

USB0_ID USB_REXT

+3.3V_RUN_CPU

R58 0_0402_5%

1

R59 0_0402_5%@

1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

C

82

0.1U_0402_10V6K

2

1

R46 1K_0402_1%

1

R47 33_0402_5%

R48 33_0402_5%

1

C86

0.1U_0402_10V6K

2

R49 1K_0402_1%

1

+1.8V_RUN_AVDD_PLL_UTMIP

USB0_D- (17) USB0_D+ (1 7) CAM_USB1_D- (14)

CAM_USB1_D+ (14) USB2_D- (17) USB2_D+ (1 7)

USB_VBUS_EN0 (1 7)

USB_VBUS_EN1 (1 7)

PAD@

R54 1K_0402_1%

1

2

Issued Date

C

1

C

81

4.7U_0603_6.3V6M

2

1

C

83

4.7U_0402_6.3V6M

2

HDMI_TXD_0N (16)

HDMI_TXD_0P (16) HDMI_TXD_1N (16) HDMI_TXD_1P (16)

HDMI_TXD_2N (16) HDMI_TXD_2P (16) HDMI_TXC_N (16)

HDMI_TXC_P (1 6)

HDMI_CEC (16)

2

1

C87

2.2U_0402_6.3V6M

2

T3

2

+1.05V_RUN_CPU

EN_VDD_HDMI (10,16,9)

2013/11/20 2014/11/09

HDMI_INT (16,24)

HDMI_DDC_SCL (16 )

HDMI_DDC_SDA (16)

DP_TXD1N (14)

DP_TXD1P (14)

DP_TXD0N (14)

DP_TXD0P (14)

Add Net DP_TXD1N/DP_TXD1P for FHD, 02/26

EDP_HPD (14)

DP_AUXP (14) DP_AUXN (1 4)

1

C92

0.1U_0402_10V6K

2

1

C94

0.1U_0402_10V6K

2

R53 0_0402_5%

1.05V_RUN_AVDD_HDMI_PLL

+

+AVDD_LVDS0_PLL

0.1U_0402_10V6K

1

C93

4.7U_0603_6.3V6M

2

1

C95

4.7U_0603_6.3V6M

2

1

2

Compal Secret Data

Deciphered Date

D

1

C84

0.1U_0402_10V6K

2

1

C88

4.7U_0603_6.3V6M

2

+1.8V_VDDIO_LP0_OFF

2

L4BLM15AX300SN1D_2P

+3.3V_LP0_CPU

D

C

D580M_CSI_DSI_HDMI_USB

+1.05V_RUN_AVDD

1

C85

2.2U_0402_6.3V6M

2

1

C89

2

1

Title

Size Document Number Rev

Custom

Date: Sheet

+3.3V_RUN_CPU

2

L2BLM15AX300SN1D_2P

+1.8V_VDDIO_LP0_OFF

@

L3BLM15AX300SN1D_2P

2

Compal Electronics, Inc.

CSI_DSI_HDMI_USB

Z3ENN M/B LA-B551P

E

1

2

3

4

0.1

of

9 42Thursday, June 19, 2014

of

9 42Thursday, June 19, 2014

of

E

9 42Thursday, June 19, 2014

E

GEN2_I2C_SCL_3.3V_TP (27)

GEN2_I2C_SDA_3.3V_TP (27)

GEN2_I2C_SCL_3.3V_TS (28)

Change Q69/Q70 P/N to SB503010010, 05/28

GEN2_I2C_SDA_3.3V_TS (28)

Add R378 and I2C TP sch for reserve, 02/26 Add I2C TS sch for reserve, 03/07

of

10 42Thursday, June 19, 2014

of

10 42Thursday, June 19, 2014

of

E

10 42Thursday, June 19, 2014

1

2

3

4

0.1

+3.3V_LP0_CPU

1

R378

0_0402_5%

2

1

R67

R67 1K_0402_5%

1K_0402_5%

2

Deciphered Date

D

+1.8V_VDDIO_CPU

PMIC_WARM_RESET# (29,30,8)

HDSET_SW_SOC# (23)

AC_OK (31,36)

+1.8V_VDDIO_CPU

1

R377

@

0_0402_5%

2

GEN2_I2C_SCL_3.3V

GEN2_I2C_SDA_3.3V

+5V_VDD_TS

1

R404

10K_0402_5%TS@

2

GEN2_I2C_SCL_3.3V

+5V_VDD_TS

1

R406

R406 10K_0402_5%TS@

10K_0402_5%TS@

2

GEN2_I2C_SDA_3.3V

D

GEN2_I2C_PWR_TP

DMG6968U-7_SOT23-3

SB00000Q800

GEN2_I2C_PWR_TP

DMG6968U-7_SOT23-3

SB00000Q800

GEN2_I2C_PWR_TS_SCL

GEN2_I2C_PWR_TS_SDA

+3.3V_LP0

1

R379

10K_0402_5%@

G

2

3

S

Q67

10K_0402_5%@

2

1

D

@

+3.3V_LP0

1

R380

R380 10K_0402_5%@

G

2

3

S

Q68

10K_0402_5%@

2

1

D

@

+3.3V_LP0

1

R399

R399 10K_0402_5%@

10K_0402_5%@

2

G

1

3

D

S

D

S

TS@

Q69

Q69 FDV301N-NL_SOT23-3

FDV301N-NL_SOT23-3

SB503010010

+3.3V_LP0

1

R401

R401 10K_0402_5%@

10K_0402_5%@

2

G

1

3

D

S

D

S

TS@

Q70

FDV301N-NL_SOT23-3

SB503010010

Compal Electronics, Inc.

Title

UART_GMI_DAP_SPI

Size Document Number Rev

C

Z3ENN M/B LA-B551P

Date: Sheet

C

1

C

102

C

103

4.7U_0402_6.3V6M

2

SET E_OD PAD = 1 WHEN PU VALUE DIFFERS FROM VDD SOURCE

Delete 3G interface, 12/19

3.3V_LP0_CPU

+

1

2

1.8V_VDDIO_CPU

+

SHARE DECOUPLING WITH VDDIO_UA RT

KBC_IRQ# (29)

BOOT_SEL0 (26) BOOT_SEL1 (26)

BOOT_SEL2 (26) BOOT_SEL3 (26)

RAM_CODE0 (26) SPI4_SCK (18,26) SPI4_MOSI (18,26)

SPI4_MISO (18,26)

LCD_BL_PWM (15) LCD_BL_EN (15)

CODEC_IRQ# (22)

TPM_DAVINT# (21) GPIO_PH7 (9)

GPIO_PI0 (26)

AP_FORCE_RECOVERY# (26)

SPI4_CS0# (18)

TEMP_ALERT# (21)

ARM_JTAG0 (26)

TS_SHDN# (28)

TS_IRQ# (28)

TS_RESET# (28) ARM_JTAG1 (26)

BD_ID_STRAP2 (26)

BD_ID_STRAP3 (26)

WF_EN (20)

TOUCH_IRQ# (27)

DVFS_PWM (33)

DVFS_CLK (33)

R64 51_0402_5%

R65 0_0402_5%

STRAPS

1

2

R109 100K_0402_5%

@

1

2

1

2

1

D

2

G

Q5

S

3

MESS138W-G_SOT323-3

1

R66

R66 1K_0402_5%

1K_0402_5%

2

U

10

L9 M8 M1

P4

M3 M2

R8 R9

P3

P5 P1 N1

P7 M7

R7 P2

M10

P8 M9 M4

M5

P6 M6

K31

H28

L28

J28

P31

L29

M31

L30 J29

R30 M29

AA8

AC4

B

U

1C

BGA

(1.8V-3.3V)

V

DDIO_UART

UART2_RXD UART2_TXD UART2_CTS_N

UART2_RTS_N

UART3_RXD UART3_TXD

UART3_CTS_N UART3_RTS_N

DAP4_DIN

DAP4_DOUT DAP4_FS

DAP4_SCLK

CLK3_OUT CLK3_REQ

GPIO_PU0

GPIO_PU1 GPIO_PU2 GPIO_PU3

GPIO_PU4 GPIO_PU5 GPIO_PU6

GEN1_I2C_SCL GEN1_I2C_SDA

(1.8V-3.3V)

VDDIO_AUDIO

DAP1_DIN DAP1_DOUT DAP1_FS

DAP1_SCLK

DAP_MCLK1 DAP_MCLK1_REQ

DAP2_DIN DAP2_DOUT DAP2_FS

DAP2_SCLK

SPDIF_IN SPDIF_OUT

C

D580M

SEC 3 OF 8

2.8V-3.3V)

(

V

DDIO_HV

(1.8V-3.3V)

V

DDIO_GMI 1

VDDIO_GMI 2

GPIO_PB0 GPIO_PB1 GPIO_PC7

GPIO_PG0 GPIO_PG1 GPIO_PG2

GPIO_PG3 GPIO_PG4 GPIO_PG5

GPIO_PG6 GPIO_PG7 GPIO_PH0

GPIO_PH1 GPIO_PH2 GPIO_PH3

GPIO_PH4 GPIO_PH5 GPIO_PH6

GPIO_PH7

GPIO_PI0 GPIO_PI1

GPIO_PI2 GPIO_PI3 GPIO_PI4

GPIO_PI5 GPIO_PI6 GPIO_PI7

GPIO_PJ0 GPIO_PJ2 GPIO_PJ7

GPIO_PK0 GPIO_PK1 GPIO_PK2

GPIO_PK3 GPIO_PK4 GPIO_PK7

GEN2_I2C_SCL GEN2_I2C_SDA

SDMMC2_COMP_PU

SDMMC2_COMP_PD

GPIO_X1_AUD GPIO_X3_AUD

GPIO_X4_AUD GPIO_X5_AUD GPIO_X6_AUD

GPIO_X7_AUD

GPIO_W2_AUD GPIO_W3_AUD

DVFS_PWM

DVFS_CLK

Y

10

0.1U_0402_10V6K

9

U V10

U4 V9 U1

V2 V6 Y7

AA5 Y3 AA3

Y8 V3 Y6

U3 AA4 V8

R5 R4 U8

U2 Y5 AA6

V1 V7 Y9

U7 R1 Y4

U6 W1 V4

AA1

Delete 3G interface, 12/19

R3 Y1

R2 T1 V5

Y2 AA2

U5

R6

P29 M30

R28 R31 N31

P28 M28 J30

P30 R29

SOC_WARM_RESET#

HDSET_SW_SOCR# AC_OK_AP#

A

1.8V_VDDIO_CPU

+

1

4.7U_0402_6.3V6M

1

C

100

0.1U_0402_10V6K

2

+1.8V_VDDIO_CPU

1

R62

R63

1K_0402_5%

GEN1_I2C_SCL(21,22)

+1.8V_VDDIO_CPU

1

C104

4.7U_0402_6.3V6M

2

GEN1_I2C_SDA(21,22)

1

C105

0.1U_0402_10V6K

2

DAP_MCLK1(22)

2

DAP2_DIN(22)

DAP2_DOUT(22)

DAP2_FS(22)

DAP2_SCLK(22)

EN_VDD_HDMI(16,9)

4.7P_0402_50V8B

1K_0402_5%

2

R85 22_0402_5%

@

1

C106

2

1

R96 22_0402_5%

@

1

C107

4.7P_0402_50V8B

2

1

C

101

2

32K CLK for GPS-->

EC_IN_RW(29) WF_WAKE#(20)

BT_IRQ#(20)

2

1

2

DAP_MCLK1_L

DAP2_SCLK_R

C106/C107 change to @, R85/R96 change to 22ohm, follow nV FFD Rev3.11, 12/20

3

1

2

GEN2_I2C_SCL_3.3V

GEN2_I2C_SDA_3.3V

R381 0_0402_5%

1

R398 0_0402_5%@

1

R382 0_0402_5%

1

R400 0_0402_5%@

GEN2_I2C_SCL_3.3V_TP

2

GEN2_I2C_SCL_3.3V_TS

2

GEN2_I2C_SDA_3.3V_TP

2

GEN2_I2C_SDA_3.3V_TS

Add R381/R382 at GEN2 I2C TP net, 02/26 Add R398/R400 at GEN2 I2C TS net, 03/07

Change R398/R400 to @(un-mount), 03/10

Add R406 10K pull high for Q70 G, follow NV comment, 05/22

Change net GEN2_I2C_PWR to GEN2_I2C_PWR_TP/GEN2_I2C_PWR_TS,

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

Add R404 10K between +5V_VDD_TS and GEN2_I2C_PWR_TS, Swap Q69@/Q70@ D and S, follow Google command, 03/08

Compal Secret Data

2013/11/20 2014/11/09

Compal Secret Data

1

2

3

4

+1.05V_RUN_AVDD

C119

2.2U_0402_6.3V6M

C119

A

1

0.1U_0402_10V6K

2

C120

1

Top site

2

T22

T23

T24

T25

T26

T27

PAD @

DIRECTDC_CLK DIRECTDC_IN

DIRECTDC_OUT0 DIRECTDC_OUT1

DIRECTDC_OUT2 DIRECTDC_OUT3

Add T22~T27 test point, follow nV request, 01/14

D

1

C

109

1U_0402_6.3V6K

2

1

C112

4.7U_0603_6.3V6M

2

1

C114

4.7U_0402_6.3V6M

2

1

C116

2.2U_0402_6.3V6M

2

1

C

110

4.7U_0402_6.3V6M

2

1

2

L7BLM15AX300SN1D_2P

1

C117

0.1U_0402_10V6K

2

+

1.05V_RUN_CPU

+

3.3V_LP0_CPU

+1.05V_RUN_CPU

+1.05V_RUN_AVDD

1

C118

2.2U_0402_6.3V6M

2

(1.05V)

A

VDDIO_PEX

A

VDDIO_PEX

AVDDIO_PEX

(1.05V)

DVDDIO_PEX DVDDIO_PEX

DVDDIO_PEX

(3.3V)

HVDD_PEX

(1.05V)

AVDD_PEX_PLL

(1.05V)

AVDD_PLL_X

AVDD_PLL_CG

USB3_TX0N

USB3_TX0P

USB3_RX0N

USB3_RX0P

PEX_TX2N

PEX_TX2P

PEX_RX2N

PEX_RX2P

PEX_TX3N

PEX_TX3P

PEX_RX3N

PEX_RX3P

PEX_TX4N

PEX_TX4P

PEX_RX4N

PEX_RX4P

PEX_CLK1P

PEX_CLK1N

PEX_CLK2P

PEX_CLK2N

PEX_REFCLKP

PEX_REFCLKN

PEX_TESTCLKP

PEX_TERMP

PEX_L0_RST_N

PEX_L1_RST_N

PEX_WAKE_N

GPIO_PFF2

C

1

C

108

0.1U_0402_10V6K

A

B17

A

C17

AC18

AB20 AC20

AB18

AL28

AL29

AC21

AG31

L31

J31

AJ21

AH21 AL21

AK21 AG21

AF21 AL23

AK23 AJ23

AH23 AE21

AD21

AG23

AF23 AK24

AL24

AH26

AJ26 AL26

AK26

AF26

AG26

AC26

AC27

AH24

AJ24

AF24 AG24

AL22

+1.05V_RUN_AVDD_PEX_PLL

PEX_TERMP

2

1

C111

0.1U_0402_10V6K

2

1

C113

0.1U_0402_10V6K

2

1

C115

0.1U_0402_10V6K

2

USBSS_TX0N ( 17)

USBSS_TX0P (17)

USBSS_RX0N (17)

USBSS_RX0P (17)

USBSS_TX1N ( 17)

USBSS_TX1P (17)

USBSS_RX1N (17)

USBSS_RX1P (17)

1

R68

AE31

AJ29 AJ31

AK29 AJ30

R68

2.49K_0402_1%

2

AG28

AG30

AG29

B

U

1D

BGA

A

F31

AK30

AH31

AL27

AK27

AJ27

AH27

AG27

AF27

AL25

P10

U24 U23

U31 V31

V26 V29

J25

H27

F26

AD27

F27

AD25

AB22

J27

AD24

J24

U30 H25

H26

J26

K25

AD23

AD26 AC23

AC24 AC25

AA24

BGA

(3.3V)

H

VDD_SATA

(1.05V)

VDDIO_SATA

(1.05V)

AVDD_SATA_PLL

SATA_L0_TXP

SATA_L0_TXN SATA_L0_RXP

SATA_L0_RXN

SATA_TESTCLKP

SATA_TESTCLKN SATA_TERMP

(1.05V)

AVDD_PLL_C4

DIRECTDC_CLK

DIRECTDC_IN DIRECTDC_OUT0

DIRECTDC_OUT1 DIRECTDC_OUT2

DIRECTDC_OUT3

NC 1

NC 2 NC 3

NC 4 NC 5

NC 6 NC 7

NC 8 NC 9

NC 10 NC 11

NC 12 NC 13

NC 14 NC 15

NC 16 NC 17

NC 18 NC 19

NC 20 NC 21

D580M

C

SEC 4 OF 8

HVDD_PEX_PLL_E

AVDD_PLL_EREFE

PEX_USB3_TX1N

PEX_USB3_TX1P

PEX_USB3_RX1N

PEX_USB3_RX1P

PEX_TESTCLKN

(1.8V - 3.3V)

VDDIO_PEX_CTL

PEX_L0_CLKREQ_N

PEX_L1_CLKREQ_N

USB_VBUS_EN2

E

1

2

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SATA,USB 3.0,PEX

Z3ENN M/B LA-B551P

E

0.1

of

11 42Thursday, June 19, 2014

of

11 42Thursday, June 19, 2014

of

11 42Thursday, June 19, 2014

+

VDD_GPU_AP

0.47U_0402_16V4Z

1

2

E

1

2

3

4

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

1

2

R69 0_0402_5%@

R70 0_0402_5%@

R74 0_0402_5%@

C132

C138

D

2000mA

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

1

2

1

C133

C139

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

1

2

C134

C140

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

1

4.7U_0402_6.3V6M

1

C135

2

0.47U_0402_16V4Z

1

C329

C330

2

Add C329/C330 0.47uF to +VDD_GPU_AP, follow nV comment, 01/16

VDD_GPU_SENSE_P ( 33)

VDD_GPU_SENSE_N (33)

1

2

VDD_CPU_SENSE_P (33)

VDD_CPU_SENSE_N (33)

1

2

VDD_CORE_SENSE_P (33)

VDD_CORE_SENSE_N (33)

A

+

1

2

VDD_CORE

+VDD_CPU_AP

4.7U_0402_6.3V6M

3000mA

1

C121

2

1

C124

2

4.7U_0402_6.3V6M

1

2

1

2

C128

C125

1

C129

2

4.7U_0402_6.3V6M

1

C126

2

12000mA

4.7U_0402_6.3V6M

1

C141

2

4.7U_0402_6.3V6M

1

C147

2

3

+VDD_CPU_AP

R71

10K_0402_5% @

1

2

+VDD_CORE

R72

10K_0402_5% @

1

2

10K_0402_5% @

1

C142

2

1

C148

2

+VDD_GPU_AP

R73

4.7U_0402_6.3V6M

1

C143

2

4.7U_0402_6.3V6M

1

C149

2

1

2

MAY BE NEEDED FOR MIN VR LOADING

4

B

4.7U_0402_6.3V6M

0.1U_0402_10V6K

1

C122

2

0.1U_0402_10V6K

4.7U_0402_6.3V6M

0.1U_0402_10V6K

1

C127

2

4.7U_0402_6.3V6M

0.1U_0402_10V6K

1

C144

2

4.7U_0402_6.3V6M

1

C150

2

Change C151/C152 to 4.7uF, follow nV comment, 01/16

1G

U

BGA

A

A13

DD_CORE 1

V

A

0.1U_0402_10V6K

C123

1

C130

2

1

2

1

C136

2

0.1U_0402_10V6K

1

2

1

2

C145

C151

1

C146

2

4.7U_0402_6.3V6M

1

C152

2

A

AA16 AA17

AA18 AA19 AA22

M12

N12

R12

U12

W12

R23

M13 M14

M15 M16

M17 M18

M19 M20

M22 M23

M24 M25

N13 N14

N15 N16

N17 N18

N19 N20

N21 N22

N25

R17

R18 R19

R20 R21

R22

M26

M27

A14 A15

K12 K14

K15 K17

K18 K20

K21

P12

T12

V12

Y12

Y22

L23 L24

P13

P14 P15

P16 P17

P18 P19

P20 P21

P22

L25

L26

L27

P23

V

DD_CORE 2

V

DD_CORE 3

VDD_CORE 4 VDD_CORE 5

VDD_CORE 6 VDD_CORE 7

VDD_CORE 8 VDD_CORE 9

VDD_CORE 10 VDD_CORE 11

VDD_CORE 12 VDD_CORE 13

VDD_CORE 14 VDD_CORE 15

VDD_CORE 16 VDD_CORE 17

VDD_CORE 18 VDD_CORE 19

VDD_CORE 20 VDD_CORE 21

VDD_CORE 22 VDD_CORE 23

VDD_CORE 24 VDD_CORE 25

VDD_CPU 1 VDD_CPU 2

VDD_CPU 3 VDD_CPU 4

VDD_CPU 5 VDD_CPU 6

VDD_CPU 7 VDD_CPU 8

VDD_CPU 9 VDD_CPU 10

VDD_CPU 11 VDD_CPU 12

VDD_CPU 13 VDD_CPU 14

VDD_CPU 15 VDD_CPU 16

VDD_CPU 17 VDD_CPU 18

VDD_CPU 19 VDD_CPU 20

VDD_CPU 21 VDD_CPU 22

VDD_CPU 23 VDD_CPU 24

VDD_CPU 25 VDD_CPU 26

VDD_CPU 27 VDD_CPU 28

VDD_CPU 29 VDD_CPU 30

VDD_CPU 31 VDD_CPU 32

VDD_CPU 33 VDD_CPU 34

VDD_CPU 35 VDD_CPU 36

VDD_CPU 37 VDD_CPU 38

VDD_CPU 39 VDD_CPU 40

VDD_CPU 41 VDD_CPU 42

VDD_CPU 43 VDD_CPU 44

VDD_CPU 45 VDD_CPU 46

VDD_CPU 47 VDD_CPU 48

I185

C

D580M

SEC 7 OF 8

DD_GPU 1

V

DD_GPU 2

V

DD_GPU 3

VDD_GPU 4 VDD_GPU 5

VDD_GPU 6 VDD_GPU 7

VDD_GPU 8 VDD_GPU 9

VDD_GPU 10 VDD_GPU 11

VDD_GPU 12 VDD_GPU 13

VDD_GPU 14 VDD_GPU 15

VDD_GPU 16 VDD_GPU 17

VDD_GPU 18 VDD_GPU 19

VDD_GPU 20 VDD_GPU 21

VDD_GPU 22 VDD_GPU 23

VDD_GPU 24 VDD_GPU 25

VDD_GPU 26 VDD_GPU 27

VDD_GPU_SENSE

VVDD_GPU_PROBE

GND_GPU_SENSE

VDD_CPU_SENSE

VVDD_CPU_PROBE

GND_CPU_SENSE

VDD_CORE_SENSE

VVDD_CORE_PROBE

GND_CORE_SENSE

A

U U

U19 U20

V13 V14

V15 V16

V17 V18

V19 V20

W13 W14

W15 W16

W17 W18

W19 W20

W21 Y19

Y20 Y23

U21 V21

U26 U25

U27

R26

R25 R27

P25 P27

P26

A23

17 18

C131

C137

Change C131/C132/C137 to 4.7uF, follow nV comment, 01/16

VVDD_GPU_PROBE

VVDD_CPU_PROBE

VVDD_CORE_PROBE

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

POWER RAILS

Z3ENN M/B LA-B551P

E

0.1

of

12 42Thursday, June 19, 2014

of

12 42Thursday, June 19, 2014

of

12 42Thursday, June 19, 2014

A

U

1H

BGA

A

2

A

B21

16

1

2

3

4

L

17

L

18

L

19

N2

N4 N7

N10 N11

N28

AB25

N30 P11

R11 R13

R14 R15

R16

T2

T4 T7

AB28

T10

T11 T13

T14 T15

T16 T17

T18 T19

T20

AB30

T21 T22

T25 T28

T30 U11

U13 U14

U15 U16

AC9

U22

V11 V22

W2 W4

W7

W10

W11 W22

W25 AD8

W28 W30

Y13 Y14

Y15 Y16

Y17 Y18

AK2 AE8

AB11 AB14

P24 R24

T31 V27

AE23

L22

AE2 AE4

AE7

AE10

A30

AE13

K30

L13 L14

L15

A

G

ND 1 ND 10

G

ND 100 ND 101

G

ND 102

G

ND 103

GND 104 GND 105

GND 106 GND 107

GND 108 GND 109

GND 11 GND 110

GND 111 GND 112

GND 113 GND 114

GND 115 GND 116

GND 117 GND 118

GND 119 GND 12

GND 120 GND 121

GND 122 GND 123

GND 124 GND 125

GND 126 GND 127

GND 128 GND 129

GND 13 GND 130

GND 131 GND 132

GND 133 GND 134

GND 135 GND 136

GND 137 GND 138

GND 139 GND 14

GND 140 GND 141

GND 142 GND 143

GND 144 GND 145

GND 146 GND 147

GND 148 GND 149

GND 15 GND 150

GND 151 GND 152

GND 153 GND 154

GND 155 GND 156

GND 157 GND 158

GND 159 GND 160

GND 161 GND 162

GND 163 GND 164

GND 165 GND 166

GND 167 GND 16

GND 17 GND 18

GND 19 GND 2

GND 20 GND 96 GND 97

GND 98 GND 99

C

D580M

SEC 8 OF 8

G

ND 21 ND 22

G

ND 23 ND 24

G

ND 25

G

ND 26

GND 27 GND 28

GND 29

GND 3

GND 30 GND 31

GND 32 GND 33

GND 34 GND 35

GND 36 GND 37

GND 38 GND 39

GND 4

GND 40

GND 41 GND 42

GND 43 GND 44

GND 45 GND 46

GND 47 GND 48

GND 49

GND 5

GND 50 GND 51

GND 52 GND 53

GND 54 GND 55

GND 56 GND 57

GND 58 GND 59

GND 6

GND 60

GND 61 GND 62

GND 63 GND 64

GND 65 GND 66

GND 67 GND 68

GND 69

GND 7

GND 70 GND 71

GND 72 GND 73

GND 74 GND 75

GND 76 GND 77

GND 78 GND 79

GND 8

GND 80

GND 81 GND 82

GND 83 GND 84

GND 85 GND 86

GND 87 GND 88

GND 89

GND 9

GND 90 GND 91

GND 92 GND 93

GND 94 GND 95

A

E16

A

E19

E22

A A

E28

A

E30

A

H2

AH4 AH7

AH10 AB2

AH13 AH16

AH19 AH22

AH25 AH28

AH30 AK1

AK4 AK7

AB4 AK10

AK13 AK16

AK19 AK22

AK25 AK28

AK31 AL2

AL30 AB7

B1 B4 B7

B10 B13

B16 B19

B22 B25

B28 AB10

B31 D2

D4 D7

D10 D13

D16 D19

D22 D25

AB13 D28

D30 G2

G4 G7

G10 G13

G16 G19

G22 AB16

G24 G25

G28 G30

H8 H24

J23 K2

K4 K7

AB19 K13

AE24 K19

K22 AE25

K28

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

2013/11/20 2014/11/09

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CPU_GND

Z3ENN M/B LA-B551P

E

1

2

3

4

0.1

of

13 42Thursday, June 19, 2014

of

13 42Thursday, June 19, 2014

of

13 42Thursday, June 19, 2014

E

3.3V_SYS

+

1

0U_0603_6.3V6M

U_0402_6.3V6K

1

C

154

2

1

+3.3V_RUN

LH1

1

10U_0603_6.3V6M

S SUPPRE_CHILISIN PBY160808T-471Y-N 0603

1

C

C 183

183

@

2

@

1

2

Change C305 P/N to SE025103K80, 01/06

C306

18P_0402_50V8J

3

USBHUB1_XTALOUT USBHUB1_XTALIN

USBHUB1_XTALIN

1

@

2

12MHZ_18PF_7V12000001@

Cgange Y3 P/N to SJ10000C210, 01/02

2.2U_0402_6.3V6M

1

C

155

2

@

2

R296

10K_0402_5% @

2

C3050.01U_0603_50V7K

Y3

1

2

+3.3V_RUN

1

C153

2

A

L

CD PWR

1

156

156 C

C

2

2200P_0402_50V7K

+3.3V_RUN_HUB

+5V_SYS

1

UHUB1

2

1

OVCJ

2

TESTJ

3

XOUT

4

XIN

5

DM4

6

DP4

21

DRV

22

LED1

23

LED2

24

PWRJ

SA00005E800

FE1.1S-BQFN24B_WQFN24_4X4

@

FE1.1S-BQFN24B_WQFN24_4X4

@

4

3

USBHUB1_XTALOUT

1

C307

18P_0402_50V8J

2

USB Camera PWR

1

R76 0_0603_5%@

U24

5

VIN

4

VIN

AP2821KTR-G1_SOT23-5

SA00006EE00

EN High / 2.0A

U

23

5

V

IN

4

IN

V

AP2821KTR-G1_SOT23-5

SA00006EE00

20

19

25

VSS

VDD5

VD33F

@

2

1

VOUT

2

GND

3

EN

1

V

OUT

2

G

ND

3

E

N

2

1

CAM_USB1_D+_H

CAM_USB1_D-_H

Change UHUB1 to @, 02/20

12

CAM_USB1_D+_H

DP1

11

CAM_USB1_D-_H

DM1

10

DP2

9

DM2

8

DP3

7

DM3

18

BUSJ

17

VBUSM

16

XRSTJ

15

CAM_USB1_D+

DPU

14

CAM_USB1_D-

DMU

13

R295 2.7K_0402_1%@

REXT

VBUSM_1

R297

@

R77

2

1

0_0402_5%

R79

R79 0_0402_5%

0_0402_5%

@

2

VDD_3V3_LCM

+

1

C

157

@

157

@

0.1U_0402_10V6K

2

E

N_AVDD_LCD (36)

R

78

1M_0402_5%

1

2

R104 0_0402_5%

1

2

R105 0_0402_5%

Change R104@/R105@ to mount, 02/20

1

2

100K_0402_5%

C192

@

150mA

+3.3V_USBCAM

1

2

+2.8V_RUN_CAM

2

VBUSM_1

2

reference 1%

0.1U_0402_10V6K

1

2

C158

0.1U_0402_10V6K

R93 100K_0402_5%@

R294 100K_0402_5%@

1

2

1

B

2

CAM_USB1_D+

CAM_USB1_D-

CAM_USB1_D+ (9)

CAM_USB1_D- (9)

@

1

+3.3V_RUN_HUB

R29810K_0402_5%

+5V_SYS

C

UO 13.3'' B133XTN01.0

A

+VDD_3V3_LCM

R311

1

2

0.01_0603_1%

0612 modified.

DP_AUXN(9)

DP_AUXP(9)

C159 0.1U_0402_10V6K

DP_TXD0P(9)

DP_TXD0N(9)

C159 0.1U_0402_10V6K

C160 0.1U_0402_10V6K

Change D24 P/N to SCA00000U10, follow ESD request, 01/09

1

C163

4.7U_0603_6.3V6M

2

1

R80 100K_0402_1%

R82 100K_0402_1%

2

1

2

C161 0.1U_0402_10V6K

1

2

C162 0.1U_0402_10V6K

1

2

1

2

1

2

CAM_USBD+_L

CAM_USBD-_L

2

3

D24

D24 YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

SCA00000U10

SCA00000U10 @ESD@

@ESD@

1

2

1

C164

C164 1U_0402_6.3V6K

1U_0402_6.3V6K

C165

0.1U_0402_10V6K

2

1

R81 100K_0402_1%

1

R83 100K_0402_1%

2

+3.3V_USBCAM

+VDD_LED

+VDD_3V3_LCM

R313

1

0_0603_5%

D

Del R312 by 0612.

C167

4.7U_0805_50V6K

LCD_BL_PWM_R3.3V(15)

LCD_BL_EN_R3.3V(15)

DP_TXD1P(9) DP_TXD1N(9)

Add Net DP_TXD1N/DP_TXD1P for FHD, 02/26

CAM_USB1_D+_H

CAM_USB1_D-_H

2

EDP_HPD(9)

Add C332/C333 0.1uF, 03/05

DP_AUXN_C DP_AUXP_C

4

1

Change L10 P/N SM070003Y00, follow EMI request, 01/07

200mA

1

4.7U_0805_50V6K

2

L10

4

1

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

1

@

C168

3300P_0402_25V7K

2

Change C167/C168 to 4.7uF and C168 to @, 01/15

C332 0.1U_0402_10V6K

C333 0.1U_0402_10V6K

C166 0.01U_0402_16V7K

DP_TXD0P_C DP_TXD0N_C

3

2

1

@

C169

3300P_0402_25V7K

2

1

2

1

2

1

2

CAM_USBD+_L

CAM_USBD-_L

E

1

@

C170

2

DP_TXD1P_C DP_TXD1N_C

JEDP1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_88341-3001

CONN@

CONN@ SP010023700

SP010023700

2

34

G4

33

G3

32

G2

31

G1

3

Modify by Panel SPEC. 12/24

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

EDP CONNECTOR

Size Document Number Rev

C

Z3ENN M/B LA-B551P

Date: Sheet

E

of

14 42Thursday, June 19, 2014

of

14 42Thursday, June 19, 2014

of

14 42Thursday, June 19, 2014

4

0.1

C

32

1

+

VDD_LED

2

5

1

R88

R88 75K_0402_5%@

75K_0402_5%@

2

Q9

1

D

2

G

LCD_BL_EN_R3.3V (14)

Change Q50 to U54/U55, Add R408/R409 and change R92 to 10K for LCD issue, 05/22

@

SB00000QO00

S

3

LBSS138LT1G_SOT-23-3

00mA

+

VDD_MUX

C308

4

B

L

FBMA-L11-201209-221LMA30T_0805

1

@

2

R87

@

100K_0402_5%

2

@

1

R89 1K_0402_5%

+VDD_3V3_LCM

1

R92

10K_0402_5%

2

10K_0402_5% @

L

2

EMI@

Q

52

SB00000ZC00

AON7401_DFN8-5

1 2

3

4

@

2

R90

1

A

1

1U_0603_25V6K

EN_VDD_BL(8)

2

LCD_BL_EN(10)

3

EC_BL_OVERRIDE(29)

+1.8V_VDDIO

1

R408

0_0402_5%

2

5

U54

1

2

U54

P

NC

Y

A

G

SN74LVC1G07DCKR_SC70-5

3

SA00000L800

D

E

1

2

3

+1.8V_VDDIO

R409

1

0_0402_5%

LCD_BL_PWM(10)

4

A

2

5

U55

1

2

U55

P

NC

A

4

Y

G

SN74LVC1G07DCKR_SC70-5

3

SA00000L800

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

1

R94

R94 10K_0402_5%

10K_0402_5%

2

LCD_BL_PWM_R3.3V (14)

Compal Secret Data

2013/11/20 2014/11/09

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Compal Electronics, Inc.

LCD BACKLIGHT

Z3ENN M/B LA-B551P

E

of

15 42Thursday, June 19, 2014

of

15 42Thursday, June 19, 2014

of

15 42Thursday, June 19, 2014

4

0.1

E

D

19

1

DMI_TXD_1P_L

H

1

2

H

DMI_TXD_1N_L

2

4

DMI_TXC_P_L

H

4

5

H

DMI_TXC_N_L

5

3

8

D25

1

HDMI_TXD_0P_L

10

9

7

6 5

L05ESDL5V0NA-4_SLP2510P8-10-9

@ESD@

@ESD@ SC300002C00

SC300002C00

EN_VDD_HDMI (10,9)

1

2

4

5

3

8

HDMI_TXD_0N_L

HDMI_TXD_2P_L

HDMI_TXD_2N_L

1

2

GND

GND GND

GND

D

23

22 21

20

1

2

U26

200mA 40 mil200mA 40 mil

5

IN

OUT

3

FLAG#

4

EN

GND

NCP380HSN05AAT1G_TSOP5

SA000069N00

DMI_TXD_1P_L

H

DMI_TXD_1N_L

DMI_TXC_P_L

H

DMI_TXC_N_L

HDMI_TXD_0P_L

HDMI_TXD_0N_L

HDMI_TXD_2P_L

HDMI_TXD_2N_L

9

10

8

9

7

6

L05ESDL5V0NA-4_SLP2510P8-10-9

@ESD@

@ESD@ SC300002C00

SC300002C00

9

8

7

6

Change D19/D25 P/N to SC300002C00, follow ESD request, 01/07

+5V_SYS

1

C175

C175 10U_0603_6.3V6M

10U_0603_6.3V6M

2

R299

1

2

100_0402_5%

2

1

C

173

150P_0402_50V8J

2

C

C174

0.1U_0402_10V6K

DMI_HPD

H

HDMI_CEC_CON

HDMI_DDC_SCL_CON HDMI_DDC_SDA_CON

HDMI_HPD

+5V_HDMI

1

2

C

hange JHDMI1 P/N from conn list 1226, 12/27

JHDMI1

1

D2+

2

D2_shield

3

D2-

4

D1+

5

D1_shield

6

D1-

7

D0+

8

D0_shield

9

D0-

10

CK+

11

CK_shield

12

CK-

13

CEC

14

Reserved

15

SCL

16

SDA

17

DDC/CEC_GND

18

+5V

19

HP_DET

CONCR_099AUAC19CBACN L

CONN@

+3.3V_LP0

2

3

2

3

2

3

2

3

B

2

3

2

3

2

3

2

3

+3.3V_LP0

DMI_INT(24,9)

H

DMI_TXD_2P_L

H

DMI_TXD_2N_L

HDMI_TXD_1P_L

HDMI_TXD_1N_L

HDMI_TXD_0P_L

HDMI_TXD_0N_L

HDMI_TXC_P_L

HDMI_TXC_N_L

R

97

22K_0402_5% @

1

95 1K_0402_5%

1

2

A

Change L11/12/13/15 P/N to SM070003Y00, follow EMI request, 01/07

11

L

H

1

2

DMI_TXD_2P(9)

H

DMI_TXD_2N(9)

HDMI_TXD_1P(9)

HDMI_TXD_1N(9)

HDMI_TXD_0P(9)

HDMI_TXD_0N(9)

HDMI_TXC_P(9)

HDMI_TXC_N(9)

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

L12

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

L13

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

L15

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

2

R107

3

HDMI_CEC(9)

1

R108 32.4K_0402_1%

+3.3V_LP0

R107

162K_0402_1%

2

+5V_HDMI

G

2

1

3

S

D2

2

3

BAT54CW_SOT323-3~D

Q10

Q10 FDV301N-NL_SOT23-3

FDV301N-NL_SOT23-3

1

R100 0_0603_5%

D

2

1

@

2

C176

C176 10P_0402_50V8J

10P_0402_50V8J

HDMI_DDC_SCL_CON

HDMI_DDC_SDA_CON

@ESD@

2

3

1

D30

D30 TVNST52302AB0 SOT523

TVNST52302AB0 SOT523

HDMI_CEC_CON

HDMI_HPD

@ESD@

2

3

D31

D31 TVNST52302AB0 SOT523

TVNST52302AB0 SOT523

1

3

1

R112

R111

1.8K_0402_5%

4

A

HDMI_DDC_SCL(9)

HDMI_DDC_SDA(9)

R112

1.8K_0402_5%

2

1

R101 0_0402_5%

R102 0_0402_5%

2

1

2

Change C177/C178 P/N to SE07156AD80, 12/31

B

1

@

2

C177

5.6P_0402_50V8C

1

@

2

C178

5.6P_0402_50V8C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

Add D30@/D31@ ESD diode, follow nV comment, 01/13

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

HDMI TYPE D

Z3ENN M/B LA-B551P

E

4

0.1

of

16 42Thursday, June 19, 2014

of

16 42Thursday, June 19, 2014

of

16 42Thursday, June 19, 2014

A

+

5V_SYS

1

179

C

4.7U_0603_6.3V6M

1

2

1

R114

R114 100K_0402_5%

100K_0402_5%

2

4.7U_0603_6.3V6M

3.3V_LP0

+

1

USB_VBUS_EN0(9)

2

R

144

100K_0402_5% @

@

Change U27 P/N to SA00006Y800, but the symbol is SY6288C20(SA000079400), 01/13

C

0.1U_0402_10V6K

2

180

B

U

27

5

I

N

4

E

N

G524B1T11U_SOT23-5

SA00006Y800

1

O

UT

2

G

ND

3

O

C

R103

1

2

0_0402_5%

USBSS_RX1N_L

USBSS_RX1P_L

USBSS_TX1N_L

USBSS_TX1P_L

Change D6 P/N to SC300002C00, follow ESD request, 01/07

9

10

8

9

7

6

6 5

L05ESDL5V0NA-4_SLP2510P8-10-9

@ESD@

@ESD@ SC300002C00

SC300002C00

1

186

C

+

100U_B2_6.3VM_R35M

2

D6

1

2

4

3

8

2

A 100 mil2A 100 mil

187

C

47U_0805_6.3V6M

1

USBSS_RX1N_L

2

USBSS_RX1P_L

4

USBSS_TX1N_L

5

USBSS_TX1P_L

3

1

184

C

0.1U_0402_10V6K

2

+

5V_USB_SS1

C

Change L19/L20 P/N SM070003Y00, follow EMI request, 01/07

19

L

1

C

470P_0402_50V8J

2

SB2_D-(9)

U

185

SB2_D+(9)

U

USBSS_RX1N(11)

USBSS_RX1P(11)

USBSS_TX1N(11)

USBSS_TX1P(11)

Add C309/C310 0.1U, follow nV FFD Rev3.12, 12/20

4

1

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

L20

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

1

C309 0.1U_0402_16V7K

1

C310 0.1U_0402_16V7K

2

USBSS_TX1N_R

2

USBSS_TX1P_R

3

2

3

SB2_D-_L

U

SB2_D+_L

U

D5

YSLC05CH_SOT23-3

SCA00000U10

@ESD@

USBSS_RX1N_L

USBSS_RX1P_L

L21

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

Change L21 P/N SM070003Y00, follow EMI request, 01/07

2

3

D

5V_USB_SS1

+

2

3

1

2

USBSS_TX1N_L

3

USBSS_TX1P_L

Change JUSB1 P/N from DC23300F8B0 to DC23300F800, 01/02

E

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

GND-DRAIN StdA-SSTX-

StdA-SSTX+

GND

GND GND

GND

7 8

9

TAITW_PUBAUE-09FLBS 1FF4H0

CONN@

1

10

11 12

13

2

+5V_SYS

3

USB_VBUS_EN1(9)

change EN0 to EN1 , 01/07

4

+3.3V_LP0

R329

100K_0402_5% @

@

Change U50 P/N to SA00006Y800, but the symbol is SY6288C20(SA000079400), 01/13

1

2

1

R327

R327 100K_0402_5%

100K_0402_5%

2

A

1

C313

C314

4

4 .7U_0603_6.3V6M

.7U_0603_6.3V6M

C314

0.1U_0402_10V6K

2

U50

5

OUT

IN

GND

4

OC

EN

G524B1T11U_SOT23-5

SA00006Y800

R328

1

0_0402_5%

+5V_USB_SS0

1

2

3

2

USBSS_RX0N_L

USBSS_RX0P_L

USBSS_TX0N_L

USBSS_TX0P_L

Change D28 P/N to SC300002C00, follow ESD request, 01/07

9

10

8

9

7

6

6 5

L05ESDL5V0NA-4_SLP2510P8-10-9

@ESD@

@ESD@ SC300002C00

SC300002C00

B

2A 100 mil2A 100 mil

1

C315

+

C316

47U_0805_6.3V6M

100U_B2_6.3VM_R35M

2

D28

1

USBSS_RX0N_L

1

2

USBSS_RX0P_L

2

4

USBSS_TX0N_L

4

5

USBSS_TX0P_L

3

8

1

C318

C317

470P_0402_50V8J

0.1U_0402_10V6K

2

Change L22/L23 P/N SM070003Y00, follow EMI request, 01/07

+5V_USB_SS0

L22

4

USB0_D-(9)

USB0_D+(9)

USBSS_RX0N(11)

USBSS_RX0P(11)

USBSS_TX0N(11)

USBSS_TX0P(11)

Add C311/C312 0.1U, follow nV FFD Rev3.12, 12/20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

1

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

L23

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

1

C311 0.1U_0402_16V7K

1

C312 0.1U_0402_16V7K

C

3

2

3

2

USBSS_TX0N_R

2

USBSS_TX0P_R

2013/11/20 2014/11/09

USB0_D-_L

USB0_D+_L

D7

YSLC05CH_SOT23-3

SCA00000U10

@ESD@

USBSS_RX0N_L

USBSS_RX0P_L

L24

1

4

DLW21HN900HQ2L_4P

SM070003Y00

SM070003Y00 EMI@

EMI@

Change L24 P/N SM070003Y00, follow EMI request, 01/07

Compal Secret Data

Deciphered Date

2

3

1

2

3

USBSS_TX0N_L

USBSS_TX0P_L

D

Micro-B Type Connector

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

TAITW_PUBAUE-09FLBS 1FF4H0

CONN@

Change JUSB1 P/N from DC23300F8B0 to DC23300F800, 01/02

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB PORTS

Z3ENN M/B LA-B551P

E

10

GND

11

GND

12

GND

13

GND

of

17 42Thursday, June 19, 2014

of

17 42Thursday, June 19, 2014

3

4

0.1

A

B

C

D

E

1

SW5

1

2

NSS506-212F-KKKG1TM_3P

SN200003F00 @

Add SW5 for write protect function, 04/14

3

4

GND

5

GND

Change JP10 footprint to CLIP_SHAPE6P0X3P0, 04/09

MNTG_WP#

SPI_ROM_SERVO_WP#(24)

@

JP10

2

CLIP_SHAPE6P0X3P0

1

R197

330K_0402_5%

R200

1K_0402_5%

MNTG_WP#

SPI4_CS0_SERVO#(24)

SPI4_MISO_SERVO(24)

+3.3V_STBY

1

2

1

2

Change Q63 P/N to SB00000FG00, 02/20

+

1.8V_SPI

AO3416_SOT23-3

SB00000FG00

0.1U_0402_10V6K

1

C268

2

1

2

R193 51_0402_5%

SPI4_CS0#(10)

SPI4_MISO(10,26)

R193 51_0402_5%

2

R194 51_0402_5%

U38

1

NC

IN A

GND

VCC

Y

2

3

NL17SZ07DFT2G_SC70 -5

SA00004BV00

1

+3.3V_STBY

5

4

R198 10K_0402_5%

2

R201 1 0K_0402_5%

U37

1

CS#

DO WP#

GND

2

VCC

HOLD#

CLK

DI

EC_WP# (2 9)

2 3

4

W25Q32DWSSIG_SO8

1

R199 1 00K_0402_5%

1

8

7 6

5

+1.8V_SPI

1

AP_WP# (8)

+

3.3V_SYS

Q

63

1

R192

R192 100K_0402_5%

100K_0402_5%

2

R19551_0402_5%

2

R19651_0402_5%

40mA

1.8V_VDDIO

+

2

G

3

D

S

D

S

SPI_HOLD_SERVO# (24) SPI4_SCK_SERVO (24)

SPI4_SCK (10 ,26)

SPI4_MOSI_SERVO (24)

SPI4_MOSI (10,26)

1

2

3

CPU hold

H_2P9N

4

@

H2

H_3P8

@

H24

1

H_3P8

@

1

H_2P9X3P5N

@

H_4P5

@

H4

H3

H_3P8

@

1

H25

1

Add H26/H27, 12/31 Delete H26, 01/03

H27

H_5P0

@

1

H8

H_3P8

@

1

A

H5

1

H_5P0

@

H11

1

MNTG_WP#(23)

H_4P5

@

H12

1

FD1

@

1

FIDUCIAL_C40M80

FD3

@

1

FIDUCIAL_C40M80

H13

H_4P5

@

1

FD2

1

FIDUCIAL_C40M80

FD4

1

FIDUCIAL_C40M80

H7

H15

H_3P0

@

1

Add H28~H31 H_6P5, 01/13

S1

@

Frame

@

H9

H_3P8N

H_3P0

@

1

H_3P8N

@

1

B

Frame

EC176000800

EC176000800 Z3ENN_MB_RAM_FRAME_EMI

Z3ENN_MB_RAM_FRAME_EMI

H32

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

H28

H_6P5

@

1

C

H30

H31

H29

H_6P5

@

1

Compal Secret Data

H31

H_6P5

@

1

CLP5

EC0M5000700

EMIST_SUL-12A2M_1P

Deciphered Date

CLP6

EC0M5000700

EMIST_SUL-12A2M_1P

D

CLP10

EC0M5000700

EMIST_SUL-12A2M_1P

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SPI ROM, SCREW

Z3ENN M/B LA-B551P

E

of

18 42Thursday, June 19, 2014

of

18 42Thursday, June 19, 2014

of

18 42Thursday, June 19, 2014

4

0.1

E

1

A

4

3

1

2

D

2

ED2

L

B

HT-297UD5-CB5 _AMBER-BLUE

SC500008S00

1

R326

R326 100_0402_5%

100_0402_5%

2

BAT_LED1_R

CHARGING_R

A

P

+

3.3V_STBY

(

1

Orange)

R323

560_0402_5%

B

OWER_LED

+

3.3V_LP0

(BLUE)

2

4

A

3

1

2

L

ED1

B

HT-297UD5-CB5 _AMBER-BLUE

SC500008S00

1

R324

R324 100_0402_5%

100_0402_5%

2

PWR_LED1_R

PWR_LED0_R

Cahnge R324/R326 from 1K to 100 ohm, Change R323/R325 from 2.2K to 560 ohm, 05/05

C

B

ATT_LED

+

3.3V_STBY

(Orange) (BLUE)

R325

560_0402_5%

2

PWR_LED1_R

1

D

PWR_LED1(29)

High Active

3

PWR_LED0(29)

High Active

4

A

1

R337

100K_0402_5%

2

1

R339

100K_0402_5%

2

G

2

G

3

1

3

B

D

Q58

S

AO3416_SOT23-3

SB00000FG00

PWR_LED0_R

D

Q60

S

AO3416_SOT23-3

SB00000FG00

BAT_LED1(29)

High Active

CHARGING(29)

High Active

Cahnge Q58~Q61 MOS to SB00000FG00, 01/15

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

Compal Secret Data

C

Deciphered Date

1

R338

R338 100K_0402_5%

100K_0402_5%

2

1

R340

R340 100K_0402_5%

100K_0402_5%

2

G

2

G

BAT_LED1_R

1

D

Q59

S

3

AO3416_SOT23-3

SB00000FG00

CHARGING_R

1

D

Q61

S

3

AO3416_SOT23-3

SB00000FG00

D

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

B

Date: Sheet

Compal Electronics, Inc.

LED

Z3ENN M/B LA-B551P

E

of

19 42Thursday, June 19, 2014

of

19 42Thursday, June 19, 2014

of

19 42Thursday, June 19, 2014

2

3

4

0.1

A

1

3.3V_VDD_WF

+

2

T28

PAD @

T29

PAD @

T30

PAD @

T31

PAD @

T32

PAD @

Add T28~T32 test point for SDIO, 03/07

3

4

SDMMC1_CMD

SDMMC1_DAT0

SDMMC1_DAT1

SDMMC1_DAT2

SDMMC1_DAT3

Add R354@ 10K to 1.8V, follow vendor suggestion, 01/06

ULGA1

A

B

1.8V_VDDIO

+

1

214

C

R

1M_0402_5%

2

G

Add R351/R352 0ohm and C321@/C322@ 22pF, follow RF team suggestion, 01/06 Add R366 0ohm between U30 pin45 and net WF_EN, 01/08

CLK_WIFI_32K( 36)

SDMMC1_CLK(8)

SDMMC1_CMD(8 )

Add R351/R352 0ohm and C321@/C322@ 22pF, follow RF team suggestion, 01/06

C

153

0.1U_0402_10V6K

2

1

D

Q15

Q15 DMN65D8LW-7_SOT 323-3

DMN65D8LW-7_SOT 323-3

S

3

100K_0402_5% @

WF_EN(10,20)

SDMMC1_DAT[3..0](8)

+1.8V_VDDIO

R155

22P_0402_50V8J

Q14

S TR AO3415 1P SOT23-3

Q

14

S

3

G

2

DMN65D8LW-7

+1.8V_VDDIO

1

2

1

R366 0_0402_5%

1

2

R352 0_0402_5%

C322

@

1

2

D

1

SB00000AP00

@

C321

1

22P_0402_50V8J

2

R351 0_0402_5%

2

SDMMC1_DAT0

SDMMC1_DAT1 SDMMC1_DAT2

SDMMC1_DAT3

Change Location U30 to ULGA1, follow factory request, 03/05

2

1

R354

R354 10K_0402_5%@

10K_0402_5%@

2

T7

PAD @

T8

PAD @

WF_WAKE#(10)

BT_IRQ#(10)

AZURE@

PK29S005H00

S_W/L_MOD AZUREWAVE AW-CM389NF

FOXCO@

PK29S005M00

S_W/L_MOD FOXCONN T77H526.01

PAD @

LTE_COEX1

LTE_COEX2

B

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R

152

1

2

0_0805_5%

F

ollow nV comment. 12/23

Issued Date

200mA

ULGA1

WiFi

24

NFC_ANTN

25

NFC_ANTP

67

NFC_CLK

66

NFC_SDA

15

NFC_WI_IN

16

NFC_SWAP1_VDDIN

18

NFC_SWP2_IO

22

NFC_SWP2_VOUT

19

NFC_SWP1_IO

21

NFC_SWP1_VOUT

27

SLPCLK

45

PDN

52

SD_CLK

51

SD_CMD

50

SD_DAT0

49

SD_DAT1

48

SD_DAT2

47

SD_DAT3

69

USB_D-

70

USB_D+

30

PCIE_CLKREQN

29

PCIE_WAKEN

33

PCIE_RCLK_N

34

PCIE_RCLK_P

39

PCIE_RX_N

40

PCIE_RX_P

36

PCIE_TX_N

37

PCIE_TX_P

42

GPIO[0]

11

GPIO[1]/LTE_SOUT

12

GPIO[2]/LTE_SIN

46

GPIO[3]

55

GPIO[4]

56

GPIO[5]

54

GPIO[6]

57

GPIO[7]

64

GPIO[8]

65

GPIO[9]

31

GPIO[12]

28

GPIO[13]

59

GPIO[19]

60

GPIO[20]

61

GPIO[21]

58

GPIO[22]

2

TCK

3

TDI

7

TDO

1

TMS

S_W/L_MOD AZUREWAVE AW-CM398N F

S_W/L_MOD AZUREWAVE AW-CM398N F PK29S005H00

PK29S005H00 @

@

C

R353

@

R353

@

0_0402_5%

R365

1

@

0_0402_5%

CONFIG_HOST0

CONFIG_HOST1 CONFIG_HOST2

CONFIG_HOST3

3.3V_LP0

+

2

1.8V_VDD_WF

+

Change R353 to @, follow nV comment, 01/13

1

72

3V3_USB

5

3V3_VBAT

4

3V3_VRF

73

VIO

44

VIO_SD

14

NC

43

NC

53

NC

63

NC

77

NC

96

NC

CONFIG_HOST0 CONFIG_HOST1

CONFIG_HOST2

CONFIG_HOST3

2013/11/20 2014/11/09

C

8

9 10

13

6

GND

17

GND

20

GND

23

GND

26

GND

32

GND

35

GND

38

GND

41

GND

62

GND

68

GND

71

GND

74

GND

75

GND

76

GND

78

GND

79

GND

80

GND

81

GND

82

GND

83

GND

84

GND

85

GND

86

GND

87

GND

88

GND

89

GND

90

GND

91

GND

92

GND

93

GND

94

GND

95

GND

97

GND

98

GND

99

GND

100

GND

101

GND

102

GND

103

GND

104

GND

105

GND

106

GND

107

GND

108

GND

Compal Secret Data

Deciphered Date

0.1U_0402_10V6K

1

2

R

154

1

0_0805_5%

0.1U_0402_10V6K

C215

WF_EN (10,20)

1

R368

@

R368

@

49.9K_0402_1%

2

1

R156

R156 100K_0402_5%

100K_0402_5%

2

D

00mA

5

3.3V_VDD_WF

+

E

2

+

3.3V_VDD_WF

R

356

@

356

@

1

10U_0603_6.3V6M

0.1U_0402_10V6K

1

C216

2

0.1U_0402_10V6K

Add R368@/R369@/R370@/R371@ 49.9K pull high to VIO, follow vendor suggestion, 01/10

D

10U_0603_6.3V6M

1

2

1

C219

2

1

@

2

1

R157

@

100K_0402_5%

2

1

C218

C217

C218

2

+1.8V_VDD_WF

0.1U_0402_10V6K

1

C220

2

+1.8V_VDD_WF

1

R369

49.9K_0402_1%

R370

@

R370

@

49.9K_0402_1%

2

1

R158

@

100K_0402_5%

2

Title

Size D ocument Number Rev

Custom

Date: Shee t

2

0_0402_5%

1

C323

C323 680P_0402_50V7K@

680P_0402_50V7K@

2

R357

@

R357

@

1

2

0_0402_5%

1

C324

C324 680P_0402_50V7K@

680P_0402_50V7K@

2

Add R356@/C323@ to 3.3V, Add R357@/C324@ to 1.8V, follow RF request, 01/07

1

R371

@

R371

@

49.9K_0402_1%

2

CONFIG_HOST0

CONFIG_HOST1

CONFIG_HOST2

CONFIG_HOST3

1

R159

@

100K_0402_5%

2

Compal Electronics, Inc.

WIFI BLUETOOTH

Z3ENN M/B LA-B551P

20 42Thursday, June 19, 2014

E

of

1

2

3

4

0.1

D

1

C223

1U_0402_6.3V6K

2

46mA

R163

1

0_0603_5%

+1.8V_VDDIO

2

PM

C

VDD

GND

TPM_SLB9645TT

5

10

17

NC

19

NC

20

NC

21

NC

22

NC

23

NC

24

NC

26

NC

27

NC

28

NC

4

11

18

25

1

C221

0.1U_0402_10V6K

2

+1.8V_VDDIO_TPM

1

C222

0.1U_0402_10V6K

2

A

B

T

1.8V_VDDIO

+

1

TPM_I2C_SCL(9)

TPM_I2C_SDA(9)

TPM_DAVINT#(10)

SYS_RESET#(24,25,30,36,8)

2

1

R

R 10K_0402_5%

10K_0402_5%

@

2

160

1

R

161

2.2K_0402_5%

2

10K_0402_5% @

4.7K_0402_5%

1

2

+1.8V_VDDIO

R164

R165

R

162

2.2K_0402_5%

1

2

1

2

U31

2

SCL

1

SDA

6

DAVINT#

9

RESET#

3

NC

8

NC

12

NC

13

NC

14

NC

15

NC

16

NC

7

PP

SA00007L310

Change TPM U31 P/N to SA00007L310 for GOOG, 01/07

E

1

2

TEMP SENSOR

Add +3.3V_STBY to U32.1 for reserve, follow acer request, 02/19

+3.3V_RUN

10mA

R362

3

1

2

R167

THERMD_P(8)

THERMD_N(8)

GEN1_I2C_SCL(1 0,22)

GEN1_I2C_SDA(10,22)

4

A

R167

100_0402_5%

1

R168

THERMD_P_R

C225

1000P_0402_50V7K

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C225

THERMD_N_R

Issued Date

1

2

+1.8V_VDDIO

U32

2

D+

3

D-

8

SCL

ALERT/THERM2#

7

SDA

2013/11/20 2014/11/09

R362

1

2

0_0603_5%

1

R91

THERM#

TMP451AIDQFR_D FN8_2X2

2

@

0_0402_5%

1

V+

4

6

5

GND

Compal Secret Data

C

1

C224

0.1U_0402_10V6K

2

Deciphered Date

@

R318

2

0_0402_5%

+3.3V_STBY

1

+1.8V_VDDIO

1

2

R166

R166 10K_0402_5%

10K_0402_5%

D

AP_OVERHEAT# (29,36)

TEMP_ALERT# (10)

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet

Compal Electronics, Inc.

TPM & TEMP SENSOR

Z3ENN M/B LA-B551P

E

of

21 42Thursday, June 19, 2014

of

21 42Thursday, June 19, 2014

of

21 42Thursday, June 19, 2014

3

4

0.1

A

M

AX98090AETL+T

B

C

D

E

1

2

3

4

+1.2V_GEN_AVDD

Follow vendor spec, 12/19

+1.8V_VDDIO

JP5

2

JP7

43x39

@

43x39

@

1

+

1.8V_VDDIO

C

226

R319

1

0_0603_5%

GEN1_I2C_SCL(10,21)

A

+

363

R

1

227

1U_0402_6.3V6K

2

1

2

1

2

C233

JP6

43x39

@

JP8

43x39

@

0.1U_0402_10V6K

1

C

2

HDSET_MIC(22,23)

HDSET_MIC(22,23) HDSET_GND(22,23)

DAP2_SCLK(10) DAP2_FS(10)

DAP2_DOUT(10)

DAP2_DIN(10)

GEN1_I2C_SDA(10,21)

CODEC_IRQ#(10)

DMIC_DATA(23) DMIC_CLK(23)

DAP_MCLK1(10)

2

0_0603_5%

16mA

0.1U_0402_10V6K

1

C234

2

Move R292 to Codec side, 04/09

1

25

L

1

FCM1608CF-121T03_2P

1

R169 2.2K_0402_5%

1

C239 1U_0402_6.3V6K

1

C240 1U_0402_6.3V6K

1

R170 10K_0402_5%

1

R292 22_0402_5%

1

R172 22_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.8V_CODEC

1

HPVDD

RCVP/LOUTL

RCVN/LOUTR

JACKSNS

HPGND

SPKLGND

1

17

1mA

13

SPKRVDD

HPSNS

SPKLP

SPKLN

SPKRP

SPKRN

CPVDD

CPVSS

SPKRGND

10

2

C

230

1

1U_0402_6.3V6K

1

C235

2

14

U33

Closed to IC PIN

SPKLVDD

4

HPL

5

HDSET_GND

6

HPR

39

40

16

15 12

11

8

9 7

3

2

23 24

CODEC_C1P

CODEC_C1N

JACKSNS

CODEC_CPVDD

CODEC_CPVSS

CODEC_REF

CODEC_VCM

C1P

C1N

REF

BIAS

1.8V_VDDIO_HP

+

1U_0402_6.3V6K

C

231

1U_0402_6.3V6K

1

C243

2

10U_0603_6.3V6M

1

2

1

C236

2

1

R171 0_0402_5%@

2.2U_0402_6.3V6M

2

1

C244

2

0.1U_0402_10V6K

1

C

228

2

1U_0402_6.3V6K

1

C237

2

1U_0402_6.3V6K

1

C

229

2

0.1U_0402_10V6K

1

C238

2

+MICBIAS

1

C241

C241 1U_0402_6.3V6K

1U_0402_6.3V6K

2

CODEC_HDSET_MIC

CODEC_HDSET_GND

DMIC_DATA_R

DMIC_CLK_R

MAX98090AETL+T_TQFN40_5X5

0x00100000

SA00007F200

22

20

21

33

32 30

31

36

37

34

19 18

35

41

28

27

DVDD

DVDDIO

MICBIAS

IN3

IN4

BCLK

LRCLK SDIN

SDOUT

SCL

SDA

IRQ

IN1/DMD IN2/DMC

MCLK

Thermal pad

29

DGND

38

26

AVDD

AGND

25

Closed to IC PIN

Compal Secret Data

2013/11/20 2014/11/09

B

Deciphered Date

C

D

117

R

1

0_0603_5%

R116

1

0_0603_5%

HPL (23)

HPR (23)

1

2

Custom

Date: Sheet

Closed to IC PIN

C242

C242 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1U_0402_6.3V6K

1

C245

2

Title

Size Document Number Rev

+

1.8V_VDDIO

2

+5V_SYS

2

1U_0402_6.3V6K

1

C246

2

Compal Electronics, Inc.

AUDIO CODEC

Z3ENN M/B LA-B551P

4mA

10U_0603_10V6M

1

C232

2

HDSET_GND (22,23)

SPK_L+ (23)

SPK_L- (23) SPK_R+ (23)

SPK_R- (23)

HDSET_MIC (22,23)

E

1

2

3

4

0.1

of

22 42Thursday, June 19, 2014

of

22 42Thursday, June 19, 2014

of

22 42Thursday, June 19, 2014

A

B

C

D

E

R

364

JIO1

1

2 3 4

5 6 7

8

9 10

HEAD_DET#

D

2

DMIC_CLK(22)

11

G1

12

G2

igital MIC

U

MIC1

1

DD

V

2

L

EFT/RIGHT

7

ND

G

8

G

ND

@

DMIC_DATA(22)

D

G

AKU240_8P

3

LK

C

4

ATA

5

ND

6

ND

D

MIC_CLK_D

MIC_DATA_D

D

0.1U_0402_10V6K

2

3

D21

D21 MESC5V02BD03_SOT23-3

MESC5V02BD03_SOT23-3

SCA00002M00

SCA00002M00 @ESD@

@ESD@

1

2

R

402 0_0402_5%

1

R

403 0_0402_5%

Change UMIC1/C301 to @(un-mount), 04/09 Move R402/R403 near to DMIC, 04/10

+1.8V_VDDIO

C339

1

2

Change R402@/R403@ to mount Add C339 0.1u at JMIC1.1(+1.8V_VDDIO), 04/09

2

D

MIC_CLK MIC_DATA

D

JMIC1

1

2

3

4

5

GND

6

GND

ACES_50279-0040N-001

CONN@

SP02000WI00

1

2

3

4

peaker Connector

S S

1

TIP_SENSE

DET_TRIGGER

RING2_SENSE

RING2

SLEEVE_SENSE

SLEEVE

100K_0402_5%

Q17

PK_R-_L PK_R+_L

GND

+1.8V_VDDIO

R180

S

1 2

3

4

1

C252

100P_0402_50V8J

2

1

C256

100P_0402_50V8J

2

9

5

14

7

15 6

17

3

10

1

2

1

D

2

G

S

3

J

SPK1

1 2

1

G

2

E&T_3806K-F02N-03R

CONN@

SP02E005320

HDSET_SW

FDV301N-NL_SOT23-3

PK_L-_L

S S

PK_L+_L

Change JSPK1 P/N to SP02E005320 and add JSPK2, 02/19

HPL_RL

HPR_RL

+3.3V_STBY

1

R179

R179 330K_0402_5%

330K_0402_5%

2

1

R181

@

R181

@

0_0402_5%

1

D

2

Q16

G

S

3

PLUG_DET_RC

J

SPK2

1

2

3

1

G

4

G

2

E&T_3806K-F02N-03R

CONN@

SP02E005320

+3.3V_STBY

1

2

1

+

1.8V_VDDIO

1

@

0_0402_5%

C

301

0.1U_0402_10V6K

2

Conn to Audio/B

1

2

10

PS_HPF05052-101000R

CONN@

1

C259

10P_0402_50V8J

2

2 3 4

5 6 7

8

9

RING4

RING4_SENSE

RING3

RING3_SENSE

HEAD_DET#

1

R405

MNTG_WP#(18)

Change JIO1.9 from AGND to MNTG_WP# and add R405 0ohm, 04/11

R182

R182 330K_0402_5%

330K_0402_5%

1

R183

10K_0402_5%

C258

1U_0402_6.3V6K

R405

0_0402_5%@

2

EMI@

1

L

26 PBY100505T-300Y-N_2P

S

PK_L-(22)

S

PK_L+(22)

1

SPK_R-(22) SPK_R+(22)

Change L26~L29 P/N to SM01000F100, follow EMI request, 01/07

2

3

4

26 PBY100505T-300Y-N_2P

L

28 PBY100505T-300Y-N_2P

L27 PBY100505T-300Y-N_2P

L29 PBY100505T-300Y-N_2P

2

1

2

EMI@

1

2

1

2

EMI@

HPL(22)

HPR(22)

MIC_PRSNT#(8)

+3.3V_STBY

HDSET_MIC(22) HDSET_GND(22)

@EMI@

S

1

@

EMI@

680P_0402_50V7K

C

247

2

SPK_R-_L SPK_R+_L

1

@EMI@

680P_0402_50V7K

C249

2

@

C251

100P_0402_50V8J

@

C255

100P_0402_50V8J

1

R320 0_0402_5%

PK_L-_L

PK_L+_L

1

2

3

1

C

248

2

C250

1

2

1

2

R178

10K_0402_5%

D

22

S

CA00002M00

@ESD@

1

MESC5V02BD03_SOT23-3

2

3

D23

SCA00002M00

SCA00002M00 @ESD@

@ESD@

1

MESC5V02BD03_SOT23-3

Change L30/L31 to 22ohm and R173/R176 to @(un-mount) for audio issue, 05/12

1

R173

4.7K_0402_5%@

1

R174

0_0402_5%

1

R175

0_0402_5%

2

C2570.1U_0402_10V6K

2

HPL_R

2

HPR_R

1

R176

4.7K_0402_5%@

2

0.5mA

U34

13

16

1

2 4

8

11 12

TS3A225ERTER_PWQFN16_3X3

SA000056S00

HDSET_SW_SOC#(10)

VDD

SCL

SDA ADDR_SEL

MIC_PRESENT

MIC_P MIC_N

L30

2

22_0402_5%

L31

2

22_0402_5%

FDV301N-NL_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Combo Jack & D-MIC & SPEAK

Size Document Number Rev

C

Z3ENN M/B LA-B551P

Date: Sheet

E

of

23 42Thursday, June 19, 2014

of

23 42Thursday, June 19, 2014

of

23 42Thursday, June 19, 2014

0.1

A

1

B

L

ID Sensor

+

2

3.3V_STBY

mA

0.1U_0402_10V6K

1

2

C319

51

U

2

V

DD

C

3

V

OUT

GND

1

APX9132GAI-TRG_SOT23-3

SA000079D00

R

332

1

1K_0402_5%

2

1

C320

10P_0402_50V8J

2

D

L

ID_OPEN (24,29,8)

E

1

Change U51 P/N to SA000079D00, 0303

2

Add C230 10P, follow vendor suggestion, 01/03

2

DEBUG CONNECTOR

T33

PAD @

T34

PAD @

T35

PAD @

T36

PAD @

3

PM_I2C_SDA_3.3V

HDMI_INT(16,9)

BR_UART1_RXD

BR_UART1_TXD

FORCE_RECOVERY#

SYS_RESET#

Add T33~T36 test point for debug, follow Google command, 03/07

+1.8V_VDDIO

1

R186 0_0402_5%

+1.8V_STBY_KBC

1

R187 0_0402_5%@

+3.3V_INA219

1

R188 2.2K_0402_5%

1

R190 0_0402_5%@

2

CORE_PWR_REQ(29,33,36,8)

+1.8V_SERVO_JTAG

HDMI_INT_R

+3.3V_INA219

JP4

1

SPI4_CS0_SERVO#(18)

SPI4_MISO_SERVO(18)

SPI_HOLD_SERVO#(18)

BOOT0_KBC(29)

BR_UART1_TXD(8)

SDMMC3_CD(27,8)

JTAG_TCK(29,8) JTAG_TMS(29,8)

JTAG_TDO(8)

JTAG_TRST#(8)

KBC_UART_TXD(29)

FORCE_RECOVERY#(26)

GOOG_DEV_MODE(8) SERVO_DBG_GPIO(8)

KB_COL_2(29) KB_ROW_2(29)

2

1

R2360_0402_5%

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

DC041309140

PANAS_AXK750347WG

CONN@

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

+1.8V_SPI_R

+1.8V_SPI

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

2

1

R2350_0402_5%

1

R1850_0402_5%

SPI4_SCK_SERVO (18) SPI4_MOSI_SERVO (18)

DEBUGGER_RESET# (26) BR_UART1_RXD (8)

POWER_BTN# (26,29) JTAG_TDI (8)

JTAG_RTCK (8) SYS_RESET# (21,25,30,36,8)

GOOG_RECOVERY_MODE (8) KBC_UART_RXD (29)

PM_I2C_SCL_3.3V

SPI_ROM_SERVO_WP# (18)

LID_OPEN (24,29,8)

KB_COL_1 (29) KB_ROW_1 (29)

KB_ROW_3 (29)

CPU_PWR_REQ (33,8)

+1.8V_VDDIO

0.1U_0402_10V6K

2

1

2

C261

1

R1892.2K_0402_5%

+1.8V_STBY_KBC

0.1U_0402_10V6K

1

C262

2

+3.3V_INA219

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

C

Change JP4 Symbol to DC041309140 for Google debug conn, 01/07

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Compal Electronics, Inc.

DEBUG CONN/LID SENSOR

Z3ENN M/B LA-B551P

4

0.1

of

24 42Thursday, June 19, 2014

of

24 42Thursday, June 19, 2014

of

24 42Thursday, June 19, 2014

E

1

2

3

4

e

MMC

S

DMMC4_DAT[7..0](8)

close ball

A

dd R343~R350 0ohm, 01/03

A

1

DMMC4_DAT0

S

DMMC4_DAT1

S

DMMC4_DAT2

S

DMMC4_DAT3

DMMC4_DAT4

S

DMMC4_DAT5

S

DMMC4_DAT6

S

DMMC4_DAT7

V

DDI_DSC

1

C267

0.1U_0402_1 0V6K

2

343 0 _0402_5%

R

344 0 _0402_5%

R

345 0 _0402_5%

R

346 0 _0402_5%

347 0 _0402_5%

R

348 0 _0402_5%

R

349 0 _0402_5%

R

350 0 _0402_5%

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

B

U

36

AA4

AA6

R10

A11

B13

D14

H10

H11 H12

H13 H14

J10 J11

J12 J13

J14

R12 R13

R14

U12 U13

U14

W10

W11 W12

W13 W14

AA1

AA2

AA8 AA9

AA11

AA12 AA13

AA14

AA7

AA10

U10

P10

H3

D

AT0

H4

D

AT1

H5

AT2

D

J2

D

AT3

J3

D

AT4

J4

D

AT5

J5

AT6

D

J6

D

AT7

K2

V

DDI

K4

VSSQ

Y2

VSSQ

Y5

VSSQ

A1 INDEX / NC

M7

VSS

P5

VSS VSS

U8

VSS

A4

NC

A6

NC

A9

NC

B2

NC NC

D1

NC

H1

NC

H2

NC

H8

NC

H9

NC NC

J1

NC

J7

NC

J8

NC

J9

NC

NC NC

NC

K1

NC

K3

NC

R1

NC

R2

NC

R3

NC

NC NC

NC

U1

NC

U2

NC

U3

NC

NC NC

NC

W1

NC

W2

NC

W3

NC

W7

NC

W8

NC

W9

NC NC

NC

NC NC

NC

NC NC

NC

RFU

U7

RFU

U6

RFU

T5

RFU

R5

RFU

169 ball eM MC

SDIN4E2-16G-T_TFBGA_1 69P@

V

CCQ

V

CCQ

V

CCQ

V

CCQ

CMD

CLK

RST# / NC

RFU

RFU RFU

RFU

M6

CC

N5

CC

T10

CC

U9

CC

K6

W4

Y4

AA3

AA5

W5

W6

U5

L4

K7

NC

K8

NC

K9

NC

K10

NC

K11

NC

K12

NC

K13

NC

K14

NC

L1

NC

L2

NC

L3

NC

L12

NC

L13

NC

L14

NC

M1

NC

M2

NC

M3

NC

M12

NC

M13

NC

M14

NC

N1

NC

N2

NC

N3

NC

N12

NC

N13

NC

N14

NC

P1

NC

P2

NC

P12

NC

P13

NC

P14

NC

T1

NC

T2

NC

T3

NC

T12

NC

T13

NC

T14

NC

V1

NC

V2

NC

V3

NC

V12

NC

V13

NC

V14

NC

Y1

NC

Y3

NC

Y6

NC

Y7

NC

Y8

NC

Y9

NC

Y10

NC

Y11

NC

Y12

NC

Y13

NC

Y14

NC

AE1

NC

AG2

NC

AH4

NC

AH6

NC

AH9

NC

AH11

NC

AG13

NC

AE14

NC

H6

H7

K5

M5

M8 M9

M10

N10

P3

0.1U_0402_1 0V6K

C

1

C

264

2

SYS_RESET#_EMMC

200mA

1

C

4.7U_0603_6 .3V6M

2

R

113

2

0_0603_5%

265

C263

0.1U_0402_1 0V6K

R341

1

2

0_0402_5%

2

0_0402_5%

2

0_0402_5%

SDMMC4_CMD

R342

1

SDMMC4_CLK

Add R341/R342 0ohm, 01/03

R121

1

150mA

1

2

SYS_RESET#

3.3V_RUN

+

+1.8V_VDDIO

1

C266

4.7U_0603_6 .3V6M

2

1

R191

4.7K_0402_5 %

2

D

1.8V_VDDIO

R

110

0_0603_5%

+

2

SDMMC4_CMD (8)

SDMMC4_CLK (8)

1

C328

22P_0402_5 0V8J @

SYS_RESET# (21,24,3 0,36,8)

U

36

U

36

U36

2

Add C328@ 22P, follow RF request, 01/14

K

IN16G@

A00006MG60

S

K

ingston 16G KE4CN4K6A-E58

YN16G@

H

S

A00007QG20

Hynix 16G H26M52103FMR F:0X03

KIN32G@

SA00006DZ60

Kingston 32G KE4CN5B 6A-E58

HYN32G@

SA00007QH20

Hynix 32G H26M64103EMR F:0X03

KIN16GA@

SA00007Z600

Kingston 16G EMMC16G-S100-A06

E

1

2

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2013/11/20 2014/11/09

Compal Secret Data

C

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

eMMC

Z3ENN M/B LA-B551P

0.1

of

25 42Thursday, June 19, 2014

of

25 42Thursday, June 19, 2014

of

25 42Thursday, June 19, 2014

E

224

R

223

R

215

R

217

R223

R222

R217

R216

R222

YN2G@

H

D028100380

S

RES 1/16W 100K +-5% 0402

S

H

YN2G@

S

D028100380

RES 1/16W 100K +-5% 0402

S

H

YN2G@

S

D028100380

S

RES 1/16W 100K +-5% 0402

H

YN4G@

D028100380

S

S RES 1/16W 100K +-5% 0402

HYN4G@

SD028100380

S RES 1/16W 100K +-5% 0402

HYN4G@

SD028100380

S RES 1/16W 100K +-5% 0402

KIN2G@

SD028100380

S RES 1/16W 100K +-5% 0402

KIN2G@

SD028100380

S RES 1/16W 100K +-5% 0402

KIN2G@

SD028100380

S RES 1/16W 100K +-5% 0402

1

2

3

+

1.8V_VDDIO

0_0402_5%

R

100K_0402_5%

R213

+1.8V_VDDIO

100K_0402_5%

R217

100K_0402_5%

R224

+1.8V_VDDIO

10K_0402_5%

R229

10K_0402_5%

R233

@

D

100K_0402_5%

1

R

206

207

@

2

100K_0402_5%

1

2

100K_0402_5%

1

@

2

100K_0402_5%

1

@

2

10K_0402_5%

1

2

10K_0402_5%

1

2

B

OOT SELECT

2

B

OOT_SEL0 (10)

B

OOT_SEL1 (10)

OOT_SEL2 (10)

100K_0402_5%

1

R214

@

NOTE:

2

1011: EMMC BOOT X8 - BOOT MODE OFF 1000: SPI BOOT

100K_0402_5%

1

RAM CODE

R218

@

2

100K_0402_5%

1

R225

2

10K_0402_5%

1

R230

BOARD ID STRAPS

2

10K_0402_5%

1

R234

@

2

B B

OOT_SEL3 (10)

RAM_CODE0 (10)

SPI4_SCK (10,18) SPI4_MOSI (10,18) SPI4_MISO (10,18)

RAM_CODE0 Pin Status

0001 0100

HYNIX 2G

NOTE: RAM_CODE[1:0]:SELECTS SDRAM CO NFIGURATION FROM BCT RAM_CODE[3:2]:SELECTS SECONDAR Y BOOT DEVICE FROM BCT

BD_ID_STRAP3 (10) BD_ID_STRAP2 (10) BD_ID_STRAP1 (8)

BD_ID_STRAP0 (8)

ST PAD 100K INT RES VIHMIN 1.35V VILMAX 0.45V

Change board ID to Pre-MP 0011, 06/19

HYNIX 4G

0110

KINGSTON 2G

C

G

PIO_PI0 (10)

P_FORCE_RECOVERY# (10)

A A

RM_JTAG1 (10)

A

RM_JTAG0 (10)

DEBUGGER_RESET# (24)

KB_RST# (29)

+1.8V_VDDIO

1

R226

47K_0402_5%@

2

ONKEY# (8)

1

@

C271

C271 100P_0402_50V8J

100P_0402_50V8J

2

1

0_0402_5%

R

205

204

@

2

100K_0402_5%

1

R212

R211

R215

R222

Change R215@~R218@/R222~R225 to 100K, follow nV comment, 01/14

R227

@

R231

2

100K_0402_5%

1

R216

@

2

100K_0402_5%

1

R223

@

2

10K_0402_5%

1

R228

@

2

10K_0402_5%

1

R232

2

3

4

3

4

1000P_0402_50V7K

@

T12

T12 PAD

PAD

AOZ8231ADI-05_DFN1006-2

1

2

B

+

1.8V_VDDIO

100K_0402_5%

1

R

202

@

T

10

PAD

AOZ8231ADI-05_DFN1006-2

@

T11

T11 PAD

PAD

C269

1000P_0402_50V7K

D12

@

202

2

1

100K_0402_5%

1

R209

D10

@

2

+2.5V_AON_RTC

1

R219

R219 200K_0402_5%@

200K_0402_5%@

2

KB_RST#_R

AOZ8231ADI-05_DFN1006-2

1

D11

2

@

2

0.1U_0402_10V6K

1

C272

2

Change U15@ P/N from SA00001FW00 to SA000023400, Change D13 to @ and U15@ to mount, follow Google comment, 05/21

Change U15 to single channel SA00000L800, 05/22

1

R

203

2

R

208

1

2

2.2K_0402_5%

1

R210

2

1

R220 0_0402_5%

1

R221 0_0402_5%

+1.8V_STBY_KBC

@

C270

1

2

1

NC

2

A

1

D13 RB751V-40_SOD323-2

100K_0402_5%

GPIO_PI0 G

PIO_PI1 GPIO_PK7 GPIO_PJ7

100K_0402_5%

2

5

U15

P

4

Y

G

SN74LVC1G07DCKR_SC70-5

3

SA00000L800

2

@

A

F

ROM DEBUG

BOARD CONNECTOR

1

ORCE_RECOVERY#(24)

F

DEBUG FORCE REC SW

SW1

EVQPLMA15_4P

1

2

G

5

6

@

JP9

1

FORCE_RECOVERY#

1

2

KB_RST#_R

2

3

POWER_BTN#

3

4

5

6

7

GND1

8

GND2

E-T_6705K-Y06N-00L

CONN@

2

3

CONN@

Add JP9 conn for debug, 12/27

Change SW1/SW2/SW3 to @(un-mount), 05/28

DEBUG RESET SW

EVQPLMA15_4P

1

2

G

5

6

@

POWER_BTN#(24,29)

DEBUG POWER SW

SW3

EVQPLMA15_4P

3

1

2

4

G

5

6

@

SW2

G

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

SWITCHES & STRAPS

Z3ENN M/B LA-B551P

E

of

26 42Thursday, June 19, 2014

of

26 42Thursday, June 19, 2014

of

26 42Thursday, June 19, 2014

4

0.1

A

B

C

D

E

O

G

UT

ND

O

C

+

VDD_3V3_SD_CARD

1

2

3

Active low

SDMMC3_CD(24,8)

Add R385~R388 0ohm damping to SDIO bus, Add C335@~C338@ 4.7pF to SDIO bus for reserve, Follow EMI request, 03/07

1

R238 100_0402_5%

+

3.3V_SYS

1

C

276

0.1U_0402_10V6K

E

N_VDD_SD(8)

SDMMC3_DAT1

SDMMC3_DAT0

0.1U_0402_10V6K

2

22U_0603_6.3V6M

1

SDMMC3_CLK

6

/O4 I

2

SDMMC3_CMD

/O2 I

3

SDMMC3_DAT3

5

4

D14

DD

/O3

AZC099-04S.R7G_SOT23-6

I

V

SC300001G00

SC300001G00 @ESD@

@ESD@

ND

/O1

G

I

2

1

SDMMC3_DAT2

Change D14/D15 P/N to SC300001G00, follow ESD request, 01/07

1

C

279

1

R

300

2

100_0402_5%

SDMMC3_CD#_R

5

6

3

4

D15

D15 AZC099-04S.R7G_SOT23-6

VDD

GND

2

AZC099-04S.R7G_SOT23-6

I/O3

SC300001G00

SC300001G00 @ESD@

@ESD@

I/O1

1

SDMMC3_WP#

I/O4

I/O2

U

39

5

I

N

2

4

E

N

G524B1T11U_SOT23-5

SA00006Y800

Change U39 from SA00007M800 to SA00006Y800, 0505

+3.3V_TOUCHPAD

SDMMC3_DAT[3..0](8)

100K_0402_5%

2

+

VDD_3V3_SD_CARD

+1.8V_VDDIO

1

R237

2

1

D

Q62

S

3

0612 modified.

R

321

1

2

1

R355

100K_0402_5%

2

1

C

277

0.1U_0402_10V6K

2

DMMC3_CMD(8)

S

DMMC3_CLK(8)

R385 0_0402_5%

R386 0_0402_5%

R387 0_0402_5%

R388 0_0402_5%

1

C335 4.7P_0402_50V8B@

1

C336 4.7P_0402_50V8B@

1

C337 4.7P_0402_50V8B@

1

2

C338 4.7P_0402_50V8B@

SDMMC3_WP#(8)

0_0603_5%

R

412

1

0_0603_5%

SDMMC3_DAT0

SDMMC3_DAT1

SDMMC3_DAT2

SDMMC3_DAT3

2

G

LBSS138LT1G_SOT-23-3

SB00000QO00

Add Q62/R355 cause the SD card conn is normal close, 01/06

1

2

1

C

278

22U_0603_6.3V6M

2

S

DMMC3_CMD

DMMC3_CLK

S

2

SDMMC3_WP#

SDMMC3_DAT0_R SDMMC3_DAT1_R SDMMC3_DAT2_R

SDMMC3_DAT3_R

SDMMC3_CD#_R

S

D Card Socket

J

SD1

5

V

DD

3

MD

C

6

C

LK

7

SS

V

4

VSS

8

DAT0

9

DAT1

1

DAT2

2

CD/DAT3

10

WP_SW

11

CD_SW

SP07000VH00

T-SOL_156-2000302604

CONN@

CLOSE : connect to GND OPEN : Floating

GND_SW

1

12

13

2

1

@

R118

R115

1K_0402_5%

3

R331

100K_0402_5%

TOUCH_IRQ#(10)

4

A

B

1K_0402_5%

2

GEN2_PS2_CLK_3.3V GEN2_PS2_DAT_3.3V

Change R115/R118 to @(un-mount), 01/14

+1.8V_VDDIO

1

G

2

G

2

1

3

D

S

D

S

Q65

FDV301N-NL_SOT23-3

Add Q65/R375@ for TP 3.3V transfer to CPU 1.8V, 01/14

+3.3V_TOUCHPAD

1

R375

R375 10K_0402_5%@

10K_0402_5%@

2

TOUCH_IRQ#_R

+3.3V_LP0

2013/11/29 ,no connect

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

1

C280

1U_0402_6.3V6K

2

GEN2_PS2_CLK_3.3V

GEN2_PS2_DAT_3.3V

GEN2_I2C_SDA_3.3V_TP(10)

GEN2_I2C_SCL_3.3V_TP(10)

2013/11/20 2014/11/09

+3.3V_TOUCHPAD

R239

2

0_0603_5%

SENSOR OFF

2013/11/29 ,no connect

Compal Secret Data

Deciphered Date

1

C281

4.7U_0603_6.3V6M

2

GEN2_PS2_CLK_3.3V GEN2_PS2_DAT_3.3V

TOUCH_IRQ#_R

D

Touch PAD Conn.

1 2 3 4 5 6

7 8

Change JTP1 P/N to SP01001AB00, 01/02

JTP1

1 2 3 4 5

9

6

G1

10

7

G2

8

PS_HPF10052-08M000R

CONN@

Compal Electronics, Inc.

Title

SD CONN AND TOUCHPAD

Size Document Number Rev

C

Z3ENN M/B LA-B551P

Date: Sheet

E

of

27 42Thursday, June 19, 2014

of

27 42Thursday, June 19, 2014

of

27 42Thursday, June 19, 2014

3

4

0.1

D

+

1.8V_VDDIO

G

2

TS@

1

3

S

FDV301N-NL_SOT23-3

GEN2_I2C_SCL_3.3V

T

S_RSTQ#

D

Q18

TS_RSTQ#

+

3.3V_LP0

1

R

241

10K_0402_5%@

2

D29

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

SC300001G00

SC300001G00 @ESD@

@ESD@

T

ouch Screen

Change R241 to @(un-mount), follow Google command, 03/11

JTS1

1

2

3

4

5

6

7

GND

8

GND

SP010013W10

ACES_50208-00601-P01

CONN@

3

I/O2

2

GND

1

I/O1

Add D29, follow ESD request, 01/07

1

D

1

2

C

+

3.3V_LP0

1

2

1

C284

TS@

C284

TS@

0.1U_0402_10V6K

2

R

376

10K_0402_5%@

+5V_VDD_TS

TS_RESET#(10)

TS_IRQ#_R

GEN2_I2C_SDA_3.3V_TS(10)

GEN2_I2C_SCL_3.3V_TS(10)

+5V_SYS

IN

FLAG#

EN

B

100K_0402_5%

SN74LVC1G07DCKR_SC70-5

1

OUT

2

GND

Add Q66/R376@ for TS 3.3V transfer to 1.8V, 01/15

+

1.8V_VDDIO

1

R

242

TS@

242

TS@

G

2

SA00000L800

TS@

G

2

Q66

3

S

@

FDV301N-NL_SOT23-3

+1.8V_VDDIO

5

U53

NC

4

Y

TS@

3

R98

1

0_0603_5%

1

C283

2.2U_0402_6.3V6M

2

P

A

G

A

1

TS_IRQ#(10)

2

Change R242 from 10K to 100K, if use U53 the pull high resistor have to mount, 04/11 Change Q66 to @(un-mount), U53 buffer and R242 100K pull high resistor change to mount, follow Google comment, 05/05

+5V_SYS

U45

5

1

TS@

3

TS_SHDN#(10)

C282

4.7U_0603_6.3V6M

2

R301

TS@

1

2

100_0402_5%

3

4

NCP380HSN05AAT1G_TSOP5

SA000069N00

SA000069N00 TS@

TS@

E

1

2

GEN2_I2C_SDA_3.3V

TS_IRQ#

3

4

Security Classification

2013/11/20 2014/11/09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2013/11/20 2014/11/09

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Compal Electronics, Inc.

TOUCH SCREEN CONN

Z3ENN M/B LA-B551P

28 42Thursday, June 19, 2014

E

of

4

0.1

1U_0402_6.3V6K

1

2

3

4

+

3.3V_STBY

1

C

286

2

+1.8V_STBY_KBC

PMIC_WA RM_RESET#(10, 30,8)

EC_BL_OVERRIDE(15)

BOOT0_KBC(24)

KB_RST#(26,29)

POWER _BTN#(24,26,29)

EC_ENTERING_RW

KB_ROW _2(24,29)

KB_COL_2_SW(29)

2

68mA

390

R

1

0_0402_5%

0612 modified.

+1.8V_STBY_KBC

R263

47K_0402_5%

2

0_0402_5%

A

2

R

322

1

0.01_0603_1%

+1.8V_STBY_KBC

1

2

R282

A

U

18

1

N

I

2

G

ND

3

S

HDN#

NCT3705U-18_SOT23-5

5

O

UT

4

B

YP

1

2

Change C299 P/N to SE025103K80, 01/02

2

0.1U_0402_10V6K

1

C290

C288

2

C288

2

1U_0402_6.3V6K

1

C291

2

R285 33_0402_5%

EC_ENTERING_RW

1

R256

2

1

R254 0_0402_5%

47K_0402_5%

2

1

R257

@

R257

@

47K_0402_5%

2

1

C293

2200P_0402_50V7K

2

U43

R264

R264 47K_0402_5%

47K_0402_5%

U43

SLG4K4215

TDFN12

3

A

2

PWR_BTN_L

10

EC_ENTERING_RW

9

KSO

6

KSI_SW

7

GND

13

PAD

SA00007L000

1

2

1

B

1.8V_STBY_KBC

+

391

R

1

2

0_0402_5%

C

299

0.01U_0603_50V7K

246mA

0.1U_0402_10V6K

1

C289

2

0.1U_0402_10V6K

1

C292

2

1

Add R372@/R373@ 47K pull high to +1.8V_STBY_KBC, follow vendor suggestion, 01/10

1

287

C

4.7U_0603_6.3V6M

2

U

42

LQFP64

STM32L100R8LQFP64

1

VLCD

32

VDD1

48

VDD2

64

VDD3

19

VDD4

13

VDDA

11

PC3

5

PH0

6

PH1

60

BOOT0

7

NRST

31

VSS1

47

VSS2

63

VSS3

18

VSS4

12

VSSA

S IC STM32L100RBT6TR LQFP 64P MUC

S IC STM32L100RBT6TR LQFP 64P MUC SA00007L200

SA00007L200

KB_ROW _2_SW

KB_COL_2

R372 47K_0402_5%

R373 47K_0402_5%

22mA

1

VDD

4

Y

12

R336 0_0402_5%

EC_RST_L

EC_IN_RW

KSO_SW

R336 0_0402_5%

11

5

8

KSI

B

PC13/RTCAFA/WKUP2

PC14/OSC32_IN

PC15/OSC32_OUT

@

1

@

1

C294

C294 1U_0402_6.3V6K

1U_0402_6.3V6K

2

@

T14

1

PA0 PA1

PA2 PA3

PA4 PA5

PA6 PA7

PA8 PA9

PA10 PA11 PA12

PA13

PA14 PA15

PB0 PB1

PB2

PB3 PB4 PB5

PB6 PB7

PB8 PB9

PB10 PB11

PB12

PB13 PB14 PB15

PC0 PC1

PC2

PC4

PC5

PC6 PC7 PC8

PC9

PC10

PC11 PC12

PD2

2

R265 0_0402_5%@

2

1

EC_IN_RW (10)

KB_ROW _2_SW (29)

KB_COL_2 (24,29)

14

15 16

17

HOLD

20

21 22

23

41 42

43 44

45 46

JTAG_TMS_EC

49

JTAG_TCK_EC

50

26

27 28

55

EC_PB3

56

57 58

59

61 62

29 30

33 34

35 36

8

9 10

24

25

37

CHARGER_INT#

38

39 40

51 52

53

2

3 4

54

R262

1

0_0603_5%

1

+1.8V_STBY_KBC

2

KB_RST# (26,29)

2

R26647K_0402 _5%

+1.8V_VDDIO

2

+3.3V_LP0

D

G781_ALERT#

G781_THERM#

+3.3V_STBY

+

1.8V_STBY_KBC

1

248

R

R 100K_0402_5%

100K_0402_5%

2

C

+

1.8V_VDDIO

1

R

249

100K_0402_5%

2

ACOK_PMU (36)

KBC_SPI_CS (8 ) KBC_SPI_SCK ( 8)

KBC_SPI_MISO (8)

KBC_SPI_MOSI (8)

KBC_UART_TXD (24)

KBC_UART_RXD ( 24)

CHARGING (19) PMIC_PW RON (36)

TPS_RST (32)

KB_ROW _0 ( 29) KB_ROW _9 ( 29)

BOOT1_CHGEN# (31 )

EC_WP# ( 18)

CHARGER_I2C_SCL_3.3 V (31)

CHARGER_I2C_SDA_3. 3V (31)

KB_ROW _1 ( 24,29)

PWR_LE D0 (19)

CHARGER_THR_ALE RT (31)

KB_ROW _2 ( 24,29)

KB_ROW _3 ( 24,29) KB_ROW _4 ( 29)

KB_ROW _5 ( 29)

KB_ROW _6 ( 29)

KB_ROW _7 ( 29) KB_ROW _8 ( 29)

KB_ROW _11 (29) KB_ROW _10 (29)

CORE_PW R_REQ (24,33,36, 8) KB_COL_0 (2 9)

KB_COL_1 (2 4,29) KB_COL_2 (2 4,29)

KB_COL_3 (2 9) KB_COL_4 (2 9)

LID_OPEN (24,8)

KB_COL_5 (2 9) KB_COL_6 (2 9)

KB_COL_7 (2 9)

1

R274 0_0402_5%

R250 0_0402_5%@

R251 0_0402_5%@

R335 0_0402_5%

R252 0_0402_5%@

Add R407 10K to EC pin57(POWER_BTN#), follow NV comment, 05/22

R275 0_0402_5%

R407 10K_0402_5%

Add net CHARGER_THR_ALERT, 02/26

2

1

2

BAT_LED1 (19)

1

2

1

2

1

2

1

2

1

2

1

10K_0402_5%

CHARGER_THR_ALE RT

Change G781 thermal sensor related parts to @(un-mount), 04/10

1

+1.8V_STBY_KBC

2

R255100K_0402_5%

+3.3V_STBY

1

R392

2

AP_OVERHEAT# (21,36)

PWR_LE D1 (19)

HOLD_R (8)

JTAG_TMS (24,8)

KB_ROW _12 (29)

JTAG_TCK (24,8)

PMU_RESET_IN# (36)

POWER _BTN# (24,26,29)

2

R253100K_0402_5%

KBC_IRQ# (10)

@

R394

@

R394

@

1

0_0402_5%

R395

@

R395

@

1

0_0402_5%

Placement near to charger IC

1

R384

@

R384

@

0_0402_5%

+3.3V_STBY

+1.8V_VDDIO

CHARGER_I2C_SCL_3.3 V

CHARGER_I2C_SDA_3. 3V

@

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

C

1

R396

@

R396

@

U52

1

R397

2

2013/11/20 2014/11/09

U52

2

DXP+

3

2

DXN-

8

0_0402_5%

SCLK

7

SDATA

G781P8F_MSOP8

SA007810140

Change G781 thermal sensor related parts to @(un-mount), 04/10

0_0402_5%

1

VCC

6

4

5

GND

@

Deciphered Date

G781_ALERT#

G781_THERM#

ALERT#

THERM#

Compal Secret Data

2

@

0_0402_5%

@

D

R383

C334

1

2

0.1U_0402_10V6K

1

2

E

C Debug/Flash

E

+

1.8V_STBY_KBC

J

TAG_TMS_EC

J

TAG_TCK_EC

334

R

1

K

B_RST#

2

0_0402_5%

Add EC debug/flash function, 12/31

Reset Button / Battery discharge screw hole

SW4

EVQPLMA15_4P

1

2

BI_GATE

DMN66D0LDW -7_SOT363-6

KB_ROW _12( 29)

KB_ROW _11( 29)

KB_ROW _10( 29) KB_ROW _9(29)

KB_ROW _8(29)

KB_ROW _7(29)

KB_ROW _6(29) KB_ROW _5(29) KB_ROW _4(29) KB_ROW _3(24,29)

KB_ROW _2_SW(29)

KB_ROW _1(24,29)

KB_ROW _0(29)

3

4

G

5

6

+3.3V_STBY

3

D

G

5

S

Q64A

4

Change JP3.1 to NC, follow KB spec, 01/13

POWE R_BTN#(24,26,29)

KB_COL_0(29)

KB_COL_1(24,29)

KB_COL_2_SW(29)

KB_COL_3(29)

KB_COL_4(29)

KB_COL_5(29)

KB_COL_6(29)

KB_COL_7(29)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

EMBEDDED CONTROLLER

Z3ENN M/B LA-B551P

BI_GATE

2

R374

R374 330K_0402_5%

330K_0402_5%

1

BI_GATE_R

1

C325

0.1U_0402_16V4Z

6

D

G

2

S

1

2

Add reset key function, follow acer request, 01/10

Change R374 to 330K, follow Google comment, 01/15

1 2

3 4

5 6

7

8

9

10

11

12

13 14

15 16

17 18

19

20

21

22

23 24

CVILU_CF31241D0R4-10-N H

SP01001I000

E

T

17

PAD@

18

T

PAD@

T

19

PAD@

T

21

PAD@

20

T

PAD

@

BI_GATE (31,32)

KB_RST#

Q64B

DMN66D0LDW -7_SOT363-6

JP3

1 2

3 4

5 6

7

8

9

10

11

12

13 14

15 16

17 18

19

20

21

22

25

G1

23

26

G2

24

CONN@

of

29 42Thursday, June 19, 2014

of

29 42Thursday, June 19, 2014

of

29 42Thursday, June 19, 2014

1

2

3

4

0.1

C

4

1

R268 470_040 2_5%

2

SYS_RESET# (21 ,24,25,36,8)

1.8V_VDD IO

+

2

R

277

0_0402_ 5%@

1

C

297

0.1U_040 2_10V6K

2

SYS_RESET _R#

B

RB751V-40_SOD323-2

1

2

D18

SCS0000 0Z00

R106

1

2

4.02K_04 02_1%

1

C98

0.1U_040 2_10V6K

2

5

14

U

P

2

O

I

NC

G

SA00001 NQ00

3

74LVC1G 17GW_TSSO P5

Change U14 P/N to SA00001NQ00, 02/19

A

1.8V_STB Y_KBC

+

2

R

276

0_0402_ 5%

1

5

U44

1

P

PMU_SYS_RE SET#(36)

PMIC_W ARM_RESET#(10,29 ,8)

A

4

Y

2

B

G

NC7SZ08 P5X-G_SC70-5

3

Change R106 to 4.02K, follow nV comment, 01/14

D

rystal for PMIC

C

32.768KH Z_12.5PF_Q13F C135000040

A

S3720_X IN32K(36)

C

295

10P_040 2_50V8J

Change C295/C296 to 10p and mount, follow vendor suggestion, 03/05

1

Y

2

E

hange Y2 P/N to SJ100001K00, 01/02

C

2

1

2

A

S3720_X OUT32K (36)

C

296

10P_040 2_50V8J

1

RAIL DISCHARGE

2

+5V_STB Y

TEGRA +3.3V SEQUENCING ENABLE AFTER RTC RAIL IS UP FOR RAILS OFF IN LP0

R303

100K_0402_5%

+3.3V VDD GATING FOR RAILS ON IN LP0

1

R269 0_0805_ 5%@

U49

PMU_REG EN3(30,36)

PMU_REG EN1(30,36)

3

PMU_REG EN1(30,36)

"ENABLE AFTER RTC RAIL IS UP"

1

R270 0_0402_ 5%

R271 0_0402_ 5%@

R290 0_0402_ 5%

2

1

2

1

2

C1710.1U_0402_ 10V6K

@

1

2

1

2

C1720.1U_0402_ 10V6K

@

+3.3V_SYS

EN_RUN_ VREG

+5V_SYS

+3.3V_SYS

U49

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

APE8990 GN3B DFN 14P

SA00006 FD00

R272 0_0805_ 5%@

+1.8V VDDIO GATING TEGRA +1.8V VDDIO SEQUENCING FOR RAILS OFF IN LP0

1

R273 0_0805_ 5%

+1.8V_VD DIO

1

@

C300

0.1U_040 2_10V6K

4

0.1U_040 2_10V6K

2

PMU_REG EN3(30,36)

R273 0_0805_ 5%

U47

A2

B2

TPS2290 8YZTR_DSBGA4

@

2

VOUT

GND

A1

B1

VIN

ON

2

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

1

2

+1.8V_VD DIO_LP0_OFF

+3.3V_RU N

1

2

C298 33 0P_0402_50V8 J

1

2

C304 33 0P_0402_50V8 J

+3.3V_LP 0

VGTH(MAX)=1.5V

PMU_REG EN1(30,36)

1M_0402 _5%

+5V_STB Y

R306

1

2

@

VGTH(MAX)=1.5V

SB00001 3K00

S TR DMN6 3D8LDW-7 2N SOT363-6

PMU_REG EN3(30,36)

1

R310

1M_0402 _5%

@

2

1

PMU_REG EN1#

2

R307

1

100K_0402_5%

PMU_REG EN3#

+5V_SYS

2

R304

@

100K_0402_5%

1

3

Q53B

Q53B S TR DMN6 3D8LDW-7 2N SOT363-6

S TR DMN6 3D8LDW-7 2N SOT363-6

5

SB00001 3K00

4

+5V_SYS

2

@

R309

100K_0402_5%

1

3

Q56B

5

4

+1.8V_VD DIO

1

2

6

S TR DMN6 3D8LDW-7 2N SOT363-6

1

+3.3V_LP 0

1

R308

R308 36_0603 _1%

36_0603 _1%

2

6

S TR DMN6 3D8LDW-7 2N SOT363-6

Q56A

SB00001 3K00

Q56A

SB00001 3K00

2

1

R305

R305 36_0603 _1%

36_0603 _1%

Q53A

SB00001 3K00

Q53A

SB00001 3K00

2

PMU_REG EN1#

1/18 follow nvidia suggestion

2

3

4

Security Class ification

2013/11/ 20 2014/11/ 09

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/ 20 2014/11/ 09

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

LOAD SW, HW PARTS

Z3ENN M/B LA-B551P

E

0.1

of

30 42Thursday, June 19 , 2014

of

30 42Thursday, June 19 , 2014

of

30 42Thursday, June 19 , 2014

5

@

C1

P

0.01U_0402_25V7K

1

2

P

Q2

1 2 3

1

2

100K_0402_5%

PR11

PR11 3M_0402_5%

3M_0402_5%

PR14

1

3

1 2

3

PC3

0.1U_0402_25V7K

1

2

1

2

PQ18

Q2

AO4406AL_SO8

4

1

2

BATT_ACDRV(31)

AC_DET (31)

PDTC115EU_SOT323-3

BQ24_AC_N(31)

BQ24_AC_P(31)

VDD_ACIN1(31)

BQ24735_REGN

P

Q1

+

VDD_ACIN

D

432K_0402_1%

AC_DET(31)

66.5K_0402_1%

BATT_ACDRV(31)

C

B

+3.3V_STBY

1

2

3.9_0603_1%

C9

C9 P

P

2.2U_0805_25V6K

PR118

100K_0402_5%

PR120

100K_0402_5%

R5

R5 P

P

3.9_0603_1%

1

2

+VDD_ACIN

1

2

1

2

1

2

G

1

2

100K_0402_5%

R4

R4 P

P

1

P

R6

2

1

PR8

2

ADAPDET(31)

AON6414AL_DFN8-5

5

PC2

2200P_0402_50V7K

+VDD_ACIN

PR119

1

D

S

3

PQ19

2N7002KW_SOT323-3

Q1

4

@

PR7

PQ4

PQ4 SI1304BDL-T1-GE3 _SOT323-3

SI1304BDL-T1-GE3 _SOT323-3

1

3

D

S

D

S

G

2

VBATT_CMSRC_GATE

1M_0402_5%

1

2

4

DD_ACIN1 (31)

V

P

R1

8 7 6

+

VDD_ACIN1_R

5

AC_OK(10,36)

R1

0.01_1206_1%

1

2

1

PC7

2

1

2

PC17

0.1U_0402_25V7K

PR164.02K_0402_1%

1

PR17 4.02K_0402_1%

1

PR19 10K_0402_1%

PR20

PR20 100K_0402_1%

100K_0402_1%

2

0.1U_0402_25V7K

PC18

2

AC_DET(31)

4

@

3

0_0402_5%

1

PC8

2

0.1U_0402_25V7K

1U_0603_25V6

BATT_CMSRC_R

BATT_ACDRV_R

TP1367

P

R3

2

1U_0603_25V6

2

21

1

2

3

4

5

1

2

PC15

PD1

BAT54CW_SOT323-3

1

PAD

ACN

ACP

CMSRC

ACDRV

ACOK

PC26

@

+3.3V_STBY

+

VDD_ACIN1_R2

+VDD_ACIN

3

1

+VDD_CHARGER

1

PR10

2

10_1206_1%

+VDD_CHARGER_R

20

6

@

0.1U_0402_25V7K

B

Q24_AC_N (31)

B

Q24_AC_P (31)

2

+VDD_BAT_BACK

1

+VDD_PACK_L

19

VCC

PHASE

ACDET

IOUT

7

2

PR22

0_0402_5%

1

PC14

@

3

VDD_MUX

+

1

2

PC4

BQ24735_PHASE_R

1

0.1U_0402_25V6

PQ5 SIS412DN-T1-GE3_POWERPAK8-5

2

1

PD3

2200P_0402_50V7K

2

DH_CHG

18

HIDRV

SDA

8

CHARGER_I2C_SDA_3.3V

PD3

BAT54CW_SOT323-3

BQ24735_PHASE

1

2

PR12 0_0603_5%

3

BQ24735_REGN

16

17

BTST

REGN

LODRV

GND

SRP

SRN

BATDRV

SCL

ILIM

9

10

BATT_ILIM

PC27

CHARGER_I2C_SCL_3.3V

0.01U_0402_25V7K

PQ5 SIS412DN-T1-GE3_POWERPAK8-5

4

DH_CHG

PC161U_0402_16V6K

1

2

PQ6

DL_CHG

BQ24735_SR_P

BQ24735_SR_N

BQ24735_BATDRV

(29,31)

1

2

2N7002KW_SOT323-3

4

PR23

100K_0402_5%

PQ7

15

14

13

12

11

PU1

PU1 BQ24735RGRR_QFN20_3P5X3P5

BQ24735RGRR_QFN20_3P5X3P5

1

PC5

2

10U_0805_25V6K

5

BATTDRV(31)

1

2

3

+VDD_PACK_L

5

SIS412DN-T1-GE3_POWERPAK8-5

1

2

3

PR18

4.02K_0402_1%

1

2

+3.3V_STBY

1

PR21

316K_0402_1%

2

1

PR24

PR24 0_0402_5%

0_0402_5%

2

1

D

2

G

S

3

PC6

10U_0805_25V6K

1

2

PR25

100_0402_5%

1

PC28

0.1U_0402_10V6K

+

VDD_BAT_BACK

PR78

@

BATTDRV (31)

2

Need chage to SE095104K80 sym bol

+3.3V_STBY

2

P

Q3

AON6414AL_DFN8-5

1 2 3

1

@

1

PR9

2

PC13

2

100K_0402_5%

0.01U_0402_25V7K

PL1

3.3UH_PCMB063T-3R3MS_6.5A_20%

1

PC90

@

1000P_0402_50V7K

PR27

47K_0402_5%

2

BOOT1_CHGEN# (29)

1

2

4.7_1206_5%

1

2

1

2

P

J6

@

J6

@

1

2

1

2

JUMP_43X118

5

1

PR15

0.01_1206_1%

1

2

0.1U_0402_25V7K

1

2

PC24

1

2

PC11

PC10

10U_0805_25V6K

4

+VDD_PACK_R

3

PC23

1

2

1

2

PC25

0.1U_0402_25V7K

4

BQ24735_REGN

1

2

PC12

10U_0805_25V6K

1

+

VDD_MUX

D

2

3

@

PD2

BAT54CW_SOT323-3

1

@

PR13

PR13 1K_0402_5%

1K_0402_5%

2

1

2

PC21

PC19

PC20

10U_0805_25V6K

0.1U_0402_25V7K

+VDD_BAT_BACK

PC22

10U_0805_25V6K

C

B

0.1U_0603_25V7K

A

PH3 under CPU botten side :

CPU thermal protection at 79 degree C Recovery at 57 degree C

PH2 near charger CHOKE :

Reduce charge current at 65 degree C Charge current recovery at 60 degree C

2

R110

R121

P

@

1

AS3720_5V_VR_EN(32,36)

CHARGER_THR_ALERT(29)

1

300K_0402_5%

100K_0402_1%

1

PR32 0_0402_5%@

5

1

2

3

2

4

100K_0402_1%_NCP15WF104F03RC

1

+3.3V_STBY

PC153

0.1U_0603_25V7K

PU10

VCC

TMSNS1

GND

RHYST1

OT1

TMSNS2

RHYST2

OT2

G718TM1U_SOT23-8

56.2K_0402_1%

8

7

6

2

5

@

115K_0402_1%

@

PR113

PH2

PR111

PR112

1

PR109

PR109 34K_0402_1%

34K_0402_1%

2

1

PH3

100K_0402_1%_NCP15WF104F03RC

2

@CONN@

CVILU_CI9908M2HR0-NH

4

1

PJP2

1

2

3

4

5

6

7

BATT+

7

8

9

GND

10

GND

2

TS

1

4.7K_0402_5%

PR28

BI

JUMP_43X118@

PJ5

1

PR31 0_0402_5%

2

4.7K_0402_5%

PR29

2

BI_R

2

+VDD_BAT_BACK

DMN65D8LW-7 1N SOT323-3

CHARGER_I2C_SDA_3.3V (29,31)

CHARGER_I2C_SCL_3.3V (29,31)

1

D

S

3

PQ8

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2

G

Issued Date

@

PR122 330K_0402_5%

2

PR124 0_0402_5%

1

PR26 330K_0402_5%

1

2

@

PR93 330K_0402_5%

1

2

1

2

1

2

1

BI_GATE (29,32)

2

+2.5V_AON_RTC

+5V_STBY

@

PR79

10K_0402_1%

BATT_TS (33)

@

PR80

1K_0402_1%

Compal Secret Data

Deciphered Date

2

@CONN@

ACES_50299-00501-003

1

VIN

1

2

3

4

5

6

GND

7

GND

PJP1

Compal Electronics, Inc.

2013/11/032013/11/20

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

AC/DC in & Charger

NIKE

@

1

JUMP_43X118

1

PJ4

1

2

ADAPDET (31)

2

+VDD_ACIN

A

0.1

of

31 42Thursday, June 19, 2014

of

31 42Thursday, June 19, 2014

of

31 42Thursday, June 19, 2014

2

1

2

20K_0402_1%

1

@

2

1

D

PR43 0_1206_5%

1

2

1

PC44

@

PR51

2

330U_D2E_6.3VM_R25M

5V_VFB

PR51

0_0402_5%

2

0.1U_0402_25V7K

+5V_SYS_R1

1

PR55

40.2K_0402_1%

2

1

PR61

PR61 10K_0402_1%

10K_0402_1%

+5V_SYS

C

2

PQ10

4

5V_DRVH_R

1

5V_DRVL

4

PQ12

PR63 1K_0402_5%

1

2

@

PR67 0_0402_5%

1

2

5

1

2

3

5V_MAIN_SW

5

1

2

3

PR49

@

PC47

@

1

2

PC135

100P_0402_50V8J

PL3 3.3UH_PCMB063T-3R3MS_6.5A_20%

1

2

1

PR45

1

2

4.7_1206_5%

6.04K_0402_1%

1

2

PR53

1.33K_0402_1%

2

PC49

1

2

0.1U_0402_25V7K

1000P_0402_50V7K

AS3720_5V_VR_EN (31,32,36)

TPS_RST (29,32)

PC35

2

1

2

10U_0805_25V6K

PR50

+VDD_MUX_3/5V

PC36

10U_0805_25V6K

1

@

2

0_0402_5%

+5V_SYS_R

1

+

PC43

PC42

2

10U_0805_16V6K

+

5V_STBY

P

R81 0_0402_5%@

P

R35 10K_0402_1%

2

PR41

0_0402_5%

2

1

2

0.1U_0402_25V7K

3.3V_MAIN_SKIPSEL

1

2

+3.3V_AON

1

PC51

2

@

0.1U_0402_25V7K

2

1

@

0_0402_5%

2

300K_0402_5%

3.3V_DRVH

3.3V_VBST

3

P

R36

PU2

1

31 32 30

7 8 2

6 4

+3.3V_SYS

3.3V_MAIN_RST

1

P

R33

@

R33

@

0_0402_5%

1

2

1

2

1

PR37

2

TPS51220A_REG_EN

TPS51220A_RF

3

12

RF

EN

DRVH1 VBST1 SW1 DRVL1

TPS51220ARSNR_QFN32_4X4

CSP1 CSN1 V5SW

SKIPSEL1 EN1

PGOOD1

5

3.3V_PGOOD

2

PR57

1

100K_0402_5%

2

PR64

@

PR64

@

0_0402_5%

9

3V_VFB

TPS51220A_TRIP

14

TRIP

VFB1

FUNC

11

+2V_STBY

TPS51220A_FUNC

P

@

0_0402_5%

2

+

22

COMP1

VREF2

10

15

13

3.3V_COMP

5V_COMP

1

2

@

PR65

0_0402_5%

R34

1

3.3V_AON

P

C29

2.2U_0603_10V6K

1

2

+5V_STBY

PC30

PC30 10U_0805_16V6K

10U_0805_16V6K

1

2

+VDD_MUX

23

29

VIN

DRVH2 VBST2

VREG3

VREG5

SW2

DRVL2

CSP2 CSN2

SKIPSEL2

EN2

COMP2

VFB2

PGOOD2

GND

33

28

16

20

5V_VFB

5V_PGOOD

PR59 100K_0402_5%

2

PC50

0.22U_0402_10V6K

2

1

PC34

1U_0603_25V6

1

2

24 26 25

27

18 17

19 21

1

+5V_SYS

PR42

5V_DRVH

0_0402_5%

1

5V_VBST

5V_MAIN_CS_P 5V_MAIN_CS_N

5V_MAIN_RST

@

1

2

PR40

PR40 0_0603_5%

0_0603_5%

1

2

5V_VBST_R

5V_MAIN_SKIPSEL

1

PR58

0_0402_5%

2

+3.3V_AON

PC52

@

0.1U_0402_25V7K

AON7408L_DFN8-5

2

PC38

0.1U_0402_25V7K

2

AON7752_DFN3X3EP8-5

5

D

+

VDD_MUX

4

T

PS51220A_REG_EN

B

I_GATE(29,31,32)

+

3.3V_AON

AS3720_5V_VR_EN(31,32,36)

PJ7

@

PJ7

@

1

2

+VDD_MUX_3/5V

1

2

JUMP_43X118

PR39 0_1206_5%

1

+3.3V_SYS

C

2

1

@

PR46

0_0402_5%

2

+3.3V_SYS_R1

2

23.2K_0402_1%

23.2K_0402_1% PR54

PR54

1

3V_VFB

2

PR60

10K_0402_1%

+3.3V_SYS_R

1

PC39

2

0.1U_0402_25V7K

+

PC41

330U_D2E_6.3VM_R25M

1

PL2 3.3UH_PCMB063T-3R3MS_6.5A_20%

1

@

2

PC40

2

10U_0805_16V6K

follow NV Norrin ,change power rail to +3.3V_AON(2014/01/03)

2

PR47

0_0402_5%

1

2

1.37K_0402_1%

1

0.1U_0402_25V7K

PR52

PC48

1

2

PC31

10U_0805_25V6K

1

2

1

5.9K_0402_1%

PR48

1

2

1

2

PC33

PC32

10U_0805_25V6K

100P_0402_50V8J

1

PR44

@

2

4.7_1206_5%

1

PC46

2

@

1000P_0402_50V7K

AS3720_5V_VR_EN(31,32,36)

TPS_RST(29,32)

3V_MAIN_SW

5

AON7408L_DFN8-5

4

1

2

3

5

4

PQ11

1

2

3

AON7752_DFN3X3EP8-5

+3.3V_AON

PR62 1K_0402_5%

1

@

1

PQ9

3.3V_DRVH_R

PC37

0.1U_0402_25V7K

1

2

3.3V_VBST_R

3.3V_DRVL

2

PR66 0_0402_5%

2

PR38

PR38 0_0603_5%

0_0603_5%

1

3.3V_MAIN_CS_P

3.3V_MAIN_CS_N

+5V_SYS

PC45

PR56

@

PR56

@

0_0402_5%

PR123

PR123 10K_0402_1%

10K_0402_1%

2

+5V_STBY

2

PR72

PR72 0_0603_5%

0_0603_5%

B

1

PR73 0_0603_5%

PU3

1

2

3

1

2

PC57

1U_0402_16V6K

2

5

IN

OUT

GND

4

BYP

SHDN#

NCT3705U-33_SOT23-5

2013/11/032013/11/20

1

2

PC152

0.01U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet

PR73 0_0603_5%

1

2

1

2

PC58

4.7U_0402_6.3V6M

Compal Electronics, Inc.

+3/5VALWS

NIKE

1

+3.3V_STBY

A

0.1

of

32 42Thursday, June 19, 2014

of

32 42Thursday, June 19, 2014

of

32 42Thursday, June 19, 2014

B

+2V_STBY

PR70

20K_0402_1%

1

2

A

5

4

2

@

PR68

1K_0402_5%

1

2

1K_0402_5%

1

PC53

1

PC55

0.1U_0402_25V7K

2

150P_0402_50V8J

3.3V_COMP

+2V_STBY

1

PR71

20K_0402_1%

@

2

@

PR69

PR69 1K_0402_5%

1

2

3

1K_0402_5%

1

PC54

1

@

PC56

0.1U_0402_25V7K

2

150P_0402_50V8J

5V_COMP

PR125 0_0402_5%@

BI_GATE(29,31,32)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

Compal Secret Data

Deciphered Date

D

C

+1.35V_LP0

B

1

PC78

2.2U_0402_6 .3V6M

2

+VDD_COR E

5

+1.35V_LP0

+3.3V_RUN

+1.8V_VDD IO

+3.3V_SYS

+3.3V_RUN

2.2U_0402_6 .3V6M

1

PC80

2.2U_0402_6 .3V6M

2

PC83

B14

1

PC63

2

4.7U_0402_6.3V6M

1

PC59

2

4.7U_0402_6.3V6M

A12

1

2

PC65

2.2U_0402_6.3V6M

1

2

PC69

2.2U_0402_6.3V6M

1

2

PU4B

SEC 2 OF 3

VIN_LDO0

A8

VIN_LDO1_6

VIN_LDO2_5_7

A3

VIN_LDO3_4

PMOS

LDO

B6

VIN_LDO3_LV

NMOS

LDO

A4

VIN_LDO3_SW

SW

A6

VIN_LDO9_10

B1

VIN_LDO11

AS3722-BC TT-09_CTBGA124

PWR

PWR MUX

MUX

LDO0

LDO1 LDO6

LDO2

LDO5 LDO7

LDO4

LDO3

LDO9

LDO10

LDO11

A13

B9 A7

A9 A10 A11

A2

B7

A5

B8

B5

4

PR74 0_0603_5%

1

+1.05V_RU N_AVDD_R

1

2

PC61

2.2U_0402_6.3V6M

PR75 0_0603_5%

1

PC62

2.2U_0402_6.3V6M

1

2

+VDDIO_SD MMC3

+1.2V_GEN_ AVDD_R

+1.05V_RU N_CAM_REAR

+VDDIO_SD MMC3_R

1

2

PC66

@

2.2U_0402_6.3V6M

1

2

+1.00V_LP0 _VDD_RTC_R

1

2

1

2.2U_0402_6.3V6M

PC76

2.2U_0402_6 .3V6M

PC79

2.2U_0402_6 .3V6M

+1.8V_RUN _VPP_FUSE_R

2

PC84

2.2U_0402_6.3V6M

2

+1.05V_RU N_AVDD

1

2

+2.8V_RUN _CAM

PR77 0_0603_5%

1

+

1.6V_LPO(36 )

+1.8V_RUN _CAM

1

2

PC64

@

2.2U_0402_6.3V6M

+1.2V_RUN _CAM_FRONT

1

2

PC67

@

2.2U_0402_6.3V6M

2

+1.00V_LP0 _VDD_RTC

PR89 0_0603_5%

1

2

BATT_TS(31)

CORE_PW R_REQ(24,29,36,8)

DVFS_CL K(10) DVFS_PW M(10)

CPU_PW R_REQ(24,8)

PR76 0_0603_5%

1

+5V_SYS

PC68

2.2U_0402_6.3V6M

+1.8V_RUN _VPP_FUSE

3

2

1

2

@

1

2

+1.2V_GEN_ AVDD

PR30 0_1206_5%

1

2

PR82

100K_0402_1%

1

PR84

2

69.8K_0402_1%

PR85 0_0402_5%

1

PR86 0_0402_5%

5VSUP_S D2/3

1

2

MI solution

E

+

1.35V_LP0

1

PC155

2

PC136

1

PR83

2

100K_0402_1%

PC60

56P_0402_50V8

2

PC70

10U_0805_16V6K

1

2

1

2

1

2

B11

B12

D10

E11

1

2

PC71

2.2U_0603_10V6K

PC77

10U_0805_16V6K

N12 P12

PC81

10U_0805_16V6K

N11

P11

PC85

10U_0805_16V6K

PU4C

PWM_DAT2

F8

CORE_PWRREQ

D9

PWM_DAT1

CPU_PWRREQ

N6

VSUP_SD2

P6

VSUP_SD2

L1

VSUP_SD3

L2

VSUP_SD3

VSUP_SD4

VSUP_SD5 VSUP_SD5

AS3722-BC TT-09_CTBGA124

PWM_CLK2

PWM_CLK1

SEC 3 OF 3

TEMP2_SD6 TEMP1_SD6

CTRL2_SD6 CTRL1_SD6

FB_SD6_N

FB_SD6_P

TEMP4_SD0 TEMP3_SD0

TEMP2_SD0 TEMP1_SD0

CTRL8_SD0

CTRL7_SD0 CTRL6_SD0 CTRL5_SD0

CTRL4_SD0 CTRL3_SD0 CTRL2_SD0

CTRL1_SD0

FB_SD0_N FB_SD0_P

TEMP_SD1

CTRL2_SD1 CTRL1_SD1

FB_SD1_N FB_SD1_P

LX_SD2

LX_SD2 LX_SD2 LX_SD2

FB_SD2 VSS_SD2 VSS_SD2

VSS_SD2 VSS_SD2

LX_SD3

FB_SD3

VSS_SD3 VSS_SD3 VSS_SD3

LX_SD4

FB_SD4

VSS_SD4 VSS_SD4

LX_SD5

FB_SD5 VSS_SD5

VSS_SD5

L13

L14 C14 C13

G11 F11

K11

K13 J13 J14

H14 H13 G14

G13 F14 F13

E14 E13 J11

H11

K14 D14

D13 H9 G9

N5 N7 P7

P5 K1 N4

N8 P4 P8

M1 M2 N1

K2 N3 P2

P3

N14 P13

L10 M13 M14

N10 P10 J1

N9 P9

LX_+1.35V_ LP0

LX_+1.05V_ RUN

LX_+1.8V_V DDIO

1

PL4 0.47UH PCMB053T-R 47MS 12A_20%

@

PL5 1UH_M LV-FY12N1R0M-O1L_ 3.1A_20%

1

@

PR88 0_0402_5%

1

PL6 1UH_M LV-FY12N1R0M-O1L_ 3.1A_20%

1

@

PR910_0402_5%

PC136

100P_0402_50V8J

AS3722_TE MP2_SD6 (35)

AS3722_TE MP1_SD6 (35) AS3722_C TRL2_SD6 (35) AS3722_C TRL1_SD6 (35)

VDD_GPU _SENSE_N (12)

VDD_GPU _SENSE_P (12)

AS3722_TE MP2_SD0 (34)

AS3722_TE MP1_SD0 (34)

AS3722_C TRL4_SD0 (34) AS3722_C TRL3_SD0 (34)

AS3722_C TRL2_SD0 (34) AS3722_C TRL1_SD0 (34)

VDD_CPU _SENSE_N (12)

VDD_CPU _SENSE_P (12)

AS3722_TE MP_SD1 (35) AS3722_C TRL2_SD1 (35)

AS3722_C TRL1_SD1 (35)

VDD_COR E_SENSE_N (12)

VDD_COR E_SENSE_P (12)

2

1

2

PR87 0_0402_5%

2

1

2

0.1U_0402_10V6K

1

PC72

2

+1.05V_RU N_R

+1.8V_VDD IO_R

1

PC154

PC156

2

0.1U_0402_10V6K

100P_0402_50V8J

+1.35V_LP0

1

PC73

2

22U_0805_6.3V6M

1

PC74

2

22U_0805_6.3V6M

PR117 0_1206 _5%

2

PC75

22U_0603_6.3V6M

1

D

C

B

+1.05V_RU N

1

2

PC82

22U_0603_6.3V6M

PR90 0_1206 _5%

1

2

1

PC86

+1.8V_VDD IO

2

22U_0805_6.3V6M

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2013/11/032013/11/20

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PMIC(BUCK & LDO)

NIKE

1

of

33 42Thursday, June 19, 2014

of

33 42Thursday, June 19, 2014

of

33 42Thursday, June 19, 2014

A

0.1

5

4

3

2

1

D

+5V_SYS

PR106 0_1206_5%

1

2

C

B

+5V_CPU

+5V_SYS

LX11 LX12

LX13

LX21

LX22 LX23

LX11 LX12

LX13

LX21

LX22 LX23

A2 B2 C2

A1

VDD__CPU_BOOST0

A3 B3

C3

F1

VDD__CPU_BOOST1

D3

E3 F3

A4

B4 C4

A2 B2 C2

A1

VDD__CPU_BOOST2

A3 B3

C3

F1

VDD__CPU_BOOST3

D3

E3 F3

A4

B4 C4

1

2

PC98

10U_0805_16V6K

VDD_CPU_LX0

VDD_CPU_LX1

1

2

PC110

@

10U_0805_16V6K

@

PC112 0.1U_0402_25V6

VDD_CPU_LX2

@

PC114 0.1U_0402_25V6

VDD_CPU_LX3

1

2

PC99

10U_0805_16V6K

PC100 0.1U_0402_25V6

1

2

PC102 0.1U_0402_25V6

1

2

1

2

PC111

@

10U_0805_16V6K

1

2

1

2

PL7 0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%

1

2

1

PL8 0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%

1

2

@

PL9 0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%

1

2

1

PC115

2

@

PL10 0.68UH_MMD-05CZ-R68M-X2L_8.5A_20%

1

2

@

47U_0805_6.3V6M

1

PC105

PC103

47U_0805_6.3V6M

1

2

PC105

PC104

2

47U_0805_6.3V6M

1

PC117

PC116

2

@

47U_0805_6.3V6M

1

PC107

PC106

2

@

47U_0805_6.3V6M

1

2

@

47U_0805_6.3V6M

1

PC119

PC118

2

@

47U_0805_6.3V6M

+VDD_CPU_AP

C

B

1

2

PC97

PC96

1

2

PC113

1U_0402_16V6K

PC96

10U_0805_16V6K

AS3722_CTRL1_SD0(33)

AS3722_CTRL2_SD0(33)

AS3722_TEMP1_SD0(33)

1

2

PC108

@

10U_0805_16V6K

PC109

@

10U_0805_16V6K

PU5

D2

HVSUP4

E2

HVSUP5

F2

HVSUP6

C1

5VSUP

B1

CTRL1

E1

CTRL2

D1

TEMP

D4

PVSS4

E4

PVSS5

F4

PVSS6

AS3728-BWLT_WL-CSP24

PU6

@

PU6

@

D2

HVSUP4

E2

HVSUP5

F2

HVSUP6

C1

5VSUP

HVSUP1 HVSUP2 HVSUP3

BOOST1

BOOST2

PVSS1

PVSS2 PVSS3

HVSUP1 HVSUP2 HVSUP3

BOOST1

1

2

PC101

AS3722_CTRL3_SD0(33)

@

1U_0402_16V6K

AS3722_CTRL4_SD0(33)

AS3722_TEMP2_SD0(33)

B1

CTRL1

E1

CTRL2

D1

TEMP

D4

PVSS4

E4

PVSS5

F4

PVSS6

AS3728-BWLT_WL-CSP24

BOOST2

PVSS1

PVSS2 PVSS3

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

2013/11/032013/11/20

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CPU CORE

NIKE

1

of

34 42Thursday, June 19, 2014

of

34 42Thursday, June 19, 2014

of

34 42Thursday, June 19, 2014

A

0.1

3

@

P

U7

D

2

VSUP4

H

E

2

H

VSUP5

2

F

H

VSUP6

C

1

5

VSUP

B1

CTRL1

E1

CTRL2

D1

TEMP

D4

PVSS4

E4

PVSS5

F4

PVSS6

AS3728-BW LT_WL-CSP 24

VSUP1

H H

VSUP2

H

VSUP3

B

OOST1

L

X11

L

X12

X13

L

BOOST2

LX21

LX22 LX23

PVSS1

PVSS2 PVSS3

A

2

B

2

C

A

1

V

DD_GPU_B OOST0

3

A B

3

C

3

F1

VDD_GPU _BOOST1

D3 E3

F3

A4 B4

C4

1

2

PC122

@

1

2

PC123

@

10U_0805_16V6K

@

C124 0.1U_040 2_25V6

P

2

V

DD_GPU_L X0

@

PC125 0.1U_0 402_25V6

2

VDD_GPU _LX1

1

@

P

L11 0.68UH_M MD-05CZ-R68M -X2L_8.5A_20%

1

@

PL12 0.68UH_ MMD-05CZ-R68M -X2L_8.5A_20%

1

+

5V_SYS

4

1

2

PC120

PC121

@

PC121

@

10U_0805_16V6K

5

R107 0_1206_ 5%

P

1

+

5V_SYS

D

2

5V_GPU

+

1

2

PC128

@

1U_0402_16V6K

AS3722_C TRL1_SD6(33)

AS3722_TE MP1_SD6(33)

2

1

PC127

PC126

2

@

2

@

1

2

@

47U_0805_6.3V6M

1

PC130

PC129

2

@

47U_0805_6.3V6M

1

D

VDD_GPU _AP

+

1

PU8

2

C

+5V_SYS

1

2

PC138

1U_0402_16V6K

2

PC132

PC131

10U_0805_16V6K

AS3722_C TRL2_SD6(33)

AS3722_TE MP2_SD6(33)

PR108 0_1206 _5%

1

B

+5V_SYS

2

+5V_CORE

1

2

PC144

PC145

10U_0805_16V6K

AS3722_C TRL1_SD1(33)

AS3722_C TRL2_SD1(33)

AS3722_TE MP_SD1(33)

A

5

4

PU8

D2

HVSUP4

E2

HVSUP5

F2

HVSUP6

C1

5VSUP

B1

CTRL1

E1

CTRL2

D1

TEMP

D4

PVSS4

E4

PVSS5

F4

PVSS6

AS3728-BW LT_WL-CSP 24

PU9

A1

CTRL1

D1

CTRL2

B1

TEMP

C1

AGND

AS3729-BW LT_WL-CSP 16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

HVSUP1 HVSUP2 HVSUP3

BOOST1

LX11 LX12

LX13

BOOST2

LX21

LX22 LX23

PVSS1

PVSS2 PVSS3

VSUP VSUP VSUP

VSUP

PVSS PVSS PVSS

PVSS

LX1 LX1

LX2 LX2

A2 B2 C2

A1

VDD_GPU _BOOST2

A3 B3

C3

F1

VDD_GPU _BOOST3

D3 E3 F3

A4 B4 C4

A2 B2

C2 D2

A4 B4

C4 D4

A3

B3

C3 D3

1

2

PC133

VDD_GPU _LX2

VDD_GPU _LX3

VDD_COR E_LX0

10U_0805_16V6K

1

2

VDD_COR E_LX1

1

2

PC134

10U_0805_16V6K

PC137 0.1U_0 402_25V6

1

2

PC139 0.1U_0 402_25V6

1

2

1

2

PC147

PC146

10U_0805_16V6K

PL15 0.68UH _MMD-05CZ-R6 8M-X2L_8.5A_20%

1

PL16 0.68UH _MMD-05CZ-R6 8M-X2L_8.5A_20%

1

Compal Secret Data

Deciphered Date

PL13 0.68UH _MMD-05CZ-R6 8M-X2L_8.5A_20%

1

2

PL14 0.68UH _MMD-05CZ-R6 8M-X2L_8.5A_20%

1

2

1

PC148

PC149

2

PC149

2

47U_0805_6.3V6M

2

1

PC151

PC150

2

@

47U_0805_6.3V6M

2013/11/032013/11/20

2

1

PC140

PC141

2

1

2

PC141

2

47U_0805_6.3V6M

1

PC142

PC143

2

47U_0805_6.3V6M

PJ3

@

PJ3

@

1

2

JUMP_43X 118

Title

GPU & VDD CORE

Size Document Number Rev

Custom

Date: Sheet

2

+VDD_COR E

Compal Electronics, Inc.

NIKE

1

35 42Thursday, June 19, 2014

C

B

A

0.1

of

5

4

3

2

1

D

PR115

@

PR115

@

0_0402_5%

1

PWR_I2 C_SCL(8)

PWR_I2 C_SDA(8)

PMIC_PW RON(29)

+2.5V_AON_ RTC

AP_OVERH EAT#(21,29)

C

+1.8V_VDD IO

@

PR97

10K_0402_5 %

2

1

PR96

100K_0402_ 5%

2

1

PC91

PC91 1000P_0402 _50V7K

1000P_0402 _50V7K

2

1

CPU_OC_IN T(8)

+VDD_M UX

2

PR100

@

PR100

@

0_0402_5%

1

2

1

2

PR116 0_0402 _5%@

PR99

@

PR99

@

0_0402_5%

1

AS3720_5V _VR_EN(31,32)

+VDD_M UX_AS3720_VBA T

2

AC_OK_PM U_R_L

+2.5V_AON_ RTC

1

PC92

2

0.1U_0402_25V7K

B

+2.5V_AON_ RTC

0.1U_0402_25V7K

2

PR103

200K_0402_5%

@

PR105

1

0_0402_5%

2

PR104

1

200K_0402_5%

1

+1.8V_VDD IO

PC94

1U_0402_6.3V6K

ACOK_PM U (29)

PMU_INT_ L(8)

5V_SYS

+

1

2

1

2

1

2

1

2

PWR_I2 C_SCL_R PWR_I2 C_SDA_R

1

+VBACKU P

1

+

PC93

2

0.07F_3.3V_Z

PC87

0.1U_0402_2 5V7K

PC88

0.1U_0402_2 5V7K

PC89

0.1U_0402_2 5V7K

LID_CLOSE _PMU_L

PR126

4.7K_0402_1 %

2

AS3720_R BIAS

2

PR102

1

221K_0402_1%

AS3720_C REF

1

PC95

2

0.1U_0402_25V7K

H1

L9 F2

G4

F4

E2 H6

B10

C1 D7 D8 E1

L6 L7 L8

H2

H4

J2 J4

PU4A

VSUP_ANA

VSUP_GPIO VDD_GPIO_LV

SCL_SCLK

SDA_SDI ENABLE3_SDO SCSB

ONKEY XINT LID

THERM OC_PWRGD

EN5V

VBAT AC_OK

V2_5

VBAT_BKUP

RBIAS CREF

SEC 1 OF 3

GPIO0

GPIO1 GPIO2 GPIO3

GPIO4 GPIO5 GPIO6

GPIO7

CLK32K

XIN32K

XOUT32K

XRES_IN

XRES_OUT

VSSA VSSA

VSSA

VSSA VSSA VSSA

GNDSENSE

VSS_GPIO

D6 G6

D5 E4

PMU_GPIO3

B3 C2

CLK_32K_ WIFI

B4 D2

D1

CLK_32KH Z_PMU_R

G1 G2

J8

L5

A1 A14

F7 J7 P1

P14 K4 F1

PMU_SYS_RESET#

IGPU_PW RGD (8) PMU_RE GEN3 (30)

PMU_RE GEN1 (30)

EN_AVDD _LCD (14 )

+1.6V_LPO (33)

PR98 10_0402 _1%

1

AS3720_XIN 32K (30)

AS3720_XO UT32K (30)

@

0_0402_5%

2

PR101

PR92

@

PR92

@

0_0402_5%

1

2

PR94

33_0402_5%

1

2

CLK_32KH Z_PMU (8)

PR114 100K_ 0402_5%

1

2

+2.5V_AON_ RTC

PMU_RE SET_IN# (2 9)

1

SYS_RESET # (21,2 4,25,30,8)

PMU_SYS_R ESET# (30)

CORE_PW R_REQ (2 4,29,33,8)

CLK_W IFI_32K (20 )

D

C

B

6

D

PQ17A

2

G

S

DMN63D 8LDW-7_SOT363 -6

3

D

PQ17B

A

AC_OK(10,31 )

5

G

S

DMN63D 8LDW-7_SOT363 -6

4

5

1

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2013/11/032013/11/20

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PMIC(LOGIC & GPIO)

NIKE

1

0.1

of

36 42Thursday, June 19, 2014

of

36 42Thursday, June 19, 2014

of

36 42Thursday, June 19, 2014