Acer Aspire One D270 Schematics

1

ZE7 Block Diagram (Intel Cedar Trail-M Platform)

A A

2

VDS/eDP CONN

L

VGA

CONN

3

4

5

6

7

8

01

CL

Ce

0

DDI

P1

7

LV

HDMI 1.3a

DDI

1366x768

DS 18bit,SC

1366x

768

C

DA

1920x1200

1

I CONN

HDM

P1

8

8

P1

0ohm

darview-M

400 / 640MHz

3.5W) & DC(6.5W)

DC(

(32nm

M

icro-FCBGA8

(22x22mm)

)

~9

P5

DR III,800/1066 MT/s

D

Channel

A

K Gen.

SLG8LV631V

FERED

UNBUF
DDRIII SODIMM

B/F

RC­CL

K2/3, H=4

P2

P4

B B

IE Gen1

R

TL8105TA-VC-CG

R

J45 CONN

C C

USB PORT

Left

BA

TTERY CHAGER

D D

SY

STEM

P2

5V/3V PCU
CPU Co

re

Gfx Core

1

0

2

P2

P2

2

R

TS5209-GR

CARDREADER

IN1 CARDREADER

5

S

D3.0, MS, MS PRO,

xD, MMC

3

1

USB PORT

Ri

DDR 1

P2

9

1.05V

P3

P31

+

0

3

1

2

P2

6

P2

6

021

P2

1

P3

USB PORT

D

2

+3.3V_PRIME

ght Down Right Up

.5VSUS

Ther

P33

2

Mini card2

M

MM-

U
module

P2

ini card1

P2

SIM CARD

SB interface

P1

1

P2

5

5

9

ischarge/+1.8V/

mal Protection

5

7

5

P2

6

CCD

P3

4

5

P3

3

PC

Tiger

4

SB 2.0

U

8

P1

Ke

yboard

P19 P19

4

x2

DMI Gen1

point (NM10)

1.5W
BGA

vF

(360 balls,17x17mm)

P

EC

uch Pad

To

HD A

UDIO I/F

SAT

A II I/F

0

10~15

N

uvoton NPCE791L

Ch

Flash

SPI

P27

5

arger

A
Realtek 271X

M

obile 2.5" HDD

PW

9

P2

6

udio CODEC

P2

P27

M FAN

P6

P2

0

4

ize Document Nu mb e r Rev

ize Document Nu mb e r Rev

ize Document Nu mb e r Rev

S

S

S

Date: Sheet

Date: Sheet

Date: Sheet

7

IC In Jack

M
Analog MIC
Speaker Header (2W)

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

Q

Q

Q

PROJECT :

PROJECT :

PROJECT :

Block Diagram

Block Diagram

Block Diagram

ZE7

ZE7

ZE7

P2

0

C3

C3

C3

of

of

of

142Wednesday, August 31, 2011

142Wednesday, August 31, 2011

142Wednesday, August 31, 2011

8

C

C

C

5

CLK G

D D

EN (CLK)

+3

V

P

P

BY160808T-301Y-N/2A/300ohm_6

BY160808T-301Y-N/2A/300ohm_6

Place close to L32

V

DD_CLK_3.3V

L32

L32

C285

C285
10U/

10U/

10V_8

10V_8

C278

C278

U/10V_4

U/10V_4

.1

.1

0.

1uF near every power pin

C254

C254

U/10V_4

U/10V_4

.1

.1

C242

C242
1U/10V_4

1U/10V_4

.

.

VDD_IO can be ranging from 1.05V to 3.3V.

+1

.05V

L28

L28
2A

2A

/300ohm_6

R221

R221

ace close to L28

Pl

C C

Layout note>

<
Crystal place within 500m il of CK505

V

+3

R311

R311
*20K

B B

*20K

R310

R310
*100K

*100K

/300ohm_6

*0/short_6

*0/short_6

C228

C228

10V_8

10V_8

10U/

10U/

C238

C238
33P

33P

C236

C236
33P

33P

/J_4

/J_4

_4

_4

_XIN

CG

/50V_4

/50V_4

21

2 14.318MHZ

2 14.318MHZ

Y

Y

Load Capacitance=20p

CG

_XOUT

/50V_4

/50V_4

<20110110> CFG i
LOW = Both CPU and SRC clock drive from PLL3
HIGH = CPU clock dri ve from PLL1, SRC clock drive f rom PLL3.
Contains 100kȍ pull-down resi stor.

nput hardware strapping to allocate PLL assignment.

V

DD_CLKIO_1.05V

C249

C249

C229

C229

1U/10V_4

1U/10V_4

U/10V_4

U/10V_4

.

.

.1

.1

1uF near every power pin

0.

USB_48[10]

CLK

_ICH[13]

14M

CLK_ICH[12]

P
LCLK

_EC[27]

LK_DEBUG[25]

PC

SMBD
SMBC

C253

C253

U/10V_4

U/10V_4

.1

.1

T1[4,13,25]
K1[4,13,25]

R312

R312

R293

R293

R296

R296
R304

R304
R291

R291

33/J_4

33/J_4

33/J_4

33/J_4

22/J_4

22/J_4
22/J_4

22/J_4
33/J_4

33/J_4

4

CG
CG

SMBD
SMBC

FS
U

SB_48M

FS

TP_EN

I

3M_SEL

3

_XOUT
_XIN

B

C

T1
K1

U12

U12

5

DD_REF_3.3

V

9

DD_PCI_3.3

V

14

V

DD_48M_3.3

30

DD_SRC_IO_1.05

V

35

V

DD_SRC_IO_1.05

48

DD_CPU_IO_1.05

V

1

NC

2

NC

13

NC

54

NC

3

XT

AL_OUT

4

XT

AL_IN

7

A

SD

8

SC

L

15

U

SB48_1/FSB

17

SB48_2

U

6

R

EF/FSC

10

IF/ITP_EN

PC

11

25M

Hz/PCI_2/SEL_33MHz

12

VSS_

16

VSS_

22

VSS_

24

VSS_

39

VSS_

51

VSS_

56

VSS_

57

Th

ermal Pad

LG8LV631V

LG8LV631V

S

S

PCI
48M
LCD
SATA
SRC
CPU
REF

DD_CORE_1.5

V

DD_CORE_1.5

V

I_STOP#

PC

U_STOP#

CP

CP

CP

S

RC_1/CPU_ITP

S

RC_1/CPU_ITP#

S

S

S

S

S

DO

T96/SRC7

T96#/SRC7#

DO

CD_CLK

L

L

CD_CLK#

C

LKREQ_A#
LKREQ_B#

C

LKREQ_C#

C

PWRGD/PD#

CK

CP

CP

S

RC_2#

S

RC_3#

S

RC_4#

S

RC_5#

S

RC_6#

SAT

U_0#

U_1#

RC_2

RC_3

RC_4

RC_5

RC_6

SAT

3

2

1

02

+1

V

DD_CLK_1.5V

C225

C225

C277

C277

.

.

.

.

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

1uF near every power pin

0.

23
45

STPPCI#_R

PM_

36

P

M_STPCPU#_R

42
53

U_0

52
50

U_1

49
44

43

41
40

38
37

34
33

32
31

28
27

DRE

18

DRE

19
20

21
26

A

25

A#

CLK

REQ_LAN#_R

47

C

LKREQ_MPC#_R

46

LKREQ_MMC#_R

C

29

PG

HW

55

FCLK_R
FCLK#_R

R299

R299
R300

R300

R251

R251
R229

R229

R204

R204
R199

R199
R284

R284

*0/J_4

*0/J_4
*0/J_4

*0/J_4

*0/J_4

*0/J_4
*0/J_4

*0/J_4

475/F_4

475/F_4
475/F_4

475/F_4
475/F_4

475/F_4

C357

C357

1U/10V_4

1U/10V_4

*0.

*0.

<20100803_S

PM_
P

CLK
CLK

CLK
CLK

CLK
CLK

CLK
CLK

CLK
CLK

C
C

C
CLK

CLK
CLK

DRE
DRE

DRE
DRE

C
CLK

<20100819> Add 475ohm

CLK
CLK

LKREQ_MMC# [26]

C

HW

<20110221> R
w

ill change to 25MHz after flash BIOS and restart in first time issue.

R

R

219 2.2/J_6

219 2.2/J_6

C224

C224
10U/

10U/

10V_8

10V_8

ace close to L27

Pl

1 2

P

P

BY160808T-301Y-N/2A/300ohm_6

BY160808T-301Y-N/2A/300ohm_6

<20100819_FAE Poy

am> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.

STPPCI# [13]

M_STPCPU# [13]

_MCH_BCLK [6]
_MCH_BCLK# [6]

_DDR3_REFCLK [8]
_DDR3_REFCLK# [8]

_PCIE_LANP [22]
_PCIE_LANN [22]

_PCIE_MNC_P [25]
_PCIE_MNC_N [25]

_PCIE_MPC_P [25]
_PCIE_MPC_N [25]

LK_PCIE_DMIP [5]
LK_PCIE_DMIN [5]

LK_PCIE_MMC_P [26]

_PCIE_MMC_N [26]
_PCIE_ICH [10]

_PCIE_ICH# [10]
FCLK [5]

FCLK# [5]

FSSCLK [5]
FSSCLK# [5]

LK_PCIE_SATA [11]

_PCIE_SATA# [11]

REQ_LAN# [22]
REQ_MPC# [25]

PG [13,16,27]

From SB

To CPU (Host CLK)

To CPU (DDR3 IO CLK)

To Mini Card 2 (3G/Wimax)

To CPU (DMI CLK)

To SB (DMI CLK) 100 MHz

To CPU (DPLSS CLK) 100 MHz

resistors to prev ent current l eakage

C

ontrol SRC_1

C

ontrol SRC_3

Control SRC_5 Register B5b3 for CLKREQ_C#

eserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes

.5V

L27

L27

ueh> Add 2.2ohm resistor for noise suppress

100 MHz

100 MHz

100 MHzTo LAN (LAN)

100 MHz

100 MHzTo Mini Card 1 (WLAN)

100 MHz

100 MHzTo Card Reader (MMC)

96 MHzTo CPU (PLL CLK)

100 MHzTo SB (SATA CLK)

Reg

ister B5b6 for CLKREQ_A#
0 = SRC1, 1=SR C2
Reg

ister B5b4 for CLKREQ_B#
0 = SRC3, 1=SR C4

0 = SRC5, 1=SR C6

lace R235/ R241/ R248/ R254 close to U13

<20101109> P

<20110110> DPL_REFSSCCLK i
registers and logics of the display interface and therefore
needs to be present at all times.

s used to dri ve internal

SC FSB Frequency

F
0 0 133MHz
0 1 166MHz

R313 *10K/J_4R313 *10K/J_4

+3V

A A

R306 10K/J_4R306 10K/J_4

R301 10K/J_4R301 10K/J_4

+3V +3V +3V

R295 *10K/J_4R295 *10K/J_4

1 = Pin 43/44 as CPU_ITP

ITP_EN

33M_SEL FSC

5

n 43/44 as SRC_1

0 = Pi

1 = Pi

n 11 as 33MHz

0= Pin 11 as 25MHz

1 1 200MHz

1 0 100MHz

R289 10K/J_4R289 10K/J_4

R259 *10K/J_4R259 *10K/J_4

<20100720_S

4

am> Keep 100MHz as default.

R317 *10K/J_4R317 *10K/J_4

FSB

R318 10K/J_4R318 10K/J_4

<EMI>

USB_48M

ITP_EN

FSB

FSC

33M_SEL

C280 *10P/50V_4C280 *10P/50V_4

C259 *10P/50V_4C259 *10P/50V_4

C279 *10P/50V_4C279 *10P/50V_4

C245 *10P/50V_4C245 *10P/50V_4

C266 *10P/50V_4C266 *10P/50V_4

3

PM_STPPCI#_R

PM_STPCPU#_R

CLKREQ_MPC#_R

CLKREQ_MMC#_R

CLKREQ_LAN#_R

R250 10K/J_4R250 10K/J_4

R230 10K/J_4R230 10K/J_4

R213 10K/J_4R213 10K/J_4

R279 10K/J_4R279 10K/J_4

R212 10K/J_4R212 10K/J_4

2

+3V

Qu

Qu

Qu

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

CL

CL

CL

OCK GENERATOR

OCK GENERATOR

OCK GENERATOR

ZE7

ZE7

ZE7

242Wednesday, August 31, 2011

242Wednesday, August 31, 2011

1

242Wednesday, August 31, 2011

C3C

C3C

C3C

5

4

3

2

1

03

D D

C C

B B

A A

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

Reserved

Reserved

Reserved

ZE7

ZE7

ZE7

C3C

C3C

C3C

342Wednesday, August 31, 2011

342Wednesday, August 31, 2011

342Wednesday, August 31, 2011

1

5

DDR_ST

D D

C C

B B

D(DDR)

Popu

late rules: populate
SODIMM1 first
Strictly follow the mapping
between clock/control signal
groups and SODIMMs, as
well as SMB address. Other
configurations/mappings will
not
be supported by MRC

GN NOTE:

DESI

+3V

ADDRESS-(A2)H

R150

R150
10K/J_4

10K/J_4

R170

R170

R151

R151

10K/J_4

10K/J_4

*10K/J_4

*10K/J_4

A_A[15:0][8]

M_

M_

A_BS0[8]

M_

A_BS1[8]

M_

A_BS2[8]

M

_CS#2[8]

M

_CS#3[8]

M

_CLK2[8]

M

_CLK2#[8]

M

_CLK3[8]
_CLK3#[8]

M

_CKE2[8]

M

_CKE3[8]

M

A_CAS#[8]

M_

A_RAS#[8]

M_
M_

A_WE#[8]

SM

BCK1[2,13,25]

SM

BDT1[2,13,25]

M_

ODT2[8]

M_

ODT3[8]

M_

A_DM[7:0][8]

M_

A_DQS[7:0][8]

A_DQS#[7:0][8]

M_

M_

A_A0

M_

A_A1
A_A2

M_

A_A3

M_

A_A4

M_

A_A5

M_

A_A6

M_

A_A7

M_
M_

A_A8

M_

A_A9

M_

A_A10

M_

A_A11

M_

A_A12

M_

A_A13

M_

A_A14

M_

A_A15

D

IMM1_SA0

D

IMM1_SA1

BCK1

SM

BDT1

SM

M_

A_DM0

M_

A_DM1

M_

A_DM2

M_

A_DM3

M_

A_DM4

M_

A_DM5

M_

A_DM6

M_

A_DM7
A_DQS0

M_

A_DQS1

M_

A_DQS2

M_

A_DQS3

M_

A_DQS4

M_
M_

A_DQS5

M_

A_DQS6

M_

A_DQS7

M_

A_DQS#0

M_

A_DQS#1

M_

A_DQS#2

M_

A_DQS#3

M_

A_DQS#4

M_

A_DQS#5
A_DQS#6

M_

A_DQS#7

M_

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

109
108

79
114
121
101
103
102
104

73

74
115
110
113
197
201
202
200

116
120

11

28

46

63
136
153
170
187

12

29

47

64
137
154
171
188

10

27

45

62
135
152
169
186

4

JDI

JDI

M1A

M1A

#

AP
BC#

H=4mm

C2100 DDR3 SDRAM SO-DIMM

C2100 DDR3 SDRAM SO-DIMM
P

P

DIMM0

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/
A11
A12/
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDR3-DIMM0_H=4_STD

DDR3-DIMM0_H=4_STD

3

+1.5VSUS

+3V

C179

C179

.1U/10V_4

.1U/10V_4

DDR3_DRA

2.48A

C178

C178

MRST#[8]

+SM
+SM

DDR_VREF_DQ0
DDR_VREF_DIMM

_A_DQ[63:0] [8]

M_

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

(204P)

(204P)

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

A_DQ0

M_

A_DQ1
A_DQ2

M_

A_DQ3

M_

A_DQ4

M_

A_DQ5

M_

A_DQ6

M_

A_DQ7

M_
M_

A_DQ8

M_

A_DQ9

M

_A_DQ10

M

_A_DQ11

M

_A_DQ12

M

_A_DQ13

M

_A_DQ14

M

_A_DQ15

M

_A_DQ16
_A_DQ17

M

_A_DQ18

M

_A_DQ19

M

_A_DQ20

M

_A_DQ21

M

_A_DQ22

M
M

_A_DQ23

M

_A_DQ24

M

_A_DQ25

M

_A_DQ26

M

_A_DQ27

M

_A_DQ28

M

_A_DQ29

M

_A_DQ30

M

_A_DQ31

M

_A_DQ32
_A_DQ33

M

_A_DQ34

M

_A_DQ35

M

_A_DQ36

M

_A_DQ37

M
M

_A_DQ38

M

_A_DQ39

M

_A_DQ40

M

_A_DQ41

M

_A_DQ42

M

_A_DQ43

M

_A_DQ44

M

_A_DQ45

M

_A_DQ46

M

_A_DQ47
_A_DQ48

M

_A_DQ49

M

_A_DQ50

M

_A_DQ51

M

_A_DQ52

M
M

_A_DQ53

M

_A_DQ54

M

_A_DQ55

M

_A_DQ56

M

_A_DQ57

M

_A_DQ58

M

_A_DQ59

M

_A_DQ60

M

_A_DQ61
_A_DQ62

M

_A_DQ63

M

M

.1U/10V_4

.1U/10V_4

2

M1B

M1B

JDI

JDI

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

PC2100 DDR3 SDRAM SO-DIMM

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

R191

R191

PC2100 DDR3 SDRAM SO-DIMM

1K/F_4

1K/F_4

25
26
31
32
37
38
43

DDR3-DIMM0_H=4_STD

DDR3-DIMM0_H=4_STD

<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON
DDR_VREF_CA

+1.5VSUS

C194

C194

.1U/10V_4

.1U/10V_4

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

(204P)

(204P)

VTT1
VTT2

GND
GND

DDR_VREF_DIMM_R

+SM

R208

R208
1K/F_4

1K/F_4

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

+0.75V_DDR_VT

203
204

205
206

*0/J_4

*0/J_4

R198

R198

R205

R205

+SM

T

DDR_VREF

0/J_4

0/J_4

+SM

DDR_VREF

C205

C205

0.1U/50V_6

0.1U/50V_6

1

DDR_VREF_DIMM

+SM

04

<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ

P

lace these Caps near DIMM0

+1.5VSUS

+

C168

C163

C163
10U/6.3V_6

10U/6.3V_6

C165

C165
1U/6.3V_4

1U/6.3V_4

C168
10U/6.3V_6

10U/6.3V_6

C161

C161
1U/6.3V_4

1U/6.3V_4

C198

C198
10U/6.3V_6

10U/6.3V_6

C192

C192
1U/6.3V_4

1U/6.3V_4

C199

C199
10U/6.3V_6

10U/6.3V_6

C189

C189
1U/6.3V_4

1U/6.3V_4

C197

C197
10U/6.3V_6

10U/6.3V_6

C196

C196
10U/6.3V_6

10U/6.3V_6

C193

C169

C169
.1U/10V_4

.1U/10V_4

C193
.1U/10V_4

.1U/10V_4

C173

C173
1U/6.3V_4

1U/6.3V_4

C164

C164
1U/6.3V_4

1U/6.3V_4

5

C171

C171
.1U/10V_4

.1U/10V_4

A A

+1.5VSUS

C191

C191

C162

C162

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

+

C203

C203

*330U/2V_7343

*330U/2V_7343

4

<20100827> Add by DG request

C172

C172

*10U/6.3V_6

*10U/6.3V_6

DDR_VREF_DQ0

T

C200

C200

C167

C167

2.2U/6.3V_6

2.2U/6.3V_6

C190

C190

*10U/6.3V_6

*10U/6.3V_6

.1U/10V_4

.1U/10V_4

C216

C216

3

+0.75V_DDR_VT

10U/6.3V_6

10U/6.3V_6

LAYOUT NOTE: PLACE CAPS
NEAR DIMM-0

+SM

C170

C170

.1U/10V_4

.1U/10V_4

C185

C185

1U/6.3V_4

1U/6.3V_4

DDR_VREF_DIMM

+SM

C176

C176

1U/6.3V_4

1U/6.3V_4

C214

C214

2.2U/6.3V_6

2.2U/6.3V_6

+1.5VSUS

.1U/10V_4

.1U/10V_4

1U/6.3V_4

1U/6.3V_4

R148

R148

C160

C160

+0.75V_DDR_VT

C175

C175

1U/6.3V_4

1U/6.3V_4

2

C184

C184

T

1K/F_4

1K/F_4

R149

R149

+SM

DDR_VREF_DQ0_R

R147

R147
1K/F_4

1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+SM

*0/J_4

*0/J_4

R146 0/J_4R146 0/J_4

DDR_VREF

Qu

Qu

Qu

PROJECT :

PROJECT :

PROJECT :

DDRIII SO

DDRIII SO

DDRIII SO

DDR_VREF

+SM

+SM

DDR_VREF_DQ0

C166

C166

0.1U/50V_6

0.1U/50V_6

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

-DIMM-0

-DIMM-0

-DIMM-0

1

ZE7

ZE7

ZE7

of

of

of

44

44

44

C3C

C3C

C3C

2Wednesday, August 31, 2011

2Wednesday, August 31, 2011

2Wednesday, August 31, 2011

5

Cedar View

D D

C C

(CPU)

I: 7.5", 4 via, 1.65 Gbps

HDM

evel Shifter For HDMI

L

: 7", 3 via, 2.7Gbp s

eDP

.5V

+1

2

2

R3

R3
0/J_6

0/J_6

<

20101125_Colt> Please follow PDG, we will

doing BOM stuff changing in next version CRB

X2_HDMI+[17]

T

X2_HDMI-[17]

T

X1_HDMI+[17]

T
TX1_HDMI-[17]
T

X0_HDMI+[17]

T

X0_HDMI-[17]

T

X3_HDMI+[17]

T

X3_HDMI-[17]

+3

55 1U/6.3V_4

55 1U/6.3V_4

C

C

DDI

0_HDMI_SCL[17]

DDI

0_HDMI_SDA[17]

T33T3

3

T31T3

1

I_DDI0_HPD#[17]

HDM

TX2_HDMI+

66 .1U/10V_4

66 .1U/10V_4

C

C

T

X2_HDMI-

67 .1U/10V_4

67 .1U/10V_4

C

C

T

X1_HDMI+

61 .1U/10V_4

61 .1U/10V_4

C

C

T

X1_HDMI-

68 .1U/10V_4

68 .1U/10V_4

C

C

T

X0_HDMI+

43 .1U/10V_4

43 .1U/10V_4

C

C

T

X0_HDMI-

44 .1U/10V_4

44 .1U/10V_4

C

C

T

X3_HDMI+

41 .1U/10V_4

41 .1U/10V_4

C

C

T

X3_HDMI-

42 .1U/10V_4

42 .1U/10V_4

C

C

R68

R68

*2.2K/J_4

V

AC

Z_BITCLK_CPU[13]

A

CZ_SYNC_CPU[13]

Z_SDINO[13]

AC
AC

Z_SDOUT_CPU[13]

AC

Z_RST#_CPU[13]

*2.2K/J_4

R62

R62

*eDP@2.2K/J_4

*eDP@2.2K/J_4

1_AUX_DP[18]

DDI

1_AUX_DN[18]

DDI

DDI

1_HPD#[18]

DDI

1_TX0_DP[18]

DDI

1_TX0_DN[18]

DDI

1_TX1_DP[18]

DDI

1_TX1_DN[18]

DDI

1_TX2_DP[18]

DDI

1_TX2_DN[18]
1_TX3_DP[18]

DDI

1_TX3_DN[18]

DDI

R45

R45

T3T3
T9T9

T11T1
T7T7

1

7.5K/F_4

7.5K/F_4

R4

R4

H

2 33/J_4

2 33/J_4

0_AUXP

DDI

0_AUXN

DDI

I_DDI0_HPD#

HDM
DDI0_TX2_DP

DDI

0_TX2_DN

DDI

0_TX1_DP

DDI

0_TX1_DN

DDI

0_TX0_DP

DDI

0_TX0_DN

DDI

0_TX3_DP

DDI

0_TX3_DN

_RSVD_TP_H15
_RSVD_TP_J15

H

1_DDC_SCL

DDI

1_DDC_SDA

DDI
DDI

1_AUX_DP
1_AUX_DN

DDI
DDI

1_HPD#

DDI

1_TX0_DP

DDI

1_TX0_DN

DDI

1_TX1_DP
1_TX1_DN

DDI

1_TX2_DP

DDI

1_TX2_DN

DDI

1_TX3_DP

DDI

1_TX3_DN

DDI

_RSVD_TP_H17

H
H

_RSVD_TP_J17

BR

EF1.8V

EXT

_BANDGAP

AC

4

Z_SDINO_R

U24C

U24C

H25

DDI

J22

DDI

C8

D

B8

D

H22

DDI

G2

DDI

G3

DDI

F3

DDI

F2

DDI

D4

DDI

C3

DDI

B7

DDI

A7

DDI

H15

RS

J15

RS

F25

DDI

G27

DDI

D10

D

C10

D

D26

DDI

E11

DDI

F11

DDI

J11

DDI

H11

DDI

F13

DDI

E13

DDI

J13

DDI

K13

DDI

J17

RS

H17

RS

E15

BR

F15

BR

H21

A

F22

AZ

E22

A

F21

A

E21

A

CDV_22MM_REV1P10

CDV_22MM_REV1P10

0_DDC_SCL
0_DDC_SDA

DI0_AUXP
DI0_AUXN

0_HPD
0_TXP0

0_TXN0
0_TXP1
0_TXN1
0_TXP2
0_TXN2
0_TXP3
0_TXN3

VD_TP_H15
VD_TP_J15

1_DDC_SCL
1_DDC_SDA

DI1_AUXP
DI1_AUXN

1_HPD
1_TXP0

1_TXN0
1_TXP1
1_TXN1
1_TXP2
1_TXN2
1_TXP3
1_TXN3

VD_TP_J17
VD_TP_H17

EF18V
EFREXT

ZIL_BCLK

IL_SYNC

ZIL_SDI
ZIL_SDO

ZIL_RST#

3

R

R

397 *1K/J_4

397 *1K/J_4

R

R

398 *1K/J_4

R

R

414

414

150/F_4

150/F_4

*2.2K/J_4

*2.2K/J_4
*2.2K/J_4

*2.2K/J_4

[18]

TA [18]

XLOUT0+ [18]
XLOUT0- [18]
XLOUT1+ [18]
XLOUT1- [18]
XLOUT2+ [18]
XLOUT2- [18]

XLCLKOUT+ [18]
XLCLKOUT- [18]

R6

R6

5

5

*10K/J_4

*10K/J_4

398 *1K/J_4

CRT
C

R4

R4

R

R

413

413

150/F_4

150/F_4

150/F_4

150/F_4

V

+3

I

NT_LVDS_PWM [18]

DARVIEW

DARVIEW

CE

CE

REV = 1.10

REV = 1.10

DDI

DDI

CRT

CRT

DP

L_REFSSCCLKP

D

PL_REFSSCCLKN

DP
DP

LV

DS_CTRL_CLK

LV

DS_CTRL_DATA
LV

LV

DS_DDC_DATA

LVDS VGA

LVDS VGA

I

I

HDA

HDA

3 O

3 O

PA

NEL_BKLTCTL

PA

P

F 6

F 6

CRT

_HSYNC

CRT

_VSYNC

CRT

_RED

CRT

_GREEN

CRT

_BLUE

CRT

_IRTN

CRT

_IREF

_DDC_DATA

_DDC_CLK

L_REFCLKP
L_REFCLKN

DS_DDC_CLK

LV

DS_IBG

LV

DS_VBG

LV

DS_VREFH

LV

DS_VREFL

LV

DS_TXP0

LV

DS_TXN0

LV

DS_TXP1

LV

DS_TXN1

LV

DS_TXP2

LV

DS_TXN2

LV

DS_TXP3

LV

DS_TXN3

LV

DS_CLKP

LV

DS_CLKN

NEL_BKLTEN
ANEL_VDDEN

D14
C14

B12
B11
C11

D12

CRT

A13
E29

E27
F17

E17

DRE

B9

DRE

A9

F28
E24

G24
H24

LI

BG

E10
F10

R426

R426

H2

R428

R428

H3
G10

H10
F8
E8
H7
H8
G5
G6

H4
J4

G22

L

BKLT_EN

E25

NT_LVDS_DIGON_Q

I

F29

_IREF

CRT
CRT

FCLK_R1
FCLK#_R1

R

R

408 681/F_6

408 681/F_6

_DDC_SDA [18]
_DDC_SCL [18]

406 *0/J_4

406 *0/J_4

R

R

405 *0/J_4

405 *0/J_4

R

R

R6

R6

*0/short_6

*0/short_6
*0/short_6

*0/short_6

R52

R52
R48

R48

LCD_CLK
LCD_DA

12.37K/F_4

12.37K/F_4

T
T
T
T
T
T

T
T

_HSYNC [18]

RT_VSYNC [18]

15

15

DREFSSCLK [2]
DRE

FSSCLK# [2]

DRE

FCLK [2]

DRE

FCLK# [2]

T51T5

1
2

T52T5

2

+3

V

CRT

_R [18]

CRT

_G [18]

CRT

_B [18]

L

AYOUT NOTE: PLACE THESE 3 RESISTORS

CLOSE T

O PIN

<20110110> DPL_REFSSCCLK i
registers and logics of the display interface and therefore
needs to be present at all times.

<20100818_Jer

ry> If you implement XDP, you need the PU 2.2K

<20110610> R

20110630> Stuff R38/ R39 PU resistor. Intel will fixed EDID issue by VGA driver and vbios

<

s used to drive internal

emove PU resistor for Intel update.

R39

R39

2.2K/J_4

V

+3

2.2K/J_4

R38

R38

2.2K/J_4

2.2K/J_4

<EMI>

*220P/50V_4

*220P/50V_4

R58

R58

2.2K/J_4

V

+3

2.2K/J_4

R56

R56

2.2K/J_4

2.2K/J_4

<EMI>

*220P/50V_4

*220P/50V_4

1

05

LCD_CLK

TA

LCD_DA

C5

C5

C5

C5

0

0

1

1

*220P/50V_4

*220P/50V_4

_DDC_SDA

CRT

_DDC_SCL

CRT

C6

C5

C5

8

8

C6

*220P/50V_4

*220P/50V_4

5

5

LCD Panel Pow

B B

LCD Panel Backlight (LDS)

EC

PWROK[8,13,16,27]

A A

er (LDS)

EC

PWROK

NT_LVDS_DIGON_Q

I

R3

R3
100K_4

100K_4

EC

PWROK

L

BKLT_EN

R5

R5

3

3

100K_4

100K_4

5

60

60

0

0

U2

U2

2
1

355 *0/J_4

355 *0/J_4

R

R

+3

U2

U2

2
1

3 5

1 *0/J_4

1 *0/J_4

R5

R5

V

+3

29 .1U/10V_4

29 .1U/10V_4

C3

C3

3 5

V

48 .1U/10V_4

48 .1U/10V_4

C

C

TC7SH08FU

TC7SH08FU

4

C7SH08FU

C7SH08FU

T

T

4

NT_LVDS_DIGON [18]

I

NT_LVDS_BLON [18]

I

U24A

U24A

C354

C354

L3

I_RXP0

DM

L2

I_RXN0

DM

M3

I_RXP1

DM

M2

I_RXN1

DM

N2

I_RXP2

DM

N1

I_RXN2

DM

P2

I_RXP3

DM

P3

I_RXN3

DM

N9

I_REFCLKP

DM

N8

I_REFCLKN

DM

T2

I_REF1P5

DM

CDV_22MM_REV1P10

CDV_22MM_REV1P10

<20101109> A

DM

I_REF1.5V

+1.5V

D

MI_TXP0[10]

DM

I_TXN0[10]

D

MI_TXP1[10]

DM

I_TXN1[10]

MI_TXP2[10]

D

I_TXN2[10]

DM

MI_TXP3[10]

D

I_TXN3[10]

DM

LK_PCIE_DMIP[2]

C
C

LK_PCIE_DMIN[2]

*0/short_4

*0/short_4

R450

R450

1U/10V_4

1U/10V_4

For HDMI deep color mode support
(HDM

)

<20100727_S

am> Customer must to use 27MHz due to

racy concerns(<1000ppm) from Intel silicon

accu
perspective.

L

AYOUT NOTE: PLACE CLOSE TO PIN

FCLK_R1

DRE
DREFCLK#_R1

R4

R4

09

09

0/J_4

0/J_4

Y3

Y3

27MHz/+-20PPM_20PF

27MHz/+-20PPM_20PF

R385 1M/J_4R385 1M/J_4

34

34

C3

C3

33P/50V_4

33P/50V_4

4

33P/50V_4

33P/50V_4

R

R

410

410

0/J_4

0/J_4

2n

d source: BG627000289 (ZYG)

35

35

C3

C3

CEDARVIEW

CEDARVIEW

REV = 1.10

REV = 1.10

I

I
DM

DM

1 O

1 O

F 6

F 6

dd C354 to follow CRB v0.7

T

HERMAL SENSOR (THM)

<

20110414> Unstuff Thermal Sensor and related circ uit.

HERM_ALERT#[6,13,27]

T

3

K6

I_TXP0

DM

K5

I_TXN0

DM

L5

I_TXP1

DM

L6

I_TXN1

DM

L9

I_TXP2

DM

L8

I_TXN2

DM

N5

I_TXP3

DM

N6

I_TXN3

DM

R8

VD_TP_R8

RS

R7

VD_TP_R7

RS

T1

I_RCOMP

DM

A

LERT# Pull Up Value

2K ohm

7.5K ohm

10.5K ohm
14K ohm

18.7K ohm

I_REF1.5V_R

DM

V

+3

R115

R115

*

*2K/F_4

*2K/F_4

111 *0/J_4

111 *0/J_4

R

R

lert temperature point

A

75 degree

90 degree
100 degree
105 degree
110 degree

DM

I_RXP0 [10]

DM

I_RXN0 [10]

DM

I_RXP1 [10]
I_RXN1 [10]

DM

I_RXP2 [10]

DM

I_RXN2 [10]

DM

I_RXP3 [10]

DM

I_RXN3 [10]

DM

7.5K/F_4

7.5K/F_4

45

45

R4

R4

THERMAL_SCL THERMAL_SDA

HERM_ALERT#_1

T

*

I_REF1.5V

DM

<20101109> A

U5

U5

*

1

SCL

2

GND

3

ALERT#

2

dd DMI_REF1.5V to follow CRB v0.7

5

SDA

4

VDD

CT7717U

CT7717U

*N

*N

C155

C155
*0.1U/16V_4

*0.1U/16V_4

*

R119 *0/J_4R119 *0/J_4

*

+3

V

C1

C1

48

48

*0.1U/16V_4

*0.1U/16V_4

**

C156

C156
*4.7U/6.3V_6

*4.7U/6.3V_6

ize Document Number Rev

ize Document Number Rev

S

S

S

ize Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Ced

Ced

Ced

ednesday, August 31, 2011

ednesday, August 31, 2011

ednesday, August 31, 2011

W

W

W

2ND_M

2ND_M

C

C

154

154

*0.1U/16V_4

*0.1U/16V_4

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

arview DMI/Display

arview DMI/Display

arview DMI/Display

1

*0/J_4

<20110414> P

*0/J_4

R114

R114

ull up at EC side

BCLK [27]

BDATA [27]

ZE7

ZE7

ZE7

C3C

C3C

C3C

of

425

of

425

of

425

5

edar View (CPU)

C

R7

R7

4 2.2K/J_4

4 2.2K/J_4

R7

R7

1 2.2K/J_4

1 2.2K/J_4

D D

<20100811_Jerry>can be NC but pleas e reserve 2.2K pull
l

ow as CRB. can be removed later depends on CRB

validation status.
<20101019>S

as

C C

tuff R74 R71 for using 0x FFFE_0000

Punit microbase address

XDP_

TDI

R

R

449 51/J_4

449 51/J_4

XDP_

R

R

TDO

459 51/J_4

459 51/J_4

TMS

XDP_

R

R

470 51/J_4

470 51/J_4

XDP_

TCLK

446 51/J_4

446 51/J_4

R

R

XDP_

R

R

TRST#

448 51/J_4

448 51/J_4

2

2

R7

R7

49.9/F_4

49.9/F_4

HV_
MV

9

9

R6

R6

49.9/F_4

49.9/F_4

T45T45
T46T46
T47T47
T48T48
T49T49

05V

+1.

GPIO_RCOMP

_GPIO_RCOMP

TCLK

XDP_

TDI

XDP_
XDP_

TDO
TMS

XDP_

TRST#

XDP_

W25
W26

L26

L27
K28
K25

J28
K26
K27
H27
K30

L29

L30
K29

J31
H30

K24
K23

C25
C24
B25
D24
B24

R5
R6

N24
N25

U24D

U24D

RSVD_L26
RSVD_L27
RSVD_K28
RSVD_K25
RSVD_J28
RSVD_K26
RSVD_K27
RSVD_H27
RSVD_K30
RSVD_L29
RSVD_L30
RSVD_K29
RSVD_J31
RSVD_H30

HV_GPI
M

V_GPIO_RCOMP

T

CLK

TD

I

TD

O

TMS

ST#

TR
RSVD_R5

RSVD_R6
RSVD_W
RSVD_W
RSVD_N24
RSVD_N25

O_RCOMP

25
26

4

3

2

1

06

DARVIEW

DARVIEW

CE

CE

REV = 1.10

REV = 1.10

B18

I#

SM

C22

I/LINT1

NM

RSVD_C18

ST

H

H
IC

IC

U

U
CP

CP

PCLK#

DPRST

DPLSLP#
CPUSLP#

IN

TR/LINT0

IN

T

HERMTRIP#

RSVD_L11

PBE#

PROCHOT

RGOOD

PW

RESET

DBR#

PRDY
PREQ#

HPLL_REFCLK_P

HPLL_REFCLK

RSVD_E19
RSVD_F19

SVI

D_ALERT#

SVI

D_CLK

SVI

D_DATA

RSVD_K21

RSVD_L22
RSVD_L24

R

R

386 *0/short_4

386 *0/short_4

C18
D22

C21

P#

B21
B22

A23

IT#

D20

THRMTRIP#

H_

B20
L11

H_

FERR#_R

400 *0/short_4

400 *0/short_4

R

PROCHOT_R#
PWRGD
TRST#

DBRESET_N_CDV

BPM4_PRDY#
BPM5_PREQ#

K_MCH_BCLK
K_MCH_BCLK#

R

R

399

399

75/J_4

75/J_4

R

C20

H_

A19

#

H_

D23

PL

G30

#

E30

XDP_

H_

H29

#

H_

G29

CL

J19

CL

K19
E19

F19

B16
D18
C16

K21
L22
L24

CH_DPRSTP# [13]

I

DPSLP# [13]

H_
CPUSL

_INIT# [11]

H

_INTR [11]

H

R3

R3

3 1K/J_4

3 1K/J_4

SVID_ALERT# [31]

VR_

SVID_CLK [31]

VR_

H_SMI# [11]
H_

NMI [11]

H_A20M# [11]
H_STPCLK# [11]

P# [11]

FERR# [11]

H_

PWRGD [13,16]

H_
P

LTRST# [13,16,22,25,26,27]

T43T43
T44T44

K_MCH_BCLK [2]

CL
CL

K_MCH_BCLK# [2]

+3V

R

R
110/F_4

110/F_4

+1.

05V

R381

R381
100/J_4

100/J_4

Host CLK 100/133 MHz

+1.

05V

416

416

SVID_DATA [31]

VR_

<20100811_J

377 *0/short_4

377 *0/short_4

R

R

<20110520>Need c

erry>please use 100+/-5% as in PDG.

H_

PROCHOT# [31]

onfirm with Intel

H_

BPM4_PRDY#
BPM5_PREQ#

H_

268

268

C

C

.1U/10V_4

.1U/10V_4

42 *51/J_4

42 *51/J_4

R4

R4

443 51/J_4

443 51/J_4

R

R

8V

+1.

CDV_22MM_REV1P10

CDV_22MM_REV1P10

B B

125 Degree P

IMVP_PWRGD[27,31]

Fr

om CPU

A A

rotection(CPU)

IMVP_PWRGD

H_THRMTRIP#

R16 *0/short_4R16 *0/short_4

+1.

2

R17

R17
1K/J_4

1K/J_4

Q1

Q1

1 3

METR3904-G

METR3904-G

05V

3

Q2
2N7002KQ22N7002K

1

2

hutdown System Power Immediately

S

SYS_SHDN# [30,35]

T

o System Power

PM_THRMTRIP# [11]

To Tiger Point

5

4 O

4 O

F 6

F 6

U FAN CTRL(THM)

CP

+5V

+3V

R512

R512

R505 *0/short_6R505 *0/short_6

10K/J_4

10K/J_4

FANSIG [27]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, August 31, 2011

Date: Sheet of

Wednesday, August 31, 2011

Date: Sheet of

2

Wednesday, August 31, 2011

C365 0.1U/16V_4C365 0.1U/16V_4

CN18

+5V_FANVCC

FANSIG
FAN_PWM_CNCPUFAN#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

C

C

C

edarview Miscellaneous

edarview Miscellaneous

edarview Miscellaneous

CN18

345
2
1

FAN CONN

FAN CONN

1

6

ZE7

ZE7

ZE7

C3C

C3C

C3C

426

426

426

2

R509

R509
10K/J_4

10K/J_4

+5V

R507

R507
10K/J_4

10K/J_4

+3V

THERM_ALERT#[5,13,27]

CPUFAN#[27]

M SIGNAL

EC PW

EMI

For

FAN_PWM_CN

4

3

R514 * 0/J_4R514 *0/J_4

FANSIG

C368

C368
*220P/50V_6

*220P/50V_6

1 3

Q43 METR3904-GQ43 METR3904-G

C372

C372
*220P/50V_6

*220P/50V_6

1

Cedar View

(CPU)

LAYOUT NOTE: place close to VCCADDR pin

352

352

C

C
*22U/6.3V_8

129

129

C

C

C

C

149

149

2.2U/6.3V_6

2.2U/6.3V_6

R

R

77 *0/short_6

77 *0/short_6

.8V

+1

*22U/6.3V_8

130

130

C

C

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C1

C1

53

53

2.2U/6.3V_6

2.2U/6.3V_6

+

1.05V

C8

C8

1U/10V_4

1U/10V_4

+

3.3V_PR IME

R

R

384 0.2A/600ohm_6

384 0.2A/600ohm_6

C1

C1

2.2U/6.3V_6

2.2U/6.3V_6

3

3

A A

B B

<20101126_Colt> Please follow PDG to
placehold the 0805 capacitor

V

CCDDRAON_1.5[8]

R

R

134 *NS3@0/short_8

134 *NS3@0/short_8

*

+1

.5VSUS

Deep Standby

For

C

C

82 *0.1U/10V_4

+1

.5V

+1

.8V

31 *0/short_6

31 *0/short_6

R

R

46 *0/short_6

46 *0/short_6

R

R

82 *0.1U/10V_4

C

C

93 1U/10V_4

93 1U/10V_4

*1U/10V_4

*1U/10V_4

+1

.05V

<20100830> Add Farrite bead for VCCDAC low pass filter

R

R

47 *0/short_6

3.3V_PR IME

+

_1.05_CORE_RSENSE

V

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

C C

47 *0/short_6

94 *0/short_6

94 *0/short_6

R

R

120

120

C

C
1U/10V_4

1U/10V_4

28

28

C

C

146

146

419 *0/short_6

419 *0/short_6

R

R

R5

R5

5 *0/short_6

5 *0/short_6

C3

C3

36 47U/6.3V_8

36 47U/6.3V_8

C3

C3

37 47U/6.3V_8

37 47U/6.3V_8

C

C

54 2.2U/6.3V_4

54 2.2U/6.3V_4

2

141

141

C

C
*1U/10V_4

*1U/10V_4

C

C

92 *1U/10V_4

92 *1U/10V_4

C

C

116 1U/10V _4

116 1U/10V _4

CCDDRAON_1.5

V

C1

C1

52

52

2.2U/6.3V_6

2.2U/6.3V_6

91 1U/10V_4

91 1U/10V_4

C

C

139

139

C

C

*2.2U/6.3V_4

*2.2U/6.3V_4

V

_1.05_CORE_RSENSE

V

_1.05_CORE_EAST
V
V

V

V

C5

C5

6 1U/10V_4

6 1U/10V_4

R5

R5

4 *0/J_6

4 *0/J_6

C

C

59 2.2U/6.3V_4

59 2.2U/6.3V_4

_1.05_CORE_RSENSE
_1.05_VCCDDR

_1.05_VCCDDR

CCCKDDR_VSM

CCADP_1.05

V

V

CCADP0_1.5

V

CCADP1_1.5

V

_1.05_CORE_EAST
CCAGPIO_1.5

V

CCAGPIO_1.8

V

CCAGPIO_3.3

V

V

CCADAC_1.8
CCALVDS_1.8

V

CCDLVDS_1.8

V

_1.05_CORE_EAST

V
V

CCAZILAON_3.3

CCSFRMPL_1.5

V

CCDMPL_1.05

V

CCPLLCPU0_1.05

V

CCPLLCPU1_1.05

V

V

CCAHPLL_1.05

AA14
AA16

AH14
AH19
AK23

AG31

W16
W18

W11
W13

AL11
AL16
AL21

AA18
AA11

N30
N31

V4

W8
W9

AJ6

AK6

AK5

B5
C6
D6

K17

L18
L19

L16

N18
D30

D31
B13

H5

J1

L21

B29
A30

B27
C29
B30

B26

U24E

U24E

V

CCADDR_1

V

CCADDR_2
CCADDR_3

V

CCADDR_4

V

CCRAMXXX_1

V

CCRAMXXX_2

V
V

CCRAMXXX_3

V

CCACKDDR_1

V

CCACKDDR_2
CCADLLDDR_1

V

CCADLLDDR_2

V

CCCKDDR_1

V
V

CCCKDDR_2

V_

SM_1

V_

SM_2
SM_3

V_

SM_4

V_

SM_5

V_

SM_6

V_
V_

SM_7

V_

SM_8

V

CCADP_1

V

CCADP_2
CCADP_3

V

CCADP0_SFR

V

CCADP1_SFR

V
V

CCAGPIO_LV

V

CCAGPIO_REF

V

CCAGPIO_DIO
CCAGPIO_1

V

CCAGPIO_2

V

CCADAC

V
V

CCALVDS

V

CCDLVDS

CCDIO

V

CCAZILAON_1

V

CCAZILAON_2

V
V

CCSFRMPL

V

CCDMPL

V

CCPLLCPU0
CCPLLCPU1_1

V

CCPLLCPU1_2

V

CCAHPLL

V

3

DARVIEW

DARVIEW

CE

CE

REV = 1.10

REV = 1.10

U

DDR

DDR

U
CP

CP

POWER

POWER

DMI

DMI

L

L
PL

PL

4

V

CC_CPU_01

V

CC_CPU_02
CC_CPU_03

V

CC_CPU_04

V

CC_CPU_05

V

CC_CPU_06

V

CC_CPU_07

V
V

CC_CPU_08

V

CC_CPU_09

V

CC_CPU_10

V

CC_CPU_11
CC_CPU_12

V

CC_CPU_13

V

CC_CPU_14

V

CC_CPU_15

V

CC_CPU_16

V
V

CC_CPU_17

V

CC_CPU_18

V

CC_CPU_19

V

CC_CPU_20
CC_CPU_21

V

CC_CPU_22

V

CC_CPU_23

V

CC_CPU_24

V
V

CC_CPU_25

V

CC_CPU_26

V

CC_CPU_27

V

CC_CPU_28

V

CC_CPU_29

CC_GFX_01

V
V

CC_GFX_02

V

CC_GFX_03

V

CC_GFX_04

V

CC_GFX_05

V

CC_GFX_06
CC_GFX_07

V

CC_GFX_08

V

CC_GFX_09

V

CC_GFX_10

V
V

CC_GFX_11
V

CCADMI_1

V

CCADMI_2

V

CCADMI_3

CCADMI_PLLSFR

V

CCFHV_1

V

CCFHV_2

V
V

CCFHV_3

V

CC_CPUSENSE

V

SS_CPUSENSE
CC_GFXSENSE

V

SS_GFXSENSE

V

CCTHRM_1

V
V

CCTHRM_2

1.1V (0.75V~1.18V)

5.95A

+

VCC_CORE

P18

1U/10V_4

1U/10V_4

P19
P21
P28
P29
P30
R22
R23
R24
R25
R26
R27
T19
T21
T29
T30
T31
U22
U23
U24
U25
U26
U27
V18
V19
V21
V28
V29
V30

N11
N13
P11
P13
R10
R9
T11
T13
U10
V11
V13

B4
C5
A4
K4

V16
T16

V14
M28

M30
U8

U7
N16

K2

C1

C1

C1

C1

00

00

26

26

*1U/10V_4

*1U/10V_4

1U/10V_4

1U/10V_4

1.05V (0.76V~1.05V)

1.98A

CCGFX

V

C9

C9

C9

C9

5

5

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C

C

CCADMI_1.05

V

C

C

CCADMI_1.5

V
V

_1.05_CORE_RSENSE

CP

UVCC_SENSE [31]

C

PUVSS_SENSE [31]

VCC_SENSE [31]

GT

VSS_SENSE [31]

GT

V

_1.8_RSENSE

C3

C3
*1U/10V_4

*1U/10V_4

5

22U/6.3V_8

22U/6.3V_8

*1U/10V_4

*1U/10V_4

C

C

C1

C1

C

C

C1

C1

C1

C1

125

125

18

18

105

105

01

01

*1U/10V_4

*1U/10V_4

22U/6.3V_8

22U/6.3V_8

LAYOUT NOTE: PLACE
ONE 1U CAP ON BOT LAYER

LAYOUT NOTE: PLACE
TWO CAPS ON BOT LAYER

C9

C9

C

C

4

4

117

117

8

8

60 1U/10V_4

60 1U/10V_4

88 1U/10V_4

88 1U/10V_4

R

R

437 *0/short_6

437 *0/short_6

50

50

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

+1

.8V

22U/6.3V_8

22U/6.3V_8

C1

C1

03

03

06

06

22U/6.3V_8

22U/6.3V_8

C1

C1

15

15

22U/6.3V_8

22U/6.3V_8

423 *0/short_6

423 *0/short_6

R

R

456 *0/short_6

456 *0/short_6

R

R

C

C

112

112

V

CCPLLCPU0_1.05

+

1.05V

+1

.5V

R4

R4

0 *0/J_6

0 *0/J_6

6

V

CCPLLCPU1_1.05

7

C

edar View PLL Power

Default stuff 1.5VPLL, Intel verify whether

1.05VPLL is ok or not

CCSFRMPL_1.5

V

CCADP0_1.5

V

V

CCADP1_1.5

C1

C1

34

34

1U/10V_4

1U/10V_4

C5

C5

2

2

1U/10V_4

1U/10V_4

3

3

C5

C5
1U/10V_4

1U/10V_4

R

R

112 *1.5VP LL@0/short_6

112 *1.5VP LL@0/short_6

L18

L18

1.05VPLL@10uH/100mA_8

1.05VPLL@10uH/100mA_8

*

*
C

C

142

142

*10U/6.3V_8

*10U/6.3V_8

29 *1.5VPLL@0/short_6

29 *1.5VPLL@0/short_6

R

R

L3

L3

1.05VPLL@10uH/100mA_8

1.05VPLL@10uH/100mA_8

*

*
C2

C2

8

8

*10U/6.3V_8

*10U/6.3V_8

R

R

36 *1.5VPLL@0/short_6

36 *1.5VPLL@0/short_6

L4

L4
*

*

1.05VPLL@10uH/100mA_8

1.05VPLL@10uH/100mA_8
9

9

C2

C2
*10U/6.3V_8

*10U/6.3V_8

Cedar View LVDS Power

BOM structure

w/LVDS: stuff R436/ C345/ L38/ C75
w/EDP: unstuff R436/ C75
change L38/ C345 to 0ohm

V

CCDLVDS_1.8

CCALVDS_1.8

V

C7

C7

LVDS@4.7u/6.3V_6

LVDS@4.7u/6.3V_6

@0.1uH/300mA_6

@0.1uH/300mA_6

5

5

L38BOM

L38BOM

C

C

BOM@1U/10V_4

BOM@1U/10V_4

345

345

.5V

+1

+1

.5V

+1

.5V

R

R

436 LVDS@0/J_6

436 LVDS@0/J_6

8

07

+1

.05V

+1

.05V

.05V

+1

.8V

+1

LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR

.5VSUS

2nd source: CV01001MN32

1.05V

VCCPLLCPU0_1.05

1

1

C3

C3

4.7u/6.3V_6

5 OF

5 OF

6

CDV_22MM_REV1P10

CDV_22MM_REV1P10

D D

1

2

3

6

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

4

5

4.7u/6.3V_6

CCPLLCPU1_1.05

V

4.7u/6.3V_6

4.7u/6.3V_6

V

CCAHPLL_1.05

4.7u/6.3V_6

4.7u/6.3V_6

C4

C4

5

5

C32

C32

C4

C4

1U/10V_4

1U/10V_4

C4

C4

1U/10V_4

1U/10V_4

C49

C49

1U/10V_4

1U/10V_4

/100mA_8

/100mA_8

0

0

/100mA_8

/100mA_8

6

6

/100mA_8

/100mA_8

6

+

L610uH

L610uH

+

1.05V

L1110uH

L1110uH

+1.05V

L1010uH

L1010uH

CCCKDDR_VSM

V

C

C

359

359

C3

C3

62

10U/6.3V_8

10U/6.3V_8

R89 *0/short_6R89 *0/short_6

62

<2010/9/27>Reserve 0805 footprint for farrite bead
CV01001MN16 due to co-layout issue.

440 *0/short_6

440 *0/short_6

R

R

S

S

Size Document Number Rev

ize Document Number Rev

ize Document Number Rev

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

7

Wednesday, August 31, 2011

1U/6.3V_4

1U/6.3V_4

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

V

_1.05_VCCDDR

V_1.05_CORE_RSENSE

489 *NS3@0/short_8

489 *NS3@0/short_8

R

R

+1.05V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

edarView Power

edarView Power

edarView Power

C

C

C

+1

ZE7

ZE7

ZE7

8

C3

C3

C3

of

427

of

427

of

427

C

C

C

5

Cedar View

D D

<Layout note>
PLACE RESISTORS AND CAP CLOSE TO CPU DDR_VREF PIN

ON_1.5[7]

VCCDDRA

DDR_VREF

+SM

C C

<

20100810_Jerry> Please refer to Cedar Trail CPET HW section(#454349),

it is to implement Deep Standby. And please waiting the whitepaper for implementation detail.

<20100817_Jerry
because the SV folks expressed a preference on using PWROK over PWRGOOD for CDV.
This has changed from PNV to CDV.

B B

DRA

>DELAY_VR_PWRGOOD on CDV should be connected to the XDP_PWRGOOD

M Reset (CPU)

(CPU)

R482

R482

1K/F_4

1K/F_4

R492

R492

<20110520>Ch

*0/J_4

*0/J_4

ange 12.1K to 121ohm to follow CRBv1.5

<20110520>Change 10K to 100ohm to follow CRBv1.5

R483

R483

R493

R493
1K/F_4

1K/F_4

ECPW

*0/short_4

*0/short_4

ROK[5,13,16,27]

<20100811_Jerry

C360

C360

0.1U/16V_4

0.1U/16V_4

R99

R99

4

CLK_DDR3_REFCLK[2]
CLK_DDR3_REFCLK#[2]

3

T53T5
121/F_4

121/F_4

> R485 please follow CRB schematic. (274ohm)

R98

R98
100/F_4

100/F_4

R485

R485

274/F_4

274/F_4

A_A[15:0][4]

M_

R488

R488

22.6/F_4

22.6/F_4

M

3

U24B

U24B

M_

A_A0

AK14
AK16

AJ14

AJ16
AK18
AH18

AJ18
AK20

AJ20
AH20

AJ12
AK21

AJ21

AJ8

AH22

AJ22
AH10

AJ10

AJ11
AK12

AH13
AK22

AH12

AH8

AK11

AK8

AH23

AJ24
AK24
AH24

AK10

AK7

AL9
AJ7

AG15
AF15
AF17
AG17
AD17
AC17
AC15
AD15

AK25

AJ27

AL28
AC19

AB19

AA5

AJ26

AJ25
AK27

AB11
AB13
AF19
AG19

Y2
AB26
AE30
AB21
AG11

AG2
AB8
AA3

W7

8

DDR3_MA0
DDR3_MA1
DDR3_MA2
DDR3_MA3
DDR3_MA4
DDR3_MA5
DDR3_MA6
DDR3_MA7
DDR3_MA8
DDR3_MA9
DDR3_MA10
DDR3_MA11
DDR3_MA12
DDR3_MA13
DDR3_MA14
DDR3_MA15

DDR3_W
DDR3_CAS#
DDR3_RAS#

DDR3_BS0
DDR3_BS1
DDR3_BS2

DDR3_CS#0
DDR3_CS#1
DDR3_CS#2
DDR3_CS#3

DDR3_CKE0
DDR3_CKE1
DDR3_CKE2
DDR3_CKE3

DDR3_ODT0
DDR3_ODT1
DDR3_ODT2
DDR3_ODT3

DDR3_CK0
DDR3_CK#0
DDR3_CK1
DDR3_CK#1
DDR3_CK2
DDR3_CK#2
DDR3_CK3
DDR3_CK#3

DDR3_DRAMRST#
DDR3_VREF

DDR3_VREF_NCTF
DDR3_REFP

DDR3_REFN

DDR3_DRAM_PW
DDR3_VCCA_PW

DDR3_ODTPU
DDR3_CMDPU
DDR3_DQPU

RSVD_TP_AB11
RSVD_TP_AB13
RSVD_TP_AF19
RSVD_TP_AG19

DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7

CDV_22M

CDV_22M

M_

A_A1

M_

A_A2

M_

A_A3
A_A4

M_

A_A5

M_

A_A6

M_

A_A7

M_

A_A8

M_

A_A9

M_
M_

A_A10

M_

A_A11

M_

A_A12

M_

A_A13

M_

A_A14

M_

A_A15

M_

DDR_VREF

DDRA

M_
M_

M_
M_
M_

M

_CS#2

M

_CS#3

M

_CKE2

M

_CKE3

M_
M_

M

_CLK2

M

_CLK2#

M

_CLK3

M

_CLK3#

MRST#_R

M_PWROK

M_
M

_CMDPU

M_

R484

R484

33.2/F_4

33.2/F_4

M_
M_
M_
M_
M_
M_
M_
M_

A_WE#
A_CAS#
A_RAS#

A_BS0
A_BS1
A_BS2

ODT2
ODT3

ODTPU
DQPU

A_DM0
A_DM1
A_DM2
A_DM3
A_DM4
A_DM5
A_DM6
A_DM7

M_

A_WE#[4]

M_

A_CAS#[4]

M_

A_RAS#[4]

M

_A_BS0[4]

M

_A_BS1[4]

M

_A_BS2[4]

_CS#2[4]

M

_CS#3[4]

M

M

_CKE2[4]

M

_CKE3[4]

M_

ODT2[4]

M_

ODT3[4]

_CLK2[4]

M

_CLK2#[4]

M

_CLK3[4]

M
M

_CLK3#[4]

DDR3_DRA

*

DELA

Y_VR_PWRGD_CDV

C361

C361

*0.01U/25V_4

*0.01U/25V_4

_A_DM[7:0][4]

E#

DDR3

DDR3

M_REV1P10

M_REV1P10

ROK

ROK

CE

CE

DARVIEW

DARVIEW

1.5V
5V

1.

REV = 1.10

REV = 1.10

2 OF 6

2 OF 6

2

DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8

DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_DQ32
DDR3_DQ33
DDR3_DQ34
DDR3_DQ35
DDR3_DQ36
DDR3_DQ37
DDR3_DQ38
DDR3_DQ39
DDR3_DQ40
DDR3_DQ41
DDR3_DQ42
DDR3_DQ43
DDR3_DQ44
DDR3_DQ45
DDR3_DQ46
DDR3_DQ47
DDR3_DQ48
DDR3_DQ49
DDR3_DQ50
DDR3_DQ51
DDR3_DQ52
DDR3_DQ53
DDR3_DQ54
DDR3_DQ55
DDR3_DQ56
DDR3_DQ57
DDR3_DQ58
DDR3_DQ59
DDR3_DQ60
DDR3_DQ61
DDR3_DQ62
DDR3_DQ63

DDR3_DQS0
DDR3_DQS1
DDR3_DQS2
DDR3_DQS3
DDR3_DQS4
DDR3_DQS5
DDR3_DQS6
DDR3_DQS7

DDR3_DQS#0
DDR3_DQS#1
DDR3_DQS#2
DDR3_DQS#3
DDR3_DQS#4
DDR3_DQS#5
DDR3_DQS#6
DDR3_DQS#7

Y3
Y2
AC30
AC31
W3
W2
AB28
AB30
AA24
AA22
AE27
AE26
AB27
AA25
AD25
AD27
AD29
AE29
AJ30
AK29
AD28
AD30
AG30
AJ29
AE24
AG24
AD22
AC21
AG27
AG25
AG21
AE21
AD13
AD11
AG8
AG7
AG13
AE13
AD10
AF8
AH2
AG3
AD2
AD3
AH4
AK3
AE2
AD4
AD7
AD6
AA6
AB5
AE8
AE5
AB9
AA8
AB2
AB4
W4
V3
AC2
AB3
Y2
W1

AA30
AB24
AF30
AE22
AG10
AF4
AB6
Y3

AA31
AB25
AF29
AF22
AF10
AF3
AB7
AA2

1

_A_DQ[63:0] [4]

M_

A_DQ0

0

M_

A_DQ1

9

M_

A_DQ2

M_

A_DQ3
A_DQ4

M_

1

A_DQ5

M_

8

A_DQ6

M_

A_DQ7

M_

A_DQ8

M_

A_DQ9

M_
M_

A_DQ10

M_

A_DQ11

M_

A_DQ12

M_

A_DQ13

M_

A_DQ14

M_

A_DQ15

M_

A_DQ16

M_

A_DQ17

M_

A_DQ18
A_DQ19

M_

A_DQ20

M_

A_DQ21

M_

A_DQ22

M_

A_DQ23

M_

A_DQ24

M_
M_

A_DQ25

M_

A_DQ26

M_

A_DQ27

M_

A_DQ28

M_

A_DQ29

M_

A_DQ30

M_

A_DQ31

M_

A_DQ32

M_

A_DQ33

M_

A_DQ34
A_DQ35

M_

A_DQ36

M_

A_DQ37

M_

A_DQ38

M_

A_DQ39

M_
M_

A_DQ40

M_

A_DQ41

M_

A_DQ42

M_

A_DQ43

M_

A_DQ44

M_

A_DQ45

M_

A_DQ46

M_

A_DQ47

M_

A_DQ48

M_

A_DQ49
A_DQ50

M_

A_DQ51

M_

A_DQ52

M_

A_DQ53

M_

A_DQ54

M_
M_

A_DQ55

M_

A_DQ56

M_

A_DQ57

M_

A_DQ58

M_

A_DQ59

M_

A_DQ60

M_

A_DQ61

M_

A_DQ62

M_

A_DQ63
A_DQS0

M_

A_DQS1

M_

A_DQS2

M_

A_DQS3

M_

A_DQS4

M_
M_

A_DQS5

M_

A_DQS6

M_

A_DQS7

M_

A_DQS#0

M_

A_DQS#1

M_

A_DQS#2

M_

A_DQS#3

M_

A_DQS#4
A_DQS#5

M_

A_DQS#6

M_

A_DQS#7

M_

M

M

_A_DQS[7:0] [4]

_A_DQS#[7:0] [4]

M

08

<20110520>Need to confirm with Intel if
we need to add series 100ohm resistor

A A

DDR3_DRA

MRST#[4]

R537 *0/short_4R537 *0/short_4

C159

C159

0.1U/16V_4

0.1U/16V_4

<20110727> Add C159 to suppress glitch

5

+1.5VSUS

DDR3_DRA

<20110607>Keep ori
<20110707_Nick> Please stuff 100K pull down

<20110607>Keep original design first for DRAMRST#

ck> Please un-stuff 1K pull up

<20110707_Ni

R538

R538
*1K/F_4

*1K/F_4

MRST#_NS

R539 *0/short_4R539 *0/short_4

ginal design first for DRAMRST#

MRST#_R

DDR3_DRA

R474

R474
100K/J_4

100K/J_4

4

<20110727>Con

nect DDRAM_PWROK between CDV and RT8207L to meet JEDEC timing spec

+1.5VSU

S

ON_1.5

DDRA

VCCDDRA

M_PWROK[27,32]

3

R100

R100
10K/J_4

10K/J_4

DDRAM_PWROK

R97

R97
*0/J_4

*0/J_4

C388

C388

<20110727> Reserv

*1U/10V_6

*1U/10V_6

e C388 for RC delay

2

Qu

Qu

Qu

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

PROJECT :

PROJECT :

Si

Si

Size Document Number Rev

ze Document Number Rev

ze Document Number Rev

Date: Sheet

ednesday, August 31, 2011

Date: Sheet

ednesday, August 31, 2011

Date: Sheet

ednesday, August 31, 2011

W

W

W

PROJECT :

Ce

Ce

Ce

darView DDR

darView DDR

darView DDR

ZE7

ZE7

ZE7

of

428

of

428

of

1

428

C3C

C3C

C3C

1

Cedar View

A A

(CPU)

U24F

U24F

1

A1

VSS

A1

6

VSS

A2

1

VSS

A2

5

VSS

AA1

VSS

0

AA1

VSS

3

AA1

VSS

AA1

9

VSS

AA2

1

VSS

AA2

3

VSS

AA2

6

VSS

7

AA2

VSS

9

AA2

VSS

AA7

VSS

AA9

VSS

AB1

5

VSS

AB1

7

VSS

3

AB2

VSS

9

AB2

VSS

1

AC

VSS

10

AC

VSS

AC

11

VSS

AC

13

VSS

AC

22

VSS

28

AC

VSS

4

AC

VSS

19

AD

VSS

AD

21

VSS

AD

24

VSS

AD

26

VSS

AD

5

VSS

8

AD

VSS

AE1

VSS

0

AE1

VSS

AE1

1

VSS

AE1

5

VSS

AE1

7

VSS

9

AE1

VSS

AE3

VSS

1

AE3

VSS

11

AF

VSS

AF

13

VSS

AF

21

VSS

AF

24

VSS

28

AF

VSS

7

AF

VSS

22

AG

VSS

AG

5

VSS

AH

26

VSS

AH

28

VSS

AH

6

VSS

9

AH

VSS

2

AJ

VSS

3

AJ

VSS

AK1

3

VSS

AK1

9

VSS

AK2

8

VSS

AK9

VSS

13

AL

VSS

19

AL

VSS

23

AL

VSS

AL

25

VSS

AL

7

VSS

B1

0

VSS

4

B1

VSS

9

B1

VSS

3

B2

VSS

C1

2

VSS

C2

6

VSS

C3

0

VSS

C7

VSS

9

D1

VSS

8

D2

VSS

D8

VSS

D9

VSS

E2

VSS

E5

VSS

E7

VSS

4

F2

VSS

F4

VSS

G1

VSS

G11

VSS

G13

VSS

G15

VSS

G17

VSS

G19

VSS

G21

VSS

G31

VSS

G8

VSS

3

H1

VSS

CDV_22MM_REV1P10

CDV_22MM_REV1P10

DARVIEW

DARVIEW

CE

CE

REV = 1.10

REV = 1.10

D

D
GN

GN

VSS_

VSSA_

6 OF

6 OF

CDVDET
CRTDAC

6

6

9

H1

VSS

H2

6

VSS

H2

8

VSS

H6

VSS

0

J1

VSS

J2

VSS

1

J2

VSS

J3

0

VSS

K1

1

VSS

K1

5

VSS

K3

VSS

K7

VSS

K8

VSS

K9

VSS

L1

VSS

L10

VSS

L13

VSS

L23

VSS

L25

VSS

L31

VSS

L7

VSS

M2

9

VSS

M4

VSS

N1

0

VSS

4

N1

VSS

9

N1

VSS

1

N2

VSS

N2

2

VSS

N2

3

VSS

N2

6

VSS

N2

7

VSS

8

N2

VSS

N4

VSS

N7

VSS

P1

4

VSS

P1

6

VSS

P4

VSS

4

T1

VSS

8

T1

VSS

T3

VSS

U5

VSS

U6

VSS

U9

VSS

V2

VSS

0

W1

VSS

4

W1

VSS

9

W1

VSS

W2

VSS

W2

1

VSS

W2

2

VSS

W2

3

VSS

4

W2

VSS

7

W2

VSS

0

W3

VSS

W5

VSS

W6

VSS

Y4

VSS

7

A2

VSS

9

A2

VSS

A3

VSS

AH

1

VSS

AJ

1

VSS

31

AJ

VSS

AK1

VSS

AK2

VSS

AK3

0

VSS

AK3

1

VSS

AL

2

VSS

AL

29

VSS

3

AL

VSS

30

AL

VSS

5

AL

VSS

B2

VSS

B3

VSS

1

B3

VSS

C1

VSS

C2

VSS

C3

1

VSS

E1

VSS

L14
D13

09

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

ize Document Number Rev

ize Document Number Rev

ize Document Number Rev

S

S

S

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

1

Wednesday, August 31, 2011

PROJECT :

Ce

Ce

Ce

darView GND/ Deep Standby

darView GND/ Deep Standby

darView GND/ Deep Standby

ZE7

ZE7

ZE7

C

C

C

C3

C3

C3

of

429

of

429

of

429

1

Tig

er Point (CLG)

P

P

TG

22B

22B

U

U

DM

I_RXN0[5]

DM

I_RXP0[5]

I_TXN0[5]

DM
D

MI_TXP0[5]
DM

I_RXN1[5]

DM

I_RXP1[5]

I_TXN1[5]

DM
DMI_TXP1[5]

DMI_RXN2[5]
DM

I_RXP2[5]

DM

I_TXN2[5]

MI_TXP2[5]

D

I_RXN3[5]

DM
DM

I_RXP3[5]

DM

I_TXN3[5]

MI_TXP3[5]

20110222> ES2 CPU DMI will change

<

x4 to x2

from

LAN

WLAN

Card Reader

Media Processor

20110630> No support PCI-E in 3G card

A A

<

D

PC

IE_RXN0[22]

PC

IE_RXP0[22]

PC

IE_TXN0[22]
IE_TXP0[22]

PC

IE_RXN1[25]

PC
PC

IE_RXP1[25]

IE_TXN1[25]

PC
PC

IE_TXP1[25]

PC

IE_RXN2[26]

PC

IE_RXP2[26]

PC

IE_TXN2[26]
IE_TXP2[26]

PC

IE_RXN3[25]

PC

IE_RXP3[25]

PC

PC

IE_TXN3[25]
IE_TXP3[25]

PC

+1.

96 .1U/10V_4

96 .1U/10V_4

C

C
C90 .1U/10V_4C90 .1U/10V_4

113 .1U/10V_4

113 .1U/10V_4

C

C

104 .1U/10V_4

104 .1U/10V_4

C

C
R8

R8

1 *0/J_4

1 *0/J_4

R8

R8

0 *0/J_4

0 *0/J_4

C

C

110 *.1U/10V_4

110 *.1U/10V_4
122 *.1U/10V_4

122 *.1U/10V_4

C

C
R88 *0/J_4R88 *0/J_4
R8

R8

6 *0/J_4

6 *0/J_4

C

C

124 *.1U/10V_4

124 *.1U/10V_4

C

C

132 *.1U/10V_4

132 *.1U/10V_4

C63 .1U/10V_4C63 .1U/10V_4
C

C

71 .1U/10V_4

71 .1U/10V_4

C

C

343 .1U/10V_4

343 .1U/10V_4

C

C

344 .1U/10V_4

344 .1U/10V_4

C

C

87 .1U/10V_4

87 .1U/10V_4
80 .1U/10V_4

80 .1U/10V_4

C

C

C

C

347 *.1U/10V_4

347 *.1U/10V_4

C

C

346 *.1U/10V_4

346 *.1U/10V_4

<Layout note>
Close to pin within 500mil

425 24.9/F_4

425 24.9/F_4

R

R

5V

CL
C

DM

MI_TXP0_C

D

DM
D

MI_TXP1_C
DM
DM
DM
D

MI_TXP2_C
DM
DM
DM
D

MI_TXP3_C

PC
P

CIE_TXP1_C

PC
P

CIE_TXP2_C

PC

CIE_TXP3_C

P

K_PCIE_ICH#[2]

LK_PCIE_ICH[2]

I_TXN0_C

I_TXN1_C
I_RXN2_R

I_RXP2_R
I_TXN2_C

I_RXN3_R
I_RXP3_R
I_TXN3_C

PC

IE_TXN0_C

PC

IE_TXP0_C

IE_TXN1_C

IE_TXN2_C

IE_TXN3_C

DM

I_COMP

R23
R24
P21
P20
T21
T20
T24
T25
T19
T18

U23

U24
V21
V20
V24
V23

K21
K22

M18
M19

K24
K25
L23
L24
L22

M21

P17

P18
N25
N24

H24

W23
W24

J23
J24

J22

DM

I0RXN

DM

I0RXP

DM

I0TXN
I0TXP

DM

I1RXN

DM
DM

I1RXP

DM

I1TXN

DM

I1TXP
I2RXN

DM

I2RXP

DM
DM

I2TXN

DM

I2TXP

DM

I3RXN
I3RXP

DM

I3TXN

DM
DM

I3TXP

ERN1

P
PER

P1

PET

N1

PET

P1

ERN2

P
PERP2
PET

N2

PET

P2

P

ERN3

P3

PER
PET

N3

PET

P3

P

ERN4

PER

P4
PETN4
PET

P4

DM

I_ZCOMP

DM

I_IRCOMP
I_CLKN

DM

I_CLKP

DM

Tiger Point

Tiger Point

TG

H7

U

SBP0N

H6

U

SBP0P

H3

U

SBP1N

H2

SBP1P

U

J2

SBP2N

U

J3

U

DM

DM
I

I

B

B
US

US

PCI-E

PCI-E

SBP2P

U

SBP3N

U

SBP3P

SBP4N

U

SBP4P

U
U

SBP5N

U

SBP5P

U

SBP6N

SBP6P

U

SBP7N

U
U

SBP7P

OC
OC
OC
OC
OC

5#/GPIO29

OC
OC6#/GPIO30
OC

7#/GPIO31

U

SBRBIAS

U

SBRBIAS#

CL

K48

2

2

K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

BOC#R_1

US

D4

0#

BOC#R_1

US

C5

1#

U

SBOC#

D3

2#

U

SBOC#L_1

D2

3#

U

SBOC#

E5

4#

SBOC#

U

E6

SBOC#

U

C2

U

SBOC#

C3

G2

U

SBRBIAS

G3

C

LKUSB_48

F4

U

SBP0- [21]
SBP0+ [21]

U

SBP1- [21]

U
U

SBP1+ [21]

U

SBP2- [18]

U

SBP2+ [18]
SBP3- [21]

U
USBP3+ [21]
U

SBP4- [25]

U

SBP4+ [25]

U

SBP5- [25]
SBP5+ [25]

U
U

SBP6- [19]

U

SBP6+ [19]

U

SBP7- [25]
SBP7+ [25]

U

435 *0/short_4

435 *0/short_4

R

R

R427 *0/short_4R427 *0/short_4

<Layout note>
Close to pin within 200mil ; keep away from CLK/High speed signals

438 22.6/F_4

438 22.6/F_4

R

R

EM

6

6

R6

R6
*10/F_4

*10/F_4

1

1

C8

C8
*10P/50V_4

*10P/50V_4

SYSTEM

(Right Down)
SYSTEM (Right Up)
CCD
SYSTEM (Left/ USB Charger)
SIM
3G
BT
WLAN

U

SBOC#R [21,27]

U

SBOC#L [21,27]

LKUSB_48 [2]

C

US
U
U

CRB ties unused OC pins together with 1k ohm

I

BOC#R_1
SBOC#L_1
SBOC#

433 8.2K/J_4

433 8.2K/J_4

R

R
R

R

429 8.2K/J_4

429 8.2K/J_4

R

R

432 1K/F_4

432 1K/F_4

+

3V_S5

10

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

S

ize Document Number Rev

ize Document Number Rev

ize Document Number Rev

S

S

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

Wednesday, August 31, 2011

Date: Sheet

1

Wednesday, August 31, 2011

PROJECT :

Tiger Point DMI/PCIE/USB

Tiger Point DMI/PCIE/USB

Tiger Point DMI/PCIE/USB

ZE7

ZE7

ZE7

C

C

C

C3

C3

C3

of

4210

of

4210

of

4210

5

4

3

2

1

Tiger Point (CLG)

NOTE

D D

AE20
AD17
AC15
AD18

AA10
AA12

AD15

C C

B B

PCH_GPIO36

AE21
AE18
AD19

AC17
AB13
AC13
AB15

AB16
AE24
AE23

AA14

AD16
AB11
AB10
AD23

烉

1. CPUSLP# is supported only on nettop platforms.

TG

TG

P

P

SATA

SATA

HOST

HOST

SAT

A0RXN
A0RXP

SAT

A0TXN

SAT

A0TXP

SAT

SAT

A1RXN

SAT

A1RXP

A1TXN

SAT

A1TXP

SAT

A_CLKN

SAT

A_CLKP

SAT

SAT

ARBIAS#

SAT

ARBIAS

ALED#

SAT

20GATE

A

A2

CP

USLP#

GNNE#

I

NIT3_3V#

I

F

RCI

SER

ST

PCLK#

HERMTRIP#

T

3

3

0M#

IT#

IN

IN

ERR#

NM

IRQ

SM

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

AD4
AC4

AD11
AC11
AD25

R102

R102

20

GA

U16

20M#

H_A

Y20

CP

USLP#_R

Y21

H_I

GNNE#

Y18
AD21

_INIT#

H

AC25

H_I

NTR

AB24

TR

N#

H_F

ERR#

Y22

H_NMI

T17

I

KBR

ST#

AC21

IRQ

SER

AA16

H_S

MI#

AA21

I#

H

_STPCLK#

V18

M_THRMTRIP#

P

AA20

SAT
SAT

ARBIAS#
ALED#

LK_PCIE_SATA# [2]

C

LK_PCIE_SATA [2]

C

10K/J_4

10K/J_4

R12

Y12

Y10

W10

V12

U12

Y14

V14

U22C

U22C

R

SVD03
SVD04

R

SVD05

R

SVD06

R
R

SVD07

R

SVD08
SVD09

R

SVD10

R

SVD11

R
R

SVD12

R

SVD13
SVD14

R

SVD15

R

SVD16

R
R

SVD17

R

SVD18
SVD19

R

SVD20

R
R

SVD21

R

SVD22
SVD23

R

SVD24

R
R

SVD25

R

SVD26

SVD27

R
R

SVD28

SVD29

R
R

SVD30

R

SVD31

IO36

GP

T

T

iger Point

iger Point

SAT

A_RXN0 [24]
A_RXP0 [24]

SAT

A_TXN0 [24]

SAT

A_TXP0 [24]

SAT

SAT

+3V

A20 [27]

G

20M# [6]

H_A

_INIT# [6]

H
H_I

NTR [6]

H_NMI

ST# [27]

KBR

IRQ [27]

SER

H_S

MI# [6]

_STPCLK# [6]

H

SA

TA HDD

<Layout note>
Close to pin within 500mil

R466

R466

ALED# [24]

R533

R533

0/J_4

0/J_4

60.4/F_4

R110

R110

[6]

60.4/F_4

24.9/F_4

24.9/F_4

+

1.05V

<Layout note>
Close to pin

+

1.05V

R104

R104

<Layout note>

60.4/F

60.4/F

_4

_4

Close to pin within 1"

M_THRMTRIP# [6]

P

<

20100811_Jerry> Please follow CRB schematic (8. 2K)

20100811_Jerry>CDV doesn't support A20M,

<
pl

ease follow CRB t o have a 1K pull up at the moment.

<

20110516>Reserve 1K PU to +1. 05V for C6-state

<

20100813_Jerry> Update for the IGNNE#, please no

stuff the resister and follow
<

20110607_C-stage> Stuff 1K to follow CRB V1.5

USLP# [6]

CP

H_F

ERR# [6]

CRB's circuit first.

<

20100811_Jerry>you can follow PDG for the pull up

esistor value and tolerance r equirement. CRB is m ore

r
strictly

.

<20100811_Jerry>for Thermtrip#, please use 60 ohms+/-5% pull up.

<Layout note>
Close to pin within 200mil

F

ollow CRB

SER
KBR

GA
P

CH_GPIO36

H_A
CP

H_I

IRQ
ST#

20

20M#

USLP#_R

GNNE#

R96

R96
R117

R117

R95

R95
R103

R103

CC3_VCC3[12,13,14]

V

R109

R109
R532

R532

R105

R105

4.7K/J_4

4.7K/J_4
10K/J_4

10K/J_4

8.2K/J_4

8.2K/J_4
*10K/J_4

*10K/J_4

1K/J_4

1K/J_4
*1K/J_4

*1K/J_4

1K/J_4

1K/J_4

11

V

+3

.05V

+1

A A

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

S

S

Size Document Number Rev

ize Document Number Rev

ize Document Number Rev

ednesday, August 31, 2011

ednesday, August 31, 2011

ednesday, August 31, 2011

W

W

W

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

PROJECT :

Tiger Point Sata/Host

Tiger Point Sata/Host

Tiger Point Sata/Host

ZE7

ZE7

ZE7

1

C3C

C3C

C3C

of

4211

of

4211

of

4211

5

4

3

2

1

ger Point (CLG)

Ti

TGP

2A

2A

U2

U2

PCI CLK 33M-Hz

K_ICH[2]

D D

PCL

EMI

R73

R73

3/J_4

3/J_4

*3

*3

C99

C99

10P/50V_4

10P/50V_4

*

*

C C

SCI#[27]

EC_

ollow CRB

F

4

T34T3

0 10K/J_4

0 10K/J_4

R7

_VCC3[11,13,14]

VCC3

B B

+3

R7
R43

R43

V

_DEVSEL#

PCI

T32T3

CI_IRDY#

P

_SERR#

PCI

_STOP#

PCI

_LOCK#

PCI

TRDY#

PCI_

_PERR#

PCI

_FRAME#

PCI

T13T1
T4T4

_REQ1#

PCI

_REQ2#

PCI

PCH_GPIO48
PCH_GPIO17
PCH_GPIO22

SCI#

EC_

CI_INTA#

P

CI_INTB#

P

CI_INTC#

P

CI_INTD#

P

CI_INTE#

P

CI_INTF#

P

CI_INTG#

P

CI_INTH#

P

A16WP

PCH_

8.2K/J_4

8.2K/J_4

A5

PAR

B15

DEVSEL#

J12

CLK

A23

C22

B11
F14

A10

D1

A16

A18
E16

G16

A20

G14
C15

H10

D1
M1

B7

A8

0

A2
C9

B2
D7
B3

E8
D6
H8
F8

1

K9

3

PCI

RST#

PCI

RDY#

I
PM

E#
SERR#
STOP#
PLOCK#
TRDY

#

PERR#

E#

FRAM

GNT1

#

GNT2

#
#

REQ1

#

REQ2

O48/ STRAP1#

GPI
GPI

O17/ STRAP2#

GPI

O22
O1

GPI

RQA#

PI
PI

RQB#

PI

RQC#

PI

RQD#

PI

RQE#/GPIO2

PI

RQF#/GPIO3
RQG#/GPIO4

PI

RQH#/GPIO5

PI
STRAP0#

RSVD01
RSVD02

Tiger Point

Tiger Point

2

3

<20090601(A1A)_Checklist Rev0.7>
Strap1#/strap2#: signals have weak
internal pull-ups

CH Boot BIOS select

I

PCH_GPIO17
(INT PU)

0
10

11

PCH_GPIO48
(INT PU)

1 SPI

Boot BIOS Locati on

PCI

LPC

CURRENTLY USE)

(

TGP

CI_INTB#

B22

AD0

8

D1

AD1

7

C1

AD2

8

C1

AD3

B17

AD4

C1

9

AD5

B18

AD6

B19

AD7

6

D1

C/
C/
C/
C/

AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

BE0#
BE1#
BE2#
BE3#

1

1

D1
A13
E14
H1
L14
J1
E10
C1
E12
B9
B13
L12
B8
A3
B5
A6
G1
H1
C8
D9
C7
C1
B1

H16
M15
C13
L16

5

4

4

1

2

2

R30

R30

4 *1K/J_4

4 *1K/J_4

R42

R42

89 *8.2K/J_4

89 *8.2K/J_4

R3

R3

20101104> Reserve R389(PCH_GPIO22 PD) for 27M Hz or 96MHz choosing, need vBI O S support

<
Pul

l up --> for 27MHz

Pull down --> for 96MHz

I

I

PC

PC

P

CI_IRDY#

P

CI_INTG#

P

CI_INTE#

P

CI_LOCK#

P

CI_INTD#

P
PCI_
PCI

PCI
PCI
PCI
PCI

CI_INTA#

P

CI_INTC#

P

CI_INTF#

P

CI_INTH#

P

PCI
PCI
EC_

*1K/J_4

*1K/J_4

TRDY#

_PERR#
_DEVSEL#

_FRAME#
_REQ1#
_REQ2#

_STOP#
_SERR#

SCI#

Q

IR

PIR
PI

RQB
PIR
PI

RQD
PIRQ
PI

RQF
PIRQG
PIRQH

3 8.2K_8P4R

3 8.2K_8P4R

RP

RP

1

2

3

4

5

6

7

8

P2 8.2K_8P4R

P2 8.2K_8P4R

R

R

1

2

3

4

5

6

7

8

1 8.2K_8P4R

1 8.2K_8P4R

RP

RP

1

2

3

4

5

6

7

8

4 8.2K_8P4R

4 8.2K_8P4R

RP

RP

1

2

3

4

5

6

7

8

8.2K/J_4

R392

R392
R391

R391
R41

R41

PCH_GPIO48
PCH_GPIO17

PCH_GPIO22

QA

QC

E

R35

R35
R421

R421
R388

R388

USB UHCI Co

C'97 Codec; option for SMBUS

A
USB UH Controller #3; SATA/IDE Native Mode
USB UHCI Controller #2
Internal LAN; Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2

8.2K/J_4

8.2K/J_4

8.2K/J_4
10K/J_4

10K/J_4

*1K/J_4

*1K/J_4
*1K/J_4

*1K/J_4

scription

De

ntroller #1, #4

8.2K/J_4

8.2K/J_4

V

+3

V

+3

V

+3

V

+3

V

+3

V

+3

V

+3

12

A16 SWAP Override strap

CH_A16WP

P

NT PU)

A A

(I

PCI_

GNT#2

Low = A16 swap override enabled
High = Default

nal PU

Inter
S

hould not be PD

5

Quanta Com

Quanta Com

Quanta Com

PROJECT :

PROJECT :

ze Document Number Rev

ze Document Number Rev

ze Document Number Rev

Si

Si

Si

Date: Sheet

Date: Sheet

4

3

Date: Sheet

2

ednesday, August 31, 2011

ednesday, August 31, 2011

ednesday, August 31, 2011

W

W

W

PROJECT :

Tige

Tige

Tige

rPoint PCI

rPoint PCI

rPoint PCI

puter Inc.

puter Inc.

puter Inc.

ZE7

ZE7

ZE7

of

of

of

1

C3C

C3C

C3C

4212

4212

4212

5

iger Point (CLG)

T

Z_BITCLK_AUDIO_R

Z_BITCLK_AUDIO_R

AC

AC

33/J_4

33/J_4

R90

AC

Z_BITCLK_CODEC[20]

AC

Z_BITCLK_CPU[5]

D D

AC

Z_RST#_CODEC[20]

AC

Z_RST#_CPU[5]

AC

Z_SDOUT_CODEC[20]
Z_SDOUT_CPU[5]

AC

CZ_SYNC_CODEC[20]

A

CZ_SYNC_CPU[5]

A

<20110516_DGv
C

C C

1.5>

hange ACZ BITCLK/RST/SDOUT/SYNC to CPU RES from 33ohm to 90.9ohm

R90
R

R

93 90.9/F_4

93 90.9/F_4

4/28 For EMI Sam requestion

2011/

R452

R452
R454

R454

R461

R461
R472

R472

R451

R451
R468

R468

33/J_4

33/J_4

90.9/F_4

90.9/F_4

33/J_4

33/J_4

90.9/F_4

90.9/F_4

33/J_4

33/J_4

90.9/F_4

90.9/F_4

C136

C136
*

*

A

A

CZ_RST#_AUDIO_R

CZ_RST#_AUDIO_R

Z_SDOUT_AUDIO_R

Z_SDOUT_AUDIO_R

AC

AC

A

A

CZ_SYNC_AUDIO_R

CZ_SYNC_AUDIO_R

30P/50V_4

30P/50V_4

<20090529(A1A)_Checklist Rev0.7>
If integrated LAN is not used
LAN_RST# tie it to GND.

3

3

2.768KHz,+-20PPM

2.768KHz,+-20PPM

C348

C348

C349

C349

AC
AC

4

3

2

1

13

+

CLK_SMB

Follow C

P

AT_SMB

PD

_BATLOW#

PM

NBSWON#

D

_SMI#

EC
SYS_

BALERT#

SM

MB_LINK_ALERT#

S
PC

IE_WAKE#

SM

LINK1

SM

LINK0

I

CH_RI#

P

CH_GPIO14

P

CH_GPIO15
CH_GPIO9

P

CH_GPIO8

P

CH_GPIO12

P

CH_GPIO13

P

RB

M

CH_SYNC#
CLK
BM

_BUSY#

T

HERM_ALERT#

MI_AC_ENABLE

D

T_PWROK

TP

_RSMRST#

EC

TGP

U22D

U22D

AA5

8

D0[25,27]

LA
LA

D1[25,27]

LA

D2[25,27]

LA

D3[25,27]

LF

RAME#[25,27]

Z_SDINO[5]
Z_SDIN1[20]

14M

_ICH[2]

6P/50V_4

6P/50V_4

Y4

Y4

1 4

2 3

6P/50V_4

6P/50V_4

T18T1

T21T2

AC

Z_BITCLK_AUDIO_R

A

CZ_RST#_AUDIO_R

Z_SDOUT_AUDIO_R

AC

CZ_SYNC_AUDIO_R

A

_ICH

14M

R434

R434
10M

10M

/J_4

/J_4

RT

CRST#

SM

BALERT#

P

CLK_SMB

PD

AT_SMB

S

MB_LINK_ALERT#

SM

LINK0

SM

LINK1

T36T3
T37T3
T14T1
T17T1
T16T1

1

RT
RT

6
7
4
7
6

C_X1
C_X2

1#/GPIO23

LDRQ

V6

D0/FWH0

LA

AA6

D1/FWH1

LA

Y5

D2/FWH2

LA

W8

D3/FWH3

LA

Y8

0#

LDRQ

Y4

RAME#

LF

P6

_BIT_CLK

HDA

U2

_RST#

HDA

W2

_SDI0

HDA

V2

_SDIN1

HDA

P8

_SDIN2

HDA

AA1

_SDOUT

HDA

Y1

_SYNC

HDA

AA3

14

CLK

U3

CS

EE_

AE2

DIN

EE_

T6

E_DOUT

E

V3

SHCLK

EE_

T4

N_CLK

LA

P7

NR_STSYNC

LA

B23

N_RST#

LA

AA2

N_RXD0

LA

AD1

N_RXD1

LA

AC2

N_RXD2

LA

W3

N_TXD0

LA

T7

N_TXD1

LA

U4

N_TXD2

LA

W4

CX1

RT

V5

CX2

RT

T5

CRST#

RT

E20

LERT#/GPIO11

SMBA

H18

LK

SMBC

E23

ATA

SMBD

H21

MLALERT#

S

F25

INK0

SML

F24

INK1

SML

R2

_MISO

SPI

T1

_MOSI

SPI

M8

_CS#

SPI

P9

PI_CLK

S

R4

_ARB

SPI

ger Point

ger Point

Ti

Ti

TGP

BUSY#/GPIO0

SC

SC
MI

MI

BM_

DP

ST

UPWRGD/GPIO49

CP

VR

CH_SYNC#

M

PW

S_STAT#/LPCPD#

SU

S_RESET#

SY

NTRUDER#

I

IN

GP
GP
GP

GP
GP
GP
GP
GP
GP

RSLPVR

P_PCI#

ST

P_CPU#

GP
GP
GP
GP
GP

CLK

GP
GP
GP
GP

HRM#

T

MPWR GD

RBTN#

SU

TRSTB

PL

W

PW

MRST#

RS

TVRM EN

P_S3#

SL

P_S4#

SL

P_S5#

SL

TLOW#

BA

RSTP#

DP

PSLP#

D
RS

LPC AUDIO LAN

LPC AUDIO LAN

EPR

EPR
OM

OM

R

R
TC SMB SPI

TC SMB SPI

IO10
IO12
IO13
IO14
IO15

IO24
IO25
IO26
IO27
IO28

RUN#

IO33
IO34
IO38
IO39

SCLK

AKE#

ROK

SPKR

VD31

_BUSY#

BM

T15

CH_GPIO6

P

W16

IO6

CH_GPIO7

P

W14

IO7

CH_GPIO8

P

K18

IO8

CH_GPIO9

P

H19

IO9

EC

_SMI#

M17

P

CH_GPIO12

A24

P

CH_GPIO13

C23

P

CH_GPIO14

P5

P

CH_GPIO15

E24

PM

_DPRSLPVR

AB20
Y16
AB19

CH_GPIO24

P

R3

MI_AC_ENABLE

D

C24

CH_GPIO26

P

D19

CH_GPIO27

P

D20

CH_GPIO28

P

F22

CLK

RUN#

AC19

P

CH_GPIO33

U14

OARDID0

B

AC1

B

OARDID1

AC23

B

OARDID2

AC24

H_P

WRGD

AB22

T

HERM_ALERT#

AB17

PG

HW

V16

CH_SYNC#

M

AC18

NBSWON#

D

E21

CH_RI#

I

H23

#

RI

G22

SCLK

SU

D22

RST#

SYS_

G18

P

LT_RST#

G23

PC

IE_WAKE#

C25

S

M_INTRUDER#

T8

TP

T_PWROK

U10

EC

_RSMRST#

AC3

I

CH_INTVRMEN

AD3

6

J1

SB#

SU

H20

SC#

SU

E25
F21

_BATLOW#

PM

B25

CH_DPRSTP_R#

I

AB23

H

_DPSLP#

AA18
F20

T20T2

0
9

T19T1

EC

_SMI# [27]

8

T38T3

_STPPCI# [2]

PM

M_STPCPU# [2]

P

5

T35T3
T8T8

T10T1

0

T6T6

CLK

RUN# [27]

T15T1

5

WRGD [6,16]

H_P

HERM_ALERT# [5,6,27]

T

PG [2,16,27]

HW

SWON# [16,27]

DNB

T5T5

S

USCLK [27]

PC

IE_WAKE# [22,25]
T_PWROK [16]

TP

_RSMRST# [16,27]

EC

SPKR

SB# [16,27]

SU

SC# [16,27]

SU

T12T1

2

R108

R108

H

_DPSLP# [6]

<20101105> GPI
GP
Pu
Pull-low: 0x00 -> SRC1/3/5

<20101108> GPIO13 for A3-test LAN chip selection
Pull-high -> for Atheros LAN AR8158
Pull-down -> for Realtek LAN RTL8105TA-VC-CG

<20110607> P
fol

[20]

*0/short_4

*0/short_4

O12 for A3-test CLKREQ setting
IO12 Command: For CLK Gen Byte5 CLKREQ# strap
ll-high: 0x58 -> SRC2/4/6

U to +3V_S5 for GPIO12/13 no use to

low checklist v1.0

<20110308> Un
thermal sensor
Stuff -> Unuse thermal sensor
Unstuff -> Use thermal sensor

R107

R107

stuff R465 for adding

*56/F_4

*56/F_4

+

1.05V
I

CH_DPRSTP# [6]

RST#

RUN#

S

M_INTRUDER#

I

CH_INTVRMEN

R378

R378
R383

R383
R402

R402
R431

R431
R49

R49
R375

R375
R379

R379
R394

R394
R404

R404
R418

R418
R420

R420
R422

R422
R28

R28
R403

R403
R380 10K/J_4R380 10K/J_4
R393

R393
R407

R407
R382

R382

V

CC3_VCC3[11,12,14]

R471

R471
R464

R464
R467

R467
R465

R465

R401

R401
R495

R495
R460

R460

R473

R473
R458

R458

2.2K/J_4

2.2K/J_4

2.2K/J_4

2.2K/J_4

8.2K/J_4

8.2K/J_4
*10K/J_4

*10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4

1K/F_4

1K/F_4

8.2K/J_4

8.2K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4

1K/J_4

1K/J_4
10K/J_4

10K/J_4
10K/J_4

10K/J_4

1M/F_6

1M/F_6
332K/F_4

332K/F_4

3V_S5

CRTC

VC

TPT Pow

B B

RTC (RTC)

A A

er OK (CLG)

+3

V

C144

C144

U4

U4

PG

HW

2

PWROK[5,8,16,27]

EC

3VPCU

+

D16

D16

CH500H-

CH500H-

40

40

D15

D15

CCRTC_3

V

CH500H-

CH500H-

40

40

R254

R254
1K/J_4

1K/J_4

IL 20MIL

20M

V

CCRTC_4

1 3

Q27

Q27

METR3904-G

METR3904-G

12

CN5

CN5

C SOCKET

C SOCKET

RT

RT

1

3 5

R101

R101

CCRTC

V

C222

C222

1U/

1U/

10V_6

10V_6

R211

R211

20K

20K

2

ML1220 Coin type
AHL03001406 Maxell (HML) 18mAH
AHL03001424 FDK (SAY) 15mAH

HL03017100 Panasonic (MAT) 17mAH

A

5

/F_6

/F_6

V

CCRTC_1

RT

C223

C223

1U/

1U/

10V_6

10V_6

R218

R218

*0/J_4

*0/J_4

CRST#

0.1U/10V_4

0.1U/10V_4

C7SH08FU

C7SH08FU

T

T

4

12

2K/F_4

2K/F_4

TPT_PWROK

R513

R513
G1

G1

SHORT_PAD

SHORT_PAD

*

*

V

CCRTC_2

<20110426 (G1A
Add 0.1uF CAP to prevent PWROK glitch issue

C143

C143

0.

0.

1U/10V_4

1U/10V_4

0/J_4

0/J_4

R217

R217

RT

2K/F_4

2K/F_4

68.1K/F_4

68.1K/F_4

150K

150K

R216

R216

R215

R215

)>

CRST#_EC [27]

+5V_S5

/F_4

/F_4

Clock GEN I2C Lev

PCH: +

3V_S5

P

CLK_SMB[25]

PCH: +

3V_S5

AT_SMB[25]

PD

4

3

3

2N7002K

2N7002K

Q3

Q3

2N7002K

2N7002K

Q37

Q37

el Shift

+3V

R374

R374

2.

2.

2K/J_4

2K/J_4

2

1

8

8

V

+3

2

1

R376

R376

2.2K/J_4

2.2K/J_4

CLK GEN:

BCK1 [2,4,25]

SM

CLK GEN:

S

MBDT1 [2,4,25]

3

+3V

+3V

Platform Reset (CLG

PL

T_RST#

R417

R417

)

Mother Board ID (CLG)

R92

R92

R462

R462

*10K

*10K

*10K

*10K

/J_4

/J_4

/J_4

/J_4

B

OARDID0
OARDID1

B
BOARDID2

R87

R87

R463

R463

10K

10K

10K

10K

/J_4

/J_4

/J_4

/J_4

<20110428 (G1A)>
Stuff 10K PD resistors for ZE7 A2-stage

2

V

+3

C338

C338

*0.1U/10V_4

R457

R457
*10K

*10K

R469

R469
10K

10K

*0.1U/10V_4

*T

*T

C7SH08FU

C7SH08FU

4

3 5

0/J_4

0/J_4

/J_4

/J_4

/J_4

/J_4

LTRST# [6,16,22,25,26,27]

P

R395

R395

_4

_4

100K

100K

ACZ
(INT PD)

INTVRMEN

ize Document Number Rev

ize Document Number Rev

S

S

S

ize Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ACZ

_SDOUT

_SYNC

escription

(INT PD)

0

0

1

Enable internal VccSus1_5 VRM

1

(default)

Disable

0

ednesday, August 31, 2011

ednesday, August 31, 2011

ednesday, August 31, 2011

W

W

W

D

0

4 x 1s

*

0

Reserved1

1

Reserved

1 x 4s(1 port/4 lanes)

1

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

TP

TP

TP

T ACZ/GPIO/RTC

T ACZ/GPIO/RTC

T ACZ/GPIO/RTC

ZE7

ZE7

ZE7

of

of

1

of

C3C

C3C

C3C

4213

4213

4213

U21

U21

2
1

V

+3