Acer Aspire One D250 Schematics

A

[e-mail]

1 1

B

C

D

E

Compal Confidential

2 2

KAV60 Schematics Document

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

3 3

2009-02-22

REV: 1.0

4 4

Security Classification

Security Classification

A

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

1 40Sunday, February 22, 2009

1 40Sunday, February 22, 2009

1 40Sunday, February 22, 2009

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Compal Confidential

Diamondville SC

FCBGA8

Model Name : KAV60
File Name : LA-5141P

1 1

P/N : DA60000BO00

CRT Conn

page 14

RGB

Thermal Sensor

EMC1402

2 2

page 4

LCD Conn.

page 13

SDIO CONN MINI Card x2

page 27

page 19

LVDS

PCI-Express

10/100 Ethernet

AR8114A

Transfermer

3 3

H_A#(3..31) H_D#(0..63)

DMI
X2 mode

page 24

page 24

437Pins

22x22mm

FSB

400/533MHz

Calistoga GSE
FCBGA998

27x27mm

page 6,7,8,9,10

ICH7M
BGA652

31x31mm

page 15,16,17,18

LPC BUS

page 4,5

Memory BUS(DDRII)

1.8V DDRII 400/533

to I/OBoard CONN

JP7

Clock Generator
CK505

DDRII-SO-DIMM

USB

HDA

SATA

page 22

page 12

Aralia Codec

ALC272

page 20

page 11

USB Port X1

page 28

I/O Board X2

page 22

to I/O board
CONN
RTS5159E

page 22

BlueToothX1

page19

CMOS CAM

page13

WLANX1

page19

WWANX1

page19

Power ON/OFF
& LED CONN

DC IN

page 26

page 31

DC/DC Interface

3VALW/5VALW

page 29

page 33

1.5VS/0.9VS/

BATT IN

CHARGER

4 4

page 32

page 34

2.5VS

1.8V/VCCP

CPU_CORE

A

page 36

page 35

page 37

B

RJ45

page 24

AMP & INT
Speaker

ENE KBC
KB926

Int.KBD

page 27

Touch Pad

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 25

page 27

C

SPI

SPI ROM

page 25

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

page 21

I/O board

D

MIC Jack

page 21 page 13

SATA CONN

USB Port X2

USB Card Reader
x1 RTS5159E

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

INT DMIC CONNHeadPhone &

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

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2 40Thursday, January 22, 2009

2 40Thursday, January 22, 2009

A

[e-mail]

1 1

B

C

D

E

Voltage Rails

S5

Description Power Plane

VIN

B+

+CPU_CORE

+VCCP

+1.5VS

+1.8V

+2.5VS

+3VALW

+3VS

+5VALW

2 2

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means th at this power plane is ON o nly with AC power availab le, otherwise it is OFF.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Adapter power supply ( 19V)

AC or battery power rail for powe r circuit.

Core voltage for CPU

0.9V switc hed power rail f or DDR termina tor+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

SIGNAL

SLP_S3#

SLP_S4#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOW LOW

SLP_S5#

HIGH HIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

S3 S1

N/A N/A N/ A

ON

ON OFF

ON

ON

ON

ON

ON

N/A N/AN/A

OFF ON

OFF

OFF ON

OFF

OFF OFFON

OFF OFFON

ON

OFF

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFF ON

ONON

+V +VS Clock

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

ON ON

LOW

OFF

OFF

OFF

External PCI Devices

'(9,&( 5(4*17

,'6(/

No PCI Device

EC SM Bus1 address

Device

Smart Battery

EEPROM(24C16/02)

Address

1010 000X b

EC SM Bus2 address

Device

EMC1402

3,54

Address

1001 100X b0001 011X b

3 3

BOARD ID Table(Page 25)

ID

0

1

2

3

4 4

BRD ID

R01 (EVT)

R02 (DVT)

R03 (PVT)

R10A (MP)

A

Ra

NC
100K
100K
100K

Rb Vab

0

8.2K
18K
NC

0V

0.25V

0.50V

3.3V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH7M SM Bus address

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

C

Address

1101 001Xb

1010 000Xb

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

3 40Thursday, January 22, 2009

3 40Thursday, January 22, 2009

3 40Thursday, January 22, 2009

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H_A#[3..16](6)

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13

D D

H_ADSTB#0(6)
H_REQ#[0..4](6)

H_A#[17..31](6)

H_ADSTB#1(6)

C C

B B

A A

H_A20M#(16)

H_FERR#(16)

H_IGNNE#(16)

H_STPCLK#(16)

H_INTR(16)

H_NMI(16)

H_SMI#(16)

+VCCP

+VCCP

+VCCP

H_A#14
H_A#15
H_A#16

H_ADSTB#0

H_AP0

T5T5

H_REQ#0

PADPAD

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1

T7 PAD T7 PAD

H_A20M#
H_FERR#
H_IGNNE# CLK_CPU_BCLK#
H_STPCLK#
H_INTR
H_NMI
H_SMI#

R34 1K_0402_5%R34 1K_0402_5%

1

R30 1K_0402_5%R30 1K_0402_5%

1

R31 1K_0402_5%R31 1K_0402_5%

1

R29 1K_0402_5%R29 1K_0402_5%

1

@

@

R28 1K_0402_5%

R28 1K_0402_5%

1 2

R32 1K_0402_5%

R32 1K_0402_5%

1 2

@

@

change BOM structure 11/14

This shall place near CPU

R200 56_0402_5%R200 56_0402_5%

1

R198 56_0402_5%R198 56_0402_5%

1

R206 56_0402_5% @R206 56_0402_5% @

1 2

R199 56_0402_5%R199 56_0402_5%

1

R205 68_0402_5%R205 68_0402_5%

1

Modify schematic by 10/21

R213 56_0402_5%R213 56_0402_5%

1

R218 56_0402_5%R218 56_0402_5%

1

U5A

U5A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14

A[22]#

C18

A[23]#

C20

A[24]#

E20

A[25]#

D20

A[26]#

B18

A[27]#

C15

A[28]#

B16

A[29]#

B17

A[30]#

C16

A[31]#

A17

A[32]#

B14

A[33]#

B15

A[34]#

A14

A[35]#

B19

ADSTB[1]#

M18

AP1

U18

A20M#

T16

FERR#

J4

IGNNE#

R16

STPCLK#

T15

LINT0

R15

LINT1

U17

SMI#

D6

NC1

G6

NC2

H6

NC3

K4

NC4

K5

NC5

M15

NC6

L16

NC7

AU80586GE025512_FCBGA437

AU80586GE025512_FCBGA437

2
2
2
2

2
2

2
2

2
2

N270@

N270@

0

0

ADDR GROUP 1

ADDR GROUP 1

NC

NC

H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#
H_IGNNE#

ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
H_PROCHOT#

ITP_TCK
ITP_TRST#

ADS#
BNR#
BPRI#

ADDR

GROUP

ADDR

GROUP

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

BR1#

PROCHOT#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THRMDA

THRMDC

THERM

THERM

THERMTRIP#

BCLK[0]
BCLK[1]

H CLK

H CLK

RSVD3
RSVD2
RSVD1

V19
Y19
U21

T21
T19
Y18

T20

F16
V16

W20

D15
W18
Y17
U20
W19

AA17
V20

K17
J18
H15
J15
K18
J16
M17
N16

TDI

M16
L17
K16
V15

G17
E4
E5

H17

V11
V12

C21
C1
A3

.

.

4

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#

H_IERR#
H_INIT#_R

H_LOCK#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

H_PROCHOT#_R
H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1

R202 22_0402_5%R202 22_0402_5%

+CPU_GTLREF

C62C62

Close to CPU pin
within 500mils.
Zo=55ohm

H_ADS# (6)

H_BNR# (6)

H_BPRI# (6)

H_DEFER# (6)

H_DRDY# (6)

H_DBSY# (6)

H_BR0# (6)

R33 1K_0402_5%R33 1K_0402_5%

1

H_LOCK# (6)

H_RESET# (6)

H_TRDY# (6)

H_HIT# (6)

H_HITM# (6)

2

+VCCP +VCCP

2

Close to CPU

Close to CPU

H_THERMTRIP# (6,16)

CLK_CPU_BCLK (12)
CLK_CPU_BCLK# (12)

+VCCP

12

R47

R47
1K_0402_1%

1K_0402_1%

12

1

R48

R48
2K_0402_1%

2K_0402_1%

2

12

R201

R201
56_0402_5%

56_0402_5%

H_RS#[0..2] (6)

U5

U5

CPU

CPU

N280@

N280@

H_PROCHOT# (37)

+CPU_EXTBGREF

C342

C342

1U_0402_6.3V4Z

1U_0402_6.3V4Z

12

R27

R27
330_0402_5%

330_0402_5%

+VCCP

1

2

Close to CPU pin
within 500mils.
Zo=55ohm

H_INIT# (16)

12

R234

R234
1K_0402_1%

1K_0402_1%

12

R238

R238
2K_0402_1%

2K_0402_1%

3

+CPU_GTLREF

+CPU_EXTBGREF

H_D#[0..15](6)

H_DSTBN#0(6)
H_DSTBP#0(6)

H_DINV#0(6)

H_D#[16..31](6)

H_DSTBN#1(6)
H_DSTBP#1(6)

H_DINV#1(6)

R240 1K_0402_5% @R240 1K_0402_5% @

1 2

R239 1K_0402_5% @R239 1K_0402_5% @

1 2

CPU_BSEL0(12)
CPU_BSEL1(12)
CPU_BSEL2(12)

+VCCP

12

R51

+CPU_CMREF

0.1U_0402_16V4Z 0.1U_0402_16V4Z

R51
1K_0402_1%

1K_0402_1%

12

1

R49

R49

C65C65

2K_0402_1%

2K_0402_1%

2

Close to CPU pin
within 500mils.
Zo=55ohm

2

U5B

Y11

W10

Y12
AA14
AA11

W12

AA16

Y10

Y9

Y13

W15

AA13

Y16

W13

AA9

W9
Y14
Y15

W16

V9

AA5

Y8

W3

U1
W7
W6

Y7

AA6

Y3
W2

V3

U2

T3

AA8

V2
W4

Y4

Y5

Y6

R4

A7

U5

V5

T17

R6
M6

N15

N6

P17

T6

J6

H5
G5

+3VS

1

C352

C352

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_THERMDA

H_THERMDC

2

2200P_0402_50V7K

2200P_0402_50V7K

U5B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1

GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]

AU80586GE025512_FCBGA437

AU80586GE025512_FCBGA437

N270@

N270@

D[32]#
D[33]#
D[34]#

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GRP 2

DATA GRP 2

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

DP#2

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

DATA GRP 3

DATA GRP 3

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

DP#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

MISC

MISC

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

CORE_DET

CMREF[1]

Layout note:
COMP0,2 connect with Zo=27.4ohm +/-15%, make
trace length shorter than 0.5"
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length shorter than0.5"

CPU THERMAL SENSOR

U17

U17

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0

T10 PAD T10 PAD

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1 H_DSTBN#3
H_DSTBP#1
H_DINV#1
H_DP#1

T13 PAD T13 PAD

ACLKPH
DCLKPH

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

C351

C351

1

R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4

C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4

T1
T2
F20
F21

R18
R17
U4
V17
N18
A13
B7

SMDATA

SMCLK

ALERT#

GND

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_DP#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBP#3
H_DINV#3
H_DP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#

8

7

6

5

1

H_D#[32..47] (6)

H_DSTBN#2 (6)
H_DSTBP#2 (6)
H_DINV#2 (6)

T15 PAD T15 PAD

H_D#[48..63] (6)

H_DSTBN#3 (6)
H_DSTBP#3 (6)
H_DINV#3 (6)

T12 PAD T12 PAD
R57 27.4_0402_1%R57 27.4_0402_1%

2

1

R58 54.9_0402_1%R58 54.9_0402_1%

1

2

R208 27.4_0402_1%R208 27.4_0402_1%

2

1

R209 54.9_0402_1%R209 54.9_0402_1%

2

1

H_DPRSTP# (16,37)
H_DPSLP# (16)
H_DPWR# (6)
H_PWRGOOD (16)
H_CPUSLP# (6)

EC_SMB_CK2

EC_SMB_DA2

R304

R304

12

10K_0402_5%

10K_0402_5%

+CPU_CMREF

EC_SMB_CK2 (25)

EC_SMB_DA2 (25)

+3VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Diamondville(1/2)

Diamondville(1/2)

Diamondville(1/2)

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

4 40Sunday, February 22, 2009

4 40Sunday, February 22, 2009

4 40Sunday, February 22, 2009

1

0.2

0.2

0.2

of

of

of

5

[e-mail]

4

3

2

1

C341

C341

C322

C322

1

2

1

2

1

2

+VCCP

1

+

+

C57

C57

2

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

+1.5VS

1

C338C338

0.1U_0402_16V7K 0.1U_0402_16V7K

2

+CPU_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C323

C323

C324

C324

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z

10U_0805_10V4Z

1

C334

C328

C328

C334

2

10U_0805_10V4Z

10U_0805_10V4Z

12

R221

R221

100_0402_1%

100_0402_1%

12

R220

R220

100_0402_1%

100_0402_1%

1

C326

C326

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

VCCSENSE (37)

VSSSENSE (37)

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C327

C327

2

1

C325

C325

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm

+CPU_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C315

C315

2

1

2

2 x 330uF(9mohm/2)

1

+

+

C51

C51

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

1

+

+

C331

C331

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

@

@

U5D

U5D

A2

VSS1

A4

VSS2

A8

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

B1

VSS9

B2

VSS10

D D

C C

B B

A A

B5

VSS11

B8

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

C8

VSS16

C17

VSS17

D1

VSS18

D5

VSS19

D8

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

E3

VSS24

E6

VSS25

E7

VSS26

E8

VSS27

E15

VSS28

E16

VSS29

E19

VSS30

F4

VSS31

F5

VSS32

F6

VSS33

F7

VSS34

F17

VSS35

F18

VSS36

G1

VSS37

G4

VSS38

G7

VSS39

G9

VSS41

G13

VSS42

G21

VSS45

H3

VSS46

H4

VSS48

H7

VSS49

H9

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

J5

VSS56

J7

VSS57

J9

VSS58

J13

VSS59

J17

VSS60

K1

VSS61

K6

VSS62

K7

VSS63

K9

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

L3

VSS68

L4

VSS69

L5

VSS70

L6

VSS71

L7

VSS72

L9

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

M1

VSS78

M5

VSS79

M7

VSS80

M9

VSS81

M13

VSS82

M21

VSS83

N4

VSS84

AU80586GE025512_FCBGA437

AU80586GE025512_FCBGA437

N270@

N270@

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

VSS99
VSS98
VSS97
VSS96
VSS95

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

+CPU_CORE

+CPU_CORE

10U_0805_10V4Z

10U_0805_10V4Z

+VCCP

1

C308

C308

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C298

C298

2

U5C

U5C

V10

VCCF

A9

VCCQ1

B9

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

AU80586GE025512_FCBGA437

AU80586GE025512_FCBGA437

N270@

N270@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C309

C309

C310

C310

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z

10U_0805_10V4Z

1

C299

C300

C300

C299

2

10U_0805_10V4Z

10U_0805_10V4Z

VCCPC64
VCCPC63
VCCPC62
VCCPC61

VCCSENSE

VSSSENSE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C311

C311

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C301

C301

2

C9

VTT1

D9

VTT2

E9

VTT3

F8

VTT4

F9

VTT5

G8

VTT6

G14

VTT7

H8

VTT8

H14

VTT9

J8

VTT10

J14

VTT11

K8

VTT12

K14

VTT13

L8

VTT14

L14

VTT15

M8

VTT16

M14

VTT17

N8

VTT18

N14

VTT19

P8

VTT20

P14

VTT21

R8

VTT22

R14

VTT23

T8

VTT24

T14

VTT25

U8

VTT26

U9

VTT27

U10

VTT28

U11

VTT29

U12

VTT30

U13

VTT31

U14

VTT32

F14
F13
E14
E13

D7

VCCA

F15

VID[0]

D16

VID[1]

E18

VID[2]

G15

VID[3]

G16

VID[4]

E17

VID[5]

G18

VID[6]

C13

D13

PLACE IN CAVITY

1

C312

C312

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C302

C302

2

10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

VCCSENSE

VSSSENSE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C313

C313

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C46

C46

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C314

C314

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C304

C304

2

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C295

C295

C307

C307

2

CPU_VID0 (37)
CPU_VID1 (37)
CPU_VID2 (37)
CPU_VID3 (37)
CPU_VID4 (37)
CPU_VID5 (37)
CPU_VID6 (37)

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C320

C320

2

2

10U_0805_10V4Z

10U_0805_10V4Z

1

1

C303

C303

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C337

C337

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

PLACE IN CAVITY

130mA

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C321

C321

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z

10U_0805_10V4Z

1

C335

C335

C47

C47

2

10U_0805_10V4Z

10U_0805_10V4Z

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification

Security Classification

5

Security Classification

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Diamondville(2/2)

Diamondville(2/2)

Diamondville(2/2)

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

5 40Sunday, February 22, 2009

5 40Sunday, February 22, 2009

5 40Sunday, February 22, 2009

1

0.2

0.2

0.2

of

of

of

5

4

3

2

1

H_D#[0..63](4)

D D

C C

+VCCP

12

12

R6

R6

R175

R175

54.9_0402_1%

54.9_0402_1%

54.9_0402_1%

54.9_0402_1%

B B

12

R7

R7

R182

R182

24.9_0402_1%

24.9_0402_1%

12

24.9_0402_1%

24.9_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP

+H_SWNG0

H_YRCOMP
H_YSCOMP

+H_SWNG1

AB4
AB8

AA9
AA8
AB1
AB7
AA2
AB5

A10

C15

C4
F6
H9
H6
F7
E3
C2
C3
K9
F5

J7
K7
H8
E5
K8

J8

J2

J3
N1

M5

K5

J5
H3

J4
N3

M4
M3

N8
N6
K3
N9

M1

V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3

W2
W1

V2

W4
W7
W5

V5

W8

A6

J1
K1
H1

U1A

U1A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_VREF0

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_VREF1

HOST

HOST

H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DPWR#

H_DRDY#

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_HITM#

H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9

HCLKN
HCLKP

H_HIT#

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

F10
C12
H16
E2
B9
C7
G8
B10
E1

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#

H_A#[3..31] (4)

H_ADS# (4)
H_ADSTB#0 (4)
H_ADSTB#1 (4)

H_BNR# (4)
H_BPRI# (4)
H_BR0# (4)
H_RESET# (4)

CLK_MCH_BCLK# (12)
CLK_MCH_BCLK (12)
H_DBSY# (4)
H_DEFER# (4)
H_DINV#0 (4)
H_DINV#1 (4)
H_DINV#2 (4)
H_DINV#3 (4)
H_DPWR# (4)
H_DRDY# (4)

H_DSTBN#[0..3] (4)

H_DSTBP# [0..3] (4)

H_HIT# (4)
H_HITM# (4)
H_LOCK# (4)

H_REQ#[0..4] (4)

H_RS#[0..2] (4)

H_CPUSLP# (4)
H_TRDY# (4)

+DIMM_VREF

DMI_TXN0(17)
DMI_TXN1(17)
DMI_TXP0(17)
DMI_TXP1(17)

DMI_RXN0(17)
DMI_RXN1(17)
DMI_RXP0(17)
DMI_RXP1(17)

M_CLK_DDR0(11)
M_CLK_DDR1(11)

M_CLK_DDR#0(11)
M_CLK_DDR#1(11)

DDR_CKE0(11)
DDR_CKE1(11)

DDR_CS0#(11)
DDR_CS1#(11)

+1.8V

R232 80.6_0402_1%R232 80.6_0402_1%

1
1

R228 80.6_0402_1%R228 80.6_0402_1%

1

Layout Note:
+DIMM_VREF trace

C53C53

2

width and spacing
is 20/20.

0.1U_0402_16V4Z 0.1U_0402_16V4Z

U1B

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR#0
M_CLK_DDR#1

DDR_CKE0
DDR_CKE1

DDR_CS0#
DDR_CS1#

M_ODT0(11)

M_ODT1(11)

2
2

M_ODT0
M_ODT1

SMRCOMPN
SMRCOMPP

10uA

Y29
Y32
Y28
Y31

V28
V31
V29
V32

AF33

AG1

AJ1

AM30

AG33

AF1

AK1

AN30

AN21
AN22
AF26
AF25

AG14
AF12
AK14
AH12

AJ21

AF11

AE12
AF14

AJ14
AJ12

AN12
AN14
AA33

AE1

U1B

DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1

DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1

SM_CK_0
SM_CK_1

SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1

SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6

DMI

DMI

RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9

CFG/RSVD

CFG/RSVD

DDR2 MUXING

DDR2 MUXING

PM_ICHSYNC#

PM_BMBUSY#
PM_EXTTS#_0

PM

PM

PM_EXTTS#_1

THRMTRIP#

PWROK

RSTIN#

D_REFCLKN
D_REFCLKP

CLK

CLK

D_REFSSCLKN
D_REFSSCLKP

CLKREQ#

C18
E18
G20
G18
J20
J18

K32
K31
C17
F18
A3

E31
G21
F26
H26
J15
AB29
W27

A27
A26
J33
H33
J22

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG5
CFG6

PM_EXTTS#0
PM_EXTTS#1

PLTRST_R#

PAD @ T32 PAD @

T32

1

R181 2.2K_0402_5%R181 2.2K_0402_5%

PADT33 @ T33 PAD @

R203 0_0402_5% R203 0_0402_5%

H_THERMTRIP#

ICH_POK

1

R211 100_0402_5%

R211 100_0402_5%

MCH_CLKSEL0 (12)
MCH_CLKSEL1 (12)
MCH_CLKSEL2 (12)

2

MCH_ICH_SYNC# (15)

PM_BMBUSY# (17)
PM_EXTTS#0 (11)

12

2

PM_DPRSLPVR (17,37)

H_THERMTRIP# (4,16)

ICH_POK (17,25)

PLTRST# (15,17,19,24,25,27)

CLK_MCH_DREFCLK# (12)
CLK_MCH_DREFCLK (12)
MCH_SSCDREFCLK# (12)
MCH_SSCDREFCLK (12)
MCH_CLKREQ# (12)

Strap Pin Table

CFG5

Low = DMI x 2

High = DMI x 4

*

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

+VCCP

1

R176

A A

R176

2

1 2

R174

R174

100_0402_1%

100_0402_1%

+H_VREF

1

C243C243

2

200_0402_1%

200_0402_1%

5

C50 be placed <100mils
from GMCH pin

0.1U_0402_16V4Z 0.1U_0402_16V4Z

+VCCP

R167

R167

R166

R166

1

221_0402_1%

221_0402_1%

2

12

100_0402_1%

100_0402_1%

+H_SWNG0

1

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

4

C240C240

+VCCP

R180

R180

R178

R178

12

221_0402_1%

221_0402_1%

12

100_0402_1%

100_0402_1%

+H_SWNG1

1

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

C251C251

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PM_EXTTS#0

PM_EXTTS#1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Calistoga(1/5)-GTL/DMI/DDR

Calistoga(1/5)-GTL/DMI/DDR

Calistoga(1/5)-GTL/DMI/DDR

1

R187 10K_0402_5%R187 10K_0402_5%

@

@

1 2

R188 10K_0402_5%

R188 10K_0402_5%

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

1

+3VS

2

0.2

0.2

0.2

of

of

of

6 40Sunday, February 22, 2009

6 40Sunday, February 22, 2009

6 40Sunday, February 22, 2009

5

[e-mail]

4

3

2

1

D D

C C

B B

DDR_A_BS0(11)
DDR_A_BS1(11)
DDR_A_BS2(11)

DDR_A_DM[0..7](11)

DDR_A_DQS[0..7](11)

DDR_A_DQS#[0..7](11)

DDR_A_MA[0..13](11)

DDR_A_CAS#(11)
DDR_A_RAS#(11)

DDR_A_WE#(11)

T9 PADT9 PAD
T8 PAD T8 PAD

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

SA_RCVENIN#

SA_RCVENOUT#

DDR_A_WE#

AK12
AH11
AG17

AB30

AL31
AF30
AK26

AL9
AG7
AK5
AH3

AC28

AJ30

AK33

AL25

AN9
AH8
AM2
AE3

AC29
AK30

AJ33

AM25

AN8

AJ8
AM3
AE2

AJ15
AM17
AM15
AH15
AK15
AN15

AJ18
AF19
AN17

AL17
AG16

AL18
AG18

AL14

AJ17
AK18
AN28
AM28
AH17

AH21

AJ20
AE27

AN20

AL21
AK21
AK22

AL22
AH22
AG22
AF21
AM21
AE21

AL20
AE22
AE26
AE20

U1C

U1C

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS_0
SB_BS_1
SB_BS_2

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47

DDR2 SYSTEM MEMORY

DDR2 SYSTEM MEMORY

SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SB_CAS#

SB_RAS#

SB_WE#

Calistoga-GSE_FCBGA998

Calistoga-GSE_FCBGA998

AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5

AG19
AG21
AG20

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AC31

DDR_A_D[0..63] (11)

A A

Security Classification

Security Classification

5

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CON SENT OF COMPAL ELE CTRONICS, INC.

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Calistoga(2/5)-DDR2

Calistoga(2/5)-DDR2

Calistoga(2/5)-DDR2

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

7 40Sunday, February 22, 2009

7 40Sunday, February 22, 2009

7 40Sunday, February 22, 2009

1

0.2

0.2

0.2

of

of

of

5

D D

4

3

2

1

U1F

U1F

H27

SDVO_CTRLDATA

J27

SDVO_CTRLCLK

GMCH_CRT_R

R10 150_0402_1%R10 150_0402_1%

R8 150_0402_1%R8 150_0402_1%

R9 150_0402_1%R9 150_0402_1%

12

12

12

GMCH_CRT_G

GMCH_CRT_B

Close to U4.H25

12

R183 255_0402_1%R183 255_0402_1%

C C

39_0402_5%

39_0402_5%

R282

R282

GMCH_CRT_VSYNC(14)

GMCH_CRT_HSYNC(14)

R296R296

1 2

1 2

39_0402_5% 39_0402_5%

GMCH_CRT_VSYNC_R

GMCH_CRT_HSYNC_R

R171 100K_0402_5%R171 100K_0402_5%

GMCH_ENBKL(25)

Place R282,R296 close to F27,D27 11/18

B B

+3VS

1 2

R192 10K_0402_5%R192 10K_0402_5%

1 2

R191 10K_0402_5%R191 10K_0402_5%

LCTLA_CLK

LCTLB_DATA

CLK_MCH_3GPLL#(12)
CLK_MCH_3GPLL(12)

GMCH_CRT_CLK(14)
GMCH_CRT_DATA(14)

GMCH_CRT_B(14)

GMCH_CRT_G(14)

GMCH_CRT_R(14)

12

LVDS_SCL(13)
LVDS_SDA(13)

GMCH_ENVDD(13)

12

R184 1.5K_0402_1%R184 1.5K_0402_1%

LVDS_ACLK#(13)
LVDS_ACLK(13)

LVDS_A0#(13)
LVDS_A1#(13)
LVDS_A2#(13)

LVDS_A0(13)
LVDS_A1(13)
LVDS_A2(13)

GMCH_CRT_B

GMCH_CRT_G

GMCH_CRT_R

GMCH_CRT_VSYNC_R
GMCH_CRT_HSYNC_R

CRT_IREF

LCTLA_CLK
LCTLB_DATA
LVDS_SCL
LVDS_SDA

L_IBG

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

Y26

AA26

H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25

H30
G29
F28
E28
G28
H28
K30
K27

J29
J30

K29

D30
C30
A30
A29

G31
F32
D31

H31
G32
C31

F33
D33
F30

E33
D32
F29

G_CLKN
G_CLKP

CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL

LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP

LA_DATAN_0
LA_DATAN_1
LA_DATAN_2

LA_DATAP_0
LA_DATAP_1
LA_DATAP_2

LB_DATAN_0
LB_DATAN_1
LB_DATAN_2

LB_DATAP_0
LB_DATAP_1
LB_DATAP_2

EXP_A_COMPI

EXP_A_ICOMPO

SDVO_TVCLKIN#

SDVO_INT#

SDVO_FLDSTALL#

MISC

MISC

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVO

SDVO

SDVO_RED#

SDVO_GREEN#

SDVO_BLUE#

SDVO_CLKN

SDVO_RED

SDVO_GREEN

SDVO_BLUE
SDVO_CLKP

TV

TV

LVDS VGA

LVDS VGA

TV_DCONSEL0
TV_DCONSEL1

Calistoga-GSE_FCBGA998

Calistoga-GSE_FCBGA998

SDVO_INT

TV_DACA
TV_DACB
TV_DACC

TV_IREF
TV_IRTNA
TV_IRTNB

TV_IRTNC

R28
M28

N30
R30
T29

M30
P30
T30

P28
N32
P32
T32

N28
M32
P33
R32

A21
C20
E20
G23
B21
C21
D21

G26
J26

PEGCOMP

+1.5VS

1 2

Disable TV

R190R190

24.9_0402_1% 24.9_0402_1%

+1.5VS_PCIE

A A

Security Classification

Security Classification

Security Classification

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Calistoga(3/5)-VGA/LVDS/TV

Calistoga(3/5)-VGA/LVDS/TV

Calistoga(3/5)-VGA/LVDS/TV

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

1

of

of

of

8 40Sunday, February 22, 2009

8 40Sunday, February 22, 2009

8 40Sunday, February 22, 2009

0.2

0.2

0.2

5

[e-mail]

+VCCP

D D

C C

+VCCP

B B

A A

M25

N24
M24

W22

U22

R22

N22
M22

W21

U21

R21

N21
M21

W20

U20

R20

N20
M20

N19
M19

N18
M18

N17
M17

N16
M16

N15
M15

W14

U14

R14

N14
M14

R10

N10

M10

AB10
AA10

T25
R25
P25
N25

P24

Y22

V22

T22

P22

Y21

V21

T21

P21

Y20

V20

T20

P20

Y19
P19

Y18
P18

Y17
P17

Y16
P16

Y15
P15

Y14

V14

T14

P14

T10

P10

L10

A18

U1H

U1H

D1

VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64

VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6

RSVD_3
RSVD_4
RSVD_5
RSVD_6

NCTF

NCTF

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

4

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

CFG_19

RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

K28

K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

+1.5VS

3

U1E

U1E

AH33

VSS_1

Y33
V33
R33

G33

AK32

AG32

AE32
AC32
AA32

U32
H32
E32
C32

AM31

AJ31

AA31

U31
T31
R31
P31
N31

M31

J31
F31

AL30

AG30

AE30
AC30
AA30

Y30

V30
U30
G30

E30

B30

AA29

U29
R29

P29
N29
M29
H29

E29

B29

AK28
AH28
AE28
AA28

U28

T28

J28
D28

AM27

AF27
AB27
AA27

Y27
U27

T27
R27

P27
N27
M27
G27

E27
C27

B27

AL26

AH26

W26

U26

AN25
AK25

AG25

AE25

J25
G25

A25
H23

F23

B23

AM22

AJ22

AF22

G22

E22

J21
H21

F21

AM20

AK20
AH20
AF20

D20

W19

R19

AM18

AH18
AF18

U18
H18
D18

AK17

V17

T17

F17

B17

AH16

U16

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110

VSS

VSS

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185

J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1

2

U1G

U1G

W33

NC1

AM33

NC2

AL33

NC3

C33

NC4

B33

NC5

AN32

NC6

A32

NC7

AN31

NC8

W28

NC9

V27

NC10

W29

NC11

J24

NC12

H24

NC13

W32

NC14

G24

NC15

F24

NC16

E24

NC17

D24

NC18

K33

NC19

A31

NC20

E21

NC21

C23

NC22

AN19

NC23

AM19

NC24

AL19

NC25

AK19

NC26

AJ19

NC27

AH19

NC28

AN3

NC29

Y9

NC30

J19

NC31

H19

NC32

G19

NC33

F19

NC34

E19

NC35

D19

NC36

C19

NC37

B19

NC38

A19

NC39

Y8

NC40

G16

NC41

F16

NC42

E16

NC43

D16

NC44

C16

NC45

B16

NC46

AN2

NC47

A16

NC48

Y7

NC49

AM4

NC50

AF4

NC51

AD4

NC52

AL4

NC53

AK4

NC54

W31

NC55

AJ4

NC56

AH4

NC57

AG4

NC58

AE4

NC59

AM1

NC60

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

NC

NC

RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42

1

NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72

W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18

Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Calistoga(4/5)-PWR/GND

Calistoga(4/5)-PWR/GND

Calistoga(4/5)-PWR/GND

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

9 40Thursday, January 22, 2009

9 40Thursday, January 22, 2009

9 40Thursday, January 22, 2009

1

0.2

0.2

0.2

of

of

of

+VCCP

C37

C37

220U_B2_2.5VM_R35

D D

C C

220U_B2_2.5VM_R35

R168

R168

10_0402_5%

10_0402_5%

To be confirmed 11/14

add net name(+VCCP_D)
20mil 12/10

B B

A A

5

2940mA

1

1

+

+

C41C41

C39C39

2

2

10U_0805_10V4Z 10U_0805_10V4Z

10U_0805_10V4Z 10U_0805_10V4Z

+VCCP

D15

D15 @

@

RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

1 2

+VCCP_D

12

+2.5VS

@

@

5

1

C261C261

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.47U_0603_16V4Z 0.47U_0603_16V4Z

1

C265C265

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z

1

+

+

C40

C40

2

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

1

2

C281C281

C266C266

C25

C25

1 2

C22

C22

1 2

1

2

4.7U_0805_6.3V6K 4.7U_0805_6.3V6K

C283C283

1

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1250mA

10mil

780mA

10mil

C276C276

4.7U_0805_6.3V6K 4.7U_0805_6.3V6K

10mil

2

1

+1.5VS

C250C250

0.1U_0402_16V4Z 0.1U_0402_16V4Z

+VCCP

1

2

1

2

U4_A14

U4_A7

U4_AA1
U4_F1

2

C248

C248

0.47U_0603_16V4Z

0.47U_0603_16V4Z

1

10mil

M26

W18

W17

W16

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18

AF17

AE17

AF16

AE16

AF15

AE15

AE9
AD9

AD8
AD7
AD6

AA1

T26
R26
P26
N26

V19
U19
T19

V18
T18
R18

U17
R17

V16
T16
R16
V15
U15
T15

J14
J10
H10

A14
D10

U9

P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6

G6

D6
U5
P5
L5

G5

D5
Y4
U4
P4
L4

G4

D4
Y3
U3
P3
L3

G3

D3
Y2
U2
P2
L2

G2

D2

F1

U1D

U1D

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

4

VCCATVDACA0
VCCATVDACA1
VCCATVDACB0

VCCATVDACB1
VCCATVDACC0
VCCATVDACC1

VCCATVBG
VSSATVBG

VCCDTVDAC

VCCDQTVDAC

VCCDLVDS0
VCCDLVDS1
VCCDLVDS2

VCCAMPLL

VCCAHPLL
VCCADPLLA
VCCADPLLB

POWER

POWER

VCCDHMPLL1
VCCDHMPLL2

VCCTXLVDS0
VCCTXLVDS1

VCCA3GPLL

VCCA3GBG
VSSA3GBG

VCCSYNC
VCCACRTDAC0
VCCACRTDAC1

VSSACRTDAC

VCCALVDS

VSSALVDS

Calistoga-GS E_FCBGA9 98

Calistoga-GS E_FCBGA9 98

4

VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51

VCC3G0
VCC3G1

VTT41
VTT42
VTT43
VTT44
VTT45

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32

P1
L1
G1
U1
Y1

+1.5VS

400mA

2mA

10mA

144mA

20mA

40mA

U4_AB33
U4_AM32

10mil

10mil

10mil

+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS

+2.5VS

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+2.5VS

3

2

Disable TV

+1.5VS

+3VS

10mil

C54

C54

150mA

60mA

10mil

1

1

C286C286

C318C318

1U_0603_10V6K

1U_0603_10V6K

2

2

1U_0603_10V6K 1U_0603_10V6K

1U_0603_10V6K 1U_0603_10V6K

1

C319

C319
1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

C329C329

2

1

1U_0603_10V6K 1U_0603_10V6K

2

45mA
45mA

50mA
50mA

Route +2.5VS from GMCH pinN33 to
decoupling cap <200mil to the edge.

1

1

C23C23

2

2

C239C239

10U_0805_10V4Z 10U_0805_10V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.8V

533 MTS=1720mA

1

1

C288

C288

2

1U_0603_10V6K

1U_0603_10V6K

1

C330C330

C293C293

2

2

4.7U_0603_6.3V6M 4.7U_0603_6.3V6M

4.7U_0603_6.3V6M 4.7U_0603_6.3V6M

C267

C267

400mA

CRTDAC: Route FB

70mA
70mA

1

+VCCP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

2

C241C241

0.022U_0402_16V7K 0.022U_0402_16V7K

3

within 3" of Calis toga

R172

R172

12

10_0603_5%

10_0603_5%

1

C244C244

C242C242

2

10U_0805_10V4Z 10U_0805_10V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

+2.5VS

1

1

C24C24

2

2

C235C235

10U_0805_10V4Z 10U_0805_10V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

C268

C268

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

Co-layout with C249
add C268 01/22

+2.5VS

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5VS

C254

C254

@

1

C256C256

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

@

1

C245C245

2

10U_0805_10V4Z 10U_0805_10V4Z

1

+

+

<BOM Structure>

<BOM Structure>

2

1

2

10U_0805_10V4Z

10U_0805_10V4Z

2

PCI-E/MEM/PSB PLL decoupling

R210

+1.5VS_3GPLL

1

1

C277C277

C278

C278

2

2

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1

C48C48

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C257

C257

1

2

45mA Max.

R45

R45
0_0603_5%

0_0603_5%

12

1

C52C52

2

10U_0805_10V4Z 10U_0805_10V4Z

L20

L20

1

FBM-L10-160808-301-T_0603

FBM-L10-160808-301-T_0603

2

+1.5VS_MPLL

change C249 BOM structure(@) 01/23

Del C249 02/18

+1.5VS_PCIE

1

C253C253

2

10U_0805_10V4Z 10U_0805_10V4Z

C259

C259

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

R177

R177

1

2

0_0805_5%

0_0805_5%

1

+

+

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

R210

12

0_0603_5%

0_0603_5%

+1.5VS

+1.5VS +1.5VS

+1.5VS

+2.5VS

1

C260C260

2

4.7U_0805_6.3V6K 4.7U_0805_6.3V6K

close pin C29/D29

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Calistoga(5/5)-PWR/GND

Calistoga(5/5)-PWR/GND

Calistoga(5/5)-PWR/GND

1

+1.5VS+1.5VS_3GPLL

+1.5VS

1

@

@

C287

C287

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C43C43

C44C44

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

FBM-L10-160808-301-T_0603

FBM-L10-160808-301-T_0603

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

C236

C236

1

2

1

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

45mA Max.

R38

R38
0_0603_5%

0_0603_5%

1

2

10U_0805_10V4Z 10U_0805_10V4Z

40mA Max.40mA Max.

L2

L2

1

1

C13

C13

+

+

2

+2.5VS

1

C237C237

2

0.01U_0402_25V7K 0.01U_0402_25V7K

+1.5VS_HPLL

+1.5VS_DPLLA+1.5VS_DPLLB

C247C247

close pin B31

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

10 40Wednesday, February 18, 2009

10 40Wednesday, February 18, 2009

10 40Wednesday, February 18, 2009

1

12

+1.5VS

2

1

C246C246

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.2

0.2

0.2

of

of

of

5

[e-mail]

DDR_A_DQS#[0..7](7)

DDR_A_D[0..63](7)

DDR_A_DM[0..7](7)

DDR_A_DQS[0..7](7)

DDR_A_MA[0..13](7)

D D

+1.8V

2

2

2

C89

C89

C90

C90

C91

C91

1

+

+

@

@

C61

C61

2

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

C C

+0.9VS

1

1

C84C84

C79C79

2

B B

A A

0.1U_0402_16V4Z 0.1U_0402_16V4Z

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

DDR_A_MA0
DDR_A_MA13
DDR_CS0#
M_ODT0

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_CAS#

DDR_A_WE#
DDR_A_BS0
M_ODT1
DDR_CS1#

1

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

1

C69C69

C68C68

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

1

C81C81

C104C104

0.1U_0402_16V4Z 0.1U_0402_16V4Z

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

RP1

RP1

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

56_0804_8P4R_5%

RP2

RP2

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

56_0804_8P4R_5%

RP3

RP3

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

56_0804_8P4R_5%

C103C103

0.1U_0402_16V4Z 0.1U_0402_16V4Z

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

2

+0.9VS

1

C88C88

0.1U_0402_16V4Z 0.1U_0402_16V4Z

C102C102

0.1U_0402_16V4Z 0.1U_0402_16V4Z

2

C71C71

C70C70

1

2.2U_0603_6.3V6K 2.2U_0603_6.3V6K

1

1

C87C87

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1

1

C83C83

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

RP5

RP5

18
27
36
45

56_0804_8P4R_5%

56_0804_8P4R_5%

RP6

RP6

18
27
36
45

56_0804_8P4R_5%

56_0804_8P4R_5%

RP4

RP4

18
27
36
45

56_0804_8P4R_5%

56_0804_8P4R_5%

2

1

2.2U_0603_6.3V6K 2.2U_0603_6.3V6K

1

C82

C82

C101C101

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_RAS#

DDR_A_MA4
DDR_A_MA2

DDR_A_BS1

DDR_CKE1
DDR_A_MA7
DDR_A_MA6

DDR_A_MA11

DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA10

Layout Note:
Place near JDIM1

1

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

4

+1.8V

12

R41

R41

1K_0402_1%

1K_0402_1%

12

R43

R43

1K_0402_1%

1K_0402_1%

+DIMM_VREF

Share +DIMM_VREF for

1.DDRII VREF

2.GMCH SM_VREF_0
SM_VREF_1

20mils

1

C86

C86

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

For EMI DDR issue

del C94 C95 01/22

1

1

1

C78C78

C99C99

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1

C80C80

C100C100

2

2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

add JDIM1 pin 200 and pin 201 to GND
01/20

return the H5.2 pootprint 11/24

C361

C361

+3VS

1

2

Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil

3

+DIMM_VREF

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C92

C92

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

CLK_SMBDATA (12,19)

DDR_A_BS2(7)

DDR_A_BS0(7)
DDR_A_WE#(7)

DDR_A_CAS#(7)

CLK_SMBCLK (12,19)

+DIMM_VREF

DDR_CKE0(6)

DDR_CS1#(6)

M_ODT1(6)

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D9
DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1#

M_ODT1

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

CLK_SMBDATA
CLK_SMBCLK

+3VS

change DIMMA from H5.2 to H4 11/17

2

+1.8V +1.8V

JDIM1

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

P-TWO_A5652C-A0G16

P-TWO_A5652C-A0G16

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DIMMA

DDR_A_D4
DDR_A_D5

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R53 10K_0402_5%R53 10K_0402_5%

1

R52 10K_0402_5%R52 10K_0402_5%

1

R54

R54

2
2

M_CLK_DDR0 (6)
M_CLK_DDR#0 (6)

1 2

DDR_CKE1 (6)

DDR_A_BS1 (7)
DDR_A_RAS# (7)
DDR_CS0# (6)

M_ODT0 (6)

M_CLK_DDR1 (6)
M_CLK_DDR#1 (6)

1

0_0402_5%

0_0402_5%

PM_EXTTS#0 (6)

DDR_A_BS2

DDR_CKE0

R159

R159

1

56_0402_5%

56_0402_5%
R160

R160

1

56_0402_5%

56_0402_5%

5

2

2

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMMA

DDRII-SODIMMA

DDRII-SODIMMA

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

11 40Sunday, February 22, 2009

11 40Sunday, February 22, 2009

11 40Sunday, February 22, 2009

1

0.2

0.2

0.2

of

of

of

5

PCI

266

SRCCPU

MHz

MHz MHz

1000

33.30

MHz

DOT_96
MHz

USB
MHz

14.318 96.0 48.0

CLKSEL1

FSA

CLKSEL0

FSC FSB REF

CLKSEL2

0

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

change R141,R140,R147,R81,R91
R82,R97,R95,R98 BOM structure 12/29

change R141,R140,R147,R81,R91
R82,R97,R95,R98 BOM structure 01/17

C C

B B

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

A A

FSA

CPU_BSEL0(4)

<BOM Structure>

<BOM Structure>

CPU_BSEL1(4)

<BOM Structure>

<BOM Structure>

FSC

CPU_BSEL2(4)

<BOM Structure>

<BOM Structure>

+VCCP

R138R138

2.2K_0402_5% 2.2K_0402_5%

1 2

12

1 2

R147

R147
0_0402_5%

0_0402_5%

1 2

R91

R91
0_0402_5%

0_0402_5%

R100

R100
10K_0402_5%

10K_0402_5%

1 2

R95

R95
0_0402_5%

0_0402_5%

1 2

12

+VCCP

1 2

FSB

1 2

12

+VCCP

1 2

1 2

12

12

C169 27P_0402_50V8J C169 27P_0402_50V8J

14.31818MHZ_16PF_DSX840GA

14.31818MHZ_16PF_DSX840GA

1 2

C162 22P_0402_50V8J C162 22P_0402_50V8J

R140
56_0402_5%

56_0402_5%

R142

R142
1K_0402_5%

1K_0402_5%

R141
1K_0402_5%

1K_0402_5%

R81

1K_0402_5%

1K_0402_5%

R86

R86
1K_0402_5%

1K_0402_5%

R82
0_0402_5%

0_0402_5%

R97

1K_0402_5%

1K_0402_5%

R99

R99
1K_0402_5%

1K_0402_5%

R98
0_0402_5%

0_0402_5%

@ R140

@

<BOM Structure>R141

<BOM Structure>

<BOM Structure> R81

<BOM Structure>

@ R82

@

<BOM Structure> R97

<BOM Structure>

@ R98

@

Reserved

del R143 and CLK_SD_48M 11/21

Change R137 from 12 ohm
to 33 ohm 11/21

change R137 BOM structure 12/15
add R143 12/15

MCH_CLKSEL0 (6)

MCH_CLKSEL1 (6)

change C32 C33 C42 C45
BOM structre 12/14

del R143 12/15

change C32 from 10P to
15p ohm 02/06

add C45 for keypart 12/14

change C42,C45 from
22p to 15p 02/06

MCH_CLKSEL2 (6)

change R115,R121 from
39 ohm to 47 ohm 02/06

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

CLK_XTAL_IN

12

Y2

Y2

<BOM Structure>

<BOM Structure>

CLK_XTAL_OUT

Routing the t race at least 10mil

change C162 from 27P to 22P 01/23

5

4

add C164,C165 01/22

+3VS

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

L12L12

1

C159

C159

2

FBMA-L11-201209-221LMA30T_0805 FB MA-L11-201209-221LMA30T_0805

1

1

C165

C165

C164

C164

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

47P_0402_50V8J

47P_0402_50V8J

Close to L12

move C159 from P11 to P12 01/22

+3VS

C32

C32

15P_0402_50V8J

15P_0402_50V8J

1 2

R645 10K_0402_5% @R645 10K_0402_5% @

CLK_ICH_48M(17)

CLK_ICH_14M(17)

H_STP_CPU#(17)

H_STP_PCI#(17)

CLK_PCI_LPC(25)

CLK_PCI_ICH(15)

H_STP_PCI#

change R137 from 33 to
39 ohm 02/06

C33 10P_0402_50V8J

C33 10P_0402_50V8J

VGATE (17, 25,37)

add C32,C33,C42
for keypart 12/08

Del R129 12/14

ITP_EN PCI4_SEL PCI2_TME

R132

R132

10K_0402_5%

10K_0402_5%

1 2

4

R117

R117

10K_0402_5%

10K_0402_5%

1 2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L11

L11

12

47P_0402_50V8J

47P_0402_50V8J

Close to L11

1

C851

C851

2

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

+1.05VM_CK505

R137 39_0402_1% R137 39_0402_1%

1 2

33_0402_5% R101

33_0402_5% R101

1 2

<BOM Structure>

15P_0402_50V8J

15P_0402_50V8J

1 2

R115 47_0402_5%R115 47_0402_5%

1 2

R121 47_0402_5%R121 47_0402_5%

R109

R109

10K_0402_5%

10K_0402_5%

1 2

Del R110,
R119 01/17

<BOM Structure>

12

<BOM Structure>

<BOM Structure>

C42

C42

C45C45

15P_0402_50V8J 15P_0402_50V 8J

+3VS

C834

C834

+1.05VM_CK505

1

C163

C163

10U_0805_10V4Z

10U_0805_10V4Z

2

VGATE

H_STP_CPU#

H_STP_PCI#

CLK_XTAL_IN

CLK_XTAL_OUT

+3VM_CK505

1

2

+3VM_CK505

FSA

FSB

FSC

PCI2_TME

PCI4_SEL

ITP_EN

3

1

C151

C151

10U_0805_10V4Z

10U_0805_10V4Z

2

1

C198

C198

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C181

C181

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C152

C152

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

U11

U11

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VTR_QFN72_10X10

SLG8SP556VTR_QFN72_10X10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C175

C175

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C153

C153

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

SRC_0#/DOT_96#

LCDCLK#/27M_SS

SRC_8#/CPU_ITP#

USB_1/CLKREQ_A#

2007/10/15 2007/8/18

2007/10/15 2007/8/18

2007/10/15 2007/8/18

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_0/DOT_96

LCDCLK/27M

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_8/CPU_ITP

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

1

C197

C197

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C167

C167

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

CLK_SMBDATA

9

SDA

CLK_SMBCLK

10

SCL

CLK_CPU_BCLK

71

CLK_CPU_BCLK#

70

CLK_MCH_BCLK

68

CLK_MCH_BCLK#

67

CLK_MCH_DREFCLK

24

CLK_MCH_DREFCLK#

25

MCH_SSCDREFCLK

28

MCH_SSCDREFCLK#

29

CLK_PCIE_SATA

32

CLK_PCIE_SATA#

33

CLK_MCH_3GPLL

35

CLK_MCH_3GPLL#

36

CLK_PCIE_CARD

39

CLK_PCIE_CARD#

40

CLK_PCIE_WLAN

57

CLK_PCIE_WLAN#

56

CLK_PCIE_WWAN

61

CLK_PCIE_WWAN#

60

64

63

CLK_PCIE_LAN

44

CLK_PCIE_LAN#

45

CLK_PCIE_ICH

50

CLK_PCIE_ICH#

51

48

47

MCH_CLKREQ#

37

41

WLAN_CLKREQ#

58

WW AN_CLKREQ#

65

43

49

46

SATA_CLKREQ#

21

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

C199

C199

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

2

Deciphered Date

Deciphered Date

Deciphered Date

2

C189

C189

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C155

C155

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C200

C200

2

1

2

ICH_SMBDATA(17)

ICH_SMBCLK(17)

add R149,R150 11/20

CLK_SMBDATA (11,19)

CLK_SMBCLK (11,19)

CLK_CPU_BCLK (4)

CLK_CPU_BCLK# (4)

CLK_MCH_BCLK (6)

CLK_MCH_BCLK# (6)

CLK_MCH_DREFCLK (6)

CLK_MCH_DREFCLK# (6)

MCH_SSCDREFCLK (6)

MCH_SSCDREFCLK# (6)

CLK_PCIE_SATA (16)

CLK_PCIE_SATA# (16)

CLK_MCH_3GPLL (8)

CLK_MCH_3GPLL# (8)

CLK_PCIE_CARD (27)

CLK_PCIE_CARD# (27)

CLK_PCIE_WLAN (19)

CLK_PCIE_WLAN# (19)

CLK_PCIE_WWAN (19)

CLK_PCIE_WWAN# (19)

CLK_PCIE_LAN (24)

CLK_PCIE_LAN# (24)

CLK_PCIE_ICH (17)

CLK_PCIE_ICH# (17)

MCH_CLKREQ# (6)

WLAN_CLKREQ# (19)

WW AN_CLKREQ# (19)

SATA_CLKREQ# (17)

1

C154

C154

change R112,R108,Q10A,Q10B
BOM structure 11/20

+3VS

R112

R112

@

@

Q10A 2N7002DW-T/R7_SOT363-6 @ Q10A 2N7002DW-T/ R7_SOT363-6 @

2

5

Q10B 2N7002DW-T/R7_SOT363-6 @ Q10B 2N7002DW-T/R7_SOT363-6 @

4

+3VS

R150 0_0402_5%R150 0_0402_5%

1 2

6 1

3

1 2

R149

R149
0_0402_5%

0_0402_5%

2.2K_0402_5%

2.2K_0402_5%

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9 PCIE_LAN
SRC10
SRC11

MCH_CLKREQ#
SATA_CLKREQ#
WLAN_CLKREQ#
WW AN_CLKREQ#

DEVICE

MCH_DREFCLK
SATA HDD
MCH_3GPLL
PCIE_CARDREADER
PCIE_WLAN
PCIE_WWAN

PCIE_ICH

R139 10K_0402_5%R139 10K_0402_5%
R111 10K_0402_5%R111 10K_0402_5%
R84 10K_0402_5%R84 10K_0402_5%
R85 10K_0402_5%R85 10K_0402_5%

REQ PORT LIST

DEVICE PORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

MCH_3GPLL

PCIE_WLAN
PCIE_WWAN

SATA

KAV60 LA-5141P

KAV60 LA-5141P

KAV60 LA-5141P

1

@

@

R108

R108

2.2K_0402_5%

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

12
12
12
12

of

12 40Sunday, February 22, 2009

of

12 40Sunday, February 22, 2009

of

12 40Sunday, February 22, 2009

+3VS

0.2

0.2

0.2