Acer Aspire 5538, Aspire 7538 Schematics

A

[e-mail]

1 1

B

C

D

E

Compal Confidential

2 2

NAL00 Schematics Document

AMD L310/L110 Processor with RS780MN/SB710/M92-S2/S3 LP

3 3

2009-04-24

REV:0.2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

149Monday, May 04, 2009

149Monday, May 04, 2009

149Monday, May 04, 2009

E

A

A

A

A

Compal Confidential

Model Name : NAL00

B

C

D

E

VRAM 512MB

1 1

LVDS Conn.

page 21

64M16 x 4

page 18

DDR3

Fan Control

page 4

ATI M92-S2 LP

CRT Conn.

page 23

HDMI Conn.

page 22

uFCBGA-631

Page 14,15,16,17,19

PCI-Express 8x

Gen1

PCI-Express 1x

Port 2

2 2

MINI Card 2
WWAN

page 31

Port 0

MINI Card 1
WLAN

page 31

Port 1

To IO board
LAN(GbE)

Realtek RTL8111CA

page 31

AMD S1G1 Processor

uPGA-638 Package

page 4,5,6,7

Hyper Transport Link
16 x 16

ATI RS780MN

uFCBGA-528

page 10,11,12,13

A link Express2

ATI SB710

uFCBGA-528

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 667/800

Thermal Sensor

ADM1032

page 32

page 6 page 20

page 31

USB conn
X 2

USB

3.3V 48MHz

HD Audio

Port 1
Port 6

3.3V 24.576MHz/48Mhz

Clock Generator

SLG8SP626VTR

To IO Board
USB conn X 2

page 21

Port 0
Port 2

Camera

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 32

page 8,9

page 31

Mini Card 2

BT Conn

page 31

(WWAN)

Mini Card 1
(WLAN)

Port 3 Port 12 Port 5

Port 8

5 in 1 socket

page 30

Card Reader

RTS5159

page 30

Port 4

S-ATA

IO Board

page 31

PWR Board

page 35

page 24,25,26,27,28

port 0

SATA HDD
Conn.

page 29

port 1

CDROM
Conn.

page 29

LPC BUS

TP Board

page 34

3 3

LID SW/Cap sensor Board

page 33

LED

page 35

ENE KB926

page 33

HDA Codec
ALC269X-GR

page 36

Phone Jack x2

page 37

Digital MIC

page 37

Power On/Off CKT.

RTC CKT.

page 24

DC/DC Interface CKT.

page 35

page 38

Int.KB

page 34

BIOS

page 34

Power Circuit

page 39,40,41,42,43,44,4546,47

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

249Monday, May 04, 2009

249Monday, May 04, 2009

249Monday, May 04, 2009

E

A

A

A

of

of

of

A

[e-mail]

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE

+NB_CORE 1.0V switched power rail ON OFFOFF
+0.9V 0.9V switched power rail for DDR terminator
+1.1VS
+1.2V_HT 1.2V switched power rail ON OFF OFF
+VGA_CORE
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)

1.1V switched power rail for NB VDDC & VGA

0.90-0.95V switched power rail

1.5V power rail for PCIE Card

1.8V power rail for CPU VDDIO and DDR

2.5V for CPU_VDDA

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON
ON OFF OFF

ON

OFF OFF

ON

ON

ON

OFF
OFF

ON
ON

ON ON*

ON

OFF

ON

ON

OFF
ON
ON

N/AN/AN/A
OFF

OFF

OFFOFFON

OFF
OFF
OFF

OFF
ON*
OFFON

ONON

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

D

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

ON

ON

ON

ON

ON

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BOARD ID Table BTO Option Table

Board ID

0
1
2
3
4
5

PCB Revision

0.1

0.2

0.3

1.0

BTO Item BOM Structure

Discrete

VGA@

UMA UMA@
UMA_HDMI UMA_H@
Side port SP@
JM51
HM52

JM@

HM@

E

LOW

OFF

OFF

OFF

6
7

3 3

EC SM Bus1 address

Device

Smart Battery

Address Address

HEX

SB710
SM Bus 0 address

Device

Clock Generator
(SILEGO SLG8SP626)

DDR DIMM1
DDR DIMM2
Mini card

4 4

A

Address

1101 001Xb

1001 000Xb
1001 010Xb

HEX

D2
90

94

EC SM Bus2 address

Device

ADI ADM1032 (CPU)

SB-Temp Sensor

1001 100X b0001 011X b

SB700
SM Bus 1 address

Device Address

New card

B

HEX
98H16H

9CH

PX_GPIO0

IGP only mode

PX_GPIO1

IGP only mode

PowerXpress mode

IGP only mode

PowerXpress mode

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Enable +1.1VS_PXFunction Description PX MODE SWITCH Enable +3VS_DELAY

H : Enable Reserved

Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)Function Description

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

C

dGPU_ResetFunction Description dGPU_PWR_Enable PX Mode Switch

XX

PX_GPIO1_SB

Compal Secret Data

Compal Secret Data

Compal Secret Data

PX_GPIO1

XX

H : EnableH : Enable L : iGPU(DC) / H : dGPU(AC)

KB926

PX_+3VSPX_GPIO2

X

H : Enable

KB926

X

H : Enable

Deciphered Date

Deciphered Date

Deciphered Date

RS780MNSB700 SB700
PX_GPIO2

PX_+1.8VS

Enable +1.8VS_PX

H : Enable

D

DISPLAY OUTPUT

X

X

Date: Sheet of

Date: Sheet of

Date: Sheet of

LVDS / CRTPowerXpress mode

PX_+VGA_CORE
Enable +VGA_CORE

X

H : Enable

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

PX_GPIO2_NB

Trigger from SB

X

Reserved

E

349Monday, May 04, 2009

349Monday, May 04, 2009

349Monday, May 04, 2009

A

A

A

5

4

3

2

1

D D

C C

B B

H_CADIP[0..15]<10>

H_CLKIP1<10>
H_CLKIN1<10>
H_CLKIP0<10>
H_CLKIN0<10>

H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>

1 2

R225 0_0402_5%R225 0_0402_5%

1 2

R226 0_0402_5%R226 0_0402_5%

H_CTLIP0<10> H_CTLOP0 <10>
H_CTLIN0<10>

+1.2V_HT

H_CADIP[0..15]
H_CADIN[0..15]

VLDT=500mA

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CTLIP1_R
H_CTLIN1_R

H_CTLIP0

R829 51_0402_1%@R829 51_0402_1%@
R814 51_0402_1%@R814 51_0402_1%@

+1.2V_HT

12
12

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

CONN@

CONN@

H_CTLIP1_R
H_CTLIN1_R

JCPU1A

JCPU1A

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0

HTT Interface

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1

L0_CTLOUT_H0
L0_CTLOUT_L0

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

Athlon 64 S1
Processor Socket

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

H_CADOP[0..15]
H_CADON[0..15]

C904 4.7U_0805_10V4ZC904 4.7U_0805_10V4Z

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CTLOP1_R
H_CTLON1_R

H_CTLOP0
H_CTLON0H_CTLIN0

1 2

H_CLKOP1 <10>
H_CLKON1 <10>
H_CLKOP0 <10>
H_CLKON0 <10>

1 2

R227 0_0402_5%R227 0_0402_5%

1 2

R250 0_0402_5%R250 0_0402_5%

H_CTLON0 <10>

H_CADOP[0..15] <10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>

H_CTLON1 <10>

FAN1 Conn

+5VS

+VCC_FAN1

EN_DFAN1<33>

R62 300_0402_5%R62 300_0402_5%

12

1

2

U10

U10

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

APL5607KI-TRG_SO8

C105

C105

0.1U_0402_16V4Z

0.1U_0402_16V4Z

FAN_SPEED1<33>

C108 10U_0805_10V4ZC108 10U_0805_10V4Z

1 2

8

GND

7

GND

6

GND

5

GND

+3VS

12

R298

R298
10K_0402_5%

10K_0402_5%

1

C670

C670
1000P_0402_50V7K

1000P_0402_50V7K

2

40mil

+VCC_FAN1

+5VS

12

D11

D11
1SS355_SOD323-2

1SS355_SOD323-2

@

@

1 2

10U_0805_10V4Z

10U_0805_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K

D12

D12

BAS16_SOT23-3@

BAS16_SOT23-3@
C121

C121

1 2

C119

C119

1 2

ACES_85205-03001

ACES_85205-03001

CONN@

CONN@

JP13

JP13

1
2
3

AMD : 49.9 1%
ATI : 51 1%

+1.2V_HT

250 mil

<BOM Structure>

<BOM Structure>

A A

5

VLDT CAP.

1

C910

C910

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C911

C911

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

1

C912

C912

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

4

1

C913

C913

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

Near CPU Socket

1

C914

C914
180P_0402_50V8J

180P_0402_50V8J

2

1

C915

C915
180P_0402_50V8J

180P_0402_50V8J

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

1

A

A

A

of

of

of

449Monday, May 04, 2009

449Monday, May 04, 2009

449Monday, May 04, 2009

A

[e-mail]

B

C

D

E

DDR_B_D[63..0]<9>

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_B_DQS7<9>
DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS0<9>
DDR_B_DQS#0<9>

R801

R801

1K_0402_1%

1K_0402_1%

R800

R800

1K_0402_1%

1K_0402_1%

+1.8V

+1.8V

1 2

1

1

2

1 2

R802

R802
R803

R803

DDR_CS3_DIMMA#<8>
DDR_CS2_DIMMA#<8>
DDR_CS1_DIMMA#<8>
DDR_CS0_DIMMA#<8>

DDR_CS3_DIMMB#<9>
DDR_CS2_DIMMB#<9>
DDR_CS1_DIMMB#<9>
DDR_CS0_DIMMB#<9>

DDR_CKE1_DIMMB<9>
DDR_CKE0_DIMMB<9>
DDR_CKE1_DIMMA<8>
DDR_CKE0_DIMMA<8>

DDR_A_MA[15..0]<8>

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

C916

C916

1 2

DDR_A_BS#2<8>
DDR_A_BS#1<8>
DDR_A_BS#0<8>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C917

C917

2

12

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

+CPU_M_VREF

1000P_0402_50V7K

1000P_0402_50V7K

+CPU_M_VREF

TP1TP1

39.2_0402_1%

39.2_0402_1%

39.2_0402_1%

39.2_0402_1%

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

W17

VTT_SENSE

Y10

M_ZN

AE10

M_ZP

AF10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

CONN@ FOX_PZ63823-284S-41F

CONN@ FOX_PZ63823-284S-41F

1

C918

C918

1.5P_0402_50V8C

1.5P_0402_50V8C

2

1

C920

C920

1.5P_0402_50V8C

1.5P_0402_50V8C

2

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

JCPU1B

JCPU1B

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

DDRII Cmd/Ctrl//Clk

DDRII Cmd/Ctrl//Clk

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

1

2

1

2

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

C919

C919

1.5P_0402_50V8C

1.5P_0402_50V8C

C921

C921

1.5P_0402_50V8C

1.5P_0402_50V8C

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_A_CLK2 <8>
DDR_A_CLK#2 <8>
DDR_A_CLK1 <8>
DDR_A_CLK#1 <8>

DDR_B_CLK2 <9>
DDR_B_CLK#2 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>

DDR_B_ODT1 <9>
DDR_B_ODT0 <9>
DDR_A_ODT1 <8>
DDR_A_ODT0 <8>

DDR_B_MA[15..0] <9>

DDR_B_BS#2 <9>
DDR_B_BS#1 <9>
DDR_B_BS#0 <9>

DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

4 4

3 3

2 2

1 1

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11

MB_DATA63

AF11

MB_DATA62

AF14

MB_DATA61

AE14

MB_DATA60

Y11

MB_DATA59

AB11

MB_DATA58

AC12

MB_DATA57

AF13

MB_DATA56

AF15

MB_DATA55

AF16

MB_DATA54

AC18

MB_DATA53

AF19

MB_DATA52

AD14

MB_DATA51

AC14

MB_DATA50

AE18

MB_DATA49

AD18

MB_DATA48

AD20

MB_DATA47

AC20

MB_DATA46

AF23

MB_DATA45

AF24

MB_DATA44

AF20

MB_DATA43

AE20

MB_DATA42

AD22

MB_DATA41

AC22

MB_DATA40

AE25

MB_DATA39

AD26

MB_DATA38

AA25

MB_DATA37

AA26

MB_DATA36

AE24

MB_DATA35

AD24

MB_DATA34

AA23

MB_DATA33

AA24

MB_DATA32

G24

MB_DATA31

G23

MB_DATA30

D26

MB_DATA29

C26

MB_DATA28

G26

MB_DATA27

G25

MB_DATA26

E24

MB_DATA25

E23

MB_DATA24

C24

MB_DATA23

B24

MB_DATA22

C20

MB_DATA21

B20

MB_DATA20

C25

MB_DATA19

D24

MB_DATA18

A21

MB_DATA17

D20

MB_DATA16

D18

MB_DATA15

C18

MB_DATA14

D14

MB_DATA13

C14

MB_DATA12

A20

MB_DATA11

A19

MB_DATA10

A16

MB_DATA9

A15

MB_DATA8

A13

MB_DATA7

D12

MB_DATA6

E11

MB_DATA5

G11

MB_DATA4

B14

MB_DATA3

A14

MB_DATA2

A11

MB_DATA1

C11

MB_DATA0

AD12

MB_DM7

AC16

MB_DM6

AE22

MB_DM5

AB26

MB_DM4

E25

MB_DM3

A22

MB_DM2

B16

MB_DM1

A12

MB_DM0

AF12

MB_DQS_H7

AE12

MB_DQS_L7

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AC25

MB_DQS_H4

AC26

MB_DQS_L4

F26

MB_DQS_H3

E26

MB_DQS_L3

A24

MB_DQS_H2

A23

MB_DQS_L2

D16

MB_DQS_H1

C16

MB_DQS_L1

C12

MB_DQS_H0

B12

MB_DQS_L0

CONN@ FOX_PZ63823-284S-41F

CONN@ FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

JCPU1C

JCPU1C

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14

DDRII Data

DDRII Data

MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] <8>

DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>

Processor DDR2 Memory Interface

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

401728

401728

401728

549Monday, May 04, 2009

549Monday, May 04, 2009

549Monday, May 04, 2009

E

A

A

A

5

+1.8VS

A:Need to re-Link "SGN00000200"

R339

R339
300_0402_5%

300_0402_5%

1 2

LDT_RST#<24>

D D

H_PWRGD<24>

C C

B B

LDT_STOP#<11,24>

C929

C929

2200P_0402_50V7K

2200P_0402_50V7K

1

2

LDT_RST#

1

C721

C721

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

+1.8VS

R338

R338
300_0402_5%

300_0402_5%

1 2

H_PWRGD

1

C720

C720

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

+1.8VS

R337

R337
300_0402_5%

300_0402_5%

1 2

LDT_STOP#

1

C719

C719

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

+3VS

C928

C928

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

U55

U55

CPU_THERMDA
CPU_THERMDC

1
2
3

ADM1032ARMZ-2REEL_MSOP8

ADM1032ARMZ-2REEL_MSOP8

F75383M_MSOP8

SMBus Address: 1001110X (b)

AMD: suggest DBREQ need pull high

+1.8V

VDD
D+

ALERT#

D­THERM#4GND

SCLK

SDATA

+2.5VS

CLK_CPU_BCLK<20>

CLK_CPU_BCLK#<20>

8
7
6
5

4

L91

L91

1 2

FCM2012CF-800T06_2P

FCM2012CF-800T06_2P

1

+

+

C391

C391
150U_B2_6.3VM

150U_B2_6.3VM

2

3900P_0402_50V7K

3900P_0402_50V7K

1 2

C926

C926

12

R816

R816
169_0402_1%

169_0402_1%

1 2

C927 3900P_0402_50V7KC927 3900P_0402_50V7K

EC_SMB_CK2 <19,33>
EC_SMB_DA2 <19,33>

+2.5VDDA

1

C923

C923

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.2V_HT

VDDA=300mA

3300P_0402_50V7K

3300P_0402_50V7K

1

1

C924

C924

C925

C925

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

2

LDT_RST#
H_PWRGD
LDT_STOP#

R808 300_0402_5%

R808 300_0402_5%

R811 44.2_0402_1%R811 44.2_0402_1%

1 2

R812 44.2_0402_1%R812 44.2_0402_1%

CPU_VCC_SENSE<46>

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

1 2

R61&R16 close to CPU within 1"

CPU_DBRDY
CPU_TMS

CPU_TCK CPU_TDO
CPU_TRST#
CPU_TDI

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_SIC

12

CPU_HTREF1
CPU_HTREF0

TP2TP2

TP3TP3

TP4TP4
TP6TP6
TP8TP8
TP10TP10
TP11TP11

CPU_THERMDC
CPU_THERMDA

3

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

CONN@

CONN@

JCPU1D

JCPU1D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT_L

PSI_L

DBREQ_L

TDO

TEST29_L

TEST24
TEST23

MISC

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

+1.8V

12

R830

R830
300_0402_5%

300_0402_5%

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

A5
C6
A6
A4
C5
B5

CPU_PRESENT#

AC6
A3

CPU_DBREQ#

E10

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

AE7
AD7
AE8
AB8
AF7

J7
H8
AF8
AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

TP5TP5
TP7TP7
TP9TP9

TP12TP12

CPU_TEST26_BURNIN#

R372

R372

1 2

0_0402_5%

0_0402_5%

CPU_VID5 <46>
CPU_VID4 <46>
CPU_VID3 <46>
CPU_VID2 <46>
CPU_VID1 <46>
CPU_VID0 <46>

PSI_L <46>CPU_VSS_SENSE<46>

1 2

CPU_TEST21_SCANEN

300_0402_5%

300_0402_5%

CPU_THERMTRIP#_R H_THERMTRIP#

2

R819

R819

80.6_0402_1%

80.6_0402_1%

+1.8V

12

R822

R822

H_PROCHOT_R# <24>

+1.8V

12

R820

R820
1K_0402_5%

1K_0402_5%

B

B

2

Q69

Q69

E

E

3 1

C

C

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

CPU_VID1
CPU_PRESENT#
CPU_TEST26_BURNIN#

CPU_TEST21_SCANEN

+1.8V

R813 510_0402_5%

R813 510_0402_5%

R815 510_0402_5%

R815 510_0402_5%
R817 300_0402_5%

R817 300_0402_5%
R818 300_0402_5%

R818 300_0402_5%

+3VALW

12

R823

R823
10K_0402_5%

10K_0402_5%

1 2

R805 300_0402_5%

R805 300_0402_5%

1 2

R806 1K_0402_5%

R806 1K_0402_5%

1 2

R807 300_0402_5%

R807 300_0402_5%

1 2

R809 300_0402_5%

R809 300_0402_5%

CPU_TEST25_H_BYPASSCLK_H

12

CPU_TEST25_L_BYPASSCLK_L

12
12
12

+3VALW

12

R821

R821

1K_0402_5%@

1K_0402_5%@

B

B

2

Q70

Q70
MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

E

E

3 1

C

C

@

@

H_THERMTRIP# <25>

1

+1.8V

VID1: For compatibility
with future processors

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

MAINPWON <42,45>

R824220_0402_5%@ R824220_0402_5%@12R826220_0402_5%@ R826220_0402_5%@

R827220_0402_5%@ R827220_0402_5%@

R825220_0402_5%@ R825220_0402_5%@

R828220_0402_5%R828220_0402_5%

12

12

12

12

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#

A A

CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

5

HDT Connector

JP18

JP18

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@SAMTEC_ASP-68200-07

@

HDT_RST#

4

4

Y

+3VS

5

LDT_RST#

2

P

B

1

A

G

U56

@U56

@

3

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

SB_PWRGD <25,35>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

1

A

A

A

of

of

of

649Monday, May 04, 2009

649Monday, May 04, 2009

649Monday, May 04, 2009

5

[e-mail]

VDD(+CPU_CORE) decoupling.

D D

C C

+CPU_CORE

1

+

+

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C931

C931
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

C936

C936
22U_0805_6.3V6M

22U_0805_6.3V6M

C945

C945

0.22U_0603_16V4Z

0.22U_0603_16V4Z

1

+

+

C930

C930
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

Near CPU Socket

1

C937

C937
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C946

C946

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C938

C938
22U_0805_6.3V6M

22U_0805_6.3V6M

2

+CPU_CORE +CPU_CORE

1

C947

C947

0.01U_0402_25V7K

0.01U_0402_25V7K

2

1

+

+

C934

C934
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

C939

C939
22U_0805_6.3V6M

22U_0805_6.3V6M

2

VDDIO decoupling.

+1.8V

1

C949

C949
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C950

C950
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

B B

+1.8V

1

C954

C954

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C966

C966

0.01U_0402_25V7K

0.01U_0402_25V7K

2

+1.8V

1

A A

2

Between CPU Socket and DIMM

1

C955

C955

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C967

C967

0.01U_0402_25V7K

0.01U_0402_25V7K

2

C980

C980

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C981

C981

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+1.8V

1

C951

C951

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C956

C956

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

2

1

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

C968

C968
180P_0402_50V8J

180P_0402_50V8J

C982

C982

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C952

C952

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C957

C957

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C969

C969
180P_0402_50V8J

180P_0402_50V8J

2

1

C983

C983

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

4

1

+

+

C935

C935
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

C940

C940
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C948

C948
180P_0402_50V8J

180P_0402_50V8J

2

1

C941

C941
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

1

C970

C970
180P_0402_50V8J

180P_0402_50V8J

2

1

+

+

C536

C536
220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

2

1

C942

C942
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C971

C971
180P_0402_50V8J

180P_0402_50V8J

2

3

+CPU_CORE +CPU_CORE

1

C943

C943
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C944

C944
22U_0805_6.3V6M

22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

2

+0.9V

1

2

C958

C958

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C972

C972

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C959

C959

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

Near CPU Socket Right side.

1

C973

C973

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

Near CPU Socket Left side.

1

2

1

2

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

CONN@

CONN@

Athlon 64 S1
Processor Socket

C960

C960

0.22U_0603_16V4Z

0.22U_0603_16V4Z

C974

C974

0.22U_0603_16V4Z

0.22U_0603_16V4Z

JCPU1E

JCPU1E

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

+

C392

C392
150U_B2_6.3VM

150U_B2_6.3VM

2

1

C961

C961

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C975

C975

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

2

+1.8V

1

C962

C962
1000P_0402_50V7K

1000P_0402_50V7K

2

1

C976

C976
1000P_0402_50V7K

1000P_0402_50V7K

2

1

C963

C963
1000P_0402_50V7K

1000P_0402_50V7K

2

1

C977

C977
1000P_0402_50V7K

1000P_0402_50V7K

2

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

CONN@

CONN@

Athlon 64 S1
Processor Socket

JCPU1F

JCPU1F

Ground

Ground

1

C964

C964
180P_0402_50V8J

180P_0402_50V8J

2

1

C978

C978
180P_0402_50V8J

180P_0402_50V8J

2

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

1

C965

C965
180P_0402_50V8J

180P_0402_50V8J

2

1

C979

C979
180P_0402_50V8J

180P_0402_50V8J

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

1

A

A

749Monday, May 04, 2009

749Monday, May 04, 2009

749Monday, May 04, 2009

A

5

4

3

2

1

1

C987

C987

2

Issued Date

Issued Date

Issued Date

3

+1.8V+DIMM_VREF

12

R832

R832

1K_0402_1%

1K_0402_1%

12

R833

R833

1K_0402_1%

1K_0402_1%

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

DDR_A_MA12
DDR_A_BS#2
DDR_CS2_DIMMA#
DDR_CKE0_DIMMA

DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_CS0_DIMMA#

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#

DDR_A_RAS#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#

DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14

Compal Secret Data

Compal Secret Data

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

RP24

RP24

RP25

RP25

RP26

RP26

RP27

RP27

RP28

RP28

RP29

RP29

RP30

RP30

RP31

RP31

+0.9V

18

1 2

C985 0.1U_0402_16V4Z

C985 0.1U_0402_16V4Z

27
36

1 2

C988 0.1U_0402_16V4Z

C988 0.1U_0402_16V4Z

45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

<BOM Structure>

<BOM Structure>

1 2

C989 0.1U_0402_16V4Z

C989 0.1U_0402_16V4Z

1 2

C990 0.1U_0402_16V4Z

C990 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

1 2

C991 0.1U_0402_16V4Z

C991 0.1U_0402_16V4Z

1 2

C992 0.1U_0402_16V4Z

C992 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

1 2

C993 0.1U_0402_16V4Z

C993 0.1U_0402_16V4Z

1 2

C994 0.1U_0402_16V4Z

C994 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

1 2

C995 0.1U_0402_16V4Z

C995 0.1U_0402_16V4Z

1 2

C996 0.1U_0402_16V4Z

C996 0.1U_0402_16V4Z

1 2

C998 0.1U_0402_16V4Z

C998 0.1U_0402_16V4Z

1 2

C997 0.1U_0402_16V4Z

C997 0.1U_0402_16V4Z

1 2

C999 0.1U_0402_16V4Z

C999 0.1U_0402_16V4Z

1 2

C1000 0.1U_0402_16V4Z

C1000 0.1U_0402_16V4Z

1 2

C1002 0.1U_0402_16V4Z

C1002 0.1U_0402_16V4Z

1 2

C1001 0.1U_0402_16V4Z

C1001 0.1U_0402_16V4Z

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401728

401728

401728

Date: Sheet

Date: Sheet

Date: Sheet

+1.8V

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

1

A

A

A

of

of

of

849Monday, May 04, 2009

849Monday, May 04, 2009

849Monday, May 04, 2009

+1.8V

0.1U_0402_16V4Z

JDIMM1

JDIMM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA<5>
DDR_CS2_DIMMA#<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>
DDR_A_WE#<5>

DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

B B

A A

SB_CK_SDAT<9,20,25,31>

SB_CK_SCLK<9,20,25,31>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C1003

C1003

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_AS0A426-M2RN-7F

FOX_AS0A426-M2RN-7F

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

NC
DM2
VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7

A6
VDD

A4

A2

A0
VDD
BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO
SA1

GND

JAWD0 used

DIMM1 REV H:5.2mm (BOT)

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R834 10K_0402_5%R834 10K_0402_5%

1 2

R835 10K_0402_5%R835 10K_0402_5%

1 2

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

DDR_CKE1_DIMMA <5>

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_CS3_DIMMA# <5>

DDR_A_CLK2 <5>
DDR_A_CLK#2 <5>

0.1U_0402_16V4Z

C986

C986

1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

DDR_A_D[0..63]<5>
DDR_A_DM[0..7]<5>

DDR_A_DQS[0..7]<5>
DDR_A_MA[0..15]<5>

DDR_A_DQS#[0..7]<5>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

[e-mail]

4

3

2

1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

+3VS

Issued Date

Issued Date

Issued Date

DDR_B_D[0..63]<5>
DDR_B_DM[0..7]<5>

DDR_B_DQS[0..7]<5>
DDR_B_MA[0..15]<5>

DDR_B_DQS#[0..7]<5>

C1006

C1006

+DIMM_VREF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3

C1007

C1007

1

2

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

Compal Secret Data

Compal Secret Data

2007/5/18 2009/06/11

2007/5/18 2009/06/11

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+0.9V

RP32

DDR_CS0_DIMMB#
DDR_B_BS#1
DDR_B_MA2
DDR_B_MA0

DDR_B_MA6
DDR_B_MA4
DDR_B_MA11
DDR_B_MA7

DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_RAS#

DDR_B_MA14
DDR_B_MA15
DDR_CKE1_DIMMB

2

RP32

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP33

RP33

18
27
36
45

RP34

RP34

18
27
36
45

RP35

RP35

18
27
36
45

RP36

RP36

18
27
36
45

RP37

RP37

18
27
36
45

RP38

RP38

18
27
36
45

RP39

RP39

18
27
36
45

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401728

401728

401728

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C1005 0.1U_0402_16V4Z

C1005 0.1U_0402_16V4Z

1 2

C1004 0.1U_0402_16V4Z

C1004 0.1U_0402_16V4Z

12

C1009 0.1U_0402_16V4Z

C1009 0.1U_0402_16V4Z

1 2

<BOM Structure>

<BOM Structure>

C1008 0.1U_0402_16V4Z

C1008 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

12

C1011 0.1U_0402_16V4Z

C1011 0.1U_0402_16V4Z

1 2

<BOM Structure>

<BOM Structure>

C1010 0.1U_0402_16V4Z

C1010 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

12

C1013 0.1U_0402_16V4Z

C1013 0.1U_0402_16V4Z

1 2

<BOM Structure>

<BOM Structure>

C1012 0.1U_0402_16V4Z

C1012 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

12

C1014 0.1U_0402_16V4Z

C1014 0.1U_0402_16V4Z

1 2

C1015 0.1U_0402_16V4Z

C1015 0.1U_0402_16V4Z

12

C1016 0.1U_0402_16V4Z

C1016 0.1U_0402_16V4Z

1 2

C1017 0.1U_0402_16V4Z

C1017 0.1U_0402_16V4Z

12

C1018 0.1U_0402_16V4Z

C1018 0.1U_0402_16V4Z

1 2

C1019 0.1U_0402_16V4Z

C1019 0.1U_0402_16V4Z

12

C1020 0.1U_0402_16V4Z

C1020 0.1U_0402_16V4Z

1 2

C1021 0.1U_0402_16V4Z

C1021 0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

+1.8V

949Monday, May 04, 2009

949Monday, May 04, 2009

1

949Monday, May 04, 2009

+1.8V

JDIMM2

JDIMM2

1

VREF

3

DDR_B_D0
DDR_B_D1

D D

C C

DDR_CKE0_DIMMB<5>
DDR_CS2_DIMMB#<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>
DDR_B_WE#<5>

DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

B B

SB_CK_SDAT<8,20,25,31>

A A

SB_CK_SCLK<8,20,25,31>

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C1022

C1022

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

P-TWO_A5652C-A0G16

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

NC
DM2
VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7
A6

VDD

A4
A2

A0
VDD
BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC

VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO
SA1

KAV10 used

DIMM2 H:5.2mm (BOT)

5

4

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196

R836 10K_0402_5%R836 10K_0402_5%

198

R837 10K_0402_5%R837 10K_0402_5%

200

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

1 2
1 2

DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>

DDR_CKE1_DIMMB <5>

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_CS3_DIMMB# <5>

DDR_B_CLK2 <5>
DDR_B_CLK#2 <5>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

A

A

A

B

C

D

E

PCIE_GTX_C_MRX_P[0..15]<14>
PCIE_GTX_C_MRX_N[0..15]<14>

1 1

PCIE_PTX_C_IRX_P0<31>
PCIE_PTX_C_IRX_N0<31>

2 2

PCIE_PTX_C_IRX_P1<31>
PCIE_PTX_C_IRX_N1<31>
PCIE_PTX_C_IRX_P2<31>
PCIE_PTX_C_IRX_N2<31>

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

SB_RX0P<24>
SB_RX0N<24>
SB_RX1P<24>
SB_RX1N<24>
SB_RX2P<24>
SB_RX2N<24>
SB_RX3P<24>
SB_RX3N<24>

U3B

U3B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

RS780M_FCBGA528

PART 2 OF 6

PART 2 OF 6

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0

A5
B5

PCIE_MTX_GRX_P1

A4

PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1

B4

PCIE_MTX_GRX_P2

C3

PCIE_MTX_GRX_N2

B2

PCIE_MTX_GRX_P3

D1

PCIE_MTX_GRX_N3

D2

PCIE_MTX_GRX_P4

E2

PCIE_MTX_GRX_N4

E1

PCIE_MTX_GRX_P5

F4

PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5

F3

PCIE_MTX_GRX_P6

F1

PCIE_MTX_GRX_N6

F2

PCIE_MTX_GRX_P7

H4

PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7

H3

PCIE_MTX_GRX_P8

H1

PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8

H2

PCIE_MTX_GRX_P9

J2

PCIE_MTX_GRX_N9

J1

PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10

K4

PCIE_MTX_GRX_N10

K3

PCIE_MTX_GRX_P11

K1

PCIE_MTX_GRX_N11

K2

PCIE_MTX_GRX_P12

M4

PCIE_MTX_GRX_N12

M3

PCIE_MTX_GRX_P13

M1

PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13

M2

PCIE_MTX_GRX_P14

N2

PCIE_MTX_GRX_N14

N1

PCIE_MTX_GRX_P15

P1

PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15

P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5
AC8

AB8

R32 1.27K_0402_1%R32 1.27K_0402_1%
R267 2K_0402_1%R267 2K_0402_1%

RS780M Display Port Support (muxed on GFX)

DP0

3 3

4 4

DP1

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

C646 0.1U_0402_16V7K@C646 0.1U_0402_16V7K@

1 2

C648 0.1U_0402_16V7K@C648 0.1U_0402_16V7K@

1 2

C650 0.1U_0402_16V7K@C650 0.1U_0402_16V7K@

1 2

C652 0.1U_0402_16V7K@C652 0.1U_0402_16V7K@

1 2

C655 0.1U_0402_16V7K@C655 0.1U_0402_16V7K@

1 2

C657 0.1U_0402_16V7K@C657 0.1U_0402_16V7K@

1 2

C659 0.1U_0402_16V7K@C659 0.1U_0402_16V7K@

1 2

C641 0.1U_0402_16V7K@C641 0.1U_0402_16V7K@

1 2

C636 0.1U_0402_16V7KVGA@C636 0.1U_0402_16V7KVGA@

1 2

C635 0.1U_0402_16V7KVGA@C635 0.1U_0402_16V7KVGA@

1 2

C632 0.1U_0402_16V7KVGA@C632 0.1U_0402_16V7KVGA@

1 2

C630 0.1U_0402_16V7KVGA@C630 0.1U_0402_16V7KVGA@

1 2

C627 0.1U_0402_16V7KVGA@C627 0.1U_0402_16V7KVGA@

1 2

C623 0.1U_0402_16V7KVGA@C623 0.1U_0402_16V7KVGA@

1 2

C624 0.1U_0402_16V7KVGA@C624 0.1U_0402_16V7KVGA@

1 2

C619 0.1U_0402_16V7KVGA@C619 0.1U_0402_16V7KVGA@

1 2

C617 0.1U_0402_16V7KC617 0.1U_0402_16V7K

1 2

C618 0.1U_0402_16V7KC618 0.1U_0402_16V7K

1 2

C614 0.1U_0402_16V7KC614 0.1U_0402_16V7K

1 2

C613 0.1U_0402_16V7KC613 0.1U_0402_16V7K

1 2

C46 0.1U_0402_16V7K@C46 0.1U_0402_16V7K@

1 2

C42 0.1U_0402_16V7K@C42 0.1U_0402_16V7K@

1 2

C615 0.1U_0402_16V7KC615 0.1U_0402_16V7K

1 2

C609 0.1U_0402_16V7KC609 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C32 0.1U_0402_16V7KC32 0.1U_0402_16V7K

1 2

C610 0.1U_0402_16V7KC610 0.1U_0402_16V7K

1 2

C616 0.1U_0402_16V7KC616 0.1U_0402_16V7K

1 2

1 2
1 2

C647 0.1U_0402_16V7K@C647 0.1U_0402_16V7K@
C649 0.1U_0402_16V7K@C649 0.1U_0402_16V7K@
C651 0.1U_0402_16V7K@C651 0.1U_0402_16V7K@
C653 0.1U_0402_16V7K@C653 0.1U_0402_16V7K@
C654 0.1U_0402_16V7K@C654 0.1U_0402_16V7K@
C656 0.1U_0402_16V7K@C656 0.1U_0402_16V7K@
C658 0.1U_0402_16V7K@C658 0.1U_0402_16V7K@
C642 0.1U_0402_16V7K@C642 0.1U_0402_16V7K@
C638 0.1U_0402_16V7KVGA@C638 0.1U_0402_16V7KVGA@
C637 0.1U_0402_16V7KVGA@C637 0.1U_0402_16V7KVGA@
C634 0.1U_0402_16V7KVGA@C634 0.1U_0402_16V7KVGA@
C631 0.1U_0402_16V7KVGA@C631 0.1U_0402_16V7KVGA@
C629 0.1U_0402_16V7KVGA@C629 0.1U_0402_16V7KVGA@
C625 0.1U_0402_16V7KVGA@C625 0.1U_0402_16V7KVGA@
C620 0.1U_0402_16V7KVGA@C620 0.1U_0402_16V7KVGA@
C621 0.1U_0402_16V7KVGA@C621 0.1U_0402_16V7KVGA@

+1.1VS

PCIE_MTX_C_GRX_P[0..15] <14>
PCIE_MTX_C_GRX_N[0..15] <14>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCIE_ITX_C_PRX_P0 <31>
PCIE_ITX_C_PRX_N0 <31>
PCIE_ITX_C_PRX_P1 <31>
PCIE_ITX_C_PRX_N1 <31>
PCIE_ITX_C_PRX_P2 <31>
PCIE_ITX_C_PRX_N2 <31>

SB_TX0P <24>
SB_TX0N <24>
SB_TX1P <24>
SB_TX1N <24>
SB_TX2P <24>
SB_TX2N <24>
SB_TX3P <24>
SB_TX3N <24>

PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0
PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15

WLAN
GLAN

( Remove 3G Function )

WWAN

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>
H_CTLOP1<4>
H_CTLON1<4>

R56

R56

1 2

301_0402_1%~D

0718 Place within 1"
layout 1:2

301_0402_1%~D

PCIE_MTX_GRX_N[0..3]

PCIE_MTX_GRX_P[0..3]

For M92 S2-LP
disable PCIE GFX 0~7

H_CADOP[0..15]<4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9

H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CTLOP0
H_CTLON0
H_CTLOP1 H_CTLIP1
H_CTLON1

H_CADON[0..15]

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

PCIE_MTX_GRX_N[0..3] <22>
PCIE_MTX_GRX_P[0..3] <22>

U3A

U3A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M_FCBGA528

RS780M_FCBGA528

H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]

PART 1 OF 6

PART 1 OF 6

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

H_CADIP[0..15] <4>

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18
H24

H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25
P19

H_CTLIN1

R18
B24

B25

0718 Place within 1"
layout 1:2

301_0402_1%~D

301_0402_1%~D

SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA

H_CLKIP0 <4>
H_CLKIN0 <4>
H_CLKIP1 <4>
H_CLKIN1 <4>

H_CTLIP0 <4>

H_CTLIN0 <4>

H_CTLIP1 <4>

H_CTLIN1 <4>

R51

R51

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

10 49Monday, May 04, 2009

10 49Monday, May 04, 2009

10 49Monday, May 04, 2009

E

A

A

A

of

of

of

A

[e-mail]

For RS780M A13
RED: Connected to GND through two separate 140ohm 1% resistor

UMA@

UMA@

1 2

R45 140_0402_1%

R45 140_0402_1%

UMA@

UMA@

1 2

R49 150_0402_1%

R49 150_0402_1%

UMA@

UMA@

1 2

R50 150_0402_1%

1 1

+1.1VS

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+1.8VS

1 2

MBK2012221YZF 0805

2 2

3 3

4 4

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+1.8VS

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

CLK_NB_14.318M

12

R477

R477
100_0402_5%

100_0402_5%

@

@

1

C854

C854
100P_0402_25V8K

100P_0402_25V8K

2

@

@

+3VS

R295 4.7K_0402_5%R295 4.7K_0402_5%
R289 4.7K_0402_5%R289 4.7K_0402_5%

PLLVDD=65mA

L59

L59

L13

L13

L9

L9

L14

L14

ALLOW_LDTSTOP<24>

+NB_PLLVDD

1

C645

C645

C93

C93

1 2
1 2

1

2

2

PLLVDD18=20mA

+NB_HTPVDD+1.8VS

1

1

2

2

VDDA18HTPLL=20mA

+VDDA18HTPLL

1

1

C66

C66

2

2

VDDA18PCIEPLL=0.12A

+VDDA18PCIEPLL

1

1

C87

C87

2

2

+1.1VS

A

C663

C663
1U_0402_6.3V4Z

1U_0402_6.3V4Z

C84

C84
1U_0402_6.3V4Z

1U_0402_6.3V4Z

C72

C72
1U_0402_6.3V4Z

1U_0402_6.3V4Z

C86

C86
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1 2

R293

R293

4.7K_0402_5%

4.7K_0402_5%

GMCH_LCD_CLK
GMCH_LCD_DATA

Un-stuff for Tigris

R50 150_0402_1%

FBM-L11-201209-300LMA30T_0805

FBM-L11-201209-300LMA30T_0805

NB_PWRGD<25>

1 2

R290

R290

4.7K_0402_5%

4.7K_0402_5%

+1.8VS

+1.8VS

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

PLT_RST#<13,14,24,31,33>

+1.8VS

R283 300_0402_5%R283 300_0402_5%

R60

R60
300_0402_5%

300_0402_5%

1 2

R59 0_0402_5%R59 0_0402_5%

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

+1.8VS

1 2

1 2

B

+3VS

1 2

FBM-L11-201209-300LMA30T_0805

FBM-L11-201209-300LMA30T_0805

AVDDDI=20mA

L10

L10

1 2

FBM-L11-201209-300LMA30T_0805

FBM-L11-201209-300LMA30T_0805

AVDDQ=4mA

L8

L8

C61

C61

12

POWER_SEL<43>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+AVDDQ

1

2

GMCH_CRT_HSYNC<13,23>
GMCH_CRT_VSYNC<13,23>

GMCH_CRT_CLK<23>
GMCH_CRT_DATA<23>

1 2

R296 0_0402_5%R296 0_0402_5%

CLK_NB_14.318M<20>

CLK_NBGFX<20>
CLK_NBGFX#<20>

CLK_SBLINK_BCLK<20>
CLK_SBLINK_BCLK#<20>

GMCH_LCD_CLK<21>

GMCH_LCD_DATA<21>

+3VS

C74

C74

GMCH_CRT_R<23>
GMCH_CRT_G<23>
GMCH_CRT_B<23>

CLK_NBHT<20>
CLK_NBHT#<20>

POWER_SEL

HIGH 1.0V

1.1VLOW

Change as 1K_5% ohm
for Tigris

NB_ALLOW_LDTSTOP

B

AVDD=0.11A

L15

L15

1

2

+NB_PLLVDD
+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R288 10K_0402_5%

R288 10K_0402_5%

POWER_SEL

+AVDD1

+AVDD2

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_CRT_HSYNC
GMCH_CRT_VSYNC

R42 715_0402_1%R42 715_0402_1%

1 2

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

CLK_NB_14.318M

GMCH_LCD_CLK
GMCH_LCD_DATA

GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK_R2
GMCH_HDMI_CLK_R1
GMCH_HDMI_DATA_R1

DVT

@

@

12

AUX_CAL<13>

Strap pin

DVT

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

GMCH_CRT_CLK
GMCH_CRT_DATA

+NB_PLLVDD
+NB_HTPVDD

NB_RESET#

GMCH_HDMI_CLK<22>

GMCH_HDMI_DATA<22>

C

C94

C94

U3C

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

RS780M_FCBGA528

GMCH_HDMI_CLK
GMCH_HDMI_DATA

LDT_STOP#<6,24>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PART 3 OF 6

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)

TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

R491 0_0402_5%@R491 0_0402_5%@

1 2

R488 0_0402_5%UMA@R488 0_0402_5%UMA@

1 2
1 2

R489 0_0402_5%UMA@R489 0_0402_5%UMA@

1 2

R492 0_0402_5%@R492 0_0402_5%@

0_0402_5%

0_0402_5%

1 2

R280

R280

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

C

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

THERMALDIODE_P
THERMALDIODE_N

GMCH_HDMI_CLK_R2

GMCH_HDMI_CLK_R1
GMCH_HDMI_DATA_R1

GMCH_HDMI_DATA_R2

NB_LDTSTOP#

Compal Secret Data

Compal Secret Data

Compal Secret Data

HPD(NC)

TESTMODE

Deciphered Date

Deciphered Date

Deciphered Date

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

1.27K_0402_1%

1.27K_0402_1%

D9
D10

D12
AE8

AD8
D13

+VDDLTP18

+VDDLT18

12

R469

R469

@

@

DVT

1 2

R297 0_0402_5%R297 0_0402_5%

1 2

R279

R279

1.8K_0402_5%

1.8K_0402_5%

D

GMCH_TXOUT0+ <21>
GMCH_TXOUT0- <21>
GMCH_TXOUT1+ <21>
GMCH_TXOUT1- <21>
GMCH_TXOUT2+ <21>
GMCH_TXOUT2- <21>

GMCH_TZOUT0+ <21>
GMCH_TZOUT0- <21>
GMCH_TZOUT1+ <21>
GMCH_TZOUT1- <21>
GMCH_TZOUT2+ <21>
GMCH_TZOUT2- <21>

GMCH_TXCLK+ <21>
GMCH_TXCLK- <21>
GMCH_TZCLK+ <21>
GMCH_TZCLK- <21>

UMA@

UMA@

R294

R294

1 2

1.27K_0402_1%

1.27K_0402_1%

D

UMA_ENVDD
UMA_ENBKL
UMA_DPST

UMA@

UMA@

R29

R29

1 2

1.27K_0402_1%

1.27K_0402_1%

HDMI_DET <15,22>

SUS_STAT# <25>
SUS_STAT_R# <13>

UMA_ENVDD

NB_PWRGD

UMA_ENBKL

E

VDDLTP18=15mA

+VDDLTP18

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VDDLT18=0.3A

+VDDLT18

C90

C90

0.1U_0402_16V4Z

0.1U_0402_16V4Z

UMA_ENBKL <21>

C665

C665

1

1

2

2

1

1

2

2

L56

L56

1 2

MBC1608121YZF_0603

MBC1608121YZF_0603
C644

C644

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L12

L12

1 2

MBC1608121YZF_0603

MBC1608121YZF_0603

C95

C95

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.8VS

+1.8VS

AMD Vari bright function

UMA_DPST ENBKL

1 2

R758 0_0402_5%@R758 0_0402_5%@

Strap pin

R744 0_0402_5%R744 0_0402_5%

1 2

+3VS

C857 0.1U_0402_16V4ZC857 0.1U_0402_16V4Z

5

2

P

B

4

Y

1

A

G

U48

U48
NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

@

@

5

2

P

B

4

Y

1

A

G

U49

U49
NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

UMA@

UMA@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

E

UMA_ENVDD_R <21>

ENBKL <33>

11 49Monday, May 04, 2009

11 49Monday, May 04, 2009

11 49Monday, May 04, 2009

A

A

A

A

VDDHTRX+VDDHT=0.68A

0.1U_0402_16V4Z

L49

+1.1VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 1

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L4

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FOR Version A11 pop 1.35VS A12
use 1.2V_HT

2 2

L4

+1.8VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L49

L11

L11

12

VDDA18PCIE=0.7A

L5

L5

12

C45

C45

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z

12

1

C612

C612

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

1

C82

C82

C83

C83

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

VDDHTTX=0.68A

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C31

C31

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C47

C47

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.8VS

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C75

C75

1

2

C49

C49

C40

C40

C89

C89

1

1

C71

C71

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C85

C85

C91

C91

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C50

C50

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C51

C51

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.8VS

VDD18_MEM=25mA

1

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C62

C62

2

1

2

1

C54

C54

C52

C52

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C48

C48

C73

C73

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VDD18=10mA

1 2

R224 0_0402_5%SP@R224 0_0402_5%SP@

+VDDHT

+VDDHTRX

+VDDHTTX

1

2

+VDDA18PCIE

1

2

0_0402_5%

0_0402_5%

+1.8V_VDD_SP

12

R223

R223

VGA@

VGA@

B

1

2

U3E

U3E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

AE25

VDDHTTX_1

AD24

VDDHTTX_2

AC23

VDDHTTX_3

AB22

VDDHTTX_4

AA21

VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2

AE11

VDD18_MEM1(NC)

AD11

VDD18_MEM2(NC)

C92

C92

RS780M_FCBGA528

RS780M_FCBGA528

SP@

SP@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

PART 5/6

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C

VDDPCIE=1.1A

+VDDA11PCIE

DVT

C350.1U_0402_16V4Z C350.1U_0402_16V4Z

1

2

VDD_MEM=70mA

R407 0_0603_5%SP@R407 0_0603_5%SP@

R406 0_0603_5%VGA@R406 0_0603_5%VGA@

VDD33=60mA

C80

C80

0.1U_0402_16V4Z

0.1U_0402_16V4Z

L3

L3

1 2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

C30 10U_0603_6.3V6MC30 10U_0603_6.3V6M

1 2

C28 10U_0603_6.3V6MC28 10U_0603_6.3V6M

1 2

C29 4.7U_0805_10V4ZC29 4.7U_0805_10V4Z

1 2

C53 1U_0402_6.3V4ZC53 1U_0402_6.3V4Z

1 2

C79 1U_0402_6.3V4ZC79 1U_0402_6.3V4Z

1 2
1 2

C88 0.1U_0402_16V4ZC88 0.1U_0402_16V4Z

1 2

C57 0.1U_0402_16V4ZC57 0.1U_0402_16V4Z

VDDC=7.6A

1 2

L6 0_1206_5%@L6 0_1206_5%@

1 2

L7 0_1206_5%@L7 0_1206_5%@

C340.1U_0402_16V4Z C340.1U_0402_16V4Z

C430.1U_0402_16V4Z C430.1U_0402_16V4Z

C760.1U_0402_16V4Z C760.1U_0402_16V4Z

C690.1U_0402_16V4Z C690.1U_0402_16V4Z

1

2

C78

C78

C640.1U_0402_16V4Z C640.1U_0402_16V4Z

1

1

2

2

+1.8VS

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

2

C249 4.7U_0805_10V4ZSP@C249 4.7U_0805_10V4ZSP@
C248 0.1U_0402_16V4ZSP@C248 0.1U_0402_16V4ZSP@
C597 0.1U_0402_16V4ZSP@C597 0.1U_0402_16V4ZSP@
C598 0.1U_0402_16V4ZSP@C598 0.1U_0402_16V4ZSP@
C599 0.1U_0402_16V4ZSP@C599 0.1U_0402_16V4ZSP@

C600.1U_0402_16V4Z C600.1U_0402_16V4Z

1

1

2

2

12
12

1

2

D

U3F

U3F

A25

VSSAHT1

D23

VSSAHT2

+1.1VS

+NB_CORE+1.1VS

C27 330U_D2E_2.5VM_R9MUMA@+C27 330U_D2E_2.5VM_R9MUMA@

C810.1U_0402_16V4Z C810.1U_0402_16V4Z

C680.1U_0402_16V4Z C680.1U_0402_16V4Z

1

1

2

2

+3VS

1

C3610U_0603_6.3V6M C3610U_0603_6.3V6M

C4410U_0603_6.3V6M C4410U_0603_6.3V6M

1

1

+

2

2

2

12
12
12
12
12

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

RS780M_FCBGA528

PART 6/6

PART 6/6

GROUND

GROUND

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

E

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

12 49Monday, May 04, 2009

12 49Monday, May 04, 2009

12 49Monday, May 04, 2009

E

A

A

A

of

of

of

A

[e-mail]

B

C

D

E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)

U61

R117

R117

R120

R120

1 2

1 2

L2
L3

R2

P7

M2

P3
P8

P2
N7
N3
N8
N2
M7
M3
M8

K8

J8

K2

L8

K3

K7

L7

F3

B3

K9

F7

E8

B7

A8

J2

A2

E2

L1
R3
R7
R8

SP@

SP@

1K_0402_1%

1K_0402_1%

SP@

SP@

1K_0402_1%

1K_0402_1%

U61

BA0
BA1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK
CK

CKE

CS
WE
RAS
CAS
LDM

UDM

ODT

LDQS
LDQS

UDQS
UDQS

VREF
NC

NC
NC
NC
NC
NC

HY5PS561621AFP-25_FBGA84

HY5PS561621AFP-25_FBGA84

@

@

C628

C628

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD

VDDL

VSSDL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

1

SP@

SP@

VSS
VSS
VSS
VSS
VSS

C626

C626

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1 1

MEM_CLKN

R135

R135

SP@

SP@

100_0402_1%

100_0402_1%

MEM_CLKP

2 2

MEM_BA0
MEM_BA1

MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0

12

MEM_CKE

MEM_CS#
MEM_WE#
MEM_RAS#
MEM_CAS#
MEM_DM0

MEM_DM1

MEM_ODT

MEM_DQS_P0
MEM_DQS_N0

MEM_DQS_P1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

Support 8M x 16bit x 8 bank side port

03/16 SA000031O00 S IC D2 64M16/500 K4N1G164QE-HC20 FBGA84
03/16 SA00002UH00 S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84

3 3

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

C197

C197

C200

C200

1

2

SP@

SP@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

SP@

SP@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C195

SP@

SP@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

SP@ C195

SP@

R118 1K_0402_1%

R118 1K_0402_1%

+MEM_VREF +MEM_VREF1

1

C207

4 4

SP@ C207

SP@

2

SP@

SP@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

R119 1K_0402_1%

R119 1K_0402_1%

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

2

1

SP@

SP@

C201

C201

1U_0402_6.3V4Z

1U_0402_6.3V4Z

MEM_DQ12
MEM_DQ13
MEM_DQ9
MEM_DQ14
MEM_DQ15
MEM_DQ8
MEM_DQ10
MEM_DQ11
MEM_DQ5
MEM_DQ2
MEM_DQ6
MEM_DQ1
MEM_DQ0
MEM_DQ4
MEM_DQ3
MEM_DQ7

+1.8V_MEM_VDDQ

1

2

220 ohm @ 100MHz,2A

1

1

C208

C208

C206

C206

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SP@

SP@

SP@

SP@

L23

SP@ L23

SP@

FBMA-L11-160808-221LMT 0603

FBMA-L11-160808-221LMT 0603

C184

Layout Note: 50 mil for VSSDL

SP@ C184

SP@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.8VS+1.8V_MEM_VDDQ

1 2

L16 0_0805_5%SP@L16 0_0805_5%SP@

1

2

SP@

SP@

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.8V_MEM_VDDQ

12

+1.8V_MEM_VDDQ

R140 40.2_0402_1%SP@R140 40.2_0402_1%SP@
R136 40.2_0402_1%SP@R136 40.2_0402_1%SP@

12
12

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P
MEM_COMP_N

GMCH_CRT_VSYNC<11,23>

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

AUX_CAL<11>

RS780 DFT_GPIO1

SUS_STAT_R#<11> PLT_RST# <11,14,24,31,33>

RS780 use HSYNC to enable SIDE PORT

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

0. Enable (RS780)
1 : Disable(RS780)

GMCH_CRT_HSYNC<11,23>

U3D

U3D

PAR 4 OF 6

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)

MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)
IOPLLVSS(NC)

MEM_VREF(NC)

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14
AD16

AE17
AD17

W12

Y12
AD18
AB13
AB18

V14

V15

W14

AE12
AD12

RS780M_FCBGA528

RS780M_FCBGA528

+1.8VS=W/S=20/10mil For Memory PLL power
+1.1VS=W/S=20/10mil For Memory PLL power

12

R286 3K_0402_5%R286 3K_0402_5%

12

R287 3K_0402_5%@R287 3K_0402_5%@

1 2

R284 150_0402_1%@R284 150_0402_1%@

D29

D29
CH751H-40_SC76@

CH751H-40_SC76@

2 1

12

R299 3K_0402_5%@R299 3K_0402_5%@

RS780 use HSYNC to enable SIDE PORT

12
12

L22

L22

12

C185

C185

SP@

SP@

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

15mA

+1.1VS

1

2

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12MEM_A12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

26mA

+MEM_VREF1

R281 3K_0402_5%VGA@R281 3K_0402_5%VGA@
R282 3K_0402_5%SP@R282 3K_0402_5%SP@

FBMA-L11-160808-221LMT 0603

FBMA-L11-160808-221LMT 0603

1

2

+3VS

+3VS

+1.8VS

L21

L21

12

FBMA-L11-160808-221LMT 0603

FBMA-L11-160808-221LMT 0603

C183

C183

SP@

SP@

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

2008/10/06 2009/10/06

2008/10/06 2009/10/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

13 49Monday, May 04, 2009

13 49Monday, May 04, 2009

13 49Monday, May 04, 2009

E

A

A

A

5

4

3

2

1

PCIE_GTX_C_MRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_MTX_C_GRX_N[0..15]<10>

D D

U64A

U64A

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12

PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11

PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10

C C

PCIE LANE REVERSAL

B B

CLK_PCIE_VGA<20>
CLK_PCIE_VGA#<20>

PLT_RST#<11,13,24,31,33>

ESD

PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P0

CLK_PCIE_VGA
CLK_PCIE_VGA#

For Future ASIC Pin
N10 need pull down

10K_0402_5%@

10K_0402_5%@

R955

R955

12

C780 10P_0402_50V8J@C780 10P_0402_50V8J@

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

L9

NC#1

N9

NC#2

N10

12

NC_PWRGOOD

AL27

PERSTB

216-0728002 A11 M92-S2_FCBGA631

216-0728002 A11 M92-S2_FCBGA631

VGA@

VGA@

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCI EXPRESS INTERFACE

PCI EXPRESS INTERFACE

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

CALIBRATION

CALIBRATION

PCIE_CALRP
PCIE_CALRN

PEG_NRX_C_GTX_P15 PCIE_GTX_C_MRX_P15

AG31

AG29

PEG_NRX_C_GTX_P14 PCIE_GTX_C_MRX_P14

AF28

PEG_NRX_C_GTX_N13 PCIE_GTX_C_MRX_N13

AF27
AF26

AD27
AD26

PEG_NRX_C_GTX_N11

AC25
AB25

PEG_NRX_C_GTX_N10

Y23
Y24

PEG_NRX_C_GTX_N9

AB27

PEG_NRX_C_GTX_P9

AB26

PEG_NRX_C_GTX_N8

Y27

PEG_NRX_C_GTX_P8

Y26

PEG_NRX_C_GTX_N7

W24

PEG_NRX_C_GTX_P7

W23

PEG_NRX_C_GTX_N6

V27

PEG_NRX_C_GTX_P6

U26

PEG_NRX_C_GTX_N5

U24
U23

T26
T27

PEG_NRX_C_GTX_N3

T24
T23

PEG_NRX_C_GTX_N2

P27
P26

PEG_NRX_C_GTX_N1

P24
P23

M27
N26

R864 1.27K_0402_1%

R864 1.27K_0402_1%

Y22

1 2

R865 2K_0402_1%

R865 2K_0402_1%

AA22

1 2

PEG_NRX_C_GTX_N15 PCIE_GTX_C_MRX_N15

AH30

C1061 0.1U_0402_16V7K

C1061 0.1U_0402_16V7K

1 2

C1060 0.1U_0402_16V7K

C1060 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1063 0.1U_0402_16V7K

C1063 0.1U_0402_16V7K

1 2

C1062 0.1U_0402_16V7K

C1062 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1065 0.1U_0402_16V7K

C1065 0.1U_0402_16V7K

1 2

C1064 0.1U_0402_16V7K

C1064 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1067 0.1U_0402_16V7K

C1067 0.1U_0402_16V7K

1 2

C1066 0.1U_0402_16V7K

C1066 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1069 0.1U_0402_16V7K

C1069 0.1U_0402_16V7K

1 2

C1068 0.1U_0402_16V7K

C1068 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1071 0.1U_0402_16V7K

C1071 0.1U_0402_16V7K

1 2

C1070 0.1U_0402_16V7K

C1070 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1073 0.1U_0402_16V7K

C1073 0.1U_0402_16V7K

1 2

C1072 0.1U_0402_16V7K

C1072 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1075 0.1U_0402_16V7K

C1075 0.1U_0402_16V7K

1 2

C1074 0.1U_0402_16V7K

C1074 0.1U_0402_16V7K

1 2

VGA@

VGA@

VGA@

VGA@

C1077 0.1U_0402_16V7K

C1077 0.1U_0402_16V7K

1 2

C1076 0.1U_0402_16V7K

C1076 0.1U_0402_16V7K

1 2

@

@

@

@

C1079 0.1U_0402_16V7K

C1079 0.1U_0402_16V7K

1 2

C1078 0.1U_0402_16V7K

C1078 0.1U_0402_16V7K

1 2

@

@

@

@

C1081 0.1U_0402_16V7K

C1081 0.1U_0402_16V7K

1 2

C1080 0.1U_0402_16V7K

C1080 0.1U_0402_16V7K

1 2

@

@

@

@

C1083 0.1U_0402_16V7K

C1083 0.1U_0402_16V7K

1 2

C1082 0.1U_0402_16V7K

C1082 0.1U_0402_16V7K

1 2

@

@

@

@

C1085 0.1U_0402_16V7K

C1085 0.1U_0402_16V7K

1 2

C1084 0.1U_0402_16V7K

C1084 0.1U_0402_16V7K

1 2

@

@

@

@

C1087 0.1U_0402_16V7K

C1087 0.1U_0402_16V7K

1 2

C1086 0.1U_0402_16V7K

C1086 0.1U_0402_16V7K

1 2

@

@

@

@

C1089 0.1U_0402_16V7K

C1089 0.1U_0402_16V7K

1 2

C1088 0.1U_0402_16V7K

C1088 0.1U_0402_16V7K

1 2

@

@

@

@

C1091 0.1U_0402_16V7K

C1091 0.1U_0402_16V7K

1 2

C1090 0.1U_0402_16V7K

C1090 0.1U_0402_16V7K

1 2

@

@

@

@

VGA@

VGA@

VGA@

VGA@

+1.1VS

PCIE_GTX_C_MRX_N14PEG_NRX_C_GTX_N14

PCIE_GTX_C_MRX_P13PEG_NRX_C_GTX_P13

PCIE_GTX_C_MRX_N12PEG_NRX_C_GTX_N12
PCIE_GTX_C_MRX_P12PEG_NRX_C_GTX_P12

PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11PEG_NRX_C_GTX_P11

PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10PEG_NRX_C_GTX_P10

PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9

PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8

PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7

PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6

PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5PEG_NRX_C_GTX_P5

PCIE_GTX_C_MRX_N4PEG_NRX_C_GTX_N4
PCIE_GTX_C_MRX_P4PEG_NRX_C_GTX_P4

PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3PEG_NRX_C_GTX_P3

PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2PEG_NRX_C_GTX_P2

PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1PEG_NRX_C_GTX_P1

PCIE_GTX_C_MRX_N0PEG_NRX_C_GTX_N0
PCIE_GTX_C_MRX_P0PEG_NRX_C_GTX_P0

PCIE LANE REVERSAL

For M92 S2-LP
disable PCIE GFX 0~7

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/10/11 200810/11

2007/10/11 200810/11

2007/10/11 200810/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

14 49Monday, May 04, 2009

14 49Monday, May 04, 2009

14 49Monday, May 04, 2009

1

A

A

A

of

of

of

For M92-S2: DO NOT Install any Component

[e-mail]

in this Box.

+1.8VS

L125

L125

1 2

MCK1608471YZF 0603@

MCK1608471YZF 0603@

10U_0603_6.3V6M@

10U_0603_6.3V6M@

D D

+1.1VS

L128

L128

1 2

MCK1608471YZF 0603@

MCK1608471YZF 0603@

10U_0603_6.3V6M@

10U_0603_6.3V6M@

+3.3V_DELAY

R871 4.7K_0402_5%VGA@R871 4.7K_0402_5%VGA@

R873 4.7K_0402_5%VGA@R873 4.7K_0402_5%VGA@

R875

R875

C C

+VGA_CORE

12

@

@

R882

R882
10K_0402_5%

10K_0402_5%

BB_EN

Do not use Back Bais than
pull high to +VDDC

+3.3V_DELAY

12

@

@

GPIO23_CLKREQB

B B

27M_NSSC<20>

+3.3V_DELAY

12

R548

R548

5.1K_0402_1%@

5.1K_0402_1%@

TESTEN

12

R889

R889

5.1K_0402_1%

5.1K_0402_1%

VGA@

VGA@

A A

5

(1.8V@120mA +DPLL_PVDD)

1

C1251

C1251

2

(1.8V@120mA +DPLL_PVDD)

1

C1258

C1258

2

VGA_LCD_CLK

1 2

VGA_LCD_DATA

1 2

12

10K_0402_5%@

10K_0402_5%@

VGA_PWRSEL<47>

1U_0402_6.3V4Z@

1U_0402_6.3V4Z@

1

2

1U_0402_6.3V4Z@

1U_0402_6.3V4Z@

1

2

VGA_PWRSEL

GPU_GPIO0<19>
GPU_GPIO1<19>
GPU_GPIO2<19>

VGA_ENBKL<33>
SOUT_GPIO8<19>
GPU_GPIO9<19>

GPU_GPIO11<19>
GPU_GPIO12<19>
GPU_GPIO13<19>

27M_SSC<20>

THM_ALERT#<19>

C1250

C1250

C1260

C1260

0.1U_0402_10V6K@

0.1U_0402_10V6K@

0.1U_0402_10V6K@

0.1U_0402_10V6K@

+DPC_VDD18

+DPC_VDD10

10/24 Reference AMD REF136-1

+1.8VS

R883

R883
10K_0402_5%

10K_0402_5%

+1.8VS

VGA@

VGA@

+1.1VS

R887

R887

MCK1608471YZF 0603

MCK1608471YZF 0603

MCK1608471YZF 0603

MCK1608471YZF 0603

VGA@

VGA@

499_0402_1%

499_0402_1%

VGA@

VGA@

249_0402_1%

249_0402_1%

VGA@

VGA@

VGA@

VGA@

75_0402_1%

75_0402_1%

1 2

R888

R888

100_0402_5%

100_0402_5%

VGA@

VGA@

+1.8VS

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

(1.8V@20mA TSVDD)

L102

L102

1 2

10U_0603_6.3V6M

10U_0603_6.3V6M

VGA@

VGA@

(1.1V@300mA +DPLL_VDDC)

L103

L103

1 2

10U_0603_6.3V6M

10U_0603_6.3V6M

VGA@

VGA@

5

R884

R884

R886

R886

1 2

L109

L109

10U_0603_6.3V

10U_0603_6.3V

VGA@

VGA@

(1.8V@120mA +DPLL_PVDD)

VGA@

VGA@

1

C1092

C1092

2

VGA@

VGA@

1

C1095

C1095

2

1

2

1

2

BB_EN

12

12

VRAM_ID0<19>

C1252

C1252

VRAM_ID1<19>
VRAM_ID2<19>
VRAM_ID3<19>

C1259

C1259

LCD

VGA_LCD_CLK<21>
VGA_LCD_DATA<21>

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2

R877 0_0402_5%@R877 0_0402_5%@

1 2

R878 10K_0402_5%VGA@R878 10K_0402_5%VGA@

1 2

SOUT_GPIO8
GPU_GPIO9

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

VGA_PWRSEL

R879 0_0402_5%@R879 0_0402_5%@

1 2

R880 10K_0402_5%@ R880 10K_0402_5%@

1 2

R881 0_0402_5%@ R881 0_0402_5%@

1 2

TESTEN<17>

HDMI_DET<11,22>

VGA@

VGA@

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C1110

C1110

2

GPU_THERMAL_D+<19>
GPU_THERMAL_D-<19>

VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

12

1

C1114

C1114

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C1093

C1093

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C1096

C1096

2

R278 150_0402_1%@R278 150_0402_1%@

+DPC_VDD10

R957 0_0402_5%@R957 0_0402_5%@

1

C1115

C1115

2

+DPLL_PVDD

1

C1094

C1094

0.1U_0402_10V6K

0.1U_0402_10V6K

2

VGA@

VGA@

+DPLL_VDDC

1

C1097

C1097

0.1U_0402_10V6K

0.1U_0402_10V6K

2

VGA@

VGA@

1 2

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

1 2

GPIO23_CLKREQB

GPIO24_TRSTB

T5 PADT5 PAD
T6 PADT6 PAD
T7 PADT7 PAD
T8 PADT8 PAD

TESTEN

+DPLL_PVDD

+DPLL_VDDC

1.8V

27MCLK
XTALOUT

T9 PADT9 PAD

1

C1116

C1116

0.1U_0402_10V6K

0.1U_0402_10V6K

2

VGA@

VGA@

+DPC_VDD18

R_27M_SSC

GPU_CTF

GPU_GPIO21

4

U64B

U64B

MUTI GFX

MUTI GFX

AA1

DVPCNTL_MVP_0

Y4

DVPCNTL_MVP_1

AC7

DVPCNTL_0

Y2

DVPCNTL_1

U5

DVPCNTL_2

U1

DVPCLK

Y7

DVPDATA_0

V2

DVPDATA_1

Y8

DVPDATA_2

V4

DVPDATA_3

AB7

DVPDATA_4

W1

DVPDATA_5

AB8

DVPDATA_6

W3

DVPDATA_7

AB9

DVPDATA_8

W5

DVPDATA_9

AC6

DVPDATA_10

W6

DVPDATA_11

AD7

DVPDATA_12

AA3

DVPDATA_13

AC8

DVPDATA_14

AA5

DVPDATA_15

AE8

DVPDATA_16

AA6

DVPDATA_17

AE9

DVPDATA_18

AB4

DVPDATA_19

AD9

DVPDATA_20

AB2

DVPDATA_21

AC10

DVPDATA_22

AC5

DVPDATA_23

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

T11

GPIO_29_DRM_0

R11

GPIO_30_DRM_1

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

AF24

TESTEN

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AC16

VREFG

PLL/CLOCK

PLL/CLOCK

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

216-0728002 A11 M92-S2_FCBGA631

216-0728002 A11 M92-S2_FCBGA631

VGA@

VGA@

4

3

AF2

TXCAP_DPA3P

AF4

TXCAM_DPA3N

AG3

TX0P_DPA2P

AG5

TX0M_DPA2N

DPA

DPA

DPB

DPB

DAC1

DAC1

I2C

I2C

DAC2

DAC2

DDC/AUX

DDC/AUX

THERMAL

THERMAL

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

HSYNC
VSYNC

RSET

AVDD

AVSSQ
VDD1DI

VSS1DI

COMP

H2SYNC
V2SYNC

VDD2DI
VSS2DI

A2VDD
A2VDDQ
A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P

AUX1N

DDC2CLK

DDC2DATA

AUX2P

AUX2N

DDCAUX5P
DDCAUX5N

DDC6CLK

DDC6DATA

NC_DDCAUX7P
NC_DDCAUX7N

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

AM26

R

AK26

RB

AL25

G

AJ25

GB

AH24

B

AG25

BB

AH26
AJ27

AD22

1 2

VGA@

VGA@

+AVDD

AG24
AE22

+VDD1DI

AE23
AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13
AJ13

+VDD2DI

AD19
AC19

+A2VDD

AE20

+A2VDDQ

AE17
AE19

AG13

1 2

AE6
AE5

AD2
AD4

AC11
AC13

AD13
AD11

AB22

NC1

AC22

NC2

AE16
AD16

AC1
AC3

AD20
AC20

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R876

R876
499_0402_1%

499_0402_1%

T2PADT2PAD
T3PADT3PAD
T4PADT4PAD

R885

R885
715_0402_1%

715_0402_1%

VGA@

VGA@

T14PADT14PAD
T13PADT13PAD

3

HDMI_CLK+_VGA <22>
HDMI_CLK-_VGA <22>

HDMI_TX0+_VGA <22>
HDMI_TX0-_VGA <22>

HDMI_TX1+_VGA <22>
HDMI_TX1-_VGA <22>

HDMI_TX2+_VGA <22>
HDMI_TX2-_VGA <22>

VGA_CRT_R <23>

GND
IN

C1117

@C1117

@

CRT

Y6

@Y6

@

3

OUT

2

GND

VGA_CRT_R

R870 150_0402_1%

R870 150_0402_1%

VGA_CRT_G

R872 150_0402_1%

R872 150_0402_1%

VGA_CRT_B

R874 150_0402_1%

R874 150_0402_1%

HDMI

12

R896

@R896

@

1M_0402_5%

1M_0402_5%

1

22P_0402_50V8J

22P_0402_50V8J

2

Close to M92

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VGA_CRT_G <23>

VGA_CRT_B <23>

VGA_CRT_HSYNC <19,23>
VGA_CRT_VSYNC <19,23>

HSYNC_DAC2 <19>
VSYNC_DAC2 <19>

VGA_CRT_CLK <23>
VGA_CRT_DATA <23>

VGA_HDMI_SCLK <22>
VGA_HDMI_SDATA <22>

4
1

1

27MHz_16PF_6P27000126

27MHz_16PF_6P27000126

2

22P_0402_50V8J

22P_0402_50V8J

2007/10/11 200810/11

2007/10/11 200810/11

2007/10/11 200810/11

2

U64F

U64F

LVDS CONTROL

LVDS CONTROL

LVTMDP

LVTMDP

VGA@

VGA@

1 2

VGA@

VGA@

1 2

VGA@

VGA@

1 2

216-0728002 A11 M92-S2_FCBGA631

216-0728002 A11 M92-S2_FCBGA631

VGA@

VGA@

+1.8VS +AVDD

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

VGA@

VGA@

L104

L104

L106

L106

VGA@

VGA@

L107

L107

VGA@

VGA@

L108

L108

VGA@

VGA@

L105

L105

VGA@

VGA@

12

10U_0603_6.3V

10U_0603_6.3V

VGA@

VGA@

12

10U_0603_6.3V

10U_0603_6.3V

12

C1104

C1104

10U_0603_6.3V

10U_0603_6.3V

12

C1107

C1107

10U_0603_6.3V

10U_0603_6.3V

12

10U_0603_6.3V

10U_0603_6.3V

(1.8V@70mA AVDD)

VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C1098

C1098

2

(1.8V@45mA VDD1DI)

VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C1101

C1101

2

(1.8V@1mA A2VDDQ)

VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

2

(1.8V@40mA VDD2DI)

VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

2

(3.3V@65mA A2VDD)

1U_0402_6.3V4Z

VGA@

1U_0402_6.3V4Z

VGA@

1

C1111

C1111

2

DO NOT INSTALL for M93-S3

27MCLK

XTALOUT

C1118

@C1118

@

2

1

AB11

VARY_BL

AB12

DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

1

2

1

2

1

C1105

C1105

2

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

1

C1108

C1108

2

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

1

C1112

C1112

2

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24

TXOUT_U3P

AJ23

TXOUT_U3N

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19

TXOUT_L3P

AK18

TXOUT_L3N

1

C1100

C1100

C1099

C1099

2

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

+VDD1DI

1

C1103

C1103

C1102

C1102

2

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

+A2VDDQ

1

C1106

C1106

2

+VDD2DI

1

C1109

C1109

2

+A2VDD+3.3V_DELAY

1

C1113

C1113

2

GPIO24_TRSTB

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

SCHEMATICS,MB A5401

401728

401728

401728

VGA_TZCLK+
VGA_TZCLK-

VGA_TZOUT0+
VGA_TZOUT0-

VGA_TZOUT1+
VGA_TZOUT1-

VGA_TZOUT2+
VGA_TZOUT2-

+3.3V_DELAY

12

12

1

VGA_DPST <21>
VGA_ENVDD <21>

VGA_TZCLK+ <21>
VGA_TZCLK- <21>

VGA_TZOUT0+ <21>
VGA_TZOUT0- <21>

VGA_TZOUT1+ <21>
VGA_TZOUT1- <21>

VGA_TZOUT2+ <21>
VGA_TZOUT2- <21>

VGA_TXCLK+ <21>
VGA_TXCLK- <21>

VGA_TXOUT0+ <21>
VGA_TXOUT0- <21>

VGA_TXOUT1+ <21>
VGA_TXOUT1- <21>

VGA_TXOUT2+ <21>
VGA_TXOUT2- <21>

@

@

R890

R890
10K_0402_5%

10K_0402_5%

@

@

R895

R895
1K_0402_5%

1K_0402_5%

15 49Monday, May 04, 2009

15 49Monday, May 04, 2009

15 49Monday, May 04, 2009

of

of

of

A

A

A