How it Works
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aspire 5535,aspire 5235
Schematics
43 pgs613.96 Kb0

Acer aspire 5535,aspire 5235 Schematics

5
4
3
2
1
Project code: 91.4K901.001
Cathedral Peak 2A Block Diagram
PCB P/N : 48.4K901.001 REVISION : 08220- -1
DDR2
D D
667/800 MHz
8,9
DDR2
667/800 MHz
CLK GEN.
ICS9LPRS480BKLFT 71.09480.A03 RTM880N-796-VB-GRT 71.00880.A03
C C
INT MIC
30
MIC In
30
INT.SPKR
30
B B
A A
Line Out (No-SPDIF)
30
RJ11
8,9
3
Codec
ALC268
OP AMP
APA2057
MODEM
MDC Card
667/800MHz
667/800MHz
AZALIA
29
30
24
HDD SATA
ODD SATA
23
23
AMD Giffin CPU S1G2 (35W)
638-Pin uFCPGA638
OUT
4,5,6,7
16X16
IN
North Bridge
AMD RS780M
CPU I/F INTEGRATED GRAHPICS
LVDS, CRT I/F
11,12,13
A-Link 4X4
South Bridge
AMD SB700
USB 2.0/1.1 ports
(10/100/1000Mb)ETHERNET
High Definition Audio
ATA 66/100
ACPI 1.1 LPC I/F
PCI/PCI BRIDGE
17,18,19,20,21
SATA
Mini USB Blue Tooth
USB
24
G792
PCIex1
CardReader Realtek RTS5158E
USB 3 Port
Camera
24
22
LPC BUS
Touch Pad
CRT
15
LCD
14
LAN
Giga LAN
BCM5764
26
New card
28 28
KBC
Winbond
WPC773L
31 31
31
INT. KB
MS/MS Pro/xD /MMC/SD
5 in 1
TXFM RJ45
27 27
PWR SW TPS2231
Mini Card
Kedron
BIOS
MXIC MX25L1605
2525
Daughter Board
32
a/b/g/n
LPC
DEBUG CONN.
28
32
LAUNCH Board
08575
5
4
3
16
2
PCB STACKUP
TOP
VCC
S
S
GND
BOTTOM
SYSTEM DC/DC
TPS51125
INPUTS
DCBATOUT
OUTPUTS
5V_S5(6A) 3D3V_S5(6A)
SYSTEM DC/DC
RT8202 X 2
INPUTS OUTPUTS
DCBATOUT
1D1V_S0(7.5A) 1D2V_S0(4A)
SYSTEM DC/DC
RT8202
INPUTS OUTPUTS
DCBATOUT 1D8V_S3(11A)
RT9026PFP
5V_S5
RT9161
3D3V_S0 2D5V_S0
G957
3D3V_S0
G9161
3D3V_S5
CHARGER
DCBATOUT
CPU DC/DC
INPUTS
DCBATOUT
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
A3
A3
A3
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
DDR_VREF_S3
0D9V_S3
(200mA)
1D5V_S0 (1A)
1D2V_S5 (400mA)
MAX8731
OUTPUTSINPUTS CHG_PWR
18V 6.0A
UP+5V
5V 100mA
ISL6265HR
OUTPUTS
VCC_CORE_S0_0
0~1.55V 18A
VCC_CORE_S0_1
0~1.55V 18A
VDDNB
0~1.55V 18A
143Friday, August 22, 2008
143Friday, August 22, 2008
143Friday, August 22, 2008
37
38
39
39
40
40
40
41
36
-1
-1
-1
5
D D
C C
4
3
2
1
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
HISTORY
HISTORY
HISTORY
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
243Friday, August 22, 2008
243Friday, August 22, 2008
243Friday, August 22, 2008
-1
-1
-1
5
4
3
2
1
3D3V_S0 3D3V_CLK_VDD
R140
R140
1 2
0R0603-PAD
0R0603-PAD
12
C213
C213
12
C220
C220
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C217
C217
C219
C219
SCD1U10V2KX-4GP
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C216
C216
12
12
C209
C209
C193
C193
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
SCD1U10V2KX-4GP
12
C194
C194
12
C211
C211
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_S0
R139
R139
1 2
2R3J-GP
2R3J-GP
DY
DY
12
C190
C190
3D3V_48MPWR_S0
12
C197
C197 SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Due to PLL issue on current clock chip, the SBlink clock need to come from SRC clocks for RS740 and RS780. Future clock chip revision will fix this.
3000mA.80ohm
D D
3D3V_S0
R308
R308
1 2
0R0603-PAD
0R0603-PAD
1D1V_S0 1D1V_CLK_VDDIO
R154
R154
1 2
DY
DY
0R3-0-U-GP
0R3-0-U-GP
12
12
C230
C230
C232
C232
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C C
R144
R144
R146
R146
CLK_PCIE_SB17
CLK_PCIE_SB#17
CLK_PCIE_LAN26
CLK_PCIE_LAN#26
CLK_NB_GPPSB12
CLK_NB_GPPSB#12
CLK_PCIE_MINI128
CLK_PCIE_MINI1#28
CLK_PCIE_NEW28
CLK_PCIE_NEW#28
NB HT
DY
DY
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
10KR2J-3-GP
10KR2J-3-GP
1 2
R148
R148
R147
R147
3D3V_S0
1 2
1 2
DY
DY
R151
R151
10KR2J-3-GP
10KR2J-3-GP
DY
DY
R150
R150
10KR2J-3-GP
10KR2J-3-GP
5
CLK_NBHT_CLK12 CLK_NBHT_CLK#12
SB A-Link
LAN
NB A-Link
MINI
NEW
B B
DY
DY
10KR2J-3-GP
10KR2J-3-GP
A A
DY
DY
10KR2J-3-GP
10KR2J-3-GP
12
C192
C192
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_CLK_VDD
TP201TPAD14-GPTP201TPAD14-GP TP202TPAD14-GPTP202TPAD14-GP
1 2
1 2
12
12
C215
C215
C200
C200
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R295
R295
1 2
0R0603-PAD
0R0603-PAD
SC1U10V2KX-1GP
SC1U10V2KX-1GP
R365 0R0402-PADR365 0R0402-PAD
1 2
R366 0R0402-PADR366 0R0402-PAD
1 2
R367 0R0402-PADR367 0R0402-PAD
1 2
R368 0R0402-PADR368 0R0402-PAD
1 2
R369 0R0402-PADR369 0R0402-PAD
1 2
R370 0R0402-PADR370 0R0402-PAD
1 2
R371 0R0402-PADR371 0R0402-PAD
1 2
R372 0R0402-PADR372 0R0402-PAD
1 2
R373 0R0402-PADR373 0R0402-PAD
1 2
R374 0R0402-PADR374 0R0402-PAD
1 2
3D3V_S5
REF0 REF1 REF2
12
12
C218
C218
C210
C210
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C206
C206
CLK_PCIE_SB_1 CLK_PCIE_SB#_1
CLK_PCIE_LAN_1 CLK_PCIE_LAN#_1
CLK_NB_GPPSB_1 CLK_NB_GPPSB#_1
CLK_PCIE_MINI1_1 CLK_PCIE_MINI1#_1
CLK_PCIE_NEW_1 CLK_PCIE_NEW#_1
CLK_SRC0T_LPRS CLK_SRC0C_LPRS
R375 0R0402-PADR375 0R0402-PAD
1 2
R376 0R0402-PADR376 0R0402-PAD
1 2
3D3V_S0
RN29
RN29
8 7 6
SRN10KJ-6-GP
SRN10KJ-6-GP
SEL_27 REF2
SEL_SATA REF1
SEL_HTT66 REF0
CPU_CLK(200MHz)
3D3V_CLK_VDD
1D1V_CLK_VDDIO
VDD_REF
3D3V_48MPWR_S0
CLK_NBHT_CLK_1 CLK_NBHT_CLK#_1
PD#
1
PCI_REQ#5
2 3
RUNPWROK_D
45
27MHz non-spreading singled clock on pin 5
1
and 27MHz spread clock on pin 6 100MHz differential spreading SRC clock
*
0
100MHz non-spreading differential SATA clock
1
100MHz differential spreading SRC clock
*0
66MHz 3.3V single ended HTT clock
1 0 * 100MHz differential HTT clock
4
26 25
48 47
16 17 11
35 34
40
4 55 56 63
PD#
51
22 21 20 19 15 14 13 12
9
8 41
6
5
37 36 32 31
54 53
PCI_REQ#5 17
RUNPWROK_D 34
U13
U13
VDDATIG VDDATIG_IO
VDDCPU VDDCPU_IO
VDDSRC VDDSRC_IO VDDSRC_IO
VDDSB_SRC VDDSB_SRC_IO
VDDSATA VDD VDDHTT VDDREF VDD48
PD#
SRC0T_LPRS SRC0C_LPRS SRC1T_LPRS SRC1C_LPRS SRC2T_LPRS SRC2C_LPRS SRC3T_LPRS SRC3C_LPRS SRC4T_LPRS SRC4C_LPRS SRC6T/SATAT_LPRS42GNDSATA SRC6C/SATAC_LPRS SRC7T_LPRS/27MHZ_SS SRC7C_LPRS/27MHZ_NS
SB_SRC0T_LPRS SB_SRC0C_LPRS SB_SRC1T_LPRS SB_SRC1C_LPRS
HTT0T_LPRS/66M HTT0C_LPRS/66M
ICS9LPRS480BKLFT-GP
ICS9LPRS480BKLFT-GP
71.09480.A03
71.09480.A03 2nd = 71.00880.A03
2nd = 71.00880.A03
SMBCLK SMBDAT
ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS
CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#
CPUKG0T_LPRS CPUKG0C_LPRS
48MHZ_0
REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27
GNDATIG
GNDHTT GNDREF GNDCPU
GND48
GNDSRC GNDSRC
GNDSB_SRC
REF0
GND
GND
X1 X2
61
GEN_XTAL_OUT
62
2 3
30 29 28 27
23 45 44 39 38
50 49
CLK_48
64
REF0
59
REF1
58
REF2
57
43 24 7 52 60 46 1
10 18
33 65
GEN_XTAL_IN
CLK_SMBCLK CLK_SMBDAT
TP207 TPAD14-GPTP207 TPAD14-GP TP208 TPAD14-GPTP208 TPAD14-GP
CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#
CPU_CLK_1 CPU_CLK#_1
150R2F-1-GP
150R2F-1-GP
75R2F-2-GP
75R2F-2-GP
OSC_14M_NB
1.1V 158R/90.9RRS780M
3
1 2
10MR2J-L-GP
10MR2J-L-GP
CL=20pF±0.2pF
GAP-CLOSE
GAP-CLOSE GAP-CLOSE
GAP-CLOSE
TP128 TPAD14-GPTP128 TPAD14-GP TP135 TPAD14-GPTP135 TPAD14-GP TP132 TPAD14-GPTP132 TPAD14-GP TP136 TPAD14-GPTP136 TPAD14-GP TP133 TPAD14-GPTP133 TPAD14-GP
R377 0R0402-PADR377 0R0402-PAD R378 0R0402-PADR378 0R0402-PAD
1 2 3
R145
R145
12
12
R149
R149
R141
R141
DY
DY
2ND = 82.30005.951
2ND = 82.30005.951
G45
G45 G44
G44
12 12
CLK_NB_GFX 12
CLK_NB_GFX# 12
1 2 1 2
RN22
RN22
4
SRN33J-5-GP-U
SRN33J-5-GP-U
CLK_NB_14M 12
X-14D31818M-35GP
X-14D31818M-35GP
82.30005.891
82.30005.891
SMBC0_SB 8,9,18
SMBD0_SB 8,9,18
DY
DY
SB
C201
C201 SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
1 2
X4
X4
12
C198
C198
1 2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SB
CLKREQ# Internal pull Low
CPU_CLK 6 CPU_CLK# 6
CLK48_USB 18
EC68
EC68
SC22P50V2JN-4GP
SC22P50V2JN-4GP
CLK48_5158E 25
12
12
EC69
EC69
DY
DY
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SA
NB CLOCK INPUT TABLE
NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF 100M DIFF
* RS780 can be used as clock buffer to output two PCIE referecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode.
2
Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose.
RS740 RX780 RS780
66M SE(SINGLE END)
NC
14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V) NC NC vref
100M DIFF NC 100M DIFF
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
100M DIFF 100M DIFF
100M DIFF 100M DIFF
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
CLKGEN_ICS9LPRS480
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
100M DIFF 100M DIFF
100M DIFF(IN/OUT)*
NC or 100M DIFF OUTPUT
343Friday, August 22, 2008
343Friday, August 22, 2008
343Friday, August 22, 2008
1
of
-1
-1
-1
5
D D
1D2V_S0
Place close to socket
12
C434
C434
C417
C417
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
C C
B B
12
12
C416
C416
C413
C413
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
DY
DY
4
3
2
1
1.5Amp
12
C409
C409
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
DY
DY
12
12
C425
C425
SC180P50V2JN-1GP
SC180P50V2JN-1GP
HT_NB_CPU_CAD_H011 HT_NB_CPU_CAD_L011 HT_NB_CPU_CAD_H111 HT_NB_CPU_CAD_L111 HT_NB_CPU_CAD_H211 HT_NB_CPU_CAD_L211 HT_NB_CPU_CAD_H311 HT_NB_CPU_CAD_L311 HT_NB_CPU_CAD_H411 HT_NB_CPU_CAD_L411 HT_NB_CPU_CAD_H511 HT_NB_CPU_CAD_L511 HT_NB_CPU_CAD_H611 HT_NB_CPU_CAD_L611 HT_NB_CPU_CAD_H711 HT_NB_CPU_CAD_L711 HT_NB_CPU_CAD_H811 HT_NB_CPU_CAD_L811 HT_NB_CPU_CAD_H911 HT_NB_CPU_CAD_L911 HT_NB_CPU_CAD_H1011 HT_NB_CPU_CAD_L1011 HT_NB_CPU_CAD_H1111 HT_NB_CPU_CAD_L1111 HT_NB_CPU_CAD_H1211 HT_NB_CPU_CAD_L1211 HT_NB_CPU_CAD_H1311 HT_NB_CPU_CAD_L1311 HT_NB_CPU_CAD_H1411 HT_NB_CPU_CAD_L1411 HT_NB_CPU_CAD_H1511 HT_NB_CPU_CAD_L1511
HT_NB_CPU_CLK_H011 HT_NB_CPU_CLK_L011 HT_NB_CPU_CLK_H111 HT_NB_CPU_CLK_L111
HT_NB_CPU_CTL_H011 HT_NB_CPU_CTL_L011 HT_NB_CPU_CTL_H111 HT_NB_CPU_CTL_L111
12
C445
C445
SC180P50V2JN-1GP
SC180P50V2JN-1GP
DY
DY
DY
DY
U42A
U42A
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
62.10055.111
62.10055.111
2ND = 62.10055.251
2ND = 62.10055.251
HT LINK
HT LINK
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
HT_CPU_NB_CAD_H0 11 HT_CPU_NB_CAD_L0 11 HT_CPU_NB_CAD_H1 11 HT_CPU_NB_CAD_L1 11 HT_CPU_NB_CAD_H2 11 HT_CPU_NB_CAD_L2 11 HT_CPU_NB_CAD_H3 11 HT_CPU_NB_CAD_L3 11 HT_CPU_NB_CAD_H4 11 HT_CPU_NB_CAD_L4 11 HT_CPU_NB_CAD_H5 11 HT_CPU_NB_CAD_L5 11 HT_CPU_NB_CAD_H6 11 HT_CPU_NB_CAD_L6 11 HT_CPU_NB_CAD_H7 11 HT_CPU_NB_CAD_L7 11 HT_CPU_NB_CAD_H8 11 HT_CPU_NB_CAD_L8 11 HT_CPU_NB_CAD_H9 11 HT_CPU_NB_CAD_L9 11 HT_CPU_NB_CAD_H10 11 HT_CPU_NB_CAD_L10 11 HT_CPU_NB_CAD_H11 11 HT_CPU_NB_CAD_L11 11 HT_CPU_NB_CAD_H12 11 HT_CPU_NB_CAD_L12 11 HT_CPU_NB_CAD_H13 11 HT_CPU_NB_CAD_L13 11 HT_CPU_NB_CAD_H14 11 HT_CPU_NB_CAD_L14 11 HT_CPU_NB_CAD_H15 11 HT_CPU_NB_CAD_L15 11
HT_CPU_NB_CLK_H0 11 HT_CPU_NB_CLK_L0 11 HT_CPU_NB_CLK_H1 11 HT_CPU_NB_CLK_L1 11
HT_CPU_NB_CTL_H0 11 HT_CPU_NB_CTL_L0 11 HT_CPU_NB_CTL_H1 11 HT_CPU_NB_CTL_L1 11
SKT-BGA638H176
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
of
443Friday, August 22, 2008
443Friday, August 22, 2008
443Friday, August 22, 2008
-1
-1
-1
5
Place near to CPU
D D
C175
C175
1D8V_S3
C C
B B
4.7u x 4 0.22u X 2 180P x 6
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
MEM_MA0_ODT08,10 MEM_MA0_ODT18,10
MEM_MA0_CS#08,10 MEM_MA0_CS#18,10
MEM_MA_CKE08,10 MEM_MA_CKE18,10
MEM_MA_CLK0_P8 MEM_MA_CLK0_N8 MEM_MA_CLK1_P8 MEM_MA_CLK1_N8
MEM_MA_ADD08,10 MEM_MA_ADD18,10 MEM_MA_ADD28,10 MEM_MA_ADD38,10 MEM_MA_ADD48,10 MEM_MA_ADD58,10 MEM_MA_ADD68,10 MEM_MA_ADD78,10 MEM_MA_ADD88,10 MEM_MA_ADD98,10 MEM_MA_ADD108,10 MEM_MA_ADD118,10 MEM_MA_ADD128,10 MEM_MA_ADD138,10 MEM_MA_ADD148,10 MEM_MA_ADD158,10
MEM_MA_BANK08,10 MEM_MA_BANK18,10 MEM_MA_BANK28,10
MEM_MA_RAS#8,10 MEM_MA_CAS#8,10 MEM_MA_WE#8,10
12
C169
C169
DY
DY
R273
R273 39D2R2F-L-GP
39D2R2F-L-GP
R263
R263 39D2R2F-L-GP
39D2R2F-L-GP
12
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
DY
DY
1 2 1 2
C165
C165
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
TP119TP119
12
12
C154
C154
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
MEMZP MEMZN
MEM_RSVD_M1
1
C156
C156
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
0D9V_S3
12
C155
C155
DY
DY
AD10
AF10
AE10
AA16
12
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
DY
DY
U42B
U42B
D10
VTT1
C10
VTT2
B10
VTT3 VTT4
MEMZP MEMZN
H16
RSVD_M1
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7 MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
12
C150
C150
C160
C160
SC180P50V2JN-1GP
SC180P50V2JN-1GP
750 mA
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
12
SC180P50V2JN-1GP
SC180P50V2JN-1GP
VTT5 VTT6 VTT7 VTT8 VTT9
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
C157
C157
4
12
12
12
C153
C153
C161
C161
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C158
C158
12
SC180P50V2JN-1GP
SC180P50V2JN-1GP
DY
DY
CLOSE TO CPU
W10 AC10 AB10 AA10 A10
Y10 W17 B18 W26
W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
VTT_SENSE
MEM_RSVD_M2
MEM_MB0_ODT0 9,10 MEM_MB0_ODT1 9,10
MEM_MB0_CS#0 9,10 MEM_MB0_CS#1 9,10
MEM_MB_CKE0 9,10 MEM_MB_CKE1 9,10
MEM_MB_CLK0_P 9 MEM_MB_CLK0_N 9 MEM_MB_CLK1_P 9 MEM_MB_CLK1_N 9
MEM_MB_ADD0 9,10 MEM_MB_ADD1 9,10 MEM_MB_ADD2 9,10 MEM_MB_ADD3 9,10 MEM_MB_ADD4 9,10 MEM_MB_ADD5 9,10 MEM_MB_ADD6 9,10 MEM_MB_ADD7 9,10 MEM_MB_ADD8 9,10 MEM_MB_ADD9 9,10 MEM_MB_ADD10 9,10 MEM_MB_ADD11 9,10 MEM_MB_ADD12 9,10 MEM_MB_ADD13 9,10 MEM_MB_ADD14 9,10 MEM_MB_ADD15 9,10
MEM_MB_BANK0 9,10 MEM_MB_BANK1 9,10 MEM_MB_BANK2 9,10
MEM_MB_RAS# 9,10 MEM_MB_CAS# 9,10 MEM_MB_WE# 9,10
1
1
TP83 TPAD14-GPTP83 TPAD14-GP
TP120TP120
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VREF_DDR_CLAW
C186
C186
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
3
MEM_MA_DATA08 MEM_MA_DATA18 MEM_MA_DATA28 MEM_MA_DATA38 MEM_MA_DATA48 MEM_MA_DATA58 MEM_MA_DATA68 MEM_MA_DATA78 MEM_MA_DATA88 MEM_MA_DATA98 MEM_MA_DATA108 MEM_MA_DATA118 MEM_MA_DATA128 MEM_MA_DATA138 MEM_MA_DATA148 MEM_MA_DATA158 MEM_MA_DATA168 MEM_MA_DATA178 MEM_MA_DATA188 MEM_MA_DATA198 MEM_MA_DATA208 MEM_MA_DATA218 MEM_MA_DATA228 MEM_MA_DATA238 MEM_MA_DATA248 MEM_MA_DATA258 MEM_MA_DATA268 MEM_MA_DATA278 MEM_MA_DATA288 MEM_MA_DATA298 MEM_MA_DATA308 MEM_MA_DATA318
1D8V_S3
12
C189
C189
RN21
RN21
1
4
2 3
SRN1KJ-7-GP
C183
C183
12
SRN1KJ-7-GP
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
MEM_MA_DATA328 MEM_MA_DATA338 MEM_MA_DATA348 MEM_MA_DATA358 MEM_MA_DATA368 MEM_MA_DATA378 MEM_MA_DATA388 MEM_MA_DATA398 MEM_MA_DATA408 MEM_MA_DATA418 MEM_MA_DATA428 MEM_MA_DATA438 MEM_MA_DATA448 MEM_MA_DATA458 MEM_MA_DATA468 MEM_MA_DATA478 MEM_MA_DATA488 MEM_MA_DATA498 MEM_MA_DATA508 MEM_MA_DATA518 MEM_MA_DATA528 MEM_MA_DATA538 MEM_MA_DATA548 MEM_MA_DATA558 MEM_MA_DATA568 MEM_MA_DATA578 MEM_MA_DATA588 MEM_MA_DATA598 MEM_MA_DATA608 MEM_MA_DATA618 MEM_MA_DATA628 MEM_MA_DATA638
MEM_MA_DM08 MEM_MA_DM18 MEM_MA_DM28 MEM_MA_DM38 MEM_MA_DM48 MEM_MA_DM58 MEM_MA_DM68 MEM_MA_DM78
MEM_MA_DQS0_P8 MEM_MA_DQS0_N8 MEM_MA_DQS1_P8 MEM_MA_DQS1_N8 MEM_MA_DQS2_P8 MEM_MA_DQS2_N8 MEM_MA_DQS3_P8 MEM_MA_DQS3_N8 MEM_MA_DQS4_P8 MEM_MA_DQS4_N8 MEM_MA_DQS5_P8 MEM_MA_DQS5_N8 MEM_MA_DQS6_P8 MEM_MA_DQS6_N8 MEM_MA_DQS7_P8 MEM_MA_DQS7_N8
2
U42C
U42C
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22
Y24 AB24 AB22 AA21
W22 W21
Y22 AA22
Y20 AA20 AA18 AB18 AB21 AD21 AD19
Y18 AD17
W16 W14
Y14
Y17 AB17 AB15 AD15 AB13 AD13
Y12
W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24
AC24
Y19
AB16
Y13 G13
H13 G16 G15 C22 C21 G22
G21 AD23 AC23 AB19 AB20
Y15
W15 W12 W13
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
MEM:DATA
MEM:DATA
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8
MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11
A12 B16 A22 E25 AB26 AE22 AC16 AD12
C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
1
MEM_MB_DATA0 9 MEM_MB_DATA1 9 MEM_MB_DATA2 9 MEM_MB_DATA3 9 MEM_MB_DATA4 9 MEM_MB_DATA5 9 MEM_MB_DATA6 9 MEM_MB_DATA7 9 MEM_MB_DATA8 9 MEM_MB_DATA9 9 MEM_MB_DATA10 9 MEM_MB_DATA11 9 MEM_MB_DATA12 9 MEM_MB_DATA13 9 MEM_MB_DATA14 9 MEM_MB_DATA15 9 MEM_MB_DATA16 9 MEM_MB_DATA17 9 MEM_MB_DATA18 9 MEM_MB_DATA19 9 MEM_MB_DATA20 9 MEM_MB_DATA21 9 MEM_MB_DATA22 9 MEM_MB_DATA23 9 MEM_MB_DATA24 9 MEM_MB_DATA25 9 MEM_MB_DATA26 9 MEM_MB_DATA27 9 MEM_MB_DATA28 9 MEM_MB_DATA29 9 MEM_MB_DATA30 9 MEM_MB_DATA31 9 MEM_MB_DATA32 9 MEM_MB_DATA33 9 MEM_MB_DATA34 9 MEM_MB_DATA35 9 MEM_MB_DATA36 9 MEM_MB_DATA37 9 MEM_MB_DATA38 9 MEM_MB_DATA39 9 MEM_MB_DATA40 9 MEM_MB_DATA41 9 MEM_MB_DATA42 9 MEM_MB_DATA43 9 MEM_MB_DATA44 9 MEM_MB_DATA45 9 MEM_MB_DATA46 9 MEM_MB_DATA47 9 MEM_MB_DATA48 9 MEM_MB_DATA49 9 MEM_MB_DATA50 9 MEM_MB_DATA51 9 MEM_MB_DATA52 9 MEM_MB_DATA53 9 MEM_MB_DATA54 9 MEM_MB_DATA55 9 MEM_MB_DATA56 9 MEM_MB_DATA57 9 MEM_MB_DATA58 9 MEM_MB_DATA59 9 MEM_MB_DATA60 9 MEM_MB_DATA61 9 MEM_MB_DATA62 9 MEM_MB_DATA63 9
MEM_MB_DM0 9 MEM_MB_DM1 9 MEM_MB_DM2 9 MEM_MB_DM3 9 MEM_MB_DM4 9 MEM_MB_DM5 9 MEM_MB_DM6 9 MEM_MB_DM7 9
MEM_MB_DQS0_P 9 MEM_MB_DQS0_N 9 MEM_MB_DQS1_P 9 MEM_MB_DQS1_N 9 MEM_MB_DQS2_P 9 MEM_MB_DQS2_N 9 MEM_MB_DQS3_P 9 MEM_MB_DQS3_N 9 MEM_MB_DQS4_P 9 MEM_MB_DQS4_N 9 MEM_MB_DQS5_P 9 MEM_MB_DQS5_N 9 MEM_MB_DQS6_P 9 MEM_MB_DQS6_N 9 MEM_MB_DQS7_P 9 MEM_MB_DQS7_N 9
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
CPU_DDR_(2/4)
CPU_DDR_(2/4)
CPU_DDR_(2/4)
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
of
543Friday, August 22, 2008
543Friday, August 22, 2008
543Friday, August 22, 2008
-1
-1
-1
5
4
3
2
1
1D8V_S0
678
RN15
RN15 SRN300J-1-GP
SRN300J-1-GP
123
4 5
R256
R256
CPU_PWRGD_SVID_REG36
1 2
1 2
R265 0R0402-PADR265 0R0402-PAD
1 2
R91 0R0402-PADR91 0R0402-PAD
1 2
R253 0R0402-PADR253 0R0402-PAD
D D
C C
B B
CPU_LDT_RST#17,43
CPU_PWRGD17,43
CPU_LDT_STOP#17
ALLOW_LDTSTOP12,17
SA
A A
5
0R0402-PAD
0R0402-PAD
10KR2J-3-GP
10KR2J-3-GP
2ND = 84.03904.H11
2ND = 84.03904.H11
1 2
DY
DY
C366
C366 SC100P50V2JN-3GP
SC100P50V2JN-3GP
LDT_RST#_CPU 12
LDT_PWROK
LDT_STP#_CPU 12
CPU_LDT_REQ#_CPU
1D8V_S3
3D3V_S0
12
DY
R277
R277
DY
DY
DY
Q18
Q18
CBE
MMBT3904-3-GP
MMBT3904-3-GP
84.03904.T11
84.03904.T11
1 2
R275 0R2J-2-GPR275 0R2J-2-GP
12
R270
R270 2K2R2J-2-GP
2K2R2J-2-GP
LDT_PWROK_G
DY
DY
LDT_PWROK
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Near CPU PIN
LDT_PWROKCPU_PWRGD_SVID_REG
4
IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491
R69
R69
1 2
0R0603-PAD
0R0603-PAD
12
C125
C125
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
Cloce To CPU
CPU_CLK3 CPU_CLK#3
For HDT DBG
-1
12
C482
C482
DY
DY
LDT_RST#_CPU
HDT_RST#
1 2
C501 SC3900P50V2KX-2GPC501 SC3900P50V2KX-2GP
1 2
C500 SC3900P50V2KX-2GPC500 SC3900P50V2KX-2GP
1 2
R258
R258 0R0402-PAD
0R0402-PAD
1D2V_S0
TP84TP84
300R2J-4-GP
300R2J-4-GP
CPU_TEST21 CPU_TEST21
1
TP178TP178
R88
R88
300R2J-4-GP
300R2J-4-GP
1 2
2K2R2J-2-GP
2K2R2J-2-GP
THERMTRIP#
R77 44D2R2F-GPR77 44D2R2F-GP R71 44D2R2F-GPR71 44D2R2F-GP
R248
R248
R269
R269
E
CPU exceeds to 125
2D5V_VDDA_S02D5V_S0
12
12
C143
C143
C132
C132
1 2 1 2
CPU_VDD0_RUN_FB_H36 CPU_VDD0_RUN_FB_L36
CPU_VDD1_RUN_FB_H36 CPU_VDD1_RUN_FB_L36
MMBT3904-3-GP
MMBT3904-3-GP
84.03904.T11
84.03904.T11
SC3300P50V2KX-1GP
SC3300P50V2KX-1GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
1 2
R284 169R2F-GPR284 169R2F-GP
LDT_PWROK LDT_STP#_CPU CPU_LDT_REQ#_CPU
TP172TPAD14-GPTP172TPAD14-GP TP173TPAD14-GPTP173TPAD14-GP TP174TPAD14-GPTP174TPAD14-GP
TP175TP175 TP93TP93
TP90TP90 TP81TP81
TP80TP80
TP179TP179
1
TP182TP182 TP85TP85 TP183TP183
1 2
0R0402-PAD
0R0402-PAD
1 2
LDT_PWROK
12
C489
C489 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1D8V_SUS_Q2
B
Q19
Q19
C
2ND = 84.03904.H11
2ND = 84.03904.H11
℃
LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.
12
12
C117
C117
C137
C137
DY
DY
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
R242
R242
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
CLKCPU_IN
CLKCPU#_IN
F10
CPU_SIC
1
CPU_SID
1
CPU_ALERT#
1
CPU_HTREF0 CPU_HTREF1
CPU_TEST23
1
CPU_TEST18
1
CPU_TEST19
1
CPU_TEST25_H
1
CPU_TEST25_L
1
CPU_TEST20
1
CPU_TEST24 CPU_TEST22
1
CPU_TEST12
1
CPU_TEST27
1
CPU_TEST9
KBC_THERMTRIP# 22,31
3
AE6
AB6 G10
AA9 AC9 AD9
AD7
AB8 AE7
AE8 AC8
AA6
AF4 AF5
AF9
H10
AF7
AF8
U42D
U42D
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK LDTSTOP_L
C6
LDTREQ_L SIC
SID ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H VDD1_FB_L
DBRDY TMS TCK TRST_L TDI
TEST23 TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L TEST21
TEST20 TEST24 TEST22 TEST12 TEST27
C2
TEST9 TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
THERMTRIP_L
PROCHOT_L
MEMHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
KEY1 KEY2
SVC SVD
THERMDC THERMDA
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
1D8V_S3
4
RN62
RN62 SRN1KJ-7-GP
M11 W18
A6 A4
THERMTRIP#
AF6
PROCHOT#
AC7
CPU_MEMHOT#
AA8
internal pull high 300 ohm
W7 W8
1 2
DY
DY
C145
C145 SC100P50V2JN-3GP
SC100P50V2JN-3GP
CPU_VDDIO_SUS_FB_H
W9
CPU_VDDIO_SUS_FB_L
Y9 H6
G6
CPU_DBREQ#
E10
CPU_TDO
AE9
CPU_TEST28_H
J7
CPU_TEST28_L
H8
CPU_TEST17
D7
CPU_TEST16
E7
CPU_TEST15
F7
CPU_TEST14
C7 C3
K8 C4
CPU_TEST29H
C9
CPU_TEST29L
C8
H18 H19 AA7 D5 C5
SRN1KJ-7-GP
1
2 3
CPU_SVC 36 CPU_SVD 36
H_THERMDC 22 H_THERMDA 22
1 1
CPU_VDDNB_RUN_FB_H 36 CPU_VDDNB_RUN_FB_L 36
LAYOUT: Route FBCLKOUT_H/L differentially impedance 80
1
TP79TP79
1
TP89TP89
1
TP74TP74
1
TP75TP75
1
TP72TP72
1
TP76TP76
TP73TP73
1
TP82TP82
1
2
1D8V_S3
678
RN14
RN14 SRN300J-1-GP
SRN300J-1-GP
123
4 5
CPU_DBREQ#
R241
R241
1 2
0R0402-PAD
0R0402-PAD
TP87TP87 TP88TP88
HDT Connectors
1D8V_S3
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
CPU_Control&Debug_(3/4)
CPU_Control&Debug_(3/4)
CPU_Control&Debug_(3/4)
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
The Processor has reached a preset maximum operating temperature. 100 I=Active HTC O=FAN
PROCHOT#_SB 17
HDT1
HDT1
1
2
DY
DY
3
4
5
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
SMC-CONN26A-FP
HDT_RST#
SMC-CONN26A-FP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 26
of
643Friday, August 22, 2008
643Friday, August 22, 2008
643Friday, August 22, 2008
℃
-1
-1
-1
5
U42F
U42F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
D D
C C
B B
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
VCC_CORE_S0_0
Bottom Side Decoupling Bottom Side Decoupling
C149
C149
C173
C173
1D8V_S3
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDNB
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C114
C114
12
C146
C146
C168
C168
12
12
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3A for VDDNB
C196
C196
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3A for VDDIO
Bottom Side Decoupling
C208
C208
C212
C212
C185
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C185
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
4
36A for VDD0&VDD1
U42E
U42E
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
C170
C170
C176
C176
12
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C174
C174
C159
C159
12
12
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
C204
C204
12
DY
DY
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C191
C191
C187
C187
12
12
DY
DY
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C180
C180
12
3
VCC_CORE_S0_1
C147
C147
C118
C118
12
12
DY
DY
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C144
C144
12
Place near to CPU
C203
C203
C181
C195
C195
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
C181
12
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
C133
C133
12
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
C179
C179
12
C151
C151
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C162
C162
C164
C164
12
12
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3A for VDDIO
C184
C184
C182
C182
C199
12
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
C199
12
12
DY
DY
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D8V_S3
C207
C207
C205
C205
12
12
DY
DY
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
C188
C188
12
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CPU_Power_(4/4)
CPU_Power_(4/4)
CPU_Power_(4/4)
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
743Friday, August 22, 2008
743Friday, August 22, 2008
743Friday, August 22, 2008
of
of
of
-1
-1
-1
5
D D
MEM_MA_DATA05 MEM_MA_DATA15 MEM_MA_DATA25 MEM_MA_DATA35 MEM_MA_DATA45 MEM_MA_DATA55 MEM_MA_DATA65 MEM_MA_DATA75 MEM_MA_DATA85 MEM_MA_DATA95 MEM_MA_DATA105 MEM_MA_DATA115 MEM_MA_DATA125 MEM_MA_DATA135 MEM_MA_DATA145 MEM_MA_DATA155 MEM_MA_DATA165 MEM_MA_DATA175 MEM_MA_DATA185 MEM_MA_DATA195 MEM_MA_DATA205 MEM_MA_DATA215
C261
C261
MEM_MA_DATA225 MEM_MA_DATA235 MEM_MA_DATA245 MEM_MA_DATA255 MEM_MA_DATA265 MEM_MA_DATA275 MEM_MA_DATA285 MEM_MA_DATA295 MEM_MA_DATA305 MEM_MA_DATA315 MEM_MA_DATA325 MEM_MA_DATA335 MEM_MA_DATA345 MEM_MA_DATA355 MEM_MA_DATA365 MEM_MA_DATA375 MEM_MA_DATA385 MEM_MA_DATA395 MEM_MA_DATA405 MEM_MA_DATA415 MEM_MA_DATA425 MEM_MA_DATA435 MEM_MA_DATA445 MEM_MA_DATA455 MEM_MA_DATA465 MEM_MA_DATA475 MEM_MA_DATA485 MEM_MA_DATA495 MEM_MA_DATA505 MEM_MA_DATA515 MEM_MA_DATA525 MEM_MA_DATA535 MEM_MA_DATA545 MEM_MA_DATA555 MEM_MA_DATA565 MEM_MA_DATA575 MEM_MA_DATA585 MEM_MA_DATA595 MEM_MA_DATA605 MEM_MA_DATA615 MEM_MA_DATA625 MEM_MA_DATA635
MEM_MA_DQS0_N5 MEM_MA_DQS1_N5 MEM_MA_DQS2_N5 MEM_MA_DQS3_N5 MEM_MA_DQS4_N5 MEM_MA_DQS5_N5 MEM_MA_DQS6_N5 MEM_MA_DQS7_N5
MEM_MA_DQS0_P5 MEM_MA_DQS1_P5 MEM_MA_DQS2_P5 MEM_MA_DQS3_P5 MEM_MA_DQS4_P5 MEM_MA_DQS5_P5 MEM_MA_DQS6_P5 MEM_MA_DQS7_P5
C C
B B
A A
5
VREF_DDR_MEM
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
4
MEM_MA_ADD05,10 MEM_MA_ADD15,10 MEM_MA_ADD25,10 MEM_MA_ADD35,10 MEM_MA_ADD45,10 MEM_MA_ADD55,10 MEM_MA_ADD65,10 MEM_MA_ADD75,10 MEM_MA_ADD85,10 MEM_MA_ADD95,10 MEM_MA_ADD105,10 MEM_MA_ADD115,10 MEM_MA_ADD125,10 MEM_MA_ADD135,10 MEM_MA_ADD145,10 MEM_MA_ADD155,10
MEM_MA_BANK25,10 MEM_MA_BANK05,10 MEM_MA_BANK15,10
MEM_MA0_ODT05,10 MEM_MA0_ODT15,10
C256
C256
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
4
12
Place C2.2uF and 0.1uF < 500mils from DDR connector
DIMM1
DIMM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
DDR2-200P-22-GP-U2
DDR2-200P-22-GP-U2
62.10017.A61
62.10017.A61
2ND = 62.10017.A51
2ND = 62.10017.A51
HI 9.2mm
3
108
RAS#
109
WE#
113
CAS#
110
CS0#
115
CS1#
79
CKE0
80
CKE1
30
CK0
32
CK0#
164
CK1
166
CK1#
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
195
SDA
197
SCL
199
VDDSPD
198
SA0
200
SA1
50
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NORMAL TYPE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS GND MH2
69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201 MH2
(A0)
1D8V_S3
3
MEM_MA_RAS# 5,10 MEM_MA_WE# 5,10 MEM_MA_CAS# 5,10
MEM_MA0_CS#0 5,10 MEM_MA0_CS#1 5,10
MEM_MA_CKE0 5,10 MEM_MA_CKE1 5,10
MEM_MA_CLK0_P 5 MEM_MA_CLK0_N 5
MEM_MA_CLK1_P 5 MEM_MA_CLK1_N 5
MEM_MA_DM0 5 MEM_MA_DM1 5 MEM_MA_DM2 5 MEM_MA_DM3 5 MEM_MA_DM4 5 MEM_MA_DM5 5 MEM_MA_DM6 5 MEM_MA_DM7 5
SMBD0_SB 3,9,18
SMBC0_SB 3,9,18
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
1D8V_S3
C253
C253
12
12
DDR_VREF
RN67
RN67
1 2 3
SRN1KJ-7-GP
SRN1KJ-7-GP
LAYOUT: Locate close to DIMM
3D3V_S0
12
12
C254
C254 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
MEM_MA_CLK0_P
C241
C241 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
MEM_MA_CLK0_N MEM_MA_CLK1_P
C240
C240
SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
MEM_MA_CLK1_N
VREF_DDR_MEM
12
C533
C533
4
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C539
C539
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
12
C257
C257 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
DDR_SO-DIMM SKT_1
DDR_SO-DIMM SKT_1
DDR_SO-DIMM SKT_1
Taipei Hsien 221, Taiwan, R.O.C.
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
843Friday, August 22, 2008
843Friday, August 22, 2008
843Friday, August 22, 2008
1
of
of
of
-1
-1
-1
5
MEM_MB_ADD05,10 MEM_MB_ADD15,10 MEM_MB_ADD25,10 MEM_MB_ADD35,10 MEM_MB_ADD45,10 MEM_MB_ADD55,10 MEM_MB_ADD65,10 MEM_MB_ADD75,10 MEM_MB_ADD85,10
MEM_MB_ADD95,10 MEM_MB_ADD105,10 MEM_MB_ADD115,10
D D
C C
B B
A A
5
VREF_DDR_MEM
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
MEM_MB_ADD125,10 MEM_MB_ADD135,10 MEM_MB_ADD145,10 MEM_MB_ADD155,10
MEM_MB_BANK25,10 MEM_MB_BANK05,10 MEM_MB_BANK15,10
MEM_MB_DATA05 MEM_MB_DATA15 MEM_MB_DATA25 MEM_MB_DATA35 MEM_MB_DATA45 SMBD0_SB 3,8,18 MEM_MB_DATA55 MEM_MB_DATA65 MEM_MB_DATA75 MEM_MB_DATA85
MEM_MB_DATA95 MEM_MB_DATA105 MEM_MB_DATA115 MEM_MB_DATA125 MEM_MB_DATA135 MEM_MB_DATA145 MEM_MB_DATA155 MEM_MB_DATA165 MEM_MB_DATA175 MEM_MB_DATA185 MEM_MB_DATA195 MEM_MB_DATA205 MEM_MB_DATA215 MEM_MB_DATA225 MEM_MB_DATA235 MEM_MB_DATA245 MEM_MB_DATA255 MEM_MB_DATA265 MEM_MB_DATA275 MEM_MB_DATA285 MEM_MB_DATA295 MEM_MB_DATA305 MEM_MB_DATA315 MEM_MB_DATA325 MEM_MB_DATA335 MEM_MB_DATA345 MEM_MB_DATA355 MEM_MB_DATA365 MEM_MB_DATA375 MEM_MB_DATA385 MEM_MB_DATA395 MEM_MB_DATA405 MEM_MB_DATA415 MEM_MB_DATA425 MEM_MB_DATA435 MEM_MB_DATA445 MEM_MB_DATA455 MEM_MB_DATA465 MEM_MB_DATA475 MEM_MB_DATA485 MEM_MB_DATA495 MEM_MB_DATA505 MEM_MB_DATA515 MEM_MB_DATA525 MEM_MB_DATA535 MEM_MB_DATA545 MEM_MB_DATA555 MEM_MB_DATA565 MEM_MB_DATA575 MEM_MB_DATA585 MEM_MB_DATA595 MEM_MB_DATA605 MEM_MB_DATA615 MEM_MB_DATA625 MEM_MB_DATA635
MEM_MB_DQS0_N5 MEM_MB_DQS1_N5 MEM_MB_DQS2_N5 MEM_MB_DQS3_N5 MEM_MB_DQS4_N5 MEM_MB_DQS5_N5 MEM_MB_DQS6_N5 MEM_MB_DQS7_N5
MEM_MB_DQS0_P5 MEM_MB_DQS1_P5 MEM_MB_DQS2_P5 MEM_MB_DQS3_P5 MEM_MB_DQS4_P5 MEM_MB_DQS5_P5 MEM_MB_DQS6_P5 MEM_MB_DQS7_P5
MEM_MB0_ODT05,10 MEM_MB0_ODT15,10
C536
C536
4
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C532
C532
Place C2.2uF and 0.1uF < 500mils from DDR connector
4
DIMM2
DIMM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
SKT-SODIMM20020U3GP
SKT-SODIMM20020U3GP
62.10017.661
62.10017.661
2ND = 62.10017.A41
2ND = 62.10017.A41
LOW 5.2 mm
3
108
RAS#
109
WE#
113
CAS#
110
CS0#
115
CS1#
79
CKE0
80
CKE1
30
CK0
32
CK0#
164
CK1
166
CK1#
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
195
SDA
197
SCL
199
VDDSPD
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
REVERSE TYPE
GND
SA0 SA1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
MH2
198 200
50 69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201 MH2
DIMM2_SA1
R157 10KR2J-3-GPR157 10KR2J-3-GP
1D8V_S3
3
1 2
(A2)
MEM_MB_RAS# 5,10 MEM_MB_WE# 5,10 MEM_MB_CAS# 5,10
MEM_MB0_CS#0 5,10 MEM_MB0_CS#1 5,10
MEM_MB_CKE0 5,10 MEM_MB_CKE1 5,10
MEM_MB_CLK0_P 5 MEM_MB_CLK0_N 5
MEM_MB_CLK1_P 5 MEM_MB_CLK1_N 5
MEM_MB_DM0 5 MEM_MB_DM1 5 MEM_MB_DM2 5 MEM_MB_DM3 5 MEM_MB_DM4 5 MEM_MB_DM5 5 MEM_MB_DM6 5 MEM_MB_DM7 5
SMBC0_SB 3,8,18
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
3D3V_S0
C527
C527
MEM_MB_CLK0_P
12
C266
C266 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
MEM_MB_CLK0_N MEM_MB_CLK1_P
12
C265
C265 SC1D5P50V2CN-1GP
SC1D5P50V2CN-1GP
MEM_MB_CLK1_N
2
12
12
DY
DY
C530
C530 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
DDR_SO-DIMM SKT_2
DDR_SO-DIMM SKT_2
DDR_SO-DIMM SKT_2
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
of
of
943Friday, August 22, 2008
943Friday, August 22, 2008
943Friday, August 22, 2008
1
-1
-1
-1
5
4
3
2
1
Decoupling Capacitor
0D9V_S3
12
12
C273
C273
SCD1U16V2ZY-2GP
D D
PARALLEL TERMINATION
SCD1U16V2ZY-2GP
Put decap near power(0.9V) and pull-up resistor
C243
C243
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C260
C260
C259
C259
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C242
C242
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C269
C269
12
C244
C244
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C272
C272
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
C224
C224
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY
DY
12
C228
C228
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
C233
C233
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
12
C221
C221
C258
C258
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
Put decap near power(0.9V) and pull-up resistor
0D9V_S30D9V_S3
RN40
RN35
RN35
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN33
RN33
1
8
2
7
3
6
4 5
SRN47J-4-GP
SRN47J-4-GP
RN36
RN36
1
8
2
7
3
6
4 5
SRN47J-4-GP
C C
B B
SRN47J-4-GP
RN32
RN32
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN34
RN34
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN38
RN38
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN37
RN37
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
8 7 6
8 7 6
8 7 6
8 7 6
MEM_MA0_ODT1 5,8 MEM_MA0_CS#1 5,8 MEM_MA_WE# 5,8 MEM_MA_CAS# 5,8
MEM_MA_ADD5 5,8 MEM_MA_ADD6 5,8 MEM_MA_ADD8 5,8 MEM_MA_CKE1 5,8
MEM_MA_ADD4 5,8 MEM_MA_ADD2 5,8
MEM_MA_BANK1 5,8
MEM_MA_ADD0 5,8
MEM_MA_ADD12 5,8
MEM_MA_ADD9 5,8
MEM_MA_BANK2 5,8
MEM_MA_CKE0 5,8
MEM_MA_BANK0 5,8
MEM_MA_ADD10 5,8 MEM_MA_ADD3 5,8 MEM_MA_ADD1 5,8
MEM_MA_ADD15 5,8
MEM_MA_ADD14 5,8 MEM_MA_ADD7 5,8
MEM_MA_ADD11 5,8
MEM_MA0_CS#0 5,8 MEM_MA_RAS# 5,8
MEM_MA0_ODT0 5,8
MEM_MA_ADD13 5,8
RN40
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN45
RN45
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN46
RN46
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN39
RN39
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN44
RN44
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
RN41
RN41
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP RN42
RN42
1 2 3 4 5
SRN47J-4-GP
SRN47J-4-GP
8 7 6
8 7 6
8 7 6
8 7 6
8 7 6
8 7 6
8 7 6
MEM_MB_ADD4 5,9 MEM_MB_ADD11 5,9 MEM_MB_ADD5 5,9 MEM_MB_ADD8 5,9
MEM_MB_ADD6 5,9 MEM_MB_ADD2 5,9 MEM_MB_ADD0 5,9 MEM_MB_BANK1 5,9
MEM_MB_RAS# 5,9 MEM_MB0_CS#0 5,9 MEM_MB0_ODT0 5,9 MEM_MB_ADD13 5,9
MEM_MB_ADD9 5,9 MEM_MB_ADD12 5,9 MEM_MB_BANK2 5,9 MEM_MB_CKE0 5,9
MEM_MB_CKE1 5,9 MEM_MB_ADD15 5,9 MEM_MB_ADD14 5,9 MEM_MB_ADD7 5,9
MEM_MB_BANK0 5,9 MEM_MB_ADD10 5,9 MEM_MB_ADD1 5,9 MEM_MB_ADD3 5,9
MEM_MB0_CS#1 5,9 MEM_MB0_ODT1 5,9 MEM_MB_CAS# 5,9 MEM_MB_WE# 5,9
Place these Caps near DM1
1D8V_S3
12
12
Place these Caps near DM2
12
Place these Caps near PARALLEL TERMINATION
0D9V_S3
12
C246
C246
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C574
C574
C237
C237
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1D8V_S3
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C268
C268
C577
C577
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C528
C528
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C227
C227
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C578
C578
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C529
C529
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
C250
C250
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
12
C575
C575
C573
C573
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C235
C235
C531
C531
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
12
12
C229
C229
C248
C248
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
12
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C262
C262
C238
C238
C263
C263
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
DY
DY
12
C249
C249
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3
12
C236
C236
C239
C239
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3
1D8V_S3
C223
C223
SCD1U16V2ZY-2GP
12
C245
C245
SCD1U16V2ZY-2GP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
Do not share the Term resistor between the DDR addess and Control Signals.
12
12
DY
DY
A A
5
4
3
C274
C274
C226
C226
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
12
12
12
C252
C252
C270
C270
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C271
C271
12
C222
C222
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
2
12
12
C247
C247
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C251
C251
C225
C225
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
DDR_DAMPING & TERMINATION
DDR_DAMPING & TERMINATION
DDR_DAMPING & TERMINATION
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
10 43Friday, August 22, 2008
10 43Friday, August 22, 2008
10 43Friday, August 22, 2008
1
-1
-1
of
of
of
-1
5
HT_CPU_NB_CAD_H04 HT_CPU_NB_CAD_L04 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H24 HT_CPU_NB_CAD_L24 HT_CPU_NB_CAD_H34 HT_CPU_NB_CAD_L34 HT_CPU_NB_CAD_H44 HT_CPU_NB_CAD_L44 HT_CPU_NB_CAD_H54
D D
C C
B B
MINICARD MINICARD NEW CARD
A A
A-LINK
5
HT_CPU_NB_CAD_L54 HT_CPU_NB_CAD_H64 HT_CPU_NB_CAD_L64 HT_CPU_NB_CAD_H74 HT_CPU_NB_CAD_L74
HT_CPU_NB_CAD_H84 HT_CPU_NB_CAD_L84 HT_CPU_NB_CAD_H94 HT_CPU_NB_CAD_L94 HT_CPU_NB_CAD_H104 HT_CPU_NB_CAD_L104 HT_CPU_NB_CAD_H114 HT_CPU_NB_CAD_L114 HT_CPU_NB_CAD_H124 HT_CPU_NB_CAD_L124 HT_CPU_NB_CAD_H134 HT_CPU_NB_CAD_L134 HT_CPU_NB_CAD_H144 HT_CPU_NB_CAD_L144 HT_CPU_NB_CAD_H154 HT_CPU_NB_CAD_L154
HT_CPU_NB_CLK_H04 HT_CPU_NB_CLK_L04 HT_CPU_NB_CLK_H14 HT_CPU_NB_CLK_L14
HT_CPU_NB_CTL_H04 HT_CPU_NB_CTL_L04 HT_CPU_NB_CTL_H14 HT_CPU_NB_CTL_L14
1 2
Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24
LAN
ALINK_NBRX_SBTX_P017 ALINK_NBRX_SBTX_N017 ALINK_NBRX_SBTX_P117 ALINK_NBRX_SBTX_N117 ALINK_NBRX_SBTX_P217 ALINK_NBRX_SBTX_N217 ALINK_NBRX_SBTX_P317 ALINK_NBRX_SBTX_N317
R216
R216 301R2F-GP
301R2F-GP
PCIE_RXP126 PCIE_RXN126 PCIE_RXP228 PCIE_RXN228 PCIE_RXP528 PCIE_RXN528
TP16TPAD14-GPTP16TPAD14-GP TP15TPAD14-GPTP15TPAD14-GP
4
U31A
U31A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCALP HT_TXCALP HT_RXCALN
GPP_RX5P GPP_RX5N
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780M-GP-U2
RS780M-GP-U2
U31B
U31B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M-GP-U2
RS780M-GP-U2
4
PART 1 OF 6
PART 1 OF 6
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_TXCALP
HT_TXCALN
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
PCE_CALRP
PCE_CALRN
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22
F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18
H24 H25 L21 L20
M24 M25 P19 R18
B24 B25
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5
AC8 AB8
3
HT_TXCALN
TXP1 TXN1 TXP2 TXN2 TXP5 TXN5
GPP_TX5P GPP_TX5N
ALINK_NBTX_SBRX_P0 ALINK_NBTX_SBRX_N0 ALINK_NBTX_SBRX_P1 ALINK_NBTX_SBRX_N1 ALINK_NBTX_SBRX_P2 ALINK_NBTX_SBRX_N2 ALINK_NBTX_SBRX_P3 ALINK_NBTX_SBRX_N3
PCE_PCAL PCE_NCAL
Place < 100mils from pin AC8 and AB8
3
HT_NB_CPU_CAD_H0 4 HT_NB_CPU_CAD_L0 4 HT_NB_CPU_CAD_H1 4 HT_NB_CPU_CAD_L1 4 HT_NB_CPU_CAD_H2 4 HT_NB_CPU_CAD_L2 4 HT_NB_CPU_CAD_H3 4 HT_NB_CPU_CAD_L3 4 HT_NB_CPU_CAD_H4 4 HT_NB_CPU_CAD_L4 4 HT_NB_CPU_CAD_H5 4 HT_NB_CPU_CAD_L5 4 HT_NB_CPU_CAD_H6 4 HT_NB_CPU_CAD_L6 4 HT_NB_CPU_CAD_H7 4 HT_NB_CPU_CAD_L7 4
HT_NB_CPU_CAD_H8 4 HT_NB_CPU_CAD_L8 4 HT_NB_CPU_CAD_H9 4 HT_NB_CPU_CAD_L9 4 HT_NB_CPU_CAD_H10 4 HT_NB_CPU_CAD_L10 4 HT_NB_CPU_CAD_H11 4 HT_NB_CPU_CAD_L11 4 HT_NB_CPU_CAD_H12 4 HT_NB_CPU_CAD_L12 4 HT_NB_CPU_CAD_H13 4 HT_NB_CPU_CAD_L13 4 HT_NB_CPU_CAD_H14 4 HT_NB_CPU_CAD_L14 4 HT_NB_CPU_CAD_H15 4 HT_NB_CPU_CAD_L15 4
HT_NB_CPU_CLK_H0 4 HT_NB_CPU_CLK_L0 4 HT_NB_CPU_CLK_H1 4 HT_NB_CPU_CLK_L1 4
HT_NB_CPU_CTL_H0 4 HT_NB_CPU_CTL_L0 4 HT_NB_CPU_CTL_H1 4 HT_NB_CPU_CTL_L1 4
1 2
C342 SCD1U10V2KX-4GPC342 SCD1U10V2KX-4GP
1 2
C341 SCD1U10V2KX-4GPC341 SCD1U10V2KX-4GP
1 2
C345 SCD1U10V2KX-4GPC345 SCD1U10V2KX-4GP
1 2
C344 SCD1U10V2KX-4GPC344 SCD1U10V2KX-4GP
1 2
C343 SCD1U10V2KX-4GPC343 SCD1U10V2KX-4GP
1 2
C340 SCD1U10V2KX-4GPC340 SCD1U10V2KX-4GP
1 2
C367 SCD1U10V2KX-4GPC367 SCD1U10V2KX-4GP C374 SCD1U10V2KX-4GPC374 SCD1U10V2KX-4GP C362 SCD1U10V2KX-4GPC362 SCD1U10V2KX-4GP C365 SCD1U10V2KX-4GPC365 SCD1U10V2KX-4GP C354 SCD1U10V2KX-4GPC354 SCD1U10V2KX-4GP C357 SCD1U10V2KX-4GPC357 SCD1U10V2KX-4GP C348 SCD1U10V2KX-4GPC348 SCD1U10V2KX-4GP C352 SCD1U10V2KX-4GPC352 SCD1U10V2KX-4GP
1 2
R196 1K27R2F-L-GPR196 1K27R2F-L-GP
1 2
R19 2KR2F-3-GPR19 2KR2F-3-GP
Placement: close RS780
R215
R215 301R2F-GP
301R2F-GP
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
TP149 TPAD14-GPTP149 TPAD14-GP TP154 TPAD14-GPTP154 TPAD14-GP
1D1V_S0
2
RS780M Display Port Support(muxed on GFX)
DP0
PCIE_TXP1 26
PCIE_TXN1 26
PCIE_TXP2 28
PCIE_TXN2 28
PCIE_TXP5 28
PCIE_TXN5 28
ALINK_NBTX_C_SBRX_P0 17 ALINK_NBTX_C_SBRX_N0 17 ALINK_NBTX_C_SBRX_P1 17 ALINK_NBTX_C_SBRX_N1 17 ALINK_NBTX_C_SBRX_P2 17 ALINK_NBTX_C_SBRX_N2 17 ALINK_NBTX_C_SBRX_P3 17 ALINK_NBTX_C_SBRX_N3 17
2
1
GFX_TX0,TX1,TX2,TX3,AUX0,HPD0 GFX_TX4,TX5,TX6,TX7,AUX1,HPD1DP1
LAN
NEW CARD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ATi-RS780M_HT LINK&PCIe(1/3)
ATi-RS780M_HT LINK&PCIe(1/3)
ATi-RS780M_HT LINK&PCIe(1/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
11 43Friday, August 22, 2008
11 43Friday, August 22, 2008
11 43Friday, August 22, 2008
1
-1
-1
of
of
-1
5
1
R190 0R2J-2-GP
R190 0R2J-2-GP
1 2
DY
LDT_RST#_CPU6
D D
PLT_RST1#17,26,31
Close to NB ball
SA
C C
LDT_STP#_CPU6
ALLOW_LDTSTOP6,17
DY
R186
R186
1 2
0R0402-PAD
0R0402-PAD
SC330P50V2KX-3GP
SC330P50V2KX-3GP
GMCH_BLUE
12
R30
R30
150R2F-1-GP
150R2F-1-GP
R87
R87
1 2
0R0402-PAD
0R0402-PAD
NB_ALLOW_LDTSTOP
R195
R195
1 2
0R0402-PAD
0R0402-PAD
1D8V_S0
C612
SC47U6D3V5MX-1-GP
SC47U6D3V5MX-1-GP
C612
SYSREST#
12
C364
C364
DY
DY
GMCH_GREEN
12
12
R31
R31
150R2F-1-GP
150R2F-1-GP
NB_LDT_STOP#
12
2ND = 68.00084.A81
2ND = 68.00084.A81
DY
DY
SA
GMCH_RED
R28
R28
140R2F-GP
140R2F-GP
1D1V_S0
2ND = 68.00084.A81
2ND = 68.00084.A81
L7
L7
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
SC47U6D3V5MX-1-GP
SC47U6D3V5MX-1-GP
1D8V_S0
12
TC1
TC1
ST100U6D3VBM-5GP
ST100U6D3VBM-5GP
L3
L3
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C613
C613
DY
DY
SB
ENABLE External CLK GEN
1D8V_S0
L9
L9
B B
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
2ND = 68.00084.A81
2ND = 68.00084.A81
1D8V_S0
L1
L1
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
2ND = 68.00084.A81
2ND = 68.00084.A81
VDDA18HTPLL
C75
C75
SC1U10V2KX-1GP
SC1U10V2KX-1GP
VDDA18PCIEPLL
C22
C22
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
DY
DY
12
12
C58
C58 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C21
C21 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
GPIO MODE STRP_DATA 01 VCC_NB
1.0V 1.1V
4
3D3V_S0
2ND = 68.00084.A81
2ND = 68.00084.A81
R29
R29
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
2ND = 68.00084.A81
2ND = 68.00084.A81
C44
C44
C56
C56
CLK_DDC_EDID14
DAT_DDC_EDID14
GMCH_GREEN15
SC1U10V2KX-1GP
SC1U10V2KX-1GP
GMCH_RED15
GMCH_BLUE15
DY
DY
12
12
1D1V_S0
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D1V_S0_PLLVDD
1D1V_S0_PLLVDD
12
DY
DY
12
C57
C57 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
*
L2
L2
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 200mA
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D8V_S0
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C39
C39 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
RN5
RN5
1 2 3
SRN1KJ-7-GP
SRN1KJ-7-GP
1 2
0R0603-PAD
0R0603-PAD
C49
C49
GMCH_HSYNC15 GMCH_VSYNC15
GMCH_DDCCLK15
GMCH_DDCDATA15
C41
C41
R27
R27
C48
C48
12
4
SB
TP155TPAD14-GPTP155TPAD14-GP TP14TPAD14-GPTP14TPAD14-GP
12
12
12
12
C52
C52 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
NB_PWRGD18,34
CLK_NBHT_CLK3 CLK_NBHT_CLK#3
CLK_NB_14M3
CLK_NB_GFX3 CLK_NB_GFX#3
3D3V_S0_AVDD
12
C27
C27 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
1D8V_S0_AVDDDI
C54
C54 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D8V_S0_AVDDQ
R23
R23
1 2
768R2F-1-GP
768R2F-1-GP
1D8V_S0_PLVDD18
VDDA18HTPLL
VDDA18PCIEPLL
SYSREST#
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
NB_REFCLK_N
CLK_NB_GFX CLK_NB_GFX#
CLK_NBGPP_CLK
TP151TPAD14-GPTP151TPAD14-GP
CLK_NBGPP_CLK#
TP153TPAD14-GPTP153TPAD14-GP
CLK_NB_GPPSB3 CLK_NB_GPPSB#3
RS780_AUX_CAL
12
DAC_RSET
NB_DVI_CLK NB_DVI_DATA
STRP_DATA
R18
R18 150R2F-1-GP
150R2F-1-GP
3
U31C
U31C
F12
AVDD1
E12
AVDD2
F14
AVDDDI
G15
AVSSDI
H15
AVDDQ
H14
AVSSQ
E17
C_Pr
F17
Y
F15
COMP_Pb
G18
RED
G17
REDb
E18
GREEN
F18
GREENb
E19
BLUE
F19
BLUEb
A11
DAC_HSYNC
B11
DAC_VSYNC
F8
DAC_SCL
E8
DAC_SDA
G14
DAC_RSET
A12
PLLVDD
D14
PLLVDD18
B12
PLLVSS
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESET#
A10
POWERGOOD
C10
LDTSTOP#
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN
F11
REFCLK_N
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP
V3
GPPSB_REFCLKN
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_CLK0/AUX0P
A8
DDC_DATA0/AUX0N
B7
DDC_CLK1/AUX1P
A7
DDC_DATA1/AUX1N
B10
STRP_DATA
G11
RESERVED
C8
AUX_CAL
RS780M-GP-U2
RS780M-GP-U2
3D3V_S0
678
123
4 5
DDC_DATA0/AUX0N DDC_CLK0/AUX0P
RN1
RN1 SRN3K3J-1-GP
SRN3K3J-1-GP
GMCH_VSYNC
GMCH_HSYNC
PART 3 OF 6
PART 3 OF 6
CRT/TVOUT
CRT/TVOUT
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
LVTM
LVTM
2
1
STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#) 1 :Disable 0 : Enable
*
RS780: Enables Side port memory ( RS780 use HSYNC#)
1 :Disable 0 : Enable
*
SUS_STAT#
Selects Loading of STRAPS From EEPROM
: Bypass the loading of EEPROM straps and use Hardware Default Values
*
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN TXCLK_UP TXCLK_UN
VDDLTP18
VSSLTP18
VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2
VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7
LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL
TMDS_HPD
HPD
SUS_STAT#
THERMALDIODE_P THERMALDIODE_N
TESTMODE
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
A13 B13
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9
GMCH_BL_ON
F7
LVDS_ENA_BL
G12
D9 D10
D12 AE8
AD8
TESTMODE_NB
D13
GMCH_TXAOUT0+ 14 GMCH_TXAOUT0- 14 GMCH_TXAOUT1+ 14 GMCH_TXAOUT1- 14 GMCH_TXAOUT2+ 14 GMCH_TXAOUT2- 14
GMCH_TXBOUT0+ 14 GMCH_TXBOUT0- 14 GMCH_TXBOUT1+ 14 GMCH_TXBOUT1- 14 GMCH_TXBOUT2+ 14 GMCH_TXBOUT2- 14
GMCH_TXACLK+ 14
GMCH_TXACLK- 14
GMCH_TXBCLK+ 14
GMCH_TXBCLK- 14
1D8V_S0_VDDLP18
C379
C379
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D8V_S0_VDDLT18
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
NB_DVI_HPD SUS_STAT#
G792_DXP3_1 G792_DXN3_1
L20
L20
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
12
12
DY
DY
12
C50
C50
RN4
RN4
2 3 1
SRN4K7J-8-GP
SRN4K7J-8-GP
R24 100KR2J-1-GP
R24 100KR2J-1-GP
1 2
DY
DY
TP17 TPAD14-GPTP17 TPAD14-GP TP18 TPAD14-GPTP18 TPAD14-GP
R15 10KR2J-3-GPR15 10KR2J-3-GP
12
R26
R26 1K8R2F-GP
1K8R2F-GP
2ND = 68.00084.A81
2ND = 68.00084.A81
C378
C378 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L4
L4
1 2
PBY201209T-221Y-N-GP
PBY201209T-221Y-N-GP
12
2ND = 68.00216.161
2ND = 68.00216.161
C47
C47
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
4
12
G6
G6
GAP-CLOSE
GAP-CLOSE
GMCH_LCDVDD_ON 14
GMCH_BL_ON 31
TP20 TPAD14-GPTP20 TPAD14-GP
12
G8
G8 GAP-CLOSE
GAP-CLOSE
12
1D8V_S0
3D3V_S0
G792_DXP3 22
G792_DXN3 22
SA
3D3V_S0
12
R17
A A
5
DY
DY
R17 2K2R2J-2-GP
2K2R2J-2-GP
STRP_DATA
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ATi-RS780M_LVDS&CRT_(2/3)
ATi-RS780M_LVDS&CRT_(2/3)
ATi-RS780M_LVDS&CRT_(2/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
3
2
Date: Sheet
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
12 43Friday, August 22, 2008
12 43Friday, August 22, 2008
12 43Friday, August 22, 2008
1
of
of
of
-1
-1
-1
5
1D1V_S0
L6
L6
1 2
PBY201209T-221Y-N-GP
PBY201209T-221Y-N-GP
220 ohm @ 100MHz,2A
2ND = 68.00216.161
2ND = 68.00216.161
D D
1D1V_S0
L8
L8
1 2
PBY201209T-221Y-N-GP
PBY201209T-221Y-N-GP
220 ohm @ 100MHz,2A
2ND = 68.00216.161
2ND = 68.00216.161
1D2V_S0
L21
L21
1 2
PBY201209T-221Y-N-GP
PBY201209T-221Y-N-GP
220 ohm @ 100MHz,2A
2ND = 68.00216.161
2ND = 68.00216.161
C C
220 ohm @ 100MHz,2A
1D8V_S0
1 2
PBY201209T-221Y-N-GP
PBY201209T-221Y-N-GP
2ND = 68.00216.161
2ND = 68.00216.161
1D8V_S0
12
L5
L5
C383
C383
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C387
C387
12
80mil Width
12
C32
C32
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
0.6A per ANT Rev1.1, Page3
+1.1V_RUN_VDDHT
C60
C61
C61
12
DY
DY
C60
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
DY
DY
C51
C51
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
0.45A per ANT Rev1.1, Page3
+1.1V_RUN_VDDHTRX
C64
C64
C65
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C70
C70
12
1 2
0R0603-PAD
0R0603-PAD
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R202
R202
+1.2V_RUN_VDDHTTX
C65
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
DY
DY
C55
C55
C62
C62
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
+1.8V_RUN_VDDA18PCIE
12
12
C34
C34
C33
C33
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
+1.8V_RUN_VDD18_MEM
C71
C71
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C40
C40
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C53
C53
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C63
C63
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
C59
C59
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
12
C35
C35
C29
C29
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
C381
C381
SC1U10V2KX-1GP
SC1U10V2KX-1GP
M16 R16
H18 G19
D22
AE25 AD24 AC23 AB22 AA21
W19
U17 R17 M17
M10
R10 AA9
AB9 AD9 AE9 U10
AE11 AD11
J17 K16 L16
P16 T16
F20 E21
B23 A23
Y20 V18 T17 P17
J10 P10 K10
L10
T10
W9
H9
Y9
F9
G9
4
U31E
U31E
VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2
RS780M-GP-U2
RS780M-GP-U2
PART 5/6
PART 5/6
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13
POWER
POWER
VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6
VDD33_1 VDD33_2
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11
+3.3V_RUN_VDD33
H12
C18
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C18
3
1D1V_S0
300mil Width
12
C12
C12
DY
DY
12
12
C20
C20
C26
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C26
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
7A per ANT Rev1.1, Page3 Per check list (Rev 0.02) RS780M: 1V ~ 1.1V, check PWR team
12
C42
C42
VDD_MEM
12
DY
DY
12
C38
C38
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
0R0603-PAD
0R0603-PAD
12
C9
C9
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
R199
R199
1 2
12
C19
C19
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
0R0603-PAD
0R0603-PAD
12
12
C45
C45
C46
C46
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
3D3V_S0
R11
R11
12
C30
C30
2
U31F
U31F
A25
VSSAHT1
D23 E22 G22 G24
12
C17
C17
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
+NB_VCORE
1D1V_S0
12
C8
C8
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
C16
C16
12
12
C15
C15
C28
C28
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5KX-1GP
G25 H19
M20 N22 P20 R19 R22 R24 R25 H20 U22
V19 W22 W24 W25
Y21
AD25
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12 W11 W15
AC12 AA14
Y18
AB11 AB15 AB17 AB19 AE20 AB21
K11
J22 L17 L22 L24 L25
L12
RS780M-GP-U2
RS780M-GP-U2
VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
PART 6/6
PART 6/6
1
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31
GROUND
GROUND
VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
B B
A A
5
AB12 AE16
AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
AD16 AE17 AD17
W12
AD18 AB13 AB18
W14
AE12 AD12
V11
Y14
Y12
V14 V15
U31D
U31D
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13
MEM_BA0 MEM_BA1 MEM_BA2
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT
MEM_CKP MEM_CKN
MEM_COMPP MEM_COMPN
RS780M-GP-U2
RS780M-GP-U2
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ4 MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3 MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9 MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11
MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN
MEM_DQS1P MEM_DQS1N
MEM_DM0
MEM_DM1/DVO_D8
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
4
IOPLLVDD18
IOPLLVDD IOPLLVSS
MEM_VREF
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23 AE18
MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions
1D8V_S0
R210
R210
1 2
0R0402-PAD
0R0402-PAD
+1.8V_IOPLLVDD18
+1.1V_IOPLLVDD
1 2
0R0402-PAD
0R0402-PAD
R211
R211
1D1V_S0
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ATi-RS780M_Side Port&PWR&GND(3/3)
ATi-RS780M_Side Port&PWR&GND(3/3)
ATi-RS780M_Side Port&PWR&GND(3/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
2
Date: Sheet of
Cathedral Peak 2A
Cathedral Peak 2A
Cathedral Peak 2A
13 43Friday, August 22, 2008
13 43Friday, August 22, 2008
13 43Friday, August 22, 2008
1
of
of
-1
-1
-1
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