Acer Aspire 4733z Schematics

5

4

3

2

1

BOM MARK

IV@: INT VGA EV@: STUFF FOR EXT VGA SP@: STUFF FOR UMA or VGA

D D

5(9%

CLOCK GENERATOR

ICS: SELGO: SLG8SP513VTR

=46<67(0%/2&.',$*5$0

X'TAL

14.318MHz

Penryn 478

uFCPGA

P2

P3, P4

Thermal Sensor

(G780P81U) (G991)

P3

Fan Driver

P25

DDR3 PWR

TPS51116

THERMAL PROTECTION

DISCHARGER

VGA CORE MAX8792

CHARGER

P40

3/5V SYS PWR

P44

CPU CORE PWR

P42

+1.05V

P41

UP6111A

ISL88731A

RT8206

ISL6266A

P36

P37

P39

P38

FSB

667/800/1067 Mhz

ATI-Park

PCIE 16X

VRAM DDRIII

DDRIII

SO-DIMM 0 SO-DIMM 1

P16,P17

C C

HDD (SATA) *1

Dual Channel DDR3

667/800 MHz

(GM45/ PM45/ GL40)

P26

NB

Cantiga

P5, P6, P7, P8, P9, P10, P11

X4 DMI interface

LVDS

RGB

512MB

Ext USB Port x 2

USB 0,2

Int USB Port x 1

USB 6

Bluetooth

USB3

B B

CCD

USB11

P27

P24

ODD (SATA)

P26

SATA0

SATA1

USB 2.0

Azalia

SB

ICH9M

P12,P13,P14,P15

PCI-Express

USB1

X'TAL

32.768KHz

P18-P23

EXT_LVDS EXT_CRT EXT_HDMI

INT_LVDS

INT_CRT

INT_HDMI

PCIE-6

SWITCH

CIRCUIT

HDMI switch (PS8101T)

PCIE-4

X'TAL 25MHz

P25

Mini Card

WLAN

CRT

LVDS

HDMI

P27

P24

P25

Media

LPC

Audio CODEC

P29

P28

Int. MIC

P29

(272)

A A

Audio Amplifier G1453L

P28

MIC Jack

EC (WPC781)

SPI ROM

Touch Pad

P33

P26 P33

P33

X'TAL

32.768KHz

K/B COON.

Int. Speaker

P29

5

4

3

Cardreader

(AU6437)

USB2

Card Reader Connector

P30

P32

2

Giga-LAN

BCM57780

Transformer

RJ45

P31

P30

P31

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

Date: Sheet

Block Diagram

1

1A

1Monday, July 12, 2010

of

43

of

43

of

43

5

&ORFN*HQHUDWRU&/.

PBY160808T-301Y-N/2A/300ohm_6

+3V

D D

C C

B B

L42

SATACLKREQ#14 LAN_CLKREQ#31 PCLK_DEBUG28

PCLK_59135

PCLK_ICH13

CLK_Card4833 CLKUSB_4814

14M_ICH14

5/5 modify

Pin 11

Pin 12

Pin 13

Pin 14

&ORFN*HQ,&

A A

PDAT_SMB14,16,28 PCLK_SMB14,16,28

C544

C544 *0.1u/10V_4

*0.1u/10V_4 C434

C434 *0.1u/10V_4

*0.1u/10V_4 C542

C542 *10u/10V_8

*10u/10V_8 C569

C569

0.1u/10V_4

0.1u/10V_4 C557

C557

0.1u/10V_4

0.1u/10V_4 C550

C550

0.1u/10V_4

0.1u/10V_4 C450

C450

0.1u/10V_4

C541

C541 10u/10V_8

10u/10V_8

R321 475/F_4R321 475/F_4 R325 475/F_4R325 475/F_4 R330 33_4R330 33_4

R334 33_4R334 33_4

PCLK_ICH

R346 33_4R346 33_4

CG_XIN CG_XOUT

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

C549

C549 33p/50V_4

33p/50V_4

CL=20p

C548

C548 33p/50V_4

33p/50V_4

ICS9LRS3165BKLFT (ALPRS365000)

PCI2/TME

PCI-3

PCI-4/27M_SEL

PCIF-5/ITP_EN

5

VDD_CK_VDD_REF

+1.05V_VDD

T95T95

R345 22_4R345 22_4 R337 22_4R337 22_4 R338 2.2K_4R338 2.2K_4

R314 10K_4R314 10K_4 R318 33_4R318 33_4

CG_XIN

21

Y2

14.318MHZ

CG_XOUT

RTM875T-606 (AL000875000)

PCI2/TME internal PD

PCI-3/SRC5_EN internal PD

PCI-4/27M_SEL internal PD

PCIF-5/ITP_EN internal PD

2

Q13

3 1

2N7002E

C573

C573 *10u/10V_8

*10u/10V_8

SATA_CLKREQ#_RSATA_CLKREQ#_R LAN_CLKREQ#_R PCLK_DEBUG_R PCI_CLK_SIO PCLK_591_R PCLK_ICH_R

FSA

FSC

C574

C574 10u/10V_8

10u/10V_8

U15

9

VDD_PCI

16

VDD_48

23

VDD_PLL3

4

VDD_REF

46

VDD_SRC

62

VDD_CPU

19

VDD_96_IO

27

VDD_PLL3_IO

33

VDD_SRC_IO_1

52

VDD_SRC_IO_3

43

VDD_SRC_IO_2

56

VDD_CPU_IO

8

PCI0/CR#_A

10

PCI1/CR#_B

11

PCI2/TME

12

PCI3

13

PCI4/SRC5_EN

14

PCIF5/ITP_EN

3

XTAL_IN

2

XTAL_OUT

17

USB_48/FSA

64

FSB/TEST/MODE

5

REF0/FSC/TESTSEL

65

VSS_BODY

15

VSS_PCI

18

VSS_48

22

VSS_IO

26

VSS_PLL3

59

VSS_CPU

30

VSS_SRC1

36

VSS_SRC2

49

VSS_SRC3

1

VSS_REF

SLG8SP513VTR ,ICS9LPRS365BKLFT

PULL HIGH PULL DOWN

NO OVERCLOCKING NORMAL RUN

PIN37/38 IS SRC5

PIN 17/18 IS 27MHz

PIN 46/47 IS CPUITP PIN 46/47 IS SRC8

+3V +3V

R258

4.7K_4

SMBDT1 SMBCK1

(default)

<MAIN>:ICS9LRS3165BKLFT QCI:ALPRS365000 <SECOND>:SLG8SP513VTR QCI:AL8SP513000 <SECOND>:RTM875N-606-VD-GRT QCI:AL000875000

4

Modfiy it 5/4

C568

C545

0.1u/10V_4

CK505

PIN37/38 IS PCI_STOP/CPU_STOP

PIN 17/18 IS SRC/DOT

C568

0.1u/10V_4

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

SRC8#/ITP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

CKPWRGD/PWRDWN#

SLG8SP513

4

IO_VOUT

SCLK

SDA

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC1/SE1

(default)

3

+1.05V_VDD

L43

PBY160808T-301Y-N/2A/300ohm_6

C551

0.1u/10V_4

55 7

SMBCK1

6

SMBDT1

45

PM_STPPCI#

44

PM_STPCPU#

61 60

58 57

54 53

42 41

40

CLK_MCH_OE#_C

39

CLK_PCIE_SRC11#

37 38

51

CLK_PCIE_SRC7

50

CLK_PCIE_SRC7#

48 47

34 35

31

CLK_PCIE_SRC3

32

CLK_PCIE_SRC3#

28 29

24

CLK_DREFSSCLK_R

25

CLK_DREFSSCLK#_R

20

CLK_DREFCLK_R

21

CLK_DREFCLK#_R

63

C546

0.1u/10V_4

R319 475/F_4R319 475/F_4 R323 475/F_4R323 475/F_4

R348 *EV@475/F_4R348 *EV@475/F_4

+3V

C435

0.1u/10V_4

T91T91 T92T92

T94T94 T93T93

T97T97

R329 10K_4R329 10K_4 R331 *10K_4R331 *10K_4 R336 EV@10K_4R336 EV@10K_4 R332 IV@10K_4R332 IV@10K_4 R342 *10K_4R342 *10K_4 R343 10K_4R343 10K_4

PBY160808T-301Y-N/2A/300ohm_6

C437

C437 *0.1u/10V_4

*0.1u/10V_4

PM_STPPCI# 14 PM_STPCPU# 14

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5

CLK_PCIE_3GPLL# 6 CLK_PCIE_3GPLL 6

CLK_MCH_OE# 6 MINI_CLKREQ# 28

CLK_PCIE_MINI1 28 CLK_PCIE_MINI1# 28

CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13

CLK_PCIE_LAN 31 CLK_PCIE_LAN# 31

PEG_CLKREQ# 19

CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12

CK_PWRGD 14

To NB

R259

4.7K_4

3

R347 0_4R347 0_4 R267 0_4R267 0_4 R315 0_4R315 0_4

5/18 Modify

CPU_BSEL03 CPU_BSEL13 CPU_BSEL23 MCH_BSEL2 6

2

Q12

3 1

2N7002E

REV:B 6/11REV:B 6/12

PCLK_DEBUG_R

PCLK_591_R

HIGH 27MHz LOW SRC

PCLK_ICH_R

MCH_BSEL0 6 MCH_BSEL1 6

+1.05V

5/7 Modfiy

To SB

To CPU

To NB

To Mini Card 1 (WLAN)

To ICH

To LAN

Modfiy it 5/4

To ICH

To NB or VGA

From GMCH

From Deisceret

2

PM_STPPCI#

PM_STPCPU#

CLK_PCIE_SRC11#

SATA_CLKREQ#_R

LAN_CLKREQ#_R

CLK_PCIE_SRC3

CLK_MCH_OE#_C

For EMI

PCLK_591_R

CLKUSB_48

14M_ICH

PCLK_ICH_R

FSC FSB FSA CPU SRC PCI

RN15

CLK_DREFCLK_R CLK_DREFCLK#_R

CLK_DREFSSCLK_R CLK_DREFSSCLK#_R

CLK_DREFCLK_R CLK_DREFCLK#_R

CLK_DREFSSCLK_R CLK_DREFSSCLK#_R

RN15

RN14

RN10

1

+3V

R313 *2.2K_4R313 *2.2K_4

R316 *2.2K_4R316 *2.2K_4

R322 10K_4R322 10K_4

R324 10K_4R324 10K_4

R320 10K_4R320 10K_4

R349 10K_4R349 10K_4

R317 10K_4R317 10K_4

C571 *33p/50V_4C571 *33p/50V_4

C581 *15p/50V_4C581 *15p/50V_4

C554 *33p/50V_4C554 *33p/50V_4

C578 *33p/50V_4C578 *33p/50V_4

SEL0SEL1SEL2

Frequence select

02

5/5 Add

1 0 1 100 100 33 0 0 1 133 100 33

Default

0 1 1 166 100 33 0 1 0 200 100 33 0 0 0 266 100 33 1 0 0 333 100 33 1 1 0 400 100 33 1 1 1 Reserved

1 2

RN9

1 3

43

IV@0_4P2R

EV@0_4P2R

2 4

*EV@33_4P2R

CLK_DREFCLK 6 CLK_DREFCLK# 6

CLK_DREFSSCLK 6 CLK_DREFSSCLK# 6

CLK_PCIE_VGA 18 CLK_PCIE_VGA# 18

27M_NONSS 19

5/22 modify

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

CLOCK GENERATOR

Date: Sheet

1

of

2Monday, July 12, 2010

1A

43

5

4

3

2

1

H_A#[3..16]5

D D

H_ADSTB#05

H_REQ#[0..4]5

H_A#[17..35]5

C C

H_ADSTB#15 H_A20M#12

H_FERR#12 H_IGNNE#12

H_STPCLK#12 H_INTR12 H_NMI12 H_SMI#12

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

U17A

J4

ADDR GROUP_0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

ADDR GROUP_1

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4 AB2 AA3

V1 A6

A5 C4

D5 C6 B4 A3

M4 N5

T2 V3 B2 D2

D22

D3

F6

A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY#

PREQ#

TCK TDO

TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA THERMDC

H CLK

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

F1 D20

H_IERR#

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6

TDI

AB3 AB5 AB6 C20

D21 A24 B25

C7

A22 A21

R245 56_4R245 56_4

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# SYS_RST#

H_PROCHOT#_D H_THERMDA H_THERMDC

PM_THRMTRIP#

T56T56 T86T86 T88T88 T55T55 T89T89

H_ADS# 5 H_BNR# 5 H_BPRI# 5

H_DEFER# 5 H_DRDY# 5 H_DBSY# 5

H_BREQ# 5

+1.05V

H_INIT# 12 H_LOCK# 5 H_CPURST# 5

H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5

H_HIT# 5 H_HITM# 5

Connect it to CPU DBR# is for ITP debug port or CPU interposer (like ICE) to reset the system

SYS_RST# 14

CLK_CPU_BCLK 2 CLK_CPU_BCLK# 2

+1.05V

R311

R311 1K/F_4

1K/F_4

R312

R312 2K/F_4

2K/F_4

Layout note: H_GTLREF: Zo=55 ohm L<0.5", 2/3*VCCP+-2%

H_D#[0..15]5

H_DSTBN#05 H_DSTBP#05 H_DINV#05

H_D#[16..31]5

H_DSTBN#15 H_DSTBP#15 H_DINV#15

CPU_BSEL02 CPU_BSEL12 CPU_BSEL22

H_D#[0..15]

H_D#[16..31]

T108T108 T112T112 T125T125 T90T90 T87T87 T126T126 T127T127

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

H_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24

H22 F26 K22 H23

H26 H25

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

AD26

C23 D25 C24

AF26

AF1 A26

B22 B23 C21

J24 J23

J26

C3

U17B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_D#[32..47]

H_D#[48..63]

R344 27.4/F_6R344 27.4/F_6 R328 54.9/F_4R328 54.9/F_4 R257 27.4/F_6R257 27.4/F_6 R254 54.9/F_4R254 54.9/F_4

H_D#[32..47] 5

H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5

H_D#[48..63] 5

Layout note: comp0,2: Zo=27.4ohm, L< 0. 5" comp1,3: Zo=55ohm, L<0. 5"

Layout note: DPRSTP# , Daisy Chain (SB>Power>NB>CPU)

H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5

ICH_DPRSTP# 6,12,39 H_DPSLP# 12 H_DPWR# 5 H_PWRGD 12 H_CPUSLP# 5 PSI# 39

03

Penryn

B B

Thermal Trip

DELAY_VR_PWRGOOD6,14,39

PM_THRMTRIP#

Processor hot

A A

H_PROCHOT#_D

+1.05V

R273

R273 56_4

56_4

R274 *0_4R274 *0_4

&38

5

+1.05V

3

2

Q18

Q18 DMN601K-7

+1.05V

R398

R398 56_4

56_4

No use Thermal trip CPU side still PU 56ohm. Use Thermal trip can share PU at SB side

No use PROCHOT CPU side still PU 56ohm. Use PROCHOT to optional receiver CPU side PU 68ohm and through isolat 2.2K ohm to receiver side

1

2

1 3

DMN601K-7

Q17

Q17 MMBT3904

MMBT3904

SYS_SHDN# 37,44PM_THRMTRIP#6,12

H_PROCHOT# 39

4

CPU Thermal monitor

2ND_MBCLK35 2ND_MBDATA35

THERM_ALERT#14

THER_OVERT#27

+3V

R401 *10K_4R401 *10K_4

R395 *0_4R395 *0_4

R394 10K_4R394 10K_4

4/20 Modify

3

+3V

R400

R400 200_6

200_6

U21

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

G780P81U(MSOP-8)

$''5(66+

VCC DXP DXN GND

VCC_TH

1 2 3 5

C624

0.1U/10V_4

H_THERMDA

C621

C621 2200p_4

2200p_4

H_THERMDC

GMT AL000780000 Use 2200p

WINDBOND AL83L771K01

2

Use 2200pAL095245000NS

Use 2200p

XDP PU/PD

+3V

SYS_RST#

ZR6 hang up issue

XDP_TDO XDP_TDI XDP_TMS XDP_BPM#5 XDP_TCK XDP_TRST#

XDP_DBRESET# and X DP_TDO reserve for XDP

Size Document Number Rev

Date: Sheet of

Date: Sheet

R391 *1K_4R391 *1K_4

R261 *54.9/F_4R261 *54.9/F_4 R260 54.9/F_4R260 54.9/F_4 R264 54.9/F_4R264 54.9/F_4 R310 54.9/F_4R310 54.9/F_4 R265 54.9/F_4R265 54.9/F_4 R266 54.9/F_4R266 54.9/F_4

352-(&7=4

4XDQWD&RPSXWHU,QF

CPU Host Bus

1

3Monday, July 12, 2010

+1.05V

1A

of

43

5

4

3

2

1

U17D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

D D

C C

B B

A A

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

C470

C470 *10U/6.3V_8

*10U/6.3V_8

C562

C562 10U/6.3V_8

10U/6.3V_8

C445

C445 10U/6.3V_8

10U/6.3V_8

C590

C590 *10U/6.3V_8

*10U/6.3V_8

C447

C447 10U/6.3V_8

10U/6.3V_8

C589

C589 10U/6.3V_8

10U/6.3V_8

C442

C442 *10U/6.3V_8

*10U/6.3V_8

Layout Note: Place these parts reference to Intel demo board.

C425

C425 *10U/6.3V_8

*10U/6.3V_8

C565

C565 10U/6.3V_8

10U/6.3V_8

C564

C444

C444 *10U/6.3V_8

*10U/6.3V_8

C588

C588 *10U/6.3V_8

*10U/6.3V_8

C421

C421 *10U/6.3V_8

*10U/6.3V_8

C591

C591 10U/6.3V_8

10U/6.3V_8

C491

+

*330U/2V_7343

C471

C471 10U/6.3V_8

10U/6.3V_8

C468

C468 *10U/6.3V_8

*10U/6.3V_8

C441

C441 *10U/6.3V_8

*10U/6.3V_8

C422

C422 10U/6.3V_8

10U/6.3V_8

C587

C587 10U/6.3V_8

10U/6.3V_8

C564 *10U/6.3V_8

*10U/6.3V_8

C466

C466 10U/6.3V_8

10U/6.3V_8

C472

C472 *10U/6.3V_8

*10U/6.3V_8

C446

C446 *10U/6.3V_8

*10U/6.3V_8

C423

C423 *10U/6.3V_8

*10U/6.3V_8

C586

C586 *10U/6.3V_8

*10U/6.3V_8

C580

+

330U/2V_7343

C563

C563 *10U/6.3V_8

*10U/6.3V_8

C429

C429 *10U/6.3V_8

*10U/6.3V_8

C433

C433 10U/6.3V_8

10U/6.3V_8

C443

C443 *10U/6.3V_8

*10U/6.3V_8

C567

C567 10U/6.3V_8

10U/6.3V_8

C469

C469 10U/6.3V_8

10U/6.3V_8

C430

+

330U/2V_7343

+

Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0 stuff 22U*34, NC 22U*2 stuff 330U*2, NC330U*2

&38

5

4

3

VCC_CORE VCC_CORE

U17C

A7

C424

C424 *10U/6.3V_8

*10U/6.3V_8

C465

C465 *10U/6.3V_8

*10U/6.3V_8

C419

C419 10U/6.3V_8

10U/6.3V_8

C420

C420 10U/6.3V_8

10U/6.3V_8

C566

C566 *10U/6.3V_8

*10U/6.3V_8

C467

C467 *10U/6.3V_8

*10U/6.3V_8

C623

*330U/2V_7343

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A9

B7 B9

C9

D9

E7 E9

F7 F9

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

2

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCC:38A (Low power type) VCC:47A (Standard type)

04

Layout Note: Inside CPU center cavity in 2 rows

VCCP : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)

+1.05V

C431

C428

0.1U/10V_4

C426

C426 *0.1U/10V_4

*0.1U/10V_4

H_VID0 39 H_VID1 39 H_VID2 39 H_VID3 39 H_VID4 39 H_VID5 39 H_VID6 39

C431

0.1U/10V_4

R308 100/F_6R308 100/F_6

R309

R309 100/F_6

100/F_6

C432

0.1U/10V_4

C599

0.01U/25V_4

C438

0.1U/10V_4

C440

0.1U/10V_4

+

VCCA:130mA

C598

C598 10U/6.3V_8

10U/6.3V_8

VCC_CORE

VCCSENSE 39

VSSSENSE 39

C622

C622 330U/2V_7343

330U/2V_7343

+1.5V

Layout Note: Z0=27.4,PU/PD L<1"

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

CPU Power

Date: Sheet

Date: Sheet of

1

1A

of

4Monday, July 12, 2010

43

5

4

3

2

1

*0&+&$17,*$

QCI P/N

D D

Intel Cantiga (G)M

Intel Cantiga (P)M

Intel Cantiga (G)L A1

C C

+1.05V

0.3125*VCCP

R411

R411 221/F_4

221/F_4

R410

R410 100/F_4

100/F_4

B B

R407

24.9/F_4

A A

WIDE(10):SPACING(20) , L<0.5"

H_SWING

H_RCOMP

5

AJSLB940T04

AJSLB970T06

AJSLGGM0T04

C642

0.1U/10V_4

Layout Note: WIDE(10):SPACING(20) , L<0.5"

2/3*VCCP WIDE(10):SPACING(20), L<0.5"

H_D#[0..63]3

+1.05V

R414

R414 1K/F_4

1K/F_4

R415

R415 2K/F_4

2K/F_4

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_CPURST#3

H_AVREF

C649

C649 *0.1U/10V_4

*0.1U/10V_4

4

M11

N12

P13

N10

AD14

Y10 Y12 Y14

W2

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AF3

AC1

AE3

AC3 AE11

AE8

AG2

AD6

C12

E11

A11

B11

F2

G8

F8 E6 G2 H6 H2

F6 D4 H3 M9

J1

J2

J6 P2

L2 R2 N9

L6 M5

J3 N2 R1 N5 N6

N8

L7 M3

Y3 Y6

Y7

Y9

C5 E3

U20A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA_PM

3

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

2

H_A#[3..35] 3

H_ADS# 3

H_ADSTB#0 3

H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BREQ# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 2 CLK_MCH_BCLK# 2 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3

H_DINV#[3..0] 3

H_DSTBN#[3..0] 3

H_DSTBP#[3..0] 3

H_REQ#[0..4] 3

H_RS#[0..2] 3H_CPUSLP#3

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

GMCH HOST

Date: Sheet

1

05

5Monday, July 12, 2010

of

1A

43

5

4

3

2

1

IV@

EV@

+3V_S5

06

DDR3

U20B

Strap table

Pin Name Strap description

CFG[2:0]

D D

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

FSB Frequency Select

Reserved

DMI X2 Select

iTPM Host Interface

ME TLS Confidentiality

Reserved

PCIE Graphics Lane Reversal

PCIE Loopback enable

ReservedCFG11

CFG12

CFG13

CFG[15:14]

C C

CFG16

CFG[18:17]

CFG19

CFG20

ALLZ

XOR

Reserved

FSB Dynamic ODT

Reserved

DMI Lane Reversal

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIE

SDVO_CTRLDATA SDVO Present

DDPC_CTRLDATA Digital Display Present

Strap pin

+3V

R203 *4.02K/F_4R203 *4.02K/F_4

B B

A A

R207 *4.02K/F_4R207 *4.02K/F_4

R417 *2.21K/F_4R417 *2.21K/F_4 R214 *2.21K/F_4R214 *2.21K/F_4 R197 *2.21K/F_4R197 *2.21K/F_4

R183 *2.21K/F_4R183 *2.21K/F_4 R416 *2.21K/F_4R416 *2.21K/F_4

R208 *2.21K/F_4R208 *2.21K/F_4 R213 *2.21K/F_4R213 *2.21K/F_4 R196 *2.21K/F_4R196 *2.21K/F_4

5/4 modify it for park reversal PCIE x16

+3V

R185 IV@2.21K/F_4R185 IV@2.21K/F_4 R192 IV@2.21K/F_4R192 IV@2.21K/F_4 R205 *2.21K/F_4R205 *2.21K/F_4 R206 *2.21K/F_4R206 *2.21K/F_4 R198 10K_4R198 10K_4 R204 10K_4R204 10K_4 R200 10K_4R200 10K_4

Configuration

000= FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

0 = DMI X2 1 = DMI X4(Default)

0 = iTPM Host Interface is enabled 1 = iTPM Host Interface is disabled(Default)

0 = AMT Firmware will use TLS cipher suite with no confidentiality 1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)

0 = Reverse Lanes 1 = Normal operation(Default)

0 = Enabled 1 = Disabled (Default)

0 = ALLZ mode enable 1 = disable(Default)

0 = XOR mode enable 1 = disable(Default)

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

0 = Normal (Default) 1 = Lanes Reversed

0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is operational (Default) 1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

0 = No SDVO/HDMI Device Present(Default) 1 = SDVO/HDMI Device present

0 = Digital display(HDMI/DP) device absent(Default) 1 = Digital display(HDMI/DP) device present

MCH_CFG_19 MCH_CFG_20

MCH_CFG_5 MCH_CFG_6

TPM Disable

MCH_CFG_7 MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13 MCH_CFG_16

SDVO_CTRLDATA SDVO_CTRLCLK DDPC_DDCDATA DDPC_CTRLCLK CLK_MCH_OE# PM_EXTTS#0 PM_EXTTS#1

PM_SYNC#14

ICH_DPRSTP#3,12,39 PM_EXTTS#016

PM_EXTTS#117

DELAY_VR_PWRGOOD3,14,39

PLT_RST#13

PM_THRMTRIP#3,12

PM_DPRSLPVR14,39

NB Thermal trip pin No use Thermal trip NB side can NC.(NB has ODT)

PM_DPRSTP# The Daisy chain topology should be routed from ICH9M to IMVP , then to (G)MCH and CPU, in that order.

R239 100/F_4R239 100/F_4 R210 *0_4R210 *0_4

T43T43 T39T39 T47T47 T44T44

MCH_BSEL02 MCH_BSEL12 MCH_BSEL22

MCH_CFG_3

T31T31

MCH_CFG_4

T35T35

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8

T28T28

MCH_CFG_9 MCH_CFG_10 MCH_CFG_11

T29T29

MCH_CFG_12 MCH_CFG_13 MCH_CFG_14

T32T32

MCH_CFG_15

T30T30

MCH_CFG_16 MCH_CFG_17

T27T27

MCH_CFG_18

T33T33

MCH_CFG_19 MCH_CFG_20

RST_IN#_MCH THRMTRIP#_R

*0&+&$17,*$

5

4

M36

AH10 AH12 AH13

AY21

BG23 BF23 BH18 BF18

AL34 AK34 AN35 AM35

M24

M20

AT40 AT11

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43

BH6 BH5 BG4 BH3

BH2 BG2

BG1 BD1

BC1

N36 R33 T33 AH9

K12

T24 B31

M1

B2

T25 R25 P25 P20 P24 C25 N24

E21 C23 C24 N21 P21 T21 R20

L21 H21 P29 R28 T28

R29

B7 N33 P32

T20 R32

BF3

BE2 BF1

F1

U20B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

RSVD14 RSVD15 RSVD17

RSVD20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

ME_JTAG_TCK ME_JTAG_TDI ME_JTAG_TDO ME_JTAG_TMS

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25

CANTIGA_PM

3

CFG

PM

NC

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

SM_RCOMP_VOH SM_RCOMP_VOL

SM_DRAMRST# DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

ME JTAG

CLK

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SB_CKE_1 SA_CS#_0

SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0

SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_E N

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36 BA17

AY16 AV16 AR13

BD17 AY17 BF15 AY13

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

M_RCOMP M_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF SM_PWROK SM_REXT

R247 499/F_4R247 499/F_4

CLK_DREFCLK CLK_DREFCLK# CLK_DREFSSCLK CLK_DREFSSCLK#

CLK_PCIE_3GPLL CLK_PCIE_3GPLL#

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

MCH_CLVREF_R

DDPC_CTRLCLK DDPC_DDCDATA

CLK_MCH_OE#

TSATN#

R169 56_4R169 56_4

HDA_BIT_CLK_HDMI HDA_RST#_HDMI HDA_SDIN_HDMI HDA_SDOUT_HDMI HDA_SYNC_HDMI

Modify 4/19

Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V

NOTE: If (G)MCH's HD Audio signals are connected to ICH9M for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be only on 1.5V. These power pins on ICH9M can be supplied with 3.3V if and only if (G)MCH's HDA is not connected to ICH9M. Consequently, only 1.5V audio/modem codecs can be used on the platform.

M_CLK0 16 M_CLK1 16 M_CLK2 17 M_CLK3 17

M_CLK#0 16 M_CLK#1 16 M_CLK#2 17 M_CLK#3 17

M_CKE0 16 M_CKE1 16 M_CKE2 17 M_CKE3 17

M_CS#0 16 M_CS#1 16 M_CS#2 17 M_CS#3 17

M_ODT0 16 M_ODT1 16 M_ODT2 17 M_ODT3 17

CLK_DREFCLK 2 CLK_DREFCLK# 2 CLK_DREFSSCLK 2 CLK_DREFSSCLK# 2

CLK_PCIE_3GPLL 2 CLK_PCIE_3GPLL# 2

DMI_TXN[3:0] 13

DMI_TXP[3:0] 13

DMI_RXN[3:0] 13

DMI_RXP[3:0] 13

CL_CLK0 14

CL_DATA0 14 MPWROK 14,35 CL_RST#0 14

SDVO_CTRLCLK 26

SDVO_CTRLDATA 26 CLK_MCH_OE# 2 MCH_ICH_SYNC# 14

+1.05V

HDA_BIT_CLK_HDMI 12 HDA_RST#_HDMI 12 HDA_SDIN_HDMI 12 HDA_SDOUT_HDMI 12 HDA_SYNC_HDMI 12

2

SM_VREF=0.5*VCC_SM SM_PWROK only for

DDR3.(DDR2 PD only) SM_DRAMRST# only for DDR3.(DDR2:NC)

DDR3_DRAMRST# 16,17

+1.05V

R227

R227 1K/F_4

1K/F_4

R228

C394

511/F_4

0.1U/10V_4

If HDMI not support HDA --> NC VCC_HDA-->GND Differential signal-->NC

R250

12.1K_4

SM_PWROK

R251

10K_4

M_RCOMP M_RCOMP#

SM_VREF

SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.

INTEL FAE Suggest PD for Ext graphics

CLK_DREFCLK# CLK_DREFCLK CLK_DREFSSCLK# CLK_DREFSSCLK

NB Thermaltrip

Check list note : CL_VREF=0.35V

DDPC_CTRL for HDMI port C SDVO_CTRL for HDMI port B

<Checklist ver0.8> If TSATN# is not used, then it must be terminated with a 56-ȍ pull-up resistor to VCCP.

<Pin out check issue> Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN

REV:B

R571

Add 6/11

*0_4

TC7SH08FU

53

1

U10

4

2

R253 *short0402R253 *short0402 R252 *0_4R252 *0_4

R340 80.6/F_4R340 80.6/F_4 R339 80.6/F_4R339 80.6/F_4

SM_RCOMP_VOH

C560

2.2U/6.3V_6

SM_RCOMP_VOL

C559

2.2U/6.3V_6

Size Document Number Rev

Date: Sheet

+1.5V_SUS

R241 10K/F_4R241 10K/F_4 R242 10K/F_4R242 10K/F_4

+1.5V_SUS

R184 EV@0_4R184 EV@0_4 R182 EV@0_4R182 EV@0_4 R190 EV@0_4R190 EV@0_4 R187 EV@0_4R187 EV@0_4

C577

R335

0.01U/25V_4

3.01K/F_4

R326

C576

1K/F_4

0.01U/25V_4

352-(&7=4

4XDQWD&RPSXWHU,QF

GMCH DMI

1

HWPG_1.5V 35,40 SUSC# 14,35 SUSB# 14,35

+1.5V_SUS

R3271K/F_4 R3271K/F_4

6Monday, July 12, 2010

1A

of

43

of

43

of

43

5

4

3

2

1

IV@

U20C

EV@

SP@

D D

07

C C

,9(9'LV(QDEOHVHWWLQJ

If LVDS no use,all signal can NC

L_BKLT_CTRL25

INT_LVDS_BLON25

+3V

INT_LVDS_EDIDCLK25 INT_LVDS_EDIDDATA25

INT_LVDS_DIGON25

INT_TXLCLKOUT-25

INT_TXLCLKOUT+25

INT_TXLOUT0-25

INT_TXLOUT1-25

INT_TXLOUT2-25

INT_TXLOUT0+25

INT_TXLOUT1+25

INT_TXLOUT2+25

R201 IV@10K_4R201 IV@10K_4 R199 IV@10K_4R199 IV@10K_4

L_CTRL_CLK L_CTRL_DATA

R188 IV@2.37K/F_4R188 IV@2.37K/F_4

INT_TXLCLKOUTINT_TXLCLKOUT+

INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2-

INT_TXLOUT0+ INT_TXLOUT1+ INT_TXLOUT2+

TV_A/B/C

SP@

B B

6/14 Modify REV:B

INT_CRT_DDCCLK25 INT_CRT_DDCDAT25

INT_HSYNC25 INT_VSYNC25

For IV: 75ohm For EV:0ohm

R189 SP@75_4R189 SP@75_4 R195 SP@75_4R195 SP@75_4 R194 SP@75_4R194 SP@75_4

INT_CRT_BLU25 INT_CRT_GRN25 INT_CRT_RED25

R425 IV@24.9_4R425 IV@24.9_4

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

HSYNC_G CRTIREF VSYNC_G

HSYNC/VSYNC serial R place close to NB

Discrete STUFFED.

A A

HSYNC_G VSYNC_G

CRTIREF pull down for IV cantiga 1k ohm/F

U20C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA_PM

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6

LVDS

TV

VGA

PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12

PCI-EXPRESS GRAPHICS

PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

L<0.5" , If PCIE not support still connect to +VCC_PEG

T37

EXP_A_COMPX

T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8

PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

PEG_RXP8

PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

C_PEG_TXN0

C_PEG_TXN1

C_PEG_TXN2

C_PEG_TXN3

C_PEG_TXN4

C_PEG_TXN5

C_PEG_TXN6

C_PEG_TXN7

C_PEG_TXN8

C_PEG_TXN9

C_PEG_TXN10

C_PEG_TXN11

C_PEG_TXN12

C_PEG_TXN13

C_PEG_TXN14

C_PEG_TXN15

C_PEG_TXP0

C_PEG_TXP1

C_PEG_TXP2

C_PEG_TXP3

C_PEG_TXP4

C_PEG_TXP5

C_PEG_TXP6

C_PEG_TXP7

C_PEG_TXP8

C_PEG_TXP9

C_PEG_TXP10

C_PEG_TXP11

C_PEG_TXP12

C_PEG_TXP13

C_PEG_TXP14

C_PEG_TXP15

R209 49.9/F_4R209 49.9/F_4

Can support reversal routing.If CFG9=1, PCI Express is normal operation. If CFG9=0, then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1 becomes PEG_TXP14, PEG_TXP2 becomes PEG_TXP13, etc. similarly for PEG_RXP[15:0] and PEG_RXN[15:0]

C309 0.1U/10V_4C309 0.1U/10V_4 C323 0.1U/10V_4C323 0.1U/10V_4 C629 0.1U/10V_4C629 0.1U/10V_4 C332 0.1U/10V_4C332 0.1U/10V_4 C330 EV@.1U/10V_4C330 EV@.1U/10V_4 C626 EV@.1U/10V_4C626 EV@.1U/10V_4 C336 EV@.1U/10V_4C336 EV@.1U/10V_4 C339 EV@.1U/10V_4C339 EV@.1U/10V_4 C351 EV@.1U/10V_4C351 EV@.1U/10V_4 C353 EV@.1U/10V_4C353 EV@.1U/10V_4 C356 EV@.1U/10V_4C356 EV@.1U/10V_4 C369 EV@.1U/10V_4C369 EV@.1U/10V_4 C376 EV@.1U/10V_4C376 EV@.1U/10V_4 C377 EV@.1U/10V_4C377 EV@.1U/10V_4 C391 EV@.1U/10V_4C391 EV@.1U/10V_4 C384 EV@.1U/10V_4C384 EV@.1U/10V_4

C311 0.1U/10V_4C311 0.1U/10V_4 C318 0.1U/10V_4C318 0.1U/10V_4 C632 0.1U/10V_4C632 0.1U/10V_4 C334 0.1U/10V_4C334 0.1U/10V_4 C324 EV@.1U/10V_4C324 EV@.1U/10V_4 C627 EV@.1U/10V_4C627 EV@.1U/10V_4 C338 EV@.1U/10V_4C338 EV@.1U/10V_4 C344 EV@.1U/10V_4C344 EV@.1U/10V_4 C346 EV@.1U/10V_4C346 EV@.1U/10V_4 C355 EV@.1U/10V_4C355 EV@.1U/10V_4 C363 EV@.1U/10V_4C363 EV@.1U/10V_4R426 IV@24.9_4R426 IV@24.9_4 C365 EV@.1U/10V_4C365 EV@.1U/10V_4 C371 EV@.1U/10V_4C371 EV@.1U/10V_4 C382 EV@.1U/10V_4C382 EV@.1U/10V_4 C396 EV@.1U/10V_4C396 EV@.1U/10V_4 C387 EV@.1U/10V_4C387 EV@.1U/10V_4

+1.05V

PEG_RXN[15:0] 18

PEG_RXP[15:0] 18,26

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

PEG_TXN[15:0] 18,26

PEG_TXP[15:0] 18,26

,9(9'LV(QDEOHVHWWLQJ

<5/31>Montevina_Schematics_Checklist_Rev0_8 a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But design guide Rev0.7 show NC.What is correct. b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA . CRT_HSYNC, CRT_VSYNCThese signals should be connected to GND. But design guide Rev0.7 show NC, Intel suggest follow Design guide.

<check list> For EV@ CRT R/G/B 0ohm to GND CRTIREF 0ohm to GND

<check list> For IV@ CRT R/G/B 150ohm to GND CRTIREF 1Kohm to GND

CRTIREF For IV: 1Kohm For EV:0ohm

R186 SP@1K/F_4R186 SP@1K/F_4

CRTIREF

SP@

CRT_R/G/B For IV: 150ohm For EV:0ohm

R179 SP@150_4R179 SP@150_4 R178 SP@150_4R178 SP@150_4 R180 SP@150_4R180 SP@150_4

INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

R413

EV@0_4

R412

EV@0_4

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

GMCH VGA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

1A

of

7Monday, July 12, 2010

43

5

4

3

2

1

08

M_A_DQ[63:0]16

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AJ38 AJ41 AN38

AM38

AJ36

AJ40 AM44 AM42

AN43

AN44

AU40

AT38

AN41

AN39

AU44

AU42

AV39

AY44

BA40

BD43

AV41

AY43

BB41

BC40

AY37

BD38

AV37

AT36

AY38

BB38

AV36

AW36

BD13

AU11

BC11

BA12

AU13

AV13

BD12

BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AN10 AM11

AM5

AJ9 AJ8

AN12 AM13

AJ11

AJ12

U20D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA_PM

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

AM37

SA_DM_0

AT41

SA_DM_1

AY41

SA_DM_2

AU39

SA_DM_3

BB12

SA_DM_4

AY6

SA_DM_5

AT7

SA_DM_6

AJ5

SA_DM_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS0 16 M_A_BS1 16 M_A_BS2 16

M_A_RAS# 16 M_A_CAS# 16 M_A_WE# 16

M_A_DM[7:0] 16

M_A_DQS[7:0] 16

M_A_DQS#[7:0] 16

M_A_A[14:0] 16

M_B_DQ[63:0]17

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK47 AH46 AP47 AP46

AJ46 AJ48

AM48

AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44

BG43

BF43 BE45 BC41 BF40 BF41

BG38

BF38 BH35

BG35

BH40 BG39 BG34

BH34

BH14 BG12

BH11

BG8 BH12 BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5 BA1 BD3 AV2 AU3 AR3 AN2

AY2 AV1 AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U20E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA_PM

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

AM47

SB_DM_0

AY47

SB_DM_1

BD40

SB_DM_2

BF35

SB_DM_3

BG11

SB_DM_4

BA3

SB_DM_5

AP1

SB_DM_6

AK2

SB_DM_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6

M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS0 17 M_B_BS1 17 M_B_BS2 17

M_B_RAS# 17 M_B_CAS# 17 M_B_WE# 17

M_B_DM[7:0] 17

M_B_DQS[7:0] 17

M_B_DQS#[7:0] 17

M_B_A[14:0] 17

A A

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

*0&+&$17,*$

5

Size Document Number Rev

GMCH DDRII

Date: Sheet

4

3

2

Date: Sheet

1

1A

of

43

of

43

of

43

8Monday, July 12, 2010

5

4

3

2

1

IV@

09

SP@

Power consumption reference to Intel 644135 Cantiga chipset EDS Volume1. Section 10

*07'3a: *67'3a:

D D

C C

B B

307'3:

+1.5V_SUS

+

C561

C558

22U/6.3V_8

9&&B609 ''50 P$B6P$B6 ''50P$B6 ''50P$B6

9 *UDSKLFVFRUH 9&&B$;* 9&&B$;*B1&7) P$

Voltage regulator is shared between the Gr aphics Core Rail, VCCA_HPLL,VCCA_MPLL,VCCA_PEG_PLLVCCD_PEG_PLL, VCCA_SM_CK, VCCA_DPLLA, VCCA_DPLLB, VCCD_HPLL, VCCA_SM, VCC_AXF

C414

0.1U/10V_4

IV@

+

C572

C572 330U/2V_7343

330U/2V_7343

+1.05V_AXG

R235 IV@10/F_4R235 IV@10/F_4 R230 IV@10/F_4R230 IV@10/F_4

+1.05V_AXG

AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21

AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15

AG15

AF15

AB15

AA15

AN14

AM14

AJ14

AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

U20G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+1.05V_AXG

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

IV@

+1.05V_AXG

+

C602

C602 IV@330U/2V_7343

IV@330U/2V_7343

Place close to the GMCH Cavity Capaci tors

Intel check list(Rev 0.8) 220U*2 near to NB(ESR=15m ohm) Intel CRB(Rev 0.7) 270U*4 near to power(+V1.05S). 330U*2 near to NB

1.8V Internal connect to power

C403

C418

0.1U/10V_4

+1.05V +1.05V_AXG

,9(9'LV(QDEOHVHWWLQJ

Design guide(Table 72) For INT VGA diasble.VCC_AXG power can connect to GND

Intel check list(Rev 0.8) No description for VCC_SM bulk CAP Intel CRB(Rev 0.7) 330U*1 Reserve near to power 330U*1 near to NB

R384 IV@0_8R384 IV@0_8 R381 IV@0_8R381 IV@0_8 R383 IV@0_8R383 IV@0_8

+

C601

C601 IV@330U/2V_7343

IV@330U/2V_7343

C417

0.22U/6.3V_4

C416

0.22U/6.3V_4

C399

C399 IV@0.47U/6.3V_4

IV@0.47U/6.3V_4

63#,96XWIIXI (9VWXIIRKP

C404

0.47U/6.3V_4

C392

C392 SP@1U/10V_6

SP@1U/10V_6

C415

C415 1U/6.3V_4

1U/6.3V_4

Intel check list(Rev 0.8) 270U*1 near to power(+V1.05M). 270U*2 near to NB Intel CRB(Rev 0.7) 270U*3 near to power(+V1.05M). 270U*1 near to NB ESR=12m ohm

+1.05V

C375

0.1U/10V_4

SP@

C367

C367 IV@10U/6.3V_8

IV@10U/6.3V_8

C413

C413 1U/6.3V_4

1U/6.3V_4

C379

0.22U/6.3V_4

C380

C380 IV@22U/6.3V_8

IV@22U/6.3V_8

C359

0.22U/6.3V_4

C393

C393 IV@0.1U/10V_4

IV@0.1U/10V_4

C381

C381 22U/6.3V_8

22U/6.3V_8

Place close to the GMCH

+

C631

C631 330U/2V_7343

330U/2V_7343

C410

C410 IV@0.1U/10V_4

IV@0.1U/10V_4

C370

C370 IV@0.1U/10V_4

IV@0.1U/10V_4

AG34 AC34 AB34 AA34

AM33 AK33

AJ33 AG33 AF33

AE33 AC33 AA33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

Y34 V34 U34

Y33

W33

V33 U33

T32

U20F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35

CANTIGA_PM

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

+1.05V

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

9&& 9&&B1&7) P$B(9 P$B,9 0((QJLQH P$ 7RWDO0D[ P$

CANTIGA_PM

A A

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VG FX_CORE_INT with 10ohm and VSS_AXG_SENSE PD with 10ohm for Intel suggest

*0&+&$17,*$

5

CANTIGA_PM

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

GMCH VCC,NCTF

Date: Sheet

4

3

2

Date: Sheet

1

1A

9Monday, July 12, 2010

of

43

of

43

of

43

5

Power consumption reference to Intel Cantiga chipset EDS Volume1. Section 10

IV@

EV@

SP@

D D

C C

3.3V

24.15mA for VCCA_TVA_DAC

39.48mA for VCCA_TVB_DAC

24.15mA for VCCA_TVC_DAC Total 87.78mA

B B

A A

1210 10UH, 10%

0.45A DCR_max = 0.39

5/12 UMA no stuff

+1.05V

1210 0.1uH, 20%, 1A, DCR_max=0.078ȍ

FB 180@100 MHz, 25% 1.5A DCR_max=90 m

CRB no 10U Check list need min 10U~100U for VCCA_TV_DAC

+1.5V

L51 IV@10uh_8L51 IV@10uh_8

9 P$IRU'3//B$%

1210 10UH, 10%

0.45A DCR_max = 0.39

L49 IV@10uh_8L49 IV@10uh_8

R397 *0/short_6R397 *0/short_6

L48 BLM18PG181SN1D_6L48 BLM18PG181SN1D_6

+1.05VM_MPLL_RC

C615

22U/6.3V_8

L53 IV@BKP1608HS181-T_6L53 IV@BKP1608HS181-T_6

+3V

C666

C666 IV@10U/6.3V_8

IV@10U/6.3V_8

R173 IV@0_6R173 IV@0_6

VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V

+1.5V

1.5V

48.363mA for CRT 5mA for TV

R175 *0/short_6R175 *0/short_6

FB 180@100 MHz, 25% 1.5A DCR_max=90 m

L32 BKP1608HS181-T_6L32 BKP1608HS181-T_6

C308

C308 10U/6.3V_8

10U/6.3V_8

CRB no 10U Check list need min 10U~100U for VCCA_QDAC

FB 220 @100 MHz, 25%, 2A

+1.05V

L47 BKP1608HS181-T_6L47 BKP1608HS181-T_6

+1.05VM_PEGPLL_RC

C618

C618 10U/6.3V_8

10U/6.3V_8

ESR=15 m

R393 0.5/F_6R393 0.5/F_6

+

C616

4.7U/6.3V_6

3.3V 79mA

1.5V 50mA

R392 1/F_4R392 1/F_4

+3V_CRT_TV_DAC

Modify 6/18 REV:B

,9(9'LV(QDEOHVHWWLQJ

63#,17XVH8 (;7XVHRKP

C333

C638

C638 IV@220U/6.3V_7343

IV@220U/6.3V_7343

C611

0.1U/10V_4

C650

C650 IV@0.1U/10V_4

IV@0.1U/10V_4

1.5V 35mA

C327

0.1U/10V_4

C345

0.1U/10V_4

C333

SP@0.1U/10V_4

1.05V

139.2mA

C609

0.1U/10V_4

+1.05V

63#,17XVH8 (;7XVHRKP

1.5V

0.5mA

1.05V 50mA

C644

EV@220U/6.3V_7343

ESR=15 m

+

If CRT have Flicker issue STUFF 5.6 ohm

R171 IV@BLM18PG181SN1D_6R171 IV@BLM18PG181SN1D_6

R429 IV@BLM18PG181SN1D_6R429 IV@BLM18PG181SN1D_6

VCCA_DPLLA/B always keep to +1.05V (If no use IV dynamic core power)

C635

SP@0.1U/10V_4

1.05V 24mA

R231 *0/short_6R231 *0/short_6

,9(9'LV(QDEOHVHWWLQJ

C648

SP@0.01U/25V_4

C319

SP@0.1U/10V_4

C335

0.01U/25V_4

C347

0.01U/25V_4

ESR=60m ohm

*0&+&$17,*$

5

4

3.9 nH, 0.2 nH, 1A , DCR_max=32 m

+1.05V

63#,17XVH8 (;7XVHRKP

C614

0.1U/10V_4

4

,9(9'LV(QDEOHVHWWLQJ

+3V_VCCA_CRT_DAC

C322

C328

IV@0.1U/10V_4

SP@0.01U/25V_4

63#,17XVH8 (;7XVHRKP

+3V_A_DAC_BG

C651

C647

IV@0.1U/10V_4

C647

SP@0.01U/25V_4

C653

C653 IV@10U/6.3V_8

IV@10U/6.3V_8

USE same GND plane

9 P$

R388 *0/short_8R388 *0/short_8

+1.5V

R233 *0/short_6R233 *0/short_6

1.05V DDR2-800 26mA

CRB : 0 ohm Check list : 2.2nH

1.05V DDR2-800 720mA

C663

C663 *IV@10U/6.3V_8

*IV@10U/6.3V_8

4/21 add

C610

0.1U/10V_4

+1.05VM_A_SM

C409

22U/6.3V_8

+1.05VM_A_SM_CK

C408

C408 *2.2U/6.3V_6

*2.2U/6.3V_6

C654

C654 *IV@10U/6.3V_8

*IV@10U/6.3V_8

C637

SP@1000P/50V_4

VCCA_PEG_PLL +1.25V for Teenah use(100mA)

VCCD_QDAC share to TV and CRT

R396 *0/short_6R396 *0/short_6

+1.05V

C613

0.1U/10V_4

+1.8V

1.05V

157.2mA

R202 IV@0_6R202 IV@0_6

1.8V

60.31mA

C606

0.1U/10V_4

,9(9'LV(QDEOHVHWWLQJ

63#,17XVH8 (;7XVHRKP

+VCCA_PEG_BG

+1.05VM_PEGPLL

C412

4.7U/6.3V_6

C406

22U/6.3V_8

+1.8VSUS_DLVDS

C312

C312 IV@10U/6.3V_8

IV@10U/6.3V_8

9 P$

9 P$

+1.05VM_DPLLA +1.05VM_DPLLB +1.05VM_HPLL +1.05VM_MPLL +1.8VSUS_TXLVDS

1.5V 414uA

1.05V 50mA

C402

C402 1U/6.3V_4

1U/6.3V_4

C405

0.1U/10V_4

+3V_CRT_TV_DAC

+VCC_HDA +1.5V_TVDAC

+1.5V_QDAC

+1.05VM_MCH_PLL2

+1.05VM_PEGPLL

B27 A26

A25 B25

F47

L48 AD1 AE1

J48

J47

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25

AN24 AM28 AM26 AM25

AL25 AM24

AL24 AM23

AL23

B24 A24

A32

M25

L28

AF1

AA47

M38

L37

C348

C348 SP@1U/6.3V_4

SP@1U/6.3V_4

3

U20H

VCCA_CRT_DAC_1 VCCA_CRT_DAC_2

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

VCCA_TV_DAC_1 VCCA_TV_DAC_2

VCC_HDA

VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL

VCCD_LVDS_1 VCCD_LVDS_2

CANTIGA_PM

Power Net Name

VCC_AXG_# VCC_AXG_NCTF_#

VCCA_PEG_BG

VCCA_DPLLA

VCCA_DPLLB

VCCA_SM_#

VCCA_HPLL

VCCA_MPLL

VCCA_SM_CK_#

VCCA_PEG_PLL

VCC_AXF_#

VCCD_HPLL

VCCD_PEG_PLL

3

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

HV

PEG

DMI

Cantiga(V)

1.05V

1.5V

1.05V

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15

VTT

VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

VCC_HV_1 VCC_HV_2 VCC_HV_3

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

VTTLF

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

2

C374

C362

0.47U/6.3V_4

2.2U/6.3V_6

1.05V

321.35mA

+1.05VM_AXF

+1.5VSUS_VCC_SM_CK

4/15 Modify

C575

0.1U/10V_4

C646

C646 1U/6.3V_4

1U/6.3V_4

,9(9'LV(QDEOHVHWWLQJ

+1.8VSUS_TXLVDS

63#,17XVHSI (;7XVHRKP

3.3V

105.3mA

1.05V 1782mA

1.05V 456mA

C617

C634

0.47U/6.3V_4

2

C603

0.1U/10V_4

C321

0.47U/6.3V_4

1.05V FSB-1067 852mA

+

C619

C360

4.7U/6.3V_6

C619 330U/2V_7343

330U/2V_7343

C361

4.7U/6.3V_6

ESR= 12m ohm

Check list : 0.1UH CRB : 0 ohm 1210 0.1 ?H, 20% 1A DCR max = 78 m

C652

C652 *10U/10V_8

*10U/10V_8

ESR = 60 m

C639

C639 SP@1000P/50V_4

SP@1000P/50V_4

+3V

C320

0.1U/10V_4

L52 *0/short_8L52 *0/short_8

1.8V DDR2-800 124mA

L44 1uh_8L44 1uh_8

+1.5VSUS_SMCK_RC

R3411/F_4 R3411/F_4

1.05V Internal connect to power

4/15 Modify

1.8V

118.8mA

L50 IV@0.1uh_6L50 IV@0.1uh_6

C643

IV@22U/6.3V_8

R176 10_4R176 10_4

C604

4.7U/6.3V_6

1

([WHUQDO*UDSKLFV *0&+,QWHJUDWHG*UDSKLFV'LVDEOH

VCCSYNC_CRT

VCCA_CRT_DAC

VCCD_LVDS

VCC_TX_LVDS

+1.05V

0805 1UH , Rdc = 0.14 - 0.26. Max rated current = 220 mA

+1.5V_SUS

C570 10U/6.3V_8C570 10U/6.3V_8

VCCA_LVDS

VCCA_TVDAC

VCCD_QDAC

VCCA_DAC_BG

VCC_AXG

VCC_AXG_NCTF

DDR3 +1.5V_SUS DDR2 +1.8V_SUS

0805 100 nH, DCR=160 m

+1.8V

+1.05V_SD

C605

22U/6.3V_8

D9 CH751D9 CH751

+1.05V

+

C625

C625 EV@220U/6.3V_7343

EV@220U/6.3V_7343

21

5/12 UMA no stuff

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

GMCH POWER

Date: Sheet

Date: Sheet of

1

+1.05V

10

GND

10Monday, July 12, 2010

of

1A

43

5

U20I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

D D

C C

B B

A A

AD47 AB47

N47

G47 BD46 BA46 AY46 AV46 AR46

AM46

V46 R46 P46 H46

F46 BF44 AH44 AD44 AA44

Y44

U44

T44

M44

F44 BC43 AV43 AU43

AM43

C43

BG42

AY42 AT42 AN42 AJ42 AE42

N42 BD41

AU41

AM41

AH41 AD41 AA41

Y41

U41

T41

M41 G41

B41

BG40

BB40 AV40 AN40

H40

E40 AT39

AM39

AJ39 AE39

N39

B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38

Y38

U38

T38

F38

C38 BF37 BB37

AW37

AT37 AN37 AJ37

H37

C37

BG36

BD36 AK15 AU36

Y47 T47

L47

J43

L42

L39

J38

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA_PM

VSS

*0&+&$17,*$

5

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

4

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

4

3

U20J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

M17

H17

C17 BA16 AU16

AN16

N16

K16

G16

E16 BG15 AC15

W15

A15 BG14 AA14

C14 BG13 BC13 BA13

AN13

AJ13

AE13

N13

L13 G13 E13

BF12

AV12

AT12 AM12 AA12

J12

A12 BD11 BB11

AY11 AN11 AH11

Y11 N11 G11 C11

BG10 AV10

AT10

AJ10 AE10 AA10

M10

BF9 BC9 AN9 AM9 AD9

G9

B9

BH8

BB8

AV8

AT8

3

VSS_230 VSS_231 VSS_232 VSS_233

VSS_235 VSS_237

VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CANTIGA_PM

VSS

VSS NCTF

VSS SCB

NC

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354 VSS_355

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4

VSS_SCB_6

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43

2

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29 AJ6

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1

A3 E1

D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

GMCH VSS

Date: Sheet

Date: Sheet of

2

Date: Sheet of

1

11

1A

of

43

11Monday, July 12, 2010

43

11Monday, July 12, 2010

43

1

11Monday, July 12, 2010

5

+VCCRTC

Internal pull-down resistors that are always enabled

SATA_LED#27

SATA_TXN127 SATA_TXP127

C594 15P/50V_4C594 15P/50V_4

C593 15P/50V_4C593 15P/50V_4

+1.5V

ACZ_SDIN029

23

Y3

32.768KHZ

4 1

R379 1M/F_6R379 1M/F_6 R364 330K/F_4R364 330K/F_4

R355 330K/F_4R355 330K/F_4

,QWHUQDO950HQDEOHGIRU 9FF6XVB9FF6XVB 9FF&/B9FF/$1BDQG 9FF&/B

+3V_S5

R378 10K_4R378 10K_4 R382 24.9/F_4R382 24.9/F_4

T23T23 T24T24

0.01u/16V_4C659 0.01u/16V_4C659

0.01u/16V_4C658 0.01u/16V_4C658

R363

R363 10M_6

10M_6

SM_INTRUDER#

ICH_GPIO56

HDA_BIT_CLK_R HDA_SYNC_R

HDA_RST#_R

HDA_SDIN2

HDA_SDOUT_R

SATA_TXN1_C SATA_TXP1_C

CLK_32KX1 CLK_32KX2

RTC_RST# SRTC_RST#

ICH_INTVRMEN LAN100_SLP

ICH9M

IV@

EV@

D D

24.9 Ohm pull up to 1.5V for GLAN_COMPI/O is required, no matter intel LAN is used or not.

C C

SATA_RXN127

ODD (S ATA)

SATA_RXP127

4

U23A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9MREV1.0

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

SATA4RXN

IHDA

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

INIT# INTR

NMI

SMI#

TP8

K5 K4 L6 K2

K3 J3

J1 N7

AJ27 AJ25

AE23 AJ26

H_FERR#_R

AD22 AF25 AE22

AG25 L3

AF23 AF24

AH27 AG26

H_THERMTRIP_R

AG27

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18

AJ7 AH7

SATABIAS L<0.5"

T38T38 T122T122

SATA_TXN0_C SATA_TXP0_C

SATA_RBIAS_PN

3

LDRQ0/1# : Internal PU

R211 8.2K_4R211 8.2K_4

R463 56_4R463 56_4

R219 10K_4R219 10K_4

R421 54.9/F_4R421 54.9/F_4

T22T22

CLK_PCIE_SATA 2

R170

24.9/F_4

+3V

0.01u/16V_4C661 0.01u/16V_4C661

0.01u/16V_4C660 0.01u/16V_4C660

SATA HDD

CLK_PCIE_SATA# 2

LAD0 28,35 LAD1 28,35 LAD2 28,35 LAD3 28,35

LFRAME# 28,35

GATEA20 35 H_A20M# 3

H_PWRGD 3 H_IGNNE# 3 H_INIT# 3

H_INTR 3

RCIN# 35 H_NMI 3 H_SMI# 3

H_STPCLK# 3

H_THERMTRIP_RR

4/21 Modify andy

SATA_RXN0 27 SATA_RXP0 27 SATA_TXN0 27 SATA_TXP0 27

2

+1.05V

R443

R443 *56_4

*56_4

R430 56_4R430 56_4 R420 *0_4R420 *0_4

No use Thermal trip SB sid e still PU 56ohm.(Serial R use 0ohm) Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm) PU L<2"

Intel ICH9M

Layout note:

R406

DPRSTP# , Daisy Chain

*56_4

(SB>Power>NB>CPU)

ICH_DPRSTP# 3,6,39 H_DPSLP# 3

+1.05V

AJSLB8Q0T03

PM_THRMTRIP# 3,6

+1.05V

R442

R442 56_4

56_4

1

12

H_FERR# 3

HD Audio

B B

HDA_SDOUT_R

Weak integrated PD on the HDA_SDOUT pin.

HDA_SYNC_R

R471 IV@33_4R471 IV@33_4 R478 33_4R478 33_4

R472 IV@33_4R472 IV@33_4 R479 33_4R479 33_4

Weak integrated PD on the HDA_SYNC pins

HDA_SDOUT_HDMI 6 ACZ_SDOUT_AUDIO 29

C671

C671 *10P/50V_4

*10P/50V_4

HDA_SYNC_HDMI 6

ACZ_SYNC_AUDIO 29 ACZ_RST#_AUDIO 29

C672

C672 *10P/50V_4

*10P/50V_4

HDA_BIT_CLK_R

24.000 MHz is output from the ICH9M.

R470 IV@33_4R470 IV@33_4 R477 33_4R477 33_4

HDA_RST#_R

HDA_SDIN2

C668

C668 *10P/50V_4

*10P/50V_4

R473 IV@33_4R473 IV@33_4 R483 33_4R483 33_4

R166 IV@0_4R166 IV@0_4

HDA_BIT_CLK_HDMI 6 ACZ_BITCLK_AUDIO 29

C664

C664 *10P/50V_4

*10P/50V_4

HDA_RST#_HDMI 6

HDA_SDIN_HDMI 6

South Bridge Strap Pin (1/ 3)

Pin Name

HDA_DOCK_EN/ GPIO33

A A

SATALED#

TP3

HDA_SDOUT

Strap description

Flash Descriptor Security Override Strap

PCI Express Lane Reversal (Lanes 1-4)

XOR Chain Entrance

XOR Chain Entrance /PCI Express* Port Config 1 bit 1(Port 1- 4)

5

Sampled

PWROK

Configuration PU/PD

0 = The Flash Descriptor Security will be overridd en. 1 = The security measures defined in the Flash Descriptor will be in effect

Internal PU

ICH_TP3

HDA_SDOUT

0

0 0

11

4

RSVD Enter XOR Chain

1

Normal opration(Default)

01

Set PCIE port config bit 1

Description

This strap should only be enabled in manufacturing environments using an external pull-up resistor.

ICH_TP314

HDA_SDOUT_R

ICH_TP3

3

R370 *1K_4R370 *1K_4

R440 *1K_4R440 *1K_4

+3V

RTC

Pjt: BCBAT54CZ04 Ons: BCBAT54CZ70

+3VPCU

VCCRTC_1

20MIL

R495

R495 1K_4

1K_4

1 3

VCCRTC_2

20MIL

CN13

1

2

RTC_CONN

Pitch: 1,25mm; Height: 1. 95mm

Change type 4/21 (ZQ7)

2

D28

BAT54C

2

RTC_N01

Q21

*MMBT3904

RTC_N03

+VCCRTC

20MIL

R480 *16K_6R480 *16K_6

RTC_RST#

1

C667

C667 1U/10V_4

1U/10V_4

C699

C699 1U/10V_4

1U/10V_4

SRTC_RST#

12

RTC_RST#

12

2

G2

*SHORT_PAD

G3

*SHORT_PAD

3

Q22

1

DMN601K-7

of

12Monday, July 12, 2010

R489 20K_6R489 20K_6

C675

C675 1U/10V_4

1U/10V_4

R497 20K_6R497 20K_6

+5VPCU

R481

R481 *68.1K/F_4

*68.1K/F_4

R482

R482 *150K/F_6

*150K/F_6

Size Document Number Rev

Date: Sheet

Date: Sheet of

RTC_EC35

352-(&7=4

4XDQWD&RPSXWHU,QF

ICH9M HOST

1A

43

5

4

3

2

1

ICH9M

U23D

N29

PERN1

PCIE_TXN4_C PCIE_TXP4_C

GLAN_TXN_SB GLAN_TXP_SB

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9MREV1.0

PCI-Express

DMI_IRCOMP

SPI

USB

U23B

D11

AD0

C8 D9

E12

E9 C9

E10

B7

INTA# INTB# INTC# INTD#

C7 C5

G11

F8

F11

E7 A3 D2

F10

D5

D10

B3 F7 C3 F3 F4 C1

G7

H7 D1

G5

H6

G1

H3

E1 C4

D D

T116T116 T115T115 T124T124 T106T106

C C

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

J5

PIRQA# PIRQB#

J6

PIRQC# PIRQD#

ICH9MREV1.0

REQ1#/GPIO50

GNT1#/GPIO51

REQ2#/GPIO52

GNT2#/GPIO53

REQ3#/GPIO54

GNT3#/GPIO55

PIRQE#/GPIO2

PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

REQ0# GNT0#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP# TRDY#

FRAME#

PLTRST#

PCICLK

PME#

F1 G4 B6 A7 F13 F12 E6 F6

D8 B4 D6 A5

D3 E3

PAR

R1 C6 E4 C2 J4 A4 F5 D7

C14 D4 R2

PME# inter nal PU 18K~42K

H4

INTE#

K6

INTF#

F2

INTG#

G2

INTH#

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#

IRDY# PCIRST#

DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME#

PLT_RST#

For EMI

5/12 Add

PCLK_ICH

T111T111 T40T40 T100T100 T107T107 T102T102 T103T103 T104T104 T41T41

T113T113

T109T109 T114T114 T110T110 T120T120 T105T105 T117T117 T101T101

T121T121 T123T123 T118T118 T119T119

C579 *33p/50V_4C579 *33p/50V_4

PCIRST# 28

PLT_RST# 6 PCLK_ICH 2

WLAN

GLAN

PCIE_RXN428 PCIE_RXP428

PCIE_TXN428

PCIE_TXP428

GLAN_RXN31 GLAN_RXP31 GLAN_TXN31 GLAN_TXP31

4/22 add it

USBOC#628

USBOC#1028

C385 0.1U/10V_4C385 0.1U/10V_4 C386 0.1U/10V_4C386 0.1U/10V_4

C401 0.1U/10V_4C401 0.1U/10V_4 C398 0.1U/10V_4C398 0.1U/10V_4

T48T48 T50T50

T51T51

SPI_CLK_R SPI_CS0#_R SPI_CS1#

SPI_MOSI SPI_MISO

USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9 USBOC#10 USBOC#11

SB_USBBIAS

4/26 add it

R172

22.6/F_4

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB27

DMI2RXN

AB26

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

T25

DMI_CLKP

Direct Media Interface

AF29

DMI_ZCOMP

AF28

DMI_IRCOMP_R

AC5

USBP0N

AC4

USBP0P

AD3

USBP1N

AD2

USBP1P

AC1

USBP2N

AC2

USBP2P

AA5

USBP3N

AA4

USBP3P

AB2

USBP4N

AB3

USBP4P

AA1

USBP5N

AA2

USBP5P

W5

USBP6N

W4

USBP6P

Y3

USBP7N

Y2

USBP7P

W1

USBP8N

W2

USBP8P

V2

USBP9N

V3

USBP9P

U5

USBP10N

U4

USBP10P

U1

USBP11N

U2

USBP11P

DMI_RXN0 6 DMI_RXP0 6 DMI_TXN0 6 DMI_TXP0 6

DMI_RXN1 6 DMI_RXP1 6 DMI_TXN1 6 DMI_TXP1 6

DMI_RXN2 6 DMI_RXP2 6 DMI_TXN2 6 DMI_TXP2 6

DMI_RXN3 6 DMI_RXP3 6 DMI_TXN3 6 DMI_TXP3 6

CLK_PCIE_ICH# 2 CLK_PCIE_ICH 2

R409 24.9/F_4R409 24.9/F_4

USBP0- 28 USBP0+ 28

USBP1- 33 USBP1+ 33 USBP2- 28 USBP2+ 28

USBP3- 28

USBP3+ 28

USBP4- 28

USBP4+ 28

USBP6- 28

USBP6+ 28

USBP7- 28

USBP7+ 28

USBP11- 25 USBP11+ 25

+1.5V

EXT-USB CardReader EXT-USB Bluetooth 3.0 Wireless

INT-USB Bluetooth 2.1

CAMERA

L<0.5",Avoid routing next to clock/high speed signals.

13

6/14 Modify

+3V

South Bridge Strap Pin (2/3)

C400

0.1U/10V_4

B B

A A

LOCK#

7

INTD#

8

REQ3#

9

DEVSEL# REQ1#

10

+3V

INTF# INTC# INTE# SERR#

+3V

PERR#

+3V

6 7 8 9

10

6 7 8 9

10

8.2K_10P8R

RN18

8.2K_10P8R

RN17

8.2K_10P8R

5/11 Swap

RN16

6

+3V

5 4

REQ2#

3

FRAME#

2 1

STOP#

+3V

5 4 3 2

INTH#

1

INTG#

+3V

5 4

IRDY#

3

INTB#REQ0#

2

INTA#

1

TRDY#

5

PLT_RST#

USBOC#0 USBOC#6 USBOC#4 USBOC#7

+3V_S5

USBOC#10 USBOC#11 USBOC#8 USBOC#9

2 1

3 5

RN19

6 7 8 9

10

10K_10P8R

RN20

6 4 2

10K_8P4R

5/11 Swap

4

U19

U19 TC7SH08FU

TC7SH08FU

5 4 3 2 1

78 5 3 1

4

R354

R354 100K_4

100K_4

USBOC#1 USBOC#5 USBOC#2 USBOC#3

PLTRST# 28,31,33,35

+3V_S5

Pin Name Strap description

HDA_SYNC

GNT2# / GPIO53 PWROK

GNT1# / GPIO51

GNT3# / GPIO55

SPI_MOSI

GNT0#

SPI_CS1# / GPIO58 / CLGPIO6

3

PCI Express Port Config 1 bit 0 (Port 1-4)

PCI Express Port Config 2 bit 2 (Port 5-6)

ESI Strap(Server Only)

Top-Block Swap Override

Integrated TPM Enable

Boot BIOS Selection 0

Sampled

PWROK

CLPWROK

PWROK

CLPWROKBoot BIOS Selection 1

Configuration PU/PD

0 = Default 1 = Setting bit 0

0 = Setting bit 2 1 = Default

0 = DMI for ESI-compatible 1 = Default

0 = "top-block swap" mode 1 = Default

0 = INT TPM disable(Default) 1 = INT TPM enable

10

01

11

Boot Location

SPI

PCI

LPC(Default)

Size Document Number Rev

Date: Sheet

SPI_CS#1PCI_GNT#0

2

GNT3#

R237 *1K_4R237 *1K_4

SPI_MOSI

R380 *10K_4R380 *10K_4

GNT0#

R236 *1K_4R236 *1K_4

SPI_CS1#

R234 *1K_4R234 *1K_4

352-(&7=4

4XDQWD&RPSXWHU,QF

ICH9M PCIE / PCI / USB

1

+3V_S5

1A

of

43

of

43

of

43

13Monday, July 12, 2010

+3V_S5

R357 10K_4R357 10K_4 R356 10K_4R356 10K_4 R366 2.2K_4R366 2.2K_4 R367 2.2K_4R367 2.2K_4 R225 10K_4R225 10K_4 R375 10K_4R375 10K_4

D D

C C

R224 10K_4R224 10K_4 R376 10K_4R376 10K_4 R223 10K_4R223 10K_4 R368 8.2K_4R368 8.2K_4 R403 *10K_4R403 *10K_4 R358 10K_4R358 10K_4 R360 10K_4R360 10K_4

+3V

R218 8.2K_4R218 8.2K_4 R217 10K_4R217 10K_4 R445 8.2K_4R445 8.2K_4 R359 10K_4R359 10K_4

R390 *10K_4R390 *10K_4 R444 *10K_4R444 *10K_4 R439 10K_4R439 10K_4 R448 10K_4R448 10K_4 R240 10K_4R240 10K_4 R221 10K_4R221 10K_4

+3V_S5

R351 10K_4R351 10K_4 R352 *100/F_4R352 *100/F_4

R449 10K_4R449 10K_4 R222 10K_4R222 10K_4

5

4/20 Modify

SMB_CLK_ME SMB_DATA_ME PCLK_SMB PDAT_SMB RI# ICH_GPIO60 RI# SYS_RST#

SMB_ALERT#

PCIE_WAKE# PM_BATLOW# DNBSWON# ICH_GPIO12 ICH_GPIO13

CLKRUN# SERIRQ THERM_ALERT# KBSMI#_ICH EC_SCI#

SATACLKREQ# MCH_ICH_SYNC# KBSMI#_ICH LID591#_ICH PM_STPPCI# PM_STPCPU#

GPIO57

CR_WAKE# ICH_PWROK

PWRBTN : 16 ms of internal debounce logic on this pin and internal PU 24K

Stuff at GEN

TPM Physical Presence for iTPM.

'$$6)LVVXHZKHQL$07LVQRWLPSOHPHQWHG ,&+060%XVDQG60/LQNVKRXOGEHFRQQHFWHGWRJHWKHUWRVXSSRUWVODYHPRGH &RQQHFW60/,1.WR60%&/.DQG60/,1.WR60%'$7$$GG55IRUGHEXJXVH

PCLK_SMB2,16,28 PDAT_SMB2,16,28

SYS_RST#3 PM_SYNC#6

PM_STPPCI#2 PM_STPCPU#2

PCIE_WAKE#28,31

THERM_ALERT#3

SATACLKREQ#2

MCH_ICH_SYNC#6

ICH_TP312

4

U23C

PCLK_SMB PDAT_SMB ICH_GPIO60

T54T54

T132T132

T98T98 T45T45

T129T129 T128T128

T130T130 T133T133 T131T131

T34T34

SMB_CLK_ME SMB_DATA_ME

SYS_RST#

SMB_ALERT# PM_STPPCI#

PM_STPCPU# CLKRUN# PCIE_WAKE# THERM_ALERT#

VR_PWRGD_CLKEN

LID591#_ICH

ICH_GPIO12 ICH_GPIO13 BOARD_ID0 BOARD_ID1 PANEL_ID1 BOARD_ID3

SATACLKREQ# CR_WAKE# ICH_GPIO39 ICH_GPIO48 DMI_TERM_SEL GPIO57

MCH_ICH_SYNC#

ICH_TP3

4/20 Modify

CLKRUN#35

SERIRQ35

KBSMI#35 LID591#25,35

EC_SCI#35

D26 BAS316D26 BAS316 D27 BAS316D27 BAS316

5/7 Modify

PCSPK29

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP12

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

LAN_PHY_PWR_CTRL/GPIO12

C21

ENERGY_DETECT/GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP9

AJ20

TP10

AJ21

TP11

ICH9MREV1.0

3

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

GPIO

SATA

SMB

Clocks

SYS GPIO

Power MGTController Link

GPIO

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

MISC

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW# PWRBTN# LAN_RST# RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

6$7$>[@*3SLQVLIXQXVHGUHTXLUH NWRNSXOOXSWR9FFBRU NWRNSXOOGRZQWRJURXQG

AH23

BOARD_ID2

AF19

PANEL_ID0

AE21

ICH_GPIO36

AD20

ICH_GPIO37

H1

14M_ICH

AF3

CLKUSB_48

P1 C16

E16 G17

C10 G20

ICH_PWROK

M2 B13

PM_BATLOW#

R3 D20

PM_LAN_ENABLE_R

D22

PM_RSMRST#_R

R5 R6 B16 F24

B19 F22

C19 C25

CL_VREF0_SB

A19

CL_VREF1_SB

F21 D18

A16 C18

ICH_GPIO10

C11

ICH_GPIO14

C20

ICH_GPIO9

=6'HIDXOWQRW VXSSRUW,$076RWKLV LQWHUIDFHIROORZ &5%&KHFNOLVW38 RQO\

R181 10K_4R181 10K_4 R446 10K_4R446 10K_4 R408 10K_4R408 10K_4

T36T36 T99T99

R372 *0/short_4R372 *0/short_4 R361 *0_4R361 *0_4

T53T53

T46T46

T49T49

T42T42 T52T52

R374 10K_4R374 10K_4 R377 10K_4R377 10K_4 R371 10K_4R371 10K_4

2

14M_ICH 2 CLKUSB_48 2

ICH_SUSCLK 35 SUSB# 6,35

SUSC# 6,35

PM_DPRSLPVR 6,39

DNBSWON# 35

PM_RSMRST#_R

CK_PWRGD 2 MPWROK 6,35

CL_CLK0 6

CL_DATA0 6

CL_RST#0 6

+3V_S5

+3V

4/14 Modify

1

14

C407

C407 *10p/50V_4

*10p/50V_4

<Checklist ver0.8> The ICH9M Controller Link 1 VREF circuit is required only if Intel AMT is to be supported.

+3V+3V

For EMI

C325

C325 *10p/50V_4

*10p/50V_4

R256

3.24K/F_6

R255

R255 453/F_4

453/F_4

CLKUSB_48 14M_ICH

<Checklist ver0.8> If integrated LAN is not used LAN_RST# tie it to GND.NC serial R from RSMRST#. If Intel LAN i s used with Wake On LAN, t ie LAN_RST# to RSMRST# and NC 0ohm.

CL_PWROK must not assert after PWROK asserts for IAMT. CL_PWROK to the NB and SB should be connected to existing PWROK inputs on the NB and SB on a platform with no IAMT

CL VREF

VREF1 CRB connect to +3V_S5 Checklist connect to +3V(iAMT reserve)

R353

R353 *3.24K/F_6

*3.24K/F_6

CL_VREF0_SBCL_VREF1_SB

C584

R373

*0.1U/10V_4

*453/F_4

C436

0.1U/10V_4

Add 4/19

+3V_S5

R369 *10K_4R369 *10K_4

B B

+3V

R451 10K_4R451 10K_4 R462 10K_4R462 10K_4 R447 10K_4R447 10K_4

EC_SCI#

PANEL_ID1 ICH_GPIO39 ICH_GPIO48

Follow CHECK LIST V1.5

ICH PWROK

+3V_S5

C582 *0.1U/10V_4C582 *0.1U/10V_4

4

ICH_PWROK

U16

TC7SH08FU

'(/$<B95B3:5*22'QHHG38.WR9 =638DWSRZHUVLGH

53

1 2

PWROK_EC

R333 100K_4R333 100K_4

DELAY_VR_PWRGOOD 3,6,39 PWROK_EC 35

South Bridge Strap Pin (3/3)

Pin Name Strap description

A A

GPIO20

SPKR

GPIO49

Reserved PWROK

No Reboot PWROK

DMI Termination Voltage

5

Sampled

PWROK

Configuration PU/PD

0 = Default 1 = No Reboot mode

0 = for desktop applications 1 = for mobile applications Internal PU

PCSPK

DMI_TERM_SEL

4

R216 *1K_4R216 *1K_4

R464 *1K_4R464 *1K_4

+3V

Resume RST

CLK Enable

3

PM_RSMRST#_R

VR_PWRGD_CK410#39

R362

R362 10K_4

10K_4

R238

2.2K_4

3 1

2

3

1 2

3

1

1 2

Q11

MMBT3906

R248 4.7K_4R248 4.7K_4

D14

BAV99

ZD1 INTEL FAE (08/17)

D12

"A dd RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"

BAV99

Default stuff for Teenah(Interposer) chipset ZS2 Intel FAE suggestion to add for to protect RTC/CMOS data from corruption when system encounters an abnormal power down sequence

+3V

C439

C439 *0.1U/10V_4

5 43

VR_PWRGD_CLKEN

*0.1U/10V_4

R350

R350 100K_4

100K_4

U18

NC7SZ04

RSMRST# 35

+3V_S5

4/20 Modify

2

M/B ID

+3V+3V +3V+3V

R467

R467 *10K_4

*10K_4

R468

R468 10K_4

10K_4

R466

R466 *10K_4

*10K_4

BOARD_ID2BOARD_ID3 BOARD_ID0BOARD_ID1

R465

R465 10K_4

10K_4

R389

R389 *10K_4

*10K_4

R385

R385 10K_4

10K_4

ID2ID3

default

0000

000

00

1

000

352-(&7=4

4XDQWD&RPSXWHU,QF

Size Document Number Rev

ICH9M GPIO

Date: Sheet

1

R469

R469 *10K_4

*10K_4

R450

R450 10K_4

10K_4

14Monday, July 12, 2010

ID0ID1Board ID

1

0

1

1A

of

43

of

43

of

43