Acer Aspire 4625, Aspire 4625G Schematics

1

2

3

4

5

6

7

8

VER : 1A

=4 % 62/( 80$ 6<67(0 ',$*5$0

BOM P/N

Description

Model

SidePort

ODD

'DQXEH 3ODWIRUP

AMD Champlain

31ZQ2MB00A0

ZQ2B 6L JM MB (W/GRN,SAM,W/O CPU)ASSY

JM

Sansung

Slim

DDR3SODIMM1

DDR3 channel A

CPU THERMAL

PWM FAN SCH.

CPU (PROCHOT)

0DLQ 6WUHDP

31ZQ2MB00E0

ZQ2B 6L JM MB (W/GRN,HYU,W/O CPU)ASSY

JM

Hynix

Slim

PAGE 5

S1G4 Processor

SENSOR

E.C. (CPUFAN#)

35mm X 35mm

(Reserve Only)

PAGE 24

A

Standard

PAGE 4

A

31ZQ2MB00H0

ZQ2B 6L JV MB (W/GRN,W/O CPU,VRAM)ASSY

JV

No Support

DDR3SODIMM2

DDR3 channel B

638P (PGA) 35W

CPU_CLK

From SB

PAGE 5

PAGE 2,3,4

CLK_PCI_775

NBGFX_CLK

NBGPP_CLK

CLK GEN

PCB STACK UP

CPU SideBand TemperatureSense I2C

HT3

SBLINK_CLK

SB820M

PCLK_DEBUG

PAGE 10

*+]

LAYER 1 : TOP

LAYER 2 : GND

LAYER 3 : IN1

PCI-Expresss

NORTH BRIDGE

6LGH 3RUW

gDDR3 VRAM

25MHz

32.768KHz

LAYER 4 : IN2

''5 ,,, 0+]

PAGE 6

LAYER 5 : VCC

P0

P2

RS880M GFX Engine: 500MHz

LAYER 6 : BOT

LAN

Mini PCI-E

A11

+'0,

HDMI

Atheros

Card

PAGE 16

IV@ -----> iGPU

B

PCIE-LAN

B

SP@ -----> Option Notice

AR8151

(Wireless LAN)

PP ; PP SLQ %*$

SIDE@ -----> SidePort VRAM

&57

CRT

(10/100/1000)

PAGE 15

GA@ ----> Green Adapter (Default stuff)

TDP: 13W

PAGE 17

PAGE 18

25MHz

0.95 ~ 1.1V

/9'6

PAGE 6,7,8,9

LVDS

RJ45

PAGE 23

Sideport-L75,L76,R583,R392,C832,R455,R550,R502

A-LINK

NB A11-R105,R108

PAGE 17

SB A12-R267,R271

JV/JM-CN16,R450,R456

EC-D8,D27

SOUTH BRIDGE

UMA-R461

SATA - HDD

SATA0 150MB

SB820M

VRAM-R358,R359,R360,R363,R365,R72

PAGE 19

*E V

P0

P9

P13

FFC

A12

USB2.0 Port

Blue Tooth

Web-Camera

SATA - ODD

SATA1 150MB

P8, 11, 12

on board x1

C

CHARGER (ISL88731A)

PP ; PP SLQ %*$

PAGE 22

PAGE 15

C

*E V

PAGE 30

USB BOARD

PAGE 26

PAGE 19

AMD CPU CORE (ISL6265)

I/F

P4

P10

USB2.0 Ports x3

CPU

PCI

Mini Card

CardReader

PAGE 22

PAGE 28

No

PCLK_DEBUG

WLAN & Debug

AU6347

TDP: 4.9W

PAGE 18

PAGE 21

Power BOARD

NB_CORE (UP6111AQDD)

PAGE 10,11,12,13, 14

FFC

PAGE 22

PAGE 30

NB

LPC

Azalia

0.9V/DDR 1.5V(RT8207)

12MHz

Switch BOARD

CLK_PCI_775

Winbond KBC

Audio CODEC

FFC

PAGE 31

PAGE 22

CPU SideBand TemperatureSense I2C

NPCE781L &

RTL ALC271X

Green Adapter

There are three Daughter boards.

SYSTEM 5V/3V (RT8206)

PAGE 25

PAGE 20

D

PAGE 27

SSID: 035E D

1.1V(UP6111AQDD)

SVID: 1025

PAGE 29

Green ADP.

Keyboard

SPI ROM

Digital MIC

AUDIO CONN

Speaker CN

352-(&7 =4

TouchPad

(H.P./ MIC)

4XDQWD &RPSXWHU ,QF

Discharge /Thermal protec

PAGE 25

PAGE 24

PAGE 25

PAGE 15 & 20

PAGE 20

PAGE 20

PAGE 32

Size

Document Number

Rev

http://hobi-

Date:

Thursday, March 04, 2010 Sheet

1 of

36

elektronika.net

Block Diagram

1A

1

2

3

4

5

6

7

8

5

4

3

2

1

S1G4 (CPU)

+2.5V

BLM21PG221SN1D(220,100M,2A)_8

W/S= 15 mil/20mil

+CPUVDDA

+1.5V

L41

+CPUVDDA

CPU CLK

CPU_LDT_RST#

300/F_4

R301

1.1V@1.5A

2.5V@250mA

C374

LS0805-100M-N

C368

C367

C369

C373

CLK_CPU_BCLKP_PR

CPU_LDT_REQ#_CPU

*300/F_

4

R298

+1.1V

+1.1V_VLDT

[10] CLK_CPU_BCLKP_PR

CPU_LDT_STOP#

300/F_4

R120

4.7u/6.3V_6

4.7u/6.3V_6

.22u/6.3V_4

3300p/50V_4

*10u/6.3V_8

CLK_CPU_BCLKN_PR

[10] CLK_CPU_BCLKN_PR

R108

0_

6

Keep trace from resisor to CPU within 0.6"

+CPUVDDA 250mA

R109

0_6

U17A

keep trace from caps to CPU within 1.2"

U17D

W/S= 15 mil/20mil

HT LINK

+CPUVDDA

F8

VDDA1

VSS

M11

C316

10u/6.3V_8

+1.1V_VLDT

D1

AE2

+1.1V_VLDT

10u/6.3V_8

C161

CLK_CPU_BCLKP_C

R292

169/F_4

CLK_CPU_BCLKN_C

+CPUVDDA

F9

W18

VLDT_A0

VLDT_B0

VDDA2

RSVD11

C158

10u/6.3V_8

+1.1V_VLDT

D2

AE3

+1.1V_VLDT

.22u/6.3V_4

C334

D

VLDT_A1

VLDT_B1

C162

.22u/6.3V_4

+1.1V_VLDT

D3

AE4

+1.1V_VLDT

180p/50V_4

C320

CLK_CPU_BCLKP_PR

C370

3900p/25V_4

CLK_CPU_BCLKP_C

A9

A6

CPU_SVC

VLDT_A2

VLDT_B2

CLKIN_H

SVC

C336

180p/50V_4

+1.1V_VLDT

D4

AE5

+1.1V_VLDT

CLK_CPU_BCLKN_PR

C371

3900p/25V_4

CLK_CPU_BCLKN_C

A8

A4

CPU_SVD

VLDT_A3

VLDT_B3

CLKIN_L

SVD

HT_CADINP0

E3

AD1

HT_CADOUTP0

CPU_LDT_RST#

B7

[6]

HT_CADINP0

HT_CADINN0

E2

L0_CADIN_H0

L0_CADOUT_H0

AC1

HT_CADOUTN0

HT_CADOUTP0

[6]

[10] CPU_LDT_RST#

CPU_PWRGD

A7

RESET_L

[6]

HT_CADINN0

L0_CADIN_L0

L0_CADOUT_L0

HT_CADOUTN0

[6]

[10,28]

CPU_PWRGD

PWROK

HT_CADINP1

E1

AC2

HT_CADOUTP1

CPU_LDT_STOP#

F10

AF6 CPU_THERMTRIP_L#

[6]

HT_CADINP1

L0_CADIN_H1

L0_CADOUT_H1

HT_CADOUTP1

[6]

[8,10]

CPU_LDT_STOP#

LDTSTOP_L THERMTRIP_L

HT_CADINN1

F1

AC3

HT_CADOUTN1

CPU_LDT_REQ#_CPU

C6

AC7

CPU_PROCHOT_L#

[6]

HT_CADINN1

L0_CADIN_L1

L0_CADOUT_L1

HT_CADOUTN1

[6]

LDTREQ_L

PROCHOT_L

HT_CADINP2

G3

AB1

HT_CADOUTP2

AA8

[6]

HT_CADINP2

L0_CADIN_H2

L0_CADOUT_H2

HT_CADOUTP2

[6]

MEMHOT_L

HT_CADINN2

G2

AA1

HT_CADOUTN2

SideBand Temp sense I2C

AF4

[6]

HT_CADINN2

L0_CADIN_L2

L0_CADOUT_L2

HT_CADOUTN2

[6]

[4]

CPU_SIC

SIC

HT_CADINP3

G1

AA2

HT_CADOUTP3

AF5

[6]

HT_CADINP3

L0_CADIN_H3

L0_CADOUT_H3

HT_CADOUTP3

[6]

[4]

CPU_SID

SID

HT_CADINN3

H1

AA3

HT_CADOUTN3

CPU_ALERT#

AE6

W7

[6]

HT_CADINN3

L0_CADIN_L3

L0_CADOUT_L3

HT_CADOUTN3

[6]

T9

ALERT_L

THERMDC

H_THRMDC

[4]

HT_CADINP4

J1

W2

HT_CADOUTP4

Eliot (02/26)

W8

[6]

HT_CADINP4

L0_CADIN_H4

L0_CADOUT_H4

HT_CADOUTP4

[6]

THERMDA

H_THRMDA

[4]

[6]

HT_CADINN4

HT_CADINN4

K1

L0_CADIN_L4

L0_CADOUT_L4

W3

HT_CADOUTN4

HT_CADOUTN4

[6]

Current Agesa bios

R67

44.2/F_4

CPU_HTREF0

R6

HT_REF0

HT_CADINP5

L3

V1

HT_CADOUTP5

doesnˇt program

+1.1V_VLDT

R62

44.2/F_4 CPU_HTREF1

P6

[6]

HT_CADINP5

HT_CADINN5

L2

L0_CADIN_H5

L0_CADOUT_H5

U1

HT_CADOUTN5

HT_CADOUTP5

[6]

HT_REF1

[6]

HT_CADINN5

L0_CADIN_L5

L0_CADOUT_L5

HT_CADOUTN5

[6]

ALERT_L and SB wonˇt

place them to CPU within 1.5"

HT_CADINP6

L1

U2

HT_CADOUTP6

process alert.

F6

W9

VDDIO_FB_H

[6]

HT_CADINP6

L0_CADIN_H6

L0_CADOUT_H6

HT_CADOUTP6

[6]

[28]

CPU_VDD0_FB_H

VDD0_FB_H

VDDIO_FB_H

T4

HT_CADINN6

M1

U3

HT_CADOUTN6

E6

Y9

VDDIO_FB_L

[6]

HT_CADINN6

L0_CADIN_L6

L0_CADOUT_L6

HT_CADOUTN6

[6]

[28]

CPU_VDD0_FB_L

VDD0_FB_L

VDDIO_FB_L

T8

HT_CADINP7

N3

T1

HT_CADOUTP7

[6]

HT_CADINP7

L0_CADIN_H7

L0_CADOUT_H7

HT_CADOUTP7

[6]

HT_CADINN7

N2

R1

HT_CADOUTN7

Y6

H6

[6]

HT_CADINN7

L0_CADIN_L7

L0_CADOUT_L7

HT_CADOUTN7

[6]

[28]

CPU_VDD1_FB_H

VDD1_FB_H

VDDNB_FB_H

CPU_VDDNB_FB_H

[28]

HT_CADINP8

E5

AD4

HT_CADOUTP8

AB6

G6

[6]

HT_CADINP8

L0_CADIN_H8

L0_CADOUT_H8

HT_CADOUTP8

[6]

[28]

CPU_VDD1_FB_L

VDD1_FB_L

VDDNB_FB_L

CPU_VDDNB_FB_L

[28]

HT_CADINN8

F5

AD3

HT_CADOUTN8

[6]

HT_CADINN8

L0_CADIN_L8

L0_CADOUT_L8

HT_CADOUTN8

[6]

HT_CADINP9

F3

AD5

HT_CADOUTP9

CPU_DBRDY

G10

[6]

HT_CADINP9

L0_CADIN_H9

L0_CADOUT_H9

HT_CADOUTP9

[6]

T1

DBRDY

HT_CADINN9

F4

AC5

HT_CADOUTN9

CPU_TMS

AA9

E10

CPU_DBREQ# R121

300/F_4

+1.5VSUS

[6]

HT_CADINN9

L0_CADIN_L9

L0_CADOUT_L9

HT_CADOUTN9

[6]

T3

TMS

DBREQ_L

HT_CADINP10

G5

AB4

HT_CADOUTP10

CPU_TCK

AC9

[6]

HT_CADINP10

L0_CADIN_H10 L0_CADOUT_H10

HT_CADOUTP10

[6]

T6

TCK

HT_CADINN10

H5

AB3

HT_CADOUTN10

CPU_TRST#

AD9

AE9

CPU_TDO

[6]

HT_CADINN10

L0_CADIN_L10 L0_CADOUT_L10

HT_CADOUTN10

[6]

T7

TRST_L

TDO

T5

HT_CADINP11

H3

AB5

HT_CADOUTP11

CPU_TDI

AF9

[6]

HT_CADINP11

L0_CADIN_H11 L0_CADOUT_H11

HT_CADOUTP11

[6]

T2

TDI

HT_CADINN11

H4

AA5

HT_CADOUTN11

[6]

HT_CADINN11

L0_CADIN_L11

L0_CADOUT_L11

HT_CADOUTN11

[6]

HT_CADINP12

K3

Y5

HT_CADOUTP12

CPUTEST23

AD7

J7

[6]

HT_CADINP12

L0_CADIN_H12 L0_CADOUT_H12

HT_CADOUTP12

[6]

TEST23

TEST28_H

HT_CADINN12

K4

W5

HT_CADOUTN12

H8

[6]

HT_CADINN12

L0_CADIN_L12

L0_CADOUT_L12

HT_CADOUTN12

[6]

TEST28_L

HT_CADINP13

L5

V4

HT_CADOUTP13

CPUTEST18

H10

C

[6]

HT_CADINP13

L0_CADIN_H13 L0_CADOUT_H13

HT_CADOUTP13

[6]

TEST18

HT_CADINN13

M5

V3

HT_CADOUTN13

CPUTEST19

G9

D7

CPUTEST17

[6]

HT_CADINN13

L0_CADIN_L13 L0_CADOUT_L13

HT_CADOUTN13

[6]

TEST19

TEST17

T19

HT_CADINP14

M3

V5

HT_CADOUTP14

E7

CPUTEST16

[6]

HT_CADINP14

L0_CADIN_H14 L0_CADOUT_H14

HT_CADOUTP14

[6]

TEST16

T29

HT_CADINN14

M4

U5

HT_CADOUTN14

+1.5VSUS

R122

510/F_4

CPUTEST25H

E9

F7

CPUTEST15

[6]

HT_CADINN14

L0_CADIN_L14 L0_CADOUT_L14

HT_CADOUTN14

[6]

TEST25_H

TEST15

T28

[6]

HT_CADINP15

HT_CADINP15

N5

L0_CADIN_H15 L0_CADOUT_H15

T4

HT_CADOUTP15

HT_CADOUTP15

[6]

R123

510/F_4

CPUTEST25L

E8

TEST25_L

TEST14

C7

CPUTEST14

T27

HT_CADINN15

P5

T3

HT_CADOUTN15

place them to CPU within 1.5"

[6]

HT_CADINN15

L0_CADIN_L15

L0_CADOUT_L15

HT_CADOUTN15

[6]

CPUTEST21

AB8

TEST21

TEST7

C3

[6]

HT_CLKINP0

HT_CLKINP0

J3

Y1

HT_CLKOUTP0

HT_CLKOUTP0

[6]

CPUTEST20

AF7

K8

L0_CLKIN_H0

L0_CLKOUT_H0

TEST20

TEST10

HT_CLKINN0

J2

W1

HT_CLKOUTN0

CPUTEST24

AE7

[6]

HT_CLKINN0

L0_CLKIN_L0

L0_CLKOUT_L0

HT_CLKOUTN0

[6]

TEST24

HT_CLKINP1

J5

Y4

HT_CLKOUTP1

CPUTEST22

AE8

C4

[6]

HT_CLKINP1

L0_CLKIN_H1

L0_CLKOUT_H1

HT_CLKOUTP1

[6]

TEST22

TEST8

HT_CLKINN1

K5

Y3

HT_CLKOUTN1

CPUTEST12

AC8

[6]

HT_CLKINN1

L0_CLKIN_L1

L0_CLKOUT_L1

HT_CLKOUTN1

[6]

TEST12

+1.5VSUS

R255

1K_4

CPUTEST27

AF8

HT_CTLINP0

N1

R2

HT_CTLOUTP0

TEST27

C9

CPUTEST29H

[6]

HT_CTLINP0

L0_CTLIN_H0

L0_CTLOUT_H0

HT_CTLOUTP0

[6]

TEST29_H

T26

HT_CTLINN0

P1

R3

HT_CTLOUTN0

R256

*300/F_4

C2

C8

[6]

HT_CTLINN0

L0_CTLIN_L0

L0_CTLOUT_L0

HT_CTLOUTN0

[6]

TEST9

TEST29_L

[6]

HT_CTLINP1

HT_CTLINP1

P3

L0_CTLIN_H1

L0_CTLOUT_H1

T5

HT_CTLOUTP1

HT_CTLOUTP1

[6]

AA6

TEST6

HT_CTLINN1

P4

R5

HT_CTLOUTN1

R126

[6]

HT_CTLINN1

L0_CTLIN_L1

L0_CTLOUT_L1

HT_CTLOUTN1

[6]

A3

H18

80.6/F_4

FOX PZ63826-284R-41F

RSVD1

RSVD10

A5

H19

DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2)

SOCKET_638_PIN

B3

RSVD2

RSVD9

AA7

CPUTEST29L

T25

RSVD3

RSVD8

B5

D5

MLX 47296-4131

RSVD4

RSVD7

C1

C5

DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)

RSVD5

RSVD6

TYC 4-1903401-2

DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2)

SOCKET_638_PIN

C300

.1u/10V_4

CNTR_VREF

[4]

+3V

Serial VID

VFIX MODE

VID Override Circuit

B

SVC

SVD

Voltage Output

+3V

R22

20K/F_4

R247

34.8K/F_4

+1.5V

R303

300/F_4

0

0

1.1V

R20

2/10 Confirmed AMD

CNTR_VREF

R295

4.7K_4

+1.5VSUS

1K_4

R300

1K_4

0

1

1.0V

2

+1.5V

CPU_LDT_REQ#_CPU

1

3

1

0

0.9V

Q21

*BSS138_NL/SOT23

2

CPU_LDT_REQ# [8]

1

3

CPU_LDT_RST_HTPA#

CPU_SVD

1

1

0.8V

CPU_LDT_RST#

CPU_SVC

CPU_SVC

[28]

Q3

CPU_PWRGD

CPU_SVD

[28]

R243

*0_4

BSS138_NL/SOT23

The RS880 family does not support CLMC architecture

1

G2

R299

*220_4

The LDTREQ# connection from the CPU to ALLOW_LDTSTOP

*SHORT_ PAD1

R297

*220_4

of the Northbridge is no longer required.

2

R302

*220_4

for debug only

+1.5VSUS

Change Q23 to BSS138 +1.5VSUS

R31

10K_4

HDT Connector

CPUTEST24

R258

1K_4

CPUTEST20

R259

1K_4

3

ECN: B3A

CPUTEST23

R260

1K_4

CPUTEST22

R257

1K_4

CN8

CPUTEST12

R34

1K_4

[8,11,14] NB_PWRGD_IN

2

Q23

+1.5VSUS

R262

300/F_4

*HDT CONN

CPUTEST15

R127

*300/F_4

BSS138_NL/SOT23

2

Q4

1

2

CPUTEST14

R128

*300/F_4

+3V/S0 PU at FAN side.

MMBT3904

3

4

CPUTEST19

R98

1K_4

A

5

6

CPUTEST18

R99

1K_4

1

CPU_PROCHOT_L#

1

3

PM_THERM# [4,24]

T46

7

8

CPUTEST21

R35

1K_4

To FAN

T47

9

10

R249

T41

11

12

T42

13

14

1K_4

+3V/S5 PU at SB side. (Reserve)

T43

15

16

352-(&7 =4

Q24

R26

To SB

T44

17

18

T33

http://hobi-elektronika.netC206 *.1u/10V 4

23

24

4XDQWD &RPSXWHU ,QF

R261

1K_4

CPU PROCHOT# [10]

T45

21

22

+1.5VSUS

2

+1.5VSUS

CPU_THERMTRIP_L#

MMBT3904

John (02/26)

KEY

25

Size

Document Number

Rev

1

3

SYS_SHDN# [27,32]

SB SCL mentions that you donˇt need level shift between CPU and SB,

S1G4 HT,CTL I/F 1/3

1A

But, you need level shift below CPU and FAN control circuit.

Date: Thursday, March 04, 2010 Sheet

2 of

36

D

C

B

A

5

4

3

2

1

A

B

C

D

E

35W CPU support 0.9V

VDDR=> 0.9V support 1066 / 800 DDR

45W CPU support 1.05V

VDDR= >1.05V support 1333 / 1066 / 800 DDR

Processor Memory Interface

+1.5VSUS

CPU_VDDR

U17B

VDDR=>1.75A

CPU_VDDR

CPU_VDDR

[5]

M_B_DQ[0..63]

PLACE THEM CLOSE TO

D10

VDDR1

VDDR5

W10

+SMDDR_VREF

U17C

CPU WITHIN 1"

C10

MEM:CMD/CTRL/CLK

AC10

M_A_DQ[0..63]

[5]

R250

B10

VDDR2

VDDR6

AB10

MEM:DATA

0_4

AD10

VDDR3

VDDR7

AA10

M_B_DQ0

C11

G12 M_A_DQ0

VDDR4

VDDR8

MB_DATA0

MA_DATA0

A10

R33

M_B_DQ1

A11

F12

M_A_DQ1

VDDR9

MB_DATA1

MA_DATA1

R253

39.2/F_4

M_ZP

AF10

*0_4

M_B_DQ2

A14

H14

M_A_DQ2

MEMZP

MB_DATA2

MA_DATA2

R254

39.2/F_4

M_ZN

AE10

Y10 CPU_VTT_SENSE

R37

*0_4

M_B_DQ3

B14

G14

M_A_DQ3

4

MEMZN

VDDR_SENSE

MB_DATA3

MA_DATA3

4

M_B_DQ4

G11

H11

M_A_DQ4

MB_DATA4

MA_DATA4

C307

[5]

M_A_RST#

H16

W17 MEMVREF_CPU

M_B_DQ5

E11

H12

M_A_DQ5

MA_RESET_L

MEMVREF

MB_DATA5

MA_DATA5

10u/6.3V_8

M_B_DQ6

D12

C13

M_A_DQ6

MB_DATA6

MA_DATA6

[5]

M_A_ODT0

T19

B18

M_B_RST#

[5]

M_B_DQ7

A13

E13

M_A_DQ7

MA0_ODT0

MB_RESET_L

MB_DATA7

MA_DATA7

V22

M_B_DQ8

A15

H15

M_A_DQ8

[5]

M_A_ODT1

MA0_ODT1

MB_DATA8

MA_DATA8

U21

W26

M_B_ODT0

[5]

M_B_DQ9

A16

E15

M_A_DQ9

MA1_ODT0

MB0_ODT0

MB_DATA9

MA_DATA9

V19

W23

C31

C35

M_B_DQ10

A19

E17

M_A_DQ10

MA1_ODT1

MB0_ODT1

M_B_ODT1

[5]

MB_DATA10

MA_DATA10

Y26

.1u/10V_4

1000P/50V_4

M_B_DQ11

A20

H17

M_A_DQ11

MB1_ODT0

MB_DATA11

MA_DATA11

[5]

M_A_CS#0

T20

M_B_DQ12

C14

E14

M_A_DQ12

MA0_CS_L0

MB_DATA12

MA_DATA12

U19

V26

M_B_DQ13

D14

F14

M_A_DQ13

[5]

M_A_CS#1

MA0_CS_L1

MB0_CS_L0

M_B_CS#0

[5]

MB_DATA13

MA_DATA13

U20

W25

M_B_DQ14

C18

C17

M_A_DQ14

MA1_CS_L0

MB0_CS_L1

M_B_CS#1

[5]

MB_DATA14

MA_DATA14

V20

U22

M_B_DQ15

D18

G17

M_A_DQ15

MA1_CS_L1

MB1_CS_L0

MB_DATA15

MA_DATA15

M_B_DQ16

D20

G18

M_A_DQ16

[5]

M_A_CKE0

J22

J25

M_B_CKE0

[5]

M_B_DQ17

A21

MB_DATA16

MA_DATA16

C19

M_A_DQ17

MA_CKE0

MB_CKE0

MB_DATA17

MA_DATA17

J20

H26

M_B_DQ18

D24

D22

M_A_DQ18

[5]

M_A_CKE1

MA_CKE1

MB_CKE1

M_B_CKE1

[5]

MB_DATA18

MA_DATA18

M_B_DQ19

C25

E20

M_A_DQ19

MB_DATA19

MA_DATA19

[5]

M_A_CLKP1

N19

P22

M_B_CLKP1

[5]

M_B_DQ20

B20

E18

M_A_DQ20

MA_CLK_H5

MB_CLK_H5

MB_DATA20

MA_DATA20

N20

R22

M_B_DQ21

C20

F18

M_A_DQ21

[5]

M_A_CLKN1

MA_CLK_L5

MB_CLK_L5

M_B_CLKN1

[5]

MB_DATA21

MA_DATA21

E16

A17

M_B_DQ22

B24

B22

M_A_DQ22

MA_CLK_H1

MB_CLK_H1

MB_DATA22

MA_DATA22

F16

A18

M_B_DQ23

C24

C23

M_A_DQ23

MA_CLK_L1

MB_CLK_L1

MB_DATA23

MA_DATA23

Y16

AF18

M_B_DQ24

E23

F20

M_A_DQ24

MA_CLK_H7

MB_CLK_H7

MB_DATA24

MA_DATA24

AA16

AF17

M_B_DQ25

E24

F22

M_A_DQ25

MA_CLK_L7

MB_CLK_L7

MB_DATA25

MA_DATA25

[5]

M_A_CLKP2

P19

R26

M_B_CLKP2

[5]

M_B_DQ26

G25

H24

M_A_DQ26

MA_CLK_H4

MB_CLK_H4

MB_DATA26

MA_DATA26

P20

R25

M_B_DQ27

G26

J19

M_A_DQ27

[5]

M_A_CLKN2

MA_CLK_L4

MB_CLK_L4

M_B_CLKN2

[5]

MB_DATA27

MA_DATA27

M_B_DQ28

C26

E21

M_A_DQ28

MB_DATA28

MA_DATA28

M_A_A0

N21

P24 M_B_A0

M_B_DQ29

D26

E22

M_A_DQ29

M_A_A1

M20

MA_ADD0

MB_ADD0

N24

M_B_A1

M_B_DQ30

G23

MB_DATA29

MA_DATA29

H20

M_A_DQ30

MA_ADD1

MB_ADD1

MB_DATA30

MA_DATA30

M_A_A2

N22

P26

M_B_A2

M_B_DQ31

G24

H22

M_A_DQ31

MA_ADD2

MB_ADD2

MB_DATA31

MA_DATA31

M_A_A3

M19

N23

M_B_A3

M_B_DQ32

AA24

Y24

M_A_DQ32

MA_ADD3

MB_ADD3

MB_DATA32

MA_DATA32

3

M_A_A4

M22

N26

M_B_A4

M_B_DQ33

AA23

AB24

M_A_DQ33

3

MA_ADD4

MB_ADD4

MB_DATA33

MA_DATA33

M_A_A5

L20

L23

M_B_A5

M_B_DQ34

AD24

AB22

M_A_DQ34

M_A_A6

M24

MA_ADD5

MB_ADD5

N25

M_B_A6

M_B_DQ35

AE24

MB_DATA34

MA_DATA34

AA21

M_A_DQ35

MA_ADD6

MB_ADD6

MB_DATA35

MA_DATA35

M_A_A7

L21

L24

M_B_A7

M_B_DQ36

AA26

W22

M_A_DQ36

MA_ADD7

MB_ADD7

MB_DATA36

MA_DATA36

M_A_A8

L19

M26

M_B_A8

M_B_DQ37

AA25

W21

M_A_DQ37

MA_ADD8

MB_ADD8

MB_DATA37

MA_DATA37

M_A_A9

K22

K26

M_B_A9

M_B_DQ38

AD26

Y22

M_A_DQ38

MA_ADD9

MB_ADD9

MB_DATA38

MA_DATA38

M_A_A10

R21

T26

M_B_A10

M_B_DQ39

AE25

AA22

M_A_DQ39

MA_ADD10

MB_ADD10

MB_DATA39

MA_DATA39

M_A_A11

L22

L26

M_B_A11

M_B_DQ40

AC22

Y20

M_A_DQ40

MA_ADD11

MB_ADD11

MB_DATA40

MA_DATA40

M_A_A12

K20

L25

M_B_A12

M_B_DQ41

AD22

AA20

M_A_DQ41

MA_ADD12

MB_ADD12

MB_DATA41

MA_DATA41

M_A_A13

V24

W24

M_B_A13

M_B_DQ42

AE20

AA18

M_A_DQ42

MA_ADD13

MB_ADD13

MB_DATA42

MA_DATA42

M_A_A14

K24

J23

M_B_A14

M_B_DQ43

AF20

AB18

M_A_DQ43

MA_ADD14

MB_ADD14

MB_DATA43

MA_DATA43

[5]

M_A_A[0..15]

M_A_A15

K19

J24

M_B_A15

M_B_A[0..15]

[5]

M_B_DQ44

AF24

AB21

M_A_DQ44

MA_ADD15

MB_ADD15

MB_DATA44

MA_DATA44

M_B_DQ45

AF23

AD21

M_A_DQ45

MB_DATA45

MA_DATA45

[5]

M_A_BANK0

R20

R24

M_B_BANK0

[5]

M_B_DQ46

AC20

AD19

M_A_DQ46

MA_BANK0

MB_BANK0

MB_DATA46

MA_DATA46

R23

U26

M_B_DQ47

AD20

Y18

M_A_DQ47

[5]

M_A_BANK1

MA_BANK1

MB_BANK1

M_B_BANK1

[5]

MB_DATA47

MA_DATA47

J21

J26

M_B_DQ48

AD18

AD17

M_A_DQ48

[5]

M_A_BANK2

MA_BANK2

MB_BANK2

M_B_BANK2

[5]

MB_DATA48

MA_DATA48

M_B_DQ49

AE18

W16

M_A_DQ49

MB_DATA49

MA_DATA49

[5]

M_A_RAS#

R19

U25

M_B_RAS#

[5]

M_B_DQ50

AC14

W14

M_A_DQ50

MA_RAS_L

MB_RAS_L

MB_DATA50

MA_DATA50

T22

U24

M_B_DQ51

AD14

Y14

M_A_DQ51

[5]

M_A_CAS#

MA_CAS_L

MB_CAS_L

M_B_CAS#

[5]

MB_DATA51

MA_DATA51

T24

U23

M_B_DQ52

AF19

Y17

M_A_DQ52

[5]

M_A_WE#

MA_WE_L

MB_WE_L

M_B_WE#

[5]

MB_DATA52

MA_DATA52

M_B_DQ53

AC18

AB17

M_A_DQ53

MB_DATA53

MA_DATA53

M_B_DQ54

AF16

AB15

M_A_DQ54

MB_DATA54

MA_DATA54

SOCKET_638_PIN

M_B_DQ55

AF15

AD15

M_A_DQ55

MB_DATA55

MA_DATA55

M_B_DQ56

AF13

AB13

M_A_DQ56

CPU_VDDR

Place close to socket

MB_DATA56

MA_DATA56

M_B_DQ57

AC12

AD13

M_A_DQ57

M_B_DQ58

AB11

MB_DATA57

MA_DATA57

Y12

M_A_DQ58

M_B_DQ59

Y11

MB_DATA58

MA_DATA58

W11

M_A_DQ59

MB_DATA59

MA_DATA59

M_B_DQ60

AE14

AB14

M_A_DQ60

MB_DATA60

MA_DATA60

M_B_DQ61

AF14

AA14

M_A_DQ61

MB_DATA61

MA_DATA61

C174

C34

C33

C175

C169

C170

C39

C37

M_B_DQ62

AF11

AB12

M_A_DQ62

2

4.7u/6.3V_6

4.7u/6.3V_6

4.7u/6.3V_6

4.7u/6.3V_6

.22u/6.3V_4

.22u/6.3V_4

.22u/6.3V_4

.22u/6.3V_4

[5]

M_B_DM[0..7]

M_B_DQ63

AD11

MB_DATA62

MA_DATA62

AA12

M_A_DQ63

M_A_DM[0..7] [5]

2

MB_DATA63

MA_DATA63

CPU_VDDR

M_B_DM0

A12

MB_DM0

MA_DM0

E12

M_A_DM0

M_B_DM1

B16

C15

M_A_DM1

MB_DM1

MA_DM1

M_B_DM2

A22

E19

M_A_DM2

M_B_DM3

E25

MB_DM2

MA_DM2

F24

M_A_DM3

MB_DM3

MA_DM3

M_B_DM4

AB26

AC24

M_A_DM4

MB_DM4

MA_DM4

C168

C171

C145

C40

C172

C38

C166

C36

M_B_DM5

AE22

Y19

M_A_DM5

MB_DM5

MA_DM5

1000P/50V_4

1000P/50V_4

1000P/50V_4

1000P/50V_4

180p/50V_4

180p/50V_4

180p/50V_4

180p/50V_4

M_B_DM6

AC16

AB16

M_A_DM6

MB_DM6

MA_DM6

M_B_DM7

AD12

Y13

M_A_DM7

MB_DM7

MA_DM7

[5]

M_B_DQSP0

C12

MB_DQS_H0

MA_DQS_H0

G13

M_A_DQSP0

[5]

[5]

M_B_DQSN0

B12

MB_DQS_L0

MA_DQS_L0

H13

M_A_DQSN0

[5]

D16

G16

[5]

M_B_DQSP1

MB_DQS_H1

MA_DQS_H1

M_A_DQSP1

[5]

C16

G15

+1.5VSUS

Reserved for AMD suggest

[5]

M_B_DQSN1

MB_DQS_L1

MA_DQS_L1

M_A_DQSN1

[5]

A24

C22

[5]

M_B_DQSP2

MB_DQS_H2

MA_DQS_H2

M_A_DQSP2 [5]

A23

C21

[5]

M_B_DQSN2

F26

MB_DQS_L2

MA_DQS_L2

G22

M_A_DQSN2

[5]

[5]

M_B_DQSP3

MB_DQS_H3

MA_DQS_H3

M_A_DQSP3

[5]

E26

G21

R30

0_4

[5]

M_B_DQSN3

MB_DQS_L3

MA_DQS_L3

M_A_DQSN3

[5]

AC25

AD23

[5]

M_B_DQSP4

MB_DQS_H4

MA_DQS_H4

M_A_DQSP4

[5]

AC26

AC23

+3VPCU

[5]

M_B_DQSN4

MB_DQS_L4

MA_DQS_L4

M_A_DQSN4

[5]

AF21

AB19

[5]

M_B_DQSP5

MB_DQS_H5

MA_DQS_H5

M_A_DQSP5

[5]

AF22

AB20

R24

C27

[5]

M_B_DQSN5

MB_DQS_L5

MA_DQS_L5

M_A_DQSN5

[5]

AE16

Y15

[5]

M_B_DQSP6

MB_DQS_H6

MA_DQS_H6

M_A_DQSP6

[5]

AD16

W15

1K/F_4

[5]

M_B_DQSN6

MB_DQS_L6

MA_DQS_L6

M_A_DQSN6

[5]

AF12

W12

[5]

M_B_DQSP7

MB_DQS_H7

MA_DQS_H7

M_A_DQSP7

[5]

AE12

W13

5

U2

*.1u/10V_4

[5]

M_B_DQSN7

MB_DQS_L7

MA_DQS_L7

M_A_DQSN7

[5]

3

R28

*10_4

1

+

1

MEMVREF_CPU

SOCKET_638_PIN

1

4

1

2

R25

2

-

*OPA343NA/3K

C29

1K/F_4

2

R29

1

*.47u/10V_4

*10K_4

352-(&7 =4

R23

*0_4

R27

*0_4

http://hobi-elektronika.net

4XDQWD &RPSXWHU ,QF

Size

Document Number

Rev

S1G4 DDRIII MEMORY I/F 2/3

1A

Date:

Thursday, March 04, 2010

Sheet

3

of

36

A

B

C

D

E

5

4

3

2

1

U17F

AA4

VSS1

VSS66

J6

U17E

AA11

J8

+VCORE

+VCORE

VSS2

VSS67

AA13

J10

VSS3

VSS68

BOTTOM SIDE DECOUPLING

AA15

J12

VSS4

VSS69

G4

P8

AA17

J14

VDD_1

VDD_24

VSS5

VSS70

H2

VDD_2

VDD_25

P10

AA19

VSS6

VSS71

J16

+VCORE

J9

R4

AB2

J18

VDD_3

VDD_26

VSS7

VSS72

J11

R7

AB7

K2

VDD_4

VDD_27

VSS8

VSS73

J13

R9

AB9

K7

VDD_5

VDD_28

VSS9

VSS74

J15

R11

AB23

K9

VDD_6

VDD_29

VSS10

VSS75

D

K6

T2

AB25

K11

D

VDD_7

VDD_30

VSS11

VSS76

C63

C105

C298

C136

C117

C118

C112

K10

T6

AC11

K13

VDD_8

VDD_31

VSS12

VSS77

K12

T8

AC13

K15

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

.22u/6.3V_4

.01u/16V_4

180p/50V_4

VDD_9

VDD_32

VSS13

VSS78

K14

T10

AC15

K17

VDD_10

VDD_33

VSS14

VSS79

L4

T12

AC17

L6

VDD_11

VDD_34

VSS15

VSS80

L7

T14

AC19

L8

VDD_12

VDD_35

VSS16

VSS81

L9

U7

AC21

L10

VDD_13

VDD_36

VSS17

VSS82

+VCORE

L11

U9

AD6

L12

VDD_14

VDD_37

VSS18

VSS83

L13

U11

AD8

L14

VDD_15

VDD_38

VSS19

VSS84

L15

U13

AD25

L16

VDD_16

VDD_39

VSS20

VSS85

M2

U15

AE11

L18

VDD_17

VDD_40

VSS21

VSS86

M6

V6

AE13

M7

VDD_18

VDD_41

VSS22

VSS87

C137

C297

C116

C296

C131

C119

C146

C138

M8

V8

AE15

M9

VDD_19

VDD_42

VSS23

VSS88

M10

V10

AE17

AC6

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

.22u/6.3V_4

.01u/16V_4

180p/50V_4

.01u/16V_4

VDD_20

VDD_43

VSS24

VSS89

N7

V12

AE19

M17

CPU_VDDNB_CORE

VDD_21

VDD_44

VSS25

VSS90

N9

V14

AE21

N4

VDD_22

VDD_45

VSS26

VSS91

N11

W4

AE23

N8

3A

VDD_23

VDD_46

VSS27

VSS92

Y2

B4

N10

VDD_47

VSS28

VSS93

CPU_VDDNB_CORE

+1.5VSUS

K16

AC4

B6

N16

VDDNB_1

VDD_48

+1.5VSUS

VSS29

VSS94

M16

VDDNB_2

VDD_49

AD2

B8

VSS30

VSS95

N18

P16

B9

P2

+1.5VSUS

VDDNB_3

VSS31

VSS96

T16

Y25

B11

P7

VDDNB_4

VDDIO27

1.5V@2A

VSS32

VSS97

V16

V25

B13

P9

VDDNB_5

VDDIO26

VSS33

VSS98

C87

C88

C86

C156

C157

C96

C133

C97

C121

V23

B15

P11

H25

VDDIO25

VSS34

VSS99

VDDIO1

VDDIO24

V21

B17

VSS35

VSS100

P17

10u/6.3V_8

10u/6.3V_8 10u/6.3V_8

10u/6.3V_8

10u/6.3V_8

.22u/6.3V_4

.22u/6.3V_4

180p/50V_4

180p/50V_4

J17

V18

B19

R8

VDDIO2

VDDIO23

VSS36

VSS101

K18

U17

B21

R10

VDDIO3

VDDIO22

VSS37

VSS102

C

K21

T25

B23

R16

C

VDDIO4

VDDIO21

VSS38

VSS103

K23

T23

B25

R18

VDDIO5

VDDIO20

VSS39

VSS104

K25

T21

D6

T7

VDDIO6

VDDIO19

VSS40

VSS105

L17

T18

D8

T9

VDDIO7

VDDIO18

VSS41

VSS106

M18

R17

D9

T11

VDDIO8

VDDIO17

VSS42

VSS107

DECOUPLING BETWEEN PROCESSOR AND DIMMs

M21

P25

D11

T13

VDDIO9

VDDIO16

VSS43

VSS108

M23

P23

D13

T15

VDDIO10

VDDIO15

VSS44

VSS109

M25

VDDIO11

VDDIO14

P21

D15

VSS45

VSS110

T17

PLACE CLOSE TO PROCESSOR AS POSSIBLE

N17

P18

D17

U4

VDDIO12

VDDIO13

VSS46

VSS111

D19

U6

VSS47

VSS112

SOCKET_638_PIN

D21

VSS48

VSS113

U8

D23

U10

VSS49

VSS114

+1.5VSUS

D25

U12

+1.5VSUS

VSS50

VSS115

E4

U14

VSS51

VSS116

F2

U16

VSS52

VSS117

[2]

CNTR_VREF

F11

U18

VSS53

VSS118

F13

V2

VSS54

VSS119

C90

C148

C92

C91

C95

C98

F15

V7

VSS55

VSS120

F17

V9

4.7u/6.3V_6

4.7u/6.3V_6

4.7u/6.3V_6

4.7u/6.3V_6

.22u/6.3V_4

.22u/6.3V_4

R263

R245

VSS56

VSS121

F19

V11

Q25

VSS57

VSS122

2

1K_4

1K_4

F21

V13

VSS58

VSS123

+1.5VSUS

BSS138_NL/SOT23

F23

V15

VSS59

VSS124

F25

V17

CPU_SMBCLK

3

1

VSS60

VSS125

CPU_SIC

[2]

H7

W6

VSS61

VSS126

H9

Y21

VSS62

VSS127

H21

Y23

VSS63

VSS128

C93

C94

C140

C159

C114

H23

N6

Q22

VSS64

VSS129

B

2

J4

.22u/6.3V_4

.22u/6.3V_4

.01u/16V_4

.01u/16V_4

180p/50V_4

B

VSS65

BSS138_NL/SOT23

SOCKET_638_PIN

CPU_SMBDATA

3

1

CPU_SID

[2]

PROCESSOR POWER AND GROUND

THERMAL IC (Reserve only)

+3V

+3V

R291

R286

*200/F_6

*10K_4

G786 PWR

C362

*.1u/10V_4

G786 ALT#

U19

A

CPU_SMBCLK

A

8

1

[25]

CPU_SMBCLK

SCLK

VCC

H_THRMDA

[2]

[25]

CPU_SMBDATA

CPU_SMBDATA

7

SDA

DXP

2

C366

*1000P/50V_4

352-(&7 =4

6

3

ALERT#

DXN

H_THRMDC

[2]

PM_THERM#

R294

1

2

*0_4

G768_OVT#

4

5

[2,24]

PM_THERM#

OVERT#

GND

http://hobi-elektronika.net

4XDQWD &RPSXWHU ,QF

MSOP

Size

Document Number

Rev

*G786P8

S1G4 PWR & GND 3/3

1A

Adress ID: 9A

5

3

2

Date:

Thursday, March 04, 2010

Sheet

4

of

36

4

1

5

4

3

2

1

[3]

M_A_A[0..15]

+1.5VSUS

M_A_A0

98

M_A_A1

97

M_A_A2

96

M_A_A3

95

M_A_A4

92

M_A_A5

91

M_A_A6

90

M_A_A7

86

M_A_A8

89

M_A_A9

85

D

M_A_A10

107

M_A_A11

84

M_A_A12

83

M_A_A13

119

M_A_A14

80

M_A_A15

78

M_A_BANK0

109

M_A_BANK1

108

[3]

M_A_BANK[0..2]

M_A_BANK2

79

M_A_DM0

11

M_A_DM1

28

M_A_DM2

46

M_A_DM3

63

M_A_DM4

136

M_A_DM5

153

M_A_DM6

170

[3] M_A_DM[0..7]

M_A_DM7

187

[3]

M_A_DQSP0

12

29

[3]

M_A_DQSP1

47

[3]

M_A_DQSP2

64

[3]

M_A_DQSP3

137

[3]

M_A_DQSP4

154

[3]

M_A_DQSP5

171

[3]

M_A_DQSP6

188

[3]

M_A_DQSP7

[3]

M_A_DQSN0

10

27

C

[3] M_A_DQSN1

45

[3]

M_A_DQSN2

62

[3]

M_A_DQSN3

135

[3]

M_A_DQSN4

152

[3]

M_A_DQSN5

169

[3]

M_A_DQSN6

186

[3]

M_A_DQSN7

101

[3]

M_A_CLKP1

103

[3]

M_A_CLKN1

102

[3]

M_A_CLKP2

104

[3]

M_A_CLKN2

[3]

M_A_CKE0

73

74

[3]

M_A_CKE1

110

[3]

M_A_RAS#

115

[3]

M_A_CAS#

113

[3]

M_A_WE#

114

[3]

M_A_CS#0

121

[3]

M_A_CS#1

[3]

M_A_ODT0

116

120

[3] M_A_ODT1

DIM1_SA0

197

DIM1_SA1

201

[11,17,18]

PDAT_SMB

200

202

B

[11,17,18]

PCLK_SMB

C32

+3V

.01u/16V_

4

199

[3]

M_A_RST#

30

198

+0.75VSMVREF_SUSA

1

+VREF_CA_A

126

+0.75V_DDR_VTT

203

204

C28

C308

C30

2

3

*10u/6.3V

1000P/50V_4

8

_6

.1u/10V_4

9

13

14

19

20

25

26

31

32

+1.5VSUS

A

+SMDDR_VREF

+VREF_CA_A

R66

*1K/F_4

R57

0_4

C73

C67

R73

.1u/10V_4

2.2u/6.3V_6

*1K/F_4

5

M_A_DQ[0..63] [3]

[3]

M_B_A[0..15]

+1.5VSUS

75

76

81

82

87

88

93

94

99

100

105

106

111

112

117

118

123

124

CN20

M_A_DQ1

+1.5VSUS

M_B_A0

75

76

81

82

87

88

93

94

99

100

105

106

111

112

117

118

123

124

CN19

M_B_DQ5

5

98

5

A2VDD0VDD1VDD2VDD3VDD4VDD5VDD6VDD7VDD8VDD9VDD10VDD11VDD12VDD13VDD14VDD15VDD16VDD17

DQ2

+SMDDR_VREF

+VREF_CA_B

A2VDD0VDD1VDD2

VDD3

VDD4

VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12

VDD13

VDD14

VDD15 VDD16

VDD17

DQ2

A0

DQ0

7

M_A_DQ0

M_B_A1

97

A0

DQ0

7

M_B_DQ4

A1

DQ1

15

M_A_DQ7

M_B_A2

96

A1

DQ1

15

M_B_DQ7

A3/A4

DQ3

17

M_A_DQ6

M_B_A3

95

A3/A4

DQ3

17

M_B_DQ6

4

M_A_DQ5

M_B_A4

92

4

M_B_DQ0

A4/A3

DQ4

A4/A3

DQ4

A5/A6

DQ5

6

M_A_DQ4

R56

M_B_A5

91

A5/A6

DQ5

6

M_B_DQ1

16

M_A_DQ2

*1K/F_4

M_B_A6

90

16

M_B_DQ3

A6/A5

DQ6

A6/A5

DQ6

18

M_A_DQ3

M_B_A7

86

18

M_B_DQ2

A7/A8

DQ7

21

M_A_DQ9

R52

0_4

M_B_A8

89

A7/A8

DQ7

21

M_B_DQ12

A8/A7

DQ8

A8/A7

DQ8

23

M_A_DQ8

M_B_A9

85

23

M_B_DQ13

A9

DQ9

33

M_A_DQ15

M_B_A10

107

A9

DQ9

33

M_B_DQ14

A10/AP

DQ10

35

M_A_DQ11

M_B_A11

84

A10/AP

DQ10

35

M_B_DQ15

A11

DQ11

A11

DQ11

A12_BC#

DQ12

22

M_A_DQ13

C72

C65

R65

M_B_A12

83

A12_BC#

DQ12

22

M_B_DQ8

A13

DQ13

24

M_A_DQ12

.1u/10V_4

2.2u/6.3V_6

*1K/F_4

M_B_A13

119

A13

DQ13

24

M_B_DQ9

A14

DQ14

34

M_A_DQ14

M_B_A14

80

A14

DQ14

34

M_B_DQ10

36

M_A_DQ10

M_B_A15

78

36

M_B_DQ11

A15/BA3

DQ15

39

M_A_DQ16

A15/BA3

DQ15

39

M_B_DQ20

DQ16

41

M_A_DQ21

M_B_BANK0

109

DQ16

41

M_B_DQ21

BA0/BA1

DQ17

51

M_A_DQ18

M_B_BANK1

108

BA0/BA1

DQ17

51

M_B_DQ23

BA1/BA0

DQ18

53

M_A_DQ23

[3]

M_B_BANK[0..2]

M_B_BANK2

79

BA1/BA0

DQ18

53

M_B_DQ22

BA2

DQ19

40

M_A_DQ17

BA2

DQ19

40

M_B_DQ17

DQ20

42

M_A_DQ20

M_B_DM0

11

DQ20

42

M_B_DQ16

DM0

DQ21

DM0

DQ21

50

M_A_DQ22

M_B_DM1

28

50

M_B_DQ19

DM1

DQ22

52

M_A_DQ19

M_B_DM2

46

DM1

DQ22

52

M_B_DQ18

DM2

DQ23

DM2

DQ23

57

M_A_DQ25

M_B_DM3

63

57

M_B_DQ24

DM3

DQ24

59

M_A_DQ24

M_B_DM4

136

DM3

DQ24

59

M_B_DQ28

DM4

DQ25

67

M_A_DQ30

M_B_DM5

153

DM4

DQ25

67

M_B_DQ30

DM5

DQ26

69

M_A_DQ27

M_B_DM6

170

DM5

DQ26

69

M_B_DQ31

DM6

DQ27

56

M_A_DQ28

[3] M_B_DM[0..7]

M_B_DM7

187

DM6

DQ27

56

M_B_DQ29

DM7

DQ28

58

M_A_DQ29

DM7

DQ28

58

M_B_DQ25

DQ29

68

M_A_DQ31

[3] M_B_DQSP0

12

DQ29

68

M_B_DQ27

DQS0

DQ30

DQS0

DQ30

70

M_A_DQ26

29

70

M_B_DQ26

DQS1

DQ31

129

M_A_DQ37

[3] M_B_DQSP1

47

DQS1

DQ31

129

M_B_DQ33

DQS2

DIMM- )

DQ32

[3] M_B_DQSP2

DQS2

DIMM- )

DQ32

131

M_A_DQ36

64

131

M_B_DQ32

DQS3

DQ33

149

M_A_DQ41

[3] M_B_DQSP3

45

DQS3

DQ33

149

M_B_DQ45

DQS2#

DQ41

[3]

M_B_DQSN2

DQS2#

DQ41

DQS4

DQ34

141

M_A_DQ35

[3] M_B_DQSP4

137

DQS4

DQ34

141

M_B_DQ34

DQS5

DQ35

143

M_A_DQ39

[3] M_B_DQSP5

154

DQS5

DQ35

143

M_B_DQ35

DQS6

DQ36

130

M_A_DQ38

[3] M_B_DQSP6

171

DQS6

DQ36

130

M_B_DQ37

DQS7

DQ37

132

M_A_DQ32

[3] M_B_DQSP7

188

DQS7

DQ37

132

M_B_DQ36

140

M_A_DQ33

140

M_B_DQ38

DQ38

142

M_A_DQ34

[3] M_B_DQSN0

10

DQ38

142

M_B_DQ39

DQS0#

DQ39

DQS0#

DQ39

147

M_A_DQ40

27

147

M_B_DQ40

DQS1#

DDR3SO

(Standard

DQ40

[3] M_B_DQSN1

DQS1#

DDR3SO

(Standard

DQ40

M_B_DQ46

DQS3#

DQ42

157

M_A_DQ46

[3] M_B_DQSN3

62

DQS3#

DQ42

157

CKE1

DQ55

176

M_A_DQ55

V1STDSODIMM200

[3]

M_B_CKE1

74

CKE1

DQ55

176

M_B_DQ51

DQS4#

DQ43

159

M_A_DQ47

Standard

[3]

M_B_DQSN4

135

DQS4#

DQ43

159

M_B_DQ47

DQS5#

DQ44

146

M_A_DQ44

Connector

[3] M_B_DQSN5

152

DQS5#

DQ44

146

M_B_DQ44

DQS6#

DQ45

148

M_A_DQ45

[3]

M_B_DQSN6

169

DQS6#

DQ45

148

M_B_DQ41

DQS7#

DQ46

158

M_A_DQ42

1

[3] M_B_DQSN7

186

DQS7#

DQ46

158

M_B_DQ43

DQ47

160

M_A_DQ43

DQ47

160

M_B_DQ42

DQ48

163

M_A_DQ52

DQ48

163

M_B_DQ53

CK0

DQ49

165

M_A_DQ49

[3] M_B_CLKP1

101

CK0

DQ49

165

M_B_DQ52

175

M_A_DQ54

103

175

M_B_DQ54

CK0#

DQ50

2

[3]

M_B_CLKN1

CK0#

DQ50

177

M_A_DQ51

102

177

M_B_DQ50

CK1

DQ51

164

M_A_DQ53

[3] M_B_CLKP2

104

CK1

DQ51

164

M_B_DQ48

CK1#

DQ52

[3] M_B_CLKN2

CK1#

DQ52

166

M_A_DQ48

166

M_B_DQ49

DQ53

DQ53

174

M_A_DQ50

[3] M_B_CKE0

73

174

M_B_DQ55

CKE0

DQ54

CKE0

DQ54

M_B_DQ60

DQ56

181

M_A_DQ61

CON_

DQ56

181

183

M_A_DQ60

[3] M_B_RAS#

110

183

M_B_DQ61

RAS#

DQ57

191

M_A_DQ59

115

RAS#

DQ57

191

M_B_DQ59

CAS#

DQ58

193

M_A_DQ58

[3] M_B_CAS#

113

CAS#

DQ58

193

M_B_DQ58

WE#

DQ59

[3] M_B_WE#

WE#

DQ59

180

M_A_DQ57

114

180

M_B_DQ57

S0#

DQ60

[3]

M_B_CS#0

S0#

DQ60

182

M_A_DQ56

121

182

M_B_DQ56

S1#

DQ61

[3]

M_B_CS#1

S1#

DQ61

192

M_A_DQ62

192

M_B_DQ62

DQ62

194

M_A_DQ63

[3]

M_B_ODT0

116

DQ62

194

M_B_DQ63

ODT0

DQ63

ODT0

DQ63

120

ODT1

77

199

200

[3] M_B_ODT1

DIM2_SA0

197

ODT1

77

SA0

NC1

SA0

NC1

122

DIM2_SA1

201

122

SA1

NC2

125

MEM_MA_TEST

T17

SA1

NC2

125

MEM_MB_TEST

TEST

PDAT_SMB

200

TEST

SDA

SDA

PCLK_SMB

202

SCL

C309

SCL

4

196

.01u/16V_

199

196

VDDspd

VSS51

195

+3V

VDDspd

VSS51

195

VSS50

190

[3]

M_B_RST#

30

VSS50

190

RST#

VSS49

RST#

VSS49

189

189

VSS48

VSS48

185

198

185

EVENT#

VSS47

EVENT#

VSS47

184

184

VSS46

179

+1.5VSUS

+0.75VSMVREF_SUSB

1

VSS46

179

VREF

VSS45

178

oVREF

VSS45

178

VSS44

173

+VREF_CA_B

126

VSS44

173

VrefCA

VSS43

VrefCA

VSS43

VSS42

172

R314

VSS42

172

168

+0.75V_DDR_VTT

203

168

VTT1

VSS41

VTT1

VSS41

VTT2

VSS40

167

+0.75VSMVREF_SUSA

1K/F_4

204

VTT2

VSS40

167

162

162

VSS39

VSS39

161

2

161

VSS0

VSS38

156

C51

C42

C43

3

VSS0

VSS38

156

VSS1

VSS37

155

*10u/6.3V_6

.1u/10V_4

1000P/50V_

4

8

VSS1

VSS37

155

VSS2

VSS36

151

9

VSS2

VSS36

151

VSS3

VSS35

150

13

VSS3

VSS35

150

VSS4

VSS34

145

14

VSS4

VSS34

145

VSS5

VSS33

VSS5

VSS33

144

19

144

VSS6

VSS32

139

20

VSS6

VSS32

139

VSS7

VSS31

C386

C390

VSS7

VSS31

VSS8

VSS30

138

R312

25

VSS8

VSS30

138

VSS9

VSS14 VSS15 VSS16 VSS17 VSS18

VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26

VSS29

134

26

VSS9

VSS13

VSS14

VSS15 VSS16 VSS17 VSS18

VSS19 VSS20 VSS21 VSS22

VSS23

VSS24

VSS25 VSS26

VSS29

134

VSS11 VSS12VSS13

VSS27

128

.1u/10V_4

32

VSS11 VSS12

VSS27

128

VSS10

VSS28

133

1K/F_4

31

VSS10

VSS28

133

2.2u/6.3V_6

37

38

43

44

48

49

54

55

60

61

65

66

71

72

127

37

38

43

44

48

49

54

55

60

61

65

66

71

72

127

M_B_DQ[0..63] [3]

Place these Caps near So-Dimm H=8.

+1.5VSUS
C127	C139	C153	C80		C115
10u/6.3V_6	10u/6.3V_6	10u/6.3V_6	.1u/10V_4		.1u/10V_4
C152
10u/6.3V_6
C110	C102	C144		C99		C154
10u/6.3V_6 10u/6.3V_6 *.1u/16V_4				*.1u/16V_4		*.1u/16V_4

Place these Caps near So-Dimm H=4.

+1.5VSUS
C150	C149		C151	C134		C126
10u/6.3V_6 10u/6.3V_6			10u/6.3V_6	.1u/10V_4		.1u/10V_4
C124
10u/6.3V_6
	C111	C89	C125		C104		C155
	10u/6.3V_6	10u/6.3V_6 *.1u/16V_4			*.1u/16V_4		*.1u/16V_4

Standard

Connector

+1.5VSUS

+1.5VSUS

1

+ C163

+ C164

STD V1

2

330u/2V_7343

330u/2V_7343

CON SODIMM200_

Place on each DIMM Connector

T18

199

200

+1.5VSUS

R139 +0.75VSMVREF_SUSB 1K/F_4

C186

C190

R136

1K/F_4

.1u/10V_4

2.2u/6.3V_6

H=8		DDR3_SO-DIMM_H=8_1.5V_Standard	H=4			DDR3_SO-DIMM_H=4_1.5V_Standard
R246	10K_4	DIM1_SA0	DIM2_SA0	R36	10K_4	+3V
							352-(&7 =4
R248	10K_4	DIM1_SA1	DIM2_SA1	R32	10K_4
SMbus address A0			SMbus address A2				4XDQWD &RPSXWHU ,QF
		4	http://hobi-elektronika.net3			Size	Document Number	Rev
						2	1	1A
							DDR2 SODIMMS: A/B CHANNEL
						Date:	Thursday, March 04, 2010 Sheet 5 of	36

D

C

B

A

5

4

3

2

1

SIDE PORT

D

C312

SIDE@.1u/10V_4

SPM_VREFDQ

C311

SIDE@.1u/10V_4

C

R17 *100/F_4

B

+1.5V_MEM_VDDQ

R242

[11] SP_DDR3_RST#

A

HT_CADOUTP0

Y25

U16A

D24

HT_CADINP0

[2]

HT_CADOUTP0

HT_RXCAD0P

HT_TXCAD0P

HT_CADINP0

[2]

HT_CADOUTN0

Y24

PART 1 OF 6

D25

HT_CADINN0

[2]

HT_CADOUTN0

HT_RXCAD0N

HT_TXCAD0N

HT_CADINN0

[2]

HT_CADOUTP1

V22

E24

HT_CADINP1

[2]

HT_CADOUTP1

HT_RXCAD1P

HT_TXCAD1P

HT_CADINP1

[2]

HT_CADOUTN1

V23

E25

HT_CADINN1

[2]

HT_CADOUTN1

HT_RXCAD1N

HT_TXCAD1N

HT_CADINN1

[2]

HT_CADOUTP2

V25

F24

HT_CADINP2

[2]

HT_CADOUTP2

HT_RXCAD2P

HT_TXCAD2P

HT_CADINP2

[2]

HT_CADOUTN2

V24

F25

HT_CADINN2

[2]

HT_CADOUTN2

HT_RXCAD2N

HT_TXCAD2N

HT_CADINN2

[2]

HT_CADOUTP3

U24

F23

HT_CADINP3

[2]

HT_CADOUTP3

HT_RXCAD3P

HT_TXCAD3P

HT_CADINP3

[2]

HT_CADOUTN3

U25

F22

HT_CADINN3

[2]

HT_CADOUTN3

HT_RXCAD3N

HT_TXCAD3N

HT_CADINN3

[2]

HT_CADOUTP4

T25

H23

HT_CADINP4

[2]

HT_CADOUTP4

HT_RXCAD4P

HT_TXCAD4P

HT_CADINP4

[2]

HT_CADOUTN4

T24

H22

HT_CADINN4

[2]

HT_CADOUTN4

HT_RXCAD4N

HT_TXCAD4N

HT_CADINN4

[2]

HT_CADOUTP5

P22

J25

HT_CADINP5

+1.5V_MEM_VDDQ

+1.5V_MEM_VDDQ

[2]

HT_CADOUTP5

HT_RXCAD5P

I/F

HT_TXCAD5P

HT_CADINP5

[2]

HT_CADOUTN5

P23

J24

HT_CADINN5

[2]

HT_CADOUTN5

HT_CADOUTP6

P25

HT_RXCAD5N

HT_TXCAD5N

K24

HT_CADINP6

HT_CADINN5

[2]

[2]

HT_CADOUTP6

HT_RXCAD6P

HT_TXCAD6P

HT_CADINP6

[2]

[2]

HT_CADOUTN6

HT_CADOUTN6

P24

HT_RXCAD6N

CPU

HT_TXCAD6N

K25

HT_CADINN6

HT_CADINN6

[2]

HT_CADOUTP7

N24

K23

HT_CADINP7

[2]

HT_CADOUTP7

HT_RXCAD7P

HT_TXCAD7P

HT_CADINP7

[2]

[2]

HT_CADOUTN7

HT_CADOUTN7

N25

HT_RXCAD7N

HT_TXCAD7N

K22

HT_CADINN7

HT_CADINN7

[2]

R251

C11

R12

[2]

HT_CADOUTP8

HT_CADOUTP8

AC24

HT_RXCAD8P

HT_TXCAD8P

F21

HT_CADINP8

HT_CADINP8

[2]

SIDE@1K/F_4

SIDE@.1u/10V_4

SIDE@1K/F_4

[2]

HT_CADOUTN8

HT_CADOUTN8

AC25

HT_RXCAD8N

TRANSPORT

HT_TXCAD8N

G21

HT_CADINN8

HT_CADINN8

[2]

[2]

HT_CADOUTP14

HT_CADOUTN14

U21

HT_RXCAD14P

HT_TXCAD14P

P21

HT_CADINN14

HT_CADINP14

[2]

[2]

HT_CADOUTP9

HT_CADOUTN9

AB24

HT_RXCAD9P

HT_TXCAD9P

H21

HT_CADINN9

HT_CADINP9

[2]

[2]

HT_CADOUTN9

HT_CADOUTP10

AA24

HT_RXCAD9N

HT_TXCAD9N

J20

HT_CADINP10

HT_CADINN9

[2]

SPM_VREFCA

[2]

HT_CADOUTP10

HT_CADOUTN10

AA25

HT_RXCAD10P

HT_TXCAD10P

J21

HT_CADINN10

HT_CADINP10

[2]

[2]

HT_CADOUTN10

HT_CADOUTP11

Y22

HT_RXCAD10N

HT_TXCAD10N

J18

HT_CADINP11

HT_CADINN10

[2]

[2]

HT_CADOUTP11

HT_CADOUTN11

Y23

HT_RXCAD11P

HT_TXCAD11P

K17

HT_CADINN11

HT_CADINP11

[2]

R252

C13

R13

[2]

HT_CADOUTN11

HT_CADOUTP12

W21

HT_RXCAD11N

HT_TXCAD11N

L19

HT_CADINP12

HT_CADINN11

[2]

[2]

HT_CADOUTP12

HT_RXCAD12P

HT_TXCAD12P

HT_CADINP12

[2]

SIDE@1K/F_4

SIDE@1K/F_4

[2]

HT_CADOUTN12

HT_CADOUTN12

W20

HT_RXCAD12N

HT_TXCAD12N

J19

HT_CADINN12

HT_CADINN12

[2]

SIDE@.1u/10V_4

[2]

HT_CADOUTP13

HT_CADOUTP13

V21

HT_RXCAD13P

HT_TXCAD13P

M19

HT_CADINP13

HT_CADINP13

[2]

Signals

RS880

RX880

[2]

HT_CADOUTN13

HT_CADOUTN13

V20

HT_RXCAD13N

HT_TXCAD13N

L18

HT_CADINN13

HT_CADINN13

[2]

HT_CADOUTP14

U20

M21

HT_CADINP14

[2]

HT_CADOUTN14

HT_RXCAD14N

HT_TXCAD14N

HT_CADINN14

[2]

HT_CADOUTP15

U19

HYPER

P18

HT_CADINP15

HT_TXCALP

[2]

HT_CADOUTP15

HT_CADOUTN15

AA22

HT_RXCAD15P

HT_TXCAD15P

L20

HT_CADINN15

HT_CADINP15

[2]

Ra

Ra

[2]

HT_CLKOUTN1

HT_RXCLK1N

HT_TXCLK1N

HT_CLKINN1

[2]

HT_RXCALP

[2]

HT_CADOUTN15

HT_CLKOUTP0

T22

HT_RXCAD15N

HT_TXCAD15N

H24

HT_CLKINP0

HT_CADINN15

[2]

HT_TXCALN

301 ohm 1%

1.21k ohm 1%

[2]

HT_CLKOUTP0

HT_CLKOUTN0

T23

HT_RXCLK0P

HT_TXCLK0P

H25

HT_CLKINN0

HT_CLKINP0

[2]

[2]

HT_CLKOUTN0

HT_RXCLK0N

HT_TXCLK0N

HT_CLKINN0

[2]

HT_CLKOUTP1

AB23

L21

HT_CLKINP1

[2]

HT_CLKOUTP1

HT_RXCLK1P

HT_TXCLK1P

HT_CLKINP1

[2]

HT_CLKOUTN1

HT_CLKINN1

Rb

Rb

HT_CTLOUTP0

M22

M24

HT_CTLINP0

[2]

HT_CTLOUTP0

HT_RXCTL0P

HT_TXCTL0P

HT_CTLINP0

[2]

HT_RXCALN

301 ohm 1%

1.21k ohm 1%

U13

HT_CTLOUTN0

M23

M25

HT_CTLINN0

[2]

HT_CTLOUTN0

HT_RXCTL0N

HT_TXCTL0N

HT_CTLINN0

[2]

[2]

HT_CTLOUTP1

HT_CTLOUTP1

R21

HT_RXCTL1P

HT_TXCTL1P

P19

HT_CTLINP1

HT_CTLINP1

[2]

SPM_VREFCA

M9

E4

SPM_DQ2

HT_CTLOUTN1

R20

R18

HT_CTLINN1

VREFCA

DQL0

[2]

HT_CTLOUTN1

HT_RXCTL1N

HT_TXCTL1N

HT_CTLINN1

[2]

SPM_VREFDQ

H2

F8

SPM_DQ1

VREFDQ

DQL1

F3

SPM_DQ5

R274

301/F_4

HT_RXCALP

C23

B24

HT_TXCALP

R273

301/F_4

DQL2

HT_RXCALP

HT_TXCALP

SPM_A0

N4

A0

DQL3

F9

SPM_DQ3

HT_RXCALN

A24

HT_RXCALN

HT_TXCALN

B25

HT_TXCALN

RES CHIP 1.21K 1/16W +-1%(0402)

SPM_A1

P8

H4

SPM_DQ7

P/N : CS21212FB18

A1

DQL4

Ra

Rb

SPM_A2

P4

H9

SPM_DQ0

RS880/RX881

SPM_A3

N3

A2

DQL5

G3

SPM_DQ4

A3

DQL6

SPM_A4

P9

H8

SPM_DQ6

A4

DQL7

SPM_A5

P3

A5

SPM_A6

R9

A6

SPM_A7

R3

D8

SPM_DQ13

SPM_A8

T9

A7

DQU0

C4

SPM_DQ8

SPM_A9

R4

A8

DQU1

C9

SPM_DQ10

A9

DQU2

SPM_A10

L8

C3

SPM_DQ12

A10/AP

DQU3

This block is for Side-Port only

SPM_A11

R8

A8

SPM_DQ15

SPM_A12

N8

A12/BC

DQU5

A3

SPM_DQ11

A11

DQU4

SPM_A13

T4

A13

DQU6

B9

SPM_DQ14

T8

A4

SPM_DQ9

A14

DQU7

M8

A15

+1.5V_MEM_VDDQ

SPM_BA0

M3

B3

U16D

+1.5V_MEM_VDDQ

BA0

VDD#B3

PAR 4 OF 6

SPM_BA1

N9

BA1

VDD#D10

D10

SPM_A0

AB12

MEM_A0(NC)

MEM_DQ0/DVO_VSYNC(NC)

AA18

SPM_DQ0

SPM_BA2

M4

G8

SPM_A1

AE16

AA20

SPM_DQ1

BA2

VDD#G8

MEM_A1(NC)

MEM_DQ1/DVO_HSYNC(NC)

VDD#K3

K3

SPM_A2

V11

MEM_A2(NC)

MEM_DQ2/DVO_DE(NC)

AA19

SPM_DQ2

VDD#K9

K9

SPM_A3

AE15

MEM_A3(NC)

MEM_DQ3/DVO_D0(NC)

Y19

SPM_DQ3

VDD#N2

N2

SPM_A4

AA12

MEM_A4(NC)

MEM_DQ4(NC)

V17

SPM_DQ4

C323

R267

SPM_CLKP

J8

CK

VDD#N10

N10

SPM_A5

AB16

MEM_A5(NC)

MEM_DQ5/DVO_D1(NC)

AA17

SPM_DQ5

SIDE@1K/F_4

SPM_CLKN

K8

CK

VDD#R2

R2

SPM_A6

AB14

MEM_A6(NC)

MEM_DQ6/DVO_D2(NC)

AA15

SPM_DQ6

SIDE@.1u/10V_4

SPM_CKE

K10

CKE

VDD#R10

R10

+1.5V_MEM_VDDQ

SPM_A7

AD14

MEM_A7(NC)

MEM_DQ7/DVO_D4(NC)

Y15

SPM_DQ7

SPM_A8

AD13

AC20

SPM_DQ8

SPM_A9

AD15

MEM_A8(NC)

I/F

MEM_DQ8/DVO_D3(NC)

AD19

SPM_DQ9

SPM_VREF1

MEM_A9(NC)

MEM_DQ9/DVO_D5(NC)

SPM_ODT

K2

ODT

VDDQ#A2

A2

SPM_A10

AC16

MEM_A10(NC)

MEM_DQ10/DVO_D6(NC)

AE22

SPM_DQ10

SPM_CS#

L3

CS

VDDQ#A9

A9

SPM_A11

AE13

MEM_A11(NC)

MEM_DQ11/DVO_D7(NC)

AC18

SPM_DQ11

C322

R266

SPM_RAS#

J4

C2

SPM_A12

AC14

AB20

SPM_DQ12

RAS

VDDQ#C2

MEM_A12(NC)

_

MEM_DQ12(NC)

SPM_CAS#

K4

CAS

VDDQ#C10

C10

SPM_A13

Y14

MEM_A13(NC)

MEM_DQ13/DVO_D9(NC)

AD22

SPM_DQ13

SP@1K/F_4

SPM_WE#

L4

D3

SPM_RAS#

W12

MEM_RASb(NC)MEM/DVO

MEM_DQS1P(NC)

AD20

SPM_DQS1P

WE

VDDQ#D3

MEM_DQ14/DVO_D10(NC)

SIDE@.1u/10V_4

VDDQ#E10

E10

SPM_BA0

AD16

MEM_BA0(NC)

MEM_DQ15/DVO_D11(NC)

AD21

SPM_DQ15

VDDQ#F2

F2

SPM_BA1

AE17

MEM_BA1(NC)

SPM_DQS0P

F4

DQSL

VDDQ#H3

H3

SPM_BA2

AD17

MEM_BA2(NC)

MEM_DQS0P/DVO_IDCKP(NC)

Y17

SPM_DQS0P

SPM_DQS1P

C8

H10

W18

SPM_DQS0N

DQSU

VDDQ#H10

MEM_DQS0N/DVO_IDCKN(NC)

SPM_CAS#

Y12

MEM_CASb(NC)_

MEM_DQS1N(NC)

AE21

SPM_DQS1N

IOPLLVDD18 - memory PLL

SPM_DM0

E8

A10

SPM_WE#

AD18

DML

VSS#A10

MEM_WEb(NC)

SBD

SPM_DM1

D4

DMU

VSS#B4

B4

SPM_CS#

AB13

MEM_CSb(NC)

MEM_DM0(NC)

W17

SPM_DM0

not applicable to RX881

E2

SPM_CKE

AB18

AE19

SPM_DM1

VSS#E2

MEM_CKE(NC)

MEM_DM1/DVO_D8(NC)

G9

SPM_ODT

SPM_DQS0N

VSS#G9

V14

MEM_ODT(NC)

IOPLLVDD18_SIDE_PORT

L37

SP@BLM18PG221SN1D(220_1.4A)_6

15mA

G4

J3

AE23

+1.8V

DQSL

VSS#J3

IOPLLVDD18(NC)

SPM_DQS1N

B8

DQSU

VSS#J9

J9

SPM_CLKP

V15

MEM_CKP(NC)

IOPLLVDD(NC)

AE24

IOPLLVDD_SIDE_PORT

L38

SP@BLM18PG221SN1D(220_1.4A)_6

+1.1V

26mA

SIDE@10K/F_4

VSS#M2

M2

SPM_CLKN

W14

MEM_CKN(NC)

VSS#M10

M10

R268

SIDE@40.2/F_4

SPM_COMPP

IOPLLVSS(NC)

AD23

C319

C332

P2

AE12

VSS#P2

MEM_COMPP(NC)

T3

P10

R269

SIDE@40.2/F_4

SPM_COMPN

AD12

AE18

SPM_VREF1

SIDE@2.2u/6.3V_6

RESET

VSS#P10

T2

+1.5V_MEM_VDDQ

MEM_COMPN(NC)

MEM_VREF(NC)

W/I SP

W/O SP

VMA_ZQ2

VSS#T2

L9

T10

ZQ

VSS#T10

R237

B2

RS880/RX881

SIDE@2.2u/6.3V_6

R266

1K

0

VSSQ#B2

L37

Bead

0

0ohm size 0603 CS00003J951

B10

SIDE@240/F_4

VSSQ#B10

D2

40 mil~50 mil

size 0402 CS00002JB38

L38

Bead

0

VSSQ#D2

VSSQ#D9

D9

1K ohm

CS21002FB24

VSSQ#E3

E3

+1.5V_MEM_VDDQ

+1.5V

Bead

CX8PG221003

J2

E9

NC#J2

VSSQ#E9

SIDE@.1u/10V_4

SIDE@1u/6.3V_4

L2

F10

NC#L2

VSSQ#F10

R244

SIDE@0_8

J10

G2

352-(&7 =4

NC#L10

VSSQ#G10

http://hobiC305

C301-

elektronika.netC15 C12

C14

C310

L10

NC#J10

VSSQ#G2

G10

SDRAM DDR3

SIDE@10u/6.3V_6

4XDQWD &RPSXWHU ,QF

100-BALL

SIDE@H5TQ1G63AFR-14C

SIDE@.1u/10V_4

SIDE@10u/6.3V_6

SIDE@1u/6.3V_4

Size

Document Number

Rev

RS880M-HT LINK I/F 1/4

1A

Date:

Thursday, March 04, 2010

Sheet

6

of

36

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

C

B

A

[17]PCIE_RX1+

[17]PCIE_RX1-

[18]PCIE_RXP2

[18]PCIE_RXN2

[10]A_RXP0

[10]A_RXN0

[10]A_RXP1

[10]A_RXN1

[10]A_RXP2

[10]A_RXN2

[10]A_RXP3

[10]A_RXN3

T16

T12

D4

C4

A3

B3

C2

C1

E5

F5

G5

G6

H5

H6

J6

J5

J7

J8

L5

L6

M8

L8

P7

M7

P5

M5

R8

P8

R6

R5

P4

P3

T4

T3

AE3

AD4

AE2

AD3

AD1

AD2

V5

W6

U5

U6

U8

U7

AA8

Y8

AA7

Y7

AA5

AA6

W5

Y5

U16B

GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N

GPP_RX0P

GPP_RX0N

GPP_RX1P

GPP_RX1N

GPP_RX2P

GPP_RX2N

GPP_RX3P

GPP_RX3N

GPP_RX4P

GPP_RX4N

GPP_RX5P

GPP_RX5N

SB_RX0P

SB_RX0N

SB_RX1P

SB_RX1N

SB_RX2P

SB_RX2N

SB_RX3P

SB_RX3N

RS880/RX881

PART 2 OF 6	GFX_TX0P
	GFX_TX0N
	GFX_TX1P
	GFX_TX1N
	GFX_TX2P
	GFX_TX2N
	GFX_TX3P
	GFX_TX3N
	GFX_TX4P
	GFX_TX4N
	GFX_TX5P
	GFX_TX5N
	GFX_TX6P
	GFX_TX6N
GFX	GFX_TX7P
	GFX_TX7N
	GFX_TX8P
	GFX_TX8N
	GFX_TX9P
I/F	GFX_TX9N
	GFX_TX10P
	GFX_TX10N
	GFX_TX11P
PCIE	GFX_TX11N
	GFX_TX13N
	GFX_TX12P
	GFX_TX12N
	GFX_TX13P
	GFX_TX14P
	GFX_TX14N
	GFX_TX15P
	GFX_TX15N
	GPP_TX0P
	GPP_TX0N
	GPP_TX1P
	GPP_TX1N
PCIE I/F GPP	GPP_TX2P
	GPP_TX2N
	GPP_TX3P
	GPP_TX3N
	GPP_TX4P
	GPP_TX4N
	GPP_TX5P
	GPP_TX5N
	SB_TX0P
	SB_TX0N
	SB_TX1P
PCIE I/F SB	SB_TX1N
	SB_TX2P
	SB_TX2N
	SB_TX3P
	SB_TX3N

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

A5

TX2_HDMI+_C

C356

.1u/10V_4

TX2_HDMI+

[16]

B5

TX2_HDMI-_C

C355

.1u/10V_4

TX2_HDMI- [16]

A4

TX1_HDMI+_C

C352

.1u/10V_4

TX1_HDMI+

[16]

B4

TX1_HDMI-_C

C351

.1u/10V_4

TX1_HDMI- [16]

HDMI

C3

TX0_HDMI+_C

C350

.1u/10V_4

TX0_HDMI+

[16]

B2

TX0_HDMI-_C

C349

.1u/10V_4

TX0_HDMI-

[16]

D1

TXC_HDMI+_C

C348

.1u/10V_4

TXC_HDMI+

[16]

D2

TXC_HDMI-_C

C347

.1u/10V_4

TXC_HDMI-

[16]

E2

E1

F4

RS880 Display Port Support (muxed on GFX)

F3

F1

F2

GFX_TX0,TX1,TX2 and TX3

H4

DP0

H3

AUX0 and HPD0

H1

H2

J2

GFX_TX4,TX5,TX6 and TX7

J1

DP1

K4

AUX1 and HPD1

K3

K1

K2

M4

M3

M1

M2

N2

N1

P1

P2

AC1

PCIE_TXP0_C

C338

.1u/10V_4

AC2

PCIE_TXN0_C

C339

.1u/10V_4

AB4

AB3

PCIE_TXP2_C

C340

.1u/10V_4

AA2

AA1

PCIE_TXN2_C

C341

.1u/10V_4

Y1

Y2

Y4

T11

Y3

T14

V1

V2

AD7

A_TXP0_C

C324

.1u/10V_4

AE7

A_TXN0_C

C325

.1u/10V_4

AE6

A_TXP1_C

C327

.1u/10V_4

AD6

A_TXN1_C

C326

.1u/10V_4

AB6

A_TXP2_C

C329

.1u/10V_4

AC6

A_TXN2_C

C328

.1u/10V_4

AD5

A_TXP3_C

C331

.1u/10V_4

AE5

A_TXN3_C

C330

.1u/10V_4

AC8

NB_PCIECALRP

R265

1.27K/F_4

AB8

NB_PCIECALRN

R264

2K/F_4

PCIE_TX1+ [17]

PCIE_TX1- [17]

PCIE_TXP2 [18]

PCIE_TXN2 [18]

A_TXP0 [10]

A_TXN0 [10]

A_TXP1 [10]

A_TXN1 [10]

A_TXP2 [10]

A_TXN2 [10]

A_TXP3 [10]

A_TXN3 [10]

+1.1V

LAN

WLAN

SB

			352-(&7 =4
http://hobi-elektronika.net			4XDQWD &RPSXWHU ,QF
		Size	Document Number		Rev
			RS880M-PCIE I/F 2/4		1A
		Date:	Thursday, March 04, 2010	Sheet 7 of	36

D

C

B

A

5

4

3

2

1

D

C

B

A

5

4

3

2

1

All RS880 variants do not support analog TV-out

U16C

For Check list JTAG

functionality. As such, Y, C_Pr, and COMP_Pb

+3V_AVDD_NB

E12

AVDD2(NC)

PART 3 OF 6

TXOUT_L0N(NC)

B22

LA_DATAN0

[15]

F12

AVDD1(NC)

TXOUT_L0P(NC)

A22

LA_DATAP0

[15]

R279

*4.7K_4

NB_PWRGD_IN

+1.8V_AVDDDI_NB

F14

AVDDDI(NC)

TXOUT_L1P(NC)

A21

LA_DATAP1

[15]

+1.8V_AVDDQ_NB

G15

AVSSDI(NC)

TXOUT_L1N(NC)

B21

LA_DATAN1

[15]

H15

B20

R88

*4.7K_4

INT_EDIDDATA

H14

AVDDQ(NC)

TXOUT_L2P(NC)

A20

LA_DATAP2

[15]

+3V

AVSSQ(NC)

TXOUT_L2N(DBG_GPIO0)

A19

LA_DATAN2

[15]

R96

*4.7K_4

INT_EDIDCLK

E17

CRT/TVOUT

TXOUT_L3P(NC)

B19

[15]

INT_CRT_BLU

R104

150/F_4

F19

BLUE(DFT_GPIO3)

TXOUT_U3P(PCIE_RESET_GPIO5)

D19

F17

C_Pr(DFT_GPIO5)

TXOUT_L3N(DBG_GPIO2)

+3V

R94

*4.7K_4

HDMI_DDC_DATA

F15

Y(DFT_GPIO2)

B18

COMP_Pb(DFT_GPIO4)

TXOUT_U0P(NC)

A18

[15]

INT_CRT_RED

G18

TXOUT_U0N(NC)

A17

R102

140/F_4

G17

REDb(NC)

TXOUT_U1N(PCIE_RESET_GPIO2)

B17

[15]

INT_CRT_GRE

E18

D20

R103

150/F_4

F18

GREEN(DFT_GPIO1)

TXOUT_U2P(NC)

D21

E19

GREENb(NC)

TXOUT_U2N(NC)

D18

BLUEb(NC)

TXOUT_U3N(NC)

[15] INT_CRT_HSYNC

INT_CRT_HSYNC

A11

DAC_HSYNC(PWM_GPIO4)

TXCLK_LP(DBG_GPIO1)

B16

LA_CLK

[15]

INT_CRT_VSYNC

B11

A16

[15]

INT_CRT_VSYNC

DAC_VSYNC(PWM_GPIO6)

TXCLK_LN(DBG_GPIO3)

LA_CLK#

[15]

E8

D16

[15]

INT_DDCDATA

DAC_SDA(PCE_TCALRN)

TXCLK_UP(PCIE_RESET_GPIO4)

F8

D17

VGA

[15]

INT_DDCCLK

DAC_SCL(PCE_RCALRN)

TXCLK_UN(PCIE_RESET_GPIO1)

R79

715/F_6

DAC_RSET_NB

G14

DAC_RSET(PWM_GPIO1)

VDDLTP18(NC)

A13

+1.8V_VDDLTP18_NB

15mA

+1.1V_PLLVDD

A12

PLLVDD(NC)

VSSLTP18(NC)

B13

+1.8V_PLLVDD18

D14

LVTM

PLLVDD18(NC)

+1.8V_VDDLT_18_NB

300mA

B12

PWR

VDDLT33_2(NC)

B14

PLLVSS(NC)

VDDLT18_1(NC)

A15

20mA

VDDLT18_2(NC)

B15

+1.8V_VDDA18HTPLL

H17

A14

VDDA18HTPLL

VDDLT33_1(NC)

120mA

+1.8V_VDDA18PCIEPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

VSSLT1(VSS)

C14

D15

PLL

VSSLT2(VSS)

[10,25]

A_RST#_SB

D8

C16

A10

SYSRESETb

VSSLT3(VSS)

C18

[2,11,14]

NB_PWRGD_IN

POWERGOOD

VSSLT4(VSS)

NB_LDT_STOP#

C10

PM

C20

LDTSTOPb

VSSLT5(VSS)

NB_ALLOW_LDTSTOP

C12

E20

ALLOW_LDTSTOP

VSSLT6(VSS)

C22

[10] CLK_NB_HTREFP_PR

C25

HT_REFCLKP

VSSLT7(VSS)

C24

For A11 version

[10] CLK_NB_HTREFN_PR

CLK_NB_REF_CLKP

E11

HT_REFCLKN

CLOCKs

[10]

CLK_NB_REF_CLKP

REFCLK_P/OSCIN(OSCIN)

E9

T15

GPP_REFCLKP

U1

GPP_REFCLKP

(02/10) Donˇt need 49.9 ohm PD.

[10]

CLK_NB_REF_CLKN

CLK_NB_REF_CLKN

F11

REFCLK_N(PWM_GPIO3)

LVDS_DIGON(PCE_TCALRP)

INT_LVDS_DIGON [15]

R46

4.7K_4

NBGFX_CLKP

T2

GFX_REFCLKP

LVDS_ENA_BL(PWM_GPIO2)

G12

INT_LVDS_BLON

[15]

R45

4.7K_4

NBGFX_CLKN

T1

GFX_REFCLKN

R47

*49.9/F_4

CLK_SBLINKP

T13

GPP_REFCLKN

U2

GPP_REFCLKN

R48

*49.9/F_4

CLK_SBLINKN

[10]

CLK_SBLINKP

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

[10]

CLK_SBLINKN

A9

GPPSB_REFCLKN(SB_REFCLKN)

[15]

INT_EDIDDATA

I2C_DATA

MIS.

B8

TMDS_HPD(NC)

D10

INT_HDMI_HPD

[16]

[15]

INT_EDIDCLK

I2C_CLK

B9

D9

[16] HDMI_DDC_DATA

DDC_DATA/AUX0N(NC)

HPD(NC)

A8

[16] HDMI_DDC_CLK

DDC_CLK/AUX0P(NC)

SUS_STAT#_NB

R111

*0/short_4

B7

D12

SUS_STAT# [11]

DDC_DATA & DDC_CLK Not applicable to RX881

A7

AUX1P(NC)

TVCLKIN(PWM_GPIO5)

AUX1N(NC)

AE8

[30]

+NB_CORE_ON

+NB_CORE_ON

B10

THERMALDIODE_P

AD8

R112

Made provision for external pull-down which is not

STRP_DATA

THERMALDIODE_N

G11

D13

TEST_EN

*3K_4

installed by default. Pulled up externally for

RSVD

TESTMODE

bypassing EEPROM strapping and using default

T74

RS880_AUX_CAL

C8

AUX_CAL(NC)

R87

values.

1.8K/F_4

RS880/RX881

RS880M --- ADD

+3V

+1.1V

+1.8V

STRAP_DEBUG_BUS_GPIO_ENABLEb

L11

+3V_AVDD_NB

L39

+1.1V_PLLVDD

L15

+1.8V_VDDLTP18_NB

BLM18PG221SN1D(220

_1.4A)_6

BLM18PG221SN1D(220

_1.4A)_6

BLM18PG221SN1D(220

_1.4A)_6

C135

AVDD-DAC Analog

PLLVDD - Graphics PLL

VDDLTP18 - LVDS or DVI/HDMI PLL

Enables the Test Debug Bus using GPIO.

C120

C123 not applicable to RX780

C359

not applicable to RX780

2.2U/6.3V_6

not applicable to RX780

*10u/6.3V_8

2.2U/6.3V_6

2.2U/6.3V_6

RS880M

L40

1 Disable

V

INT_CRT_VSYNC

R277

3K_4

+3V

+1.8V_VDDLT_18_NB

0 Enable

+1.8V

+1.8V

BLM21PG221SN1D(220,100M,2A)_8

VDDLT18 - LVDS or DVI/HDMI digital

R86

0_6

+1.8V_AVDDDI_NB

L13

+1.8V_PLLVDD18

C360

C357

not applicable to RX780

BLM18PG221SN1D(220_1.4A)_6

C113

AVDDI-DAC Digital

PLLVDD18 - Graphics PLL

4.7u/6.3V_6

.1u/10V_4

RS880M: Enables Side port memory

not applicable to RX780

not applicable to RX780

.1u/10V_4

C128

C147

4.7u/6.3V_6

RS880M:INT_CRT_HSYNC

L9

+1.8V_AVDDQ_NB

*10u/6.3V_8

Selects if Memory SIDE PORT is available or not

BLM18PG221SN1D(220

_1.4A)_6

AVDDQ-DAC Bandgap Reference

1 = Memory Side port Not available

C108

not applicable to RX780

2.2U/6.3V_6

0 = Memory Side port available

Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]

+1.8V

20mils width

+1.8V

VDDA18PCIEPLL -PCIE PLL

+1.8V

9/16 need modify PN

DDR3 based CPU : Level shifted to 1.8 V on the

Northbridge side using an open-drain buffer and

INT_CRT_HSYNC

R276

*SP@3K_4

L10

+1.8V_VDDA18PCIEPLL

R107

pulled up to 1.8V_S0 through a 2.2k Ohm 5% resistor

+3V

on the Northbridge side.

R100

SIDE@3K_4

BLM18PG221SN1D _6

5

+ U6

2.2K_4

C122

NB_LDT_STOP#

[2,10]

CPU_LDT_STOP#

2

Open

4

2.2U/6.3V_6

Drain

For extrnal EEPROM Debug only

RS780/RX780/RS880

3

- 74LVC07

VDDA18HTPLL -HT LINK PLL

20mils width

R285

1K_4

+1.8V

L14

+1.8V_VDDA18HTPLL

http://hobi-elektronika.net

R284

*0_4

NB_ALLOW_LDTSTOP

+NB_CORE_ON

R278

2K/F_4

BLM18PG221SN1D _6

[2]

CPU LDT REQ#

C106

[10]

ALLOW_LDTSTOP

R283

0_4

2.2U/6.3V_6

352-(&7 =4

Display Port interface from PCIeGraphics (RS880/rs880M only)

The RS880 family does not support CLMC architecture

4XDQWD &RPSXWHU ,QF

The LDTREQ# connection from the CPU to ALLOW_LDTSTOP

of the Northbridge is no longer required.

Size

Document Number

Rev

RS880_AUX_CAL

R282

*150/F_4

RS880M-SYSTEM I/F 3/4

1A

Date:

Thursday, March 04, 2010

Sheet

8 of

36

D

C

B

A

5

4

3

2

1

5	4			3		2	1
		A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2				AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
	U16F	VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5	VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17	VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27	VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40	VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10
D							D
		6/6
				GROUND
		PART
		VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5	VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17	VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27	VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22	VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
		A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25			L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11

+1.1V

+1.1V 2A for RS880M

C

0.68A L7

U16E

1.1A

C

+1.1V_VDDHT

J17

VDDHT_1

PART 5/6

VDDPCIE_1

A6

+1.1V_VDD_PCIE

R63

0_8

+1.1V

0_8

K16

VDDHT_2

VDDPCIE_2

B6

C68

C71

C64

C79

L16

VDDHT_3

VDDPCIE_3

C6

C85

C69

C77

C107

C60

VDDPCIE - PCIE-E Main power

M16

D6

VDDHT_4

VDDPCIE_4

4.7u/6.3V_6

.1u/10V_4

.1u/10V_4

.1u/10V_4

P16

VDDHT_5

VDDPCIE_5

E6

.1u/10V_4

.1u/10V_4

1u/10V_4

1u/10V_4

4.7u/6.3V_6

R16

VDDHT_6

VDDPCIE_6

F6

T16

G7

0.68A L12

VDDHT_7

VDDPCIE_7

+1.1V_VDDHTRX

H18

J9

VDDHTRX_1

VDDPCIE_9

VDDPCIE_8

H8

0_8

G19

VDDHTRX_2

VDDPCIE_10

K9

F20

M9

C132

C129

C141

C130

VDDHTRX_3

VDDPCIE_11

E21

L9

VDDHTRX_4

VDDPCIE_12

4.7u/6.3V_6

.1u/10V_4

.1u/10V_4

.1u/10V_4

D22

P9

+1.1V 2A for RS880M

VDDHTRX_5

VDDPCIE_13

A23

T9

VDDHTRX_6

VDDPCIE_14

B23

R9

+1.1V

L36

0.68A

+1.1V_VDDHTTX

AE25

VDDHTRX_7

VDDPCIE_15

U9

VDDHTTX_1

VDDPCIE_17

VDDPCIE_16

V9

0.95~1.1V@10A

0_6

AD24

VDDHTTX_2

K12

C317

C55

C321

C337

C335

AC23

VDDHTTX_3

VDDC_1

NB_CORE

AB22

J14

VDDHTTX_4

VDDC_2

VDDC - Core Logic power

4.7u/6.3V_6

.1u/10V_4

.1u/10V_4

.1u/10V_4

.1u/10V_4

AA21

U16

VDDHTTX_5

VDDC_3

C62

C66

C59

C78

C344

Y20

VDDHTTX_6

POWER

VDDC_4

J11

W19

K15

.1u/10V_4

.1u/10V_4

.1u/10V_4

.1u/10V_4

10u/6.3V_8

VDDHTTX_7

VDDC_5

N14

V18

VDDHTTX_8

VDDC_6

M12

U17

VDDHTTX_9

VDDC_7

L14

T17

VDDHTTX_10

VDDC_8

L11

+1.8V 1A for RS780M+SB700

R17

VDDHTTX_11

VDDC_9

M13

B

M17

VDDHTTX_12

VDDC_10

N12

B

P17

M15

0.7A

VDDHTTX_13

VDDC_11

+1.8V

L4

+1.8V_VDDA18PCIE

J10

VDDC_12

P11

C76

C74

C100

C346

VDDA18PCIE_1

VDDC_13

BLM21PG221SN1D(220,100M,2A)_8

P10

VDDA18PCIE_2

VDDC_14

P13

.1u/10V_4

.1u/10V_4

.1u/10V_4

10u/6.3V_8

K10

P14

C54

C44

C101

C58

C50

C45

VDDA18PCIE_3

VDDC_15

M10

R12

VDDA18PCIE_4

VDDC_16

4.7u/6.3V_6

4.7u/6.3V_6

.1u/10V_4

.1u/10V_4

.1u/10V_4

.1u/10V_4

L10

R15

VDDA18PCIE_5

VDDC_17

W/I SP

W/O SP

W9

T11

C313

VDDA18PCIE_6

VDDC_18

H9

T15

T10

VDDA18PCIE_7

VDDC_19

U12

(Ra)

0.1U

0 ohm

VDDA18PCIE_8

VDDC_20

R10

VDDA18PCIE_9

VDDC_21

T14

100mA

AA9

J16

Ra

SIDE@0_8

VDDA18PCIE_11

25mA

Y9

VDDA18PCIE_10

VDDC_22

+1.8V

R81

0_6

+1.8V_VDDG18_NB

AB9

VDDA18PCIE_12

VDD_MEM1(NC)

AE10

VDD_MEM_SIDE

L35

+1.5V

VDD18-RS880 I/O Transform

AD9

VDDA18PCIE_13

VDD_MEM2(NC)

AA11

C313

C333

C318

C314

C315

AE9

Y11

VDDA18PCIE_14

VDD_MEM3(NC)

U10

AD10

SIDE@.1u/10V_4

SIDE@.1u/10V_4

C109

VDDA18PCIE_15

VDD_MEM4(NC)

AB10

SP@.1u/10V_4

SIDE@.1u/10V_4

SIDE@4.7u/6.3V_6

VDD_MEM5(NC)

1u/10V_4

F9

AC10

VDDG18_1(VDD18_1) VDD_MEM6(NC)

RS880

G9

VDDG18_2(VDD18_2)

+3V_VDDG33

R74

0_4

DIS remove this BEAS ,

AE11

H11

+3V

R40

SIDE@0_6

+1.8V_VDD18_MEM

VDD18_MEM1(NC)

VDDG33_1(NC)

60mA

+1.8V

AD11

H12

VDD18_MEM2(NC)

VDDG33_2(NC)

C84

C83

3.3V(0.03A)

add Ra(C832) as ohm to GND

C41

VDD18_MEM For UMA RS880 only

RS880/RX881

.1u/10V_4

.1u/10V_4

1u/10V_4

VDD33 - 3.3V I/O

0_4

CS00002JB38

Not applicable to RX780

.1u/10V_4

CH41002KB93

Not applicable to RX780

memory I/O transform

A

A

http://hobi-elektronika.net			352-(&7 =4
			4XDQWD &RPSXWHU ,QF
		Size	Document Number		Rev
			RS880M-POWER4/4		1A
		Date:	Thursday, March 04, 2010	Sheet 9 of	36

5

4

3

2

1

D

C

B

A

5

4

3

2

1

For AMD RST

+3V_S5

C471

180p/50V_4

PLACE CAPS VERY CLOSE TO

C289

.1u/10V_4

NB & EC

BALL OF SB800M

U21A

5

SB800

Part 1 of 5

R208

2

A_RST#_SB

PCIE_RST#_SB

PCI_CLK0

A_RST#_AND

[18,21]

PCIE_RST#

R380

33_4

P1

PCIE_RST#

PCICLK0

W2

T115

[17,18]

A_RST#

33_4

4

A_RST#_SB

L1

CLKS

W1

PCI_CLK1

1

[8,25]

A_RST#_SB

A_RST#

PCICLK1/GPO36

PCI_CLK1

[14]

SB_GPIO_PCIE_RST#

[11]

W3

PCI_CLK2

C287

PCICLK2/GPO37

PCI_CLK2

[14]

GPU

C403

.1u/10V_4

A_RX0P_C

AD26

W4

PCI_CLK3

U11

[7]

A_RXP0

A_TX0P

PCICLK3/GPO38

PCI_CLK3

[14]

3

[7]

A_RXN0

C402

.1u/10V_4

A_RX0N_C

AD27

A_TX0N

PCI

PCICLK4/14M_OSC/GPO39

Y1

PCI_CLK4

PCI_CLK4

[14]

MINI-PCIE

10p/50V_4

TC7SH08FU

[7]

A_RXP1

C399

.1u/10V_4

A_RX1P_C

AC28

A_TX1P

V2

Card reader

[7]

A_RXN1

C398

.1u/10V_4

A_RX1N_C

AC29

PCIRST#

C405

.1u/10V_4

A_RX2P_C

AB29

A_TX1N

[7]

A_RXP2

A_TX2P

D

C404

.1u/10V_4

A_RX2N_C

AB28

R206

*0_4

[7]

A_RXN2

A_TX2N

C401

.1u/10V_4

A_RX3P_C

AB26

AA1

[7]

A_RXP3

A_TX3P

AD0/GPIO0

C400

.1u/10V_4

A_RX3N_C

AB27

AA4

[7]

A_RXN3

A_TX3N

AD1/GPIO1

AA3

+BAT

[25]

A_TXP0

AD2/GPIO2

20mil

[7]

A_TXP0

AE24

AB1

A_RX0P

AD3/GPIO3

ECN: B3A

[7]

A_TXN0

A_TXN0

AE23

A_RX0N

INTERFACES

AD4/GPIO4

AA5

A_TXP1

AD25

AB2

Add it for Green Adpapter.

[7]

A_TXN3

A_TXN1

AD24

A_RX3N

AD10/GPIO10

AC4

BOARD_ID1

BOARD_ID0

[12]

VCCRTC_1

+AVBAT

[7]

A_TXP1

A_RX1P

AD5/GPIO5

AB6

T111

+3VPCU

[7]

A_TXN1

A_TXP2

AC24

A_RX1N

AD6/GPIO6

AB5

It can decrease drop voltage.

[7]

A_TXP2

A_TXN2

AC25

A_RX2P

AD7/GPIO7

AA6

20MIL

D20

[7]

A_TXN2

A_TXP3

AB25

A_RX2N

AD8/GPIO8

AC2

[7]

A_TXP3

A_RX3P

AD9/GPIO9

A_TXN3

AB24

AC3

BOARD_ID0

+3VRTC

R288

10_4

+3VRTC_1

R287

499/F_4

R317

590/F_4

PCIE_CALRP_SB

AD29

EXPRESS

AD11/GPIO11

AC1

BOARD_ID2

BOARD_ID1

[12]

20MIL

PCIE_CALRP

AD12/GPIO12

BOARD_ID2

[12]

1

20MIL

from22K to 12K

+1.1V_PCIE_VDDR

R145

2K/F_4

PCIE_CALRN_SB

AD28

GPP_TX0N

AD16/GPIO16

AD1

BOARD_ID3

BOARD_ID3

[12]

BAT54C

PCIE_CALRN

AD13/GPIO13

ECN: B3A

C364

AD14/GPIO14

AD2

BOARD_ID4

BOARD_ID4

[12]

AA28

GPP_TX0P

AD15/GPIO15

AC6

Change R289

1u/10V_4

AA29

AE2

R290

Y29

GPP_TX1P

PCI

AD17/GPIO17

AE1

T113

Y28

AF8

1K_4

GPP_TX1N

AD18/GPIO18

Y26

AE3

Y27

GPP_TX2P

AD19/GPIO19

AF1

2

+5VPCU

GPP_TX2N

AD20/GPIO20

W28

AG1

GPP_TX3P

AD21/GPIO21

W29

AF2

GPP_TX3N

AD22/GPIO22

+BAT

RTC_N01

R289

GA@12K_6

AE9

AD23

[14]

1

3

AD23/GPIO23

AA22

AD9

AD24

[14]

GPP_RX0P

AD24/GPIO24

20MIL

Q26

20MIL

Y21

GPP_RX0N

AD25/GPIO25

AC11

AD25

[14]

R185

0_4

R293

AA25

GPP_RX1P

AD26/GPIO26

AF6

AD26

[14]

VDDR_1.05_EN

[12]

GA@MMBT3904

AA24

AF4

GA@68.1K/F_4

GPP_RX1N

AD27/GPIO27

AD27

[14]

W23

AF3

2

C

GPP_RX2P

AD28/GPIO28

V24

AH2

1

GPP_RX2N

AD29/GPIO29

RTC_N03

W24

AG2

GPP_RX3P

AD30/GPIO30

W25

AH3

GPP_RX3N

INTERFACE

AD31/GPIO31

AA8

2

ML2032

AHL03001034

DEVSEL#

CBE0#

AD5

CBE1#

AD8

R296

CBE2#

AA10

BAT1

GA@150K/F_6

CBE3#

ML2032 (Chargerable)

AE8

BAT_CONN

FRAME#

CLK_SBLINKP

M23

AB9

[8]

CLK_SBLINKP

PCIE_RCLKP/NB_LNK_CLKP

PCI

IRDY#

AJ3

CLK_SBLINKN

P23

AE7

[8]

CLK_SBLINKN

PCIE_RCLKN/NB_LNK_CLKN

TRDY#

CR2032 (Non-Chargeable)

Non-Green

CLK_NB_REF_CLKP

U29

PAR

AC5

[8] CLK_NB_REF_CLKP

NB_DISP_CLKP

STOP#

AF5

AHL03003003

Remove those parts.

CLK_NB_REF_CLKN

U28

AE6

[8] CLK_NB_REF_CLKN

NB_DISP_CLKN

PERR#

AE4

AHL03003014

Add "NGA@"

CLK_NB_HTREFP_PR

SERR#

+3V

[8]

CLK_NB_HTREFP_PR

T26

NB_HT_CLKP

AE11

AHL030M0009

REQ0#

[8]

CLK_NB_HTREFN_PR

CLK_NB_HTREFN_PR

T27

NB_HT_CLKN

REQ1#/GPIO40

AH5

T112

CLK_CPU_BCLKP_PR

REQ2#/CLK_REQ8#/GPIO41

AH4

R60

*10K_4

[2] CLK_CPU_BCLKP_PR

V21

AC12

T60

CPU_HT_CLKP

REQ3#/CLK_REQ5#/GPIO42

CLK_CPU_BCLKN_PR

T21

AD12

[2]

CLK_CPU_BCLKN_PR

CPU_HT_CLKN

GNT0#

AJ5

PCH_ODD_EN

[19]

GNT1#/GPO44

V23

AH6

SLT_GFX_CLKP

GNT2#/GPO45

T23

AB12

T55

SLT_GFX_CLKN

GNT3#/CLK_REQ7#/GPIO46

AB11

CLKRUN#

[25]

CLK_PCIE_LOM

CLKRUN#

[17]

CLK_PCIE_LOM

L29

AD7

T66

GPP_CLK0P

LOCK#

CLK_PCIE_LOM#

L28

[17]

CLK_PCIE_LOM#

GPP_CLK0N

AJ6

INTE#/GPIO32

N29

AG6

GPP_CLK1P

INTF#/GPIO33

For STRAPS

N28

AG4

GPP_CLK1N

INTG#/GPIO34

B

CLK_PCIE_WLANP_2

M29

INTH#/GPIO35

AJ4

[18]

CLK_PCIE_WLANP_2

GPP_CLK2P

LPC_CLK0

[14]

CLK_PCIE_WLANN_2

M28

[18]

CLK_PCIE_WLANN_2

GPP_CLK2N

GENERATORCLOCK

LPC_CLK1

[14]

P29

LDRQ1#/CLKLPC

_REQ6#/GPIO49

AA18

LDRQ1#_SB

T52

GPP_CLK6P

T25

GPP_CLK3P

R335

22_4

V25

GPP_CLK3N

LPCCLK0

H24

PCLK_DEBUG

[18]

LPCCLK1

H25

R326

22_4

CLK_PCI_775

[25]

L24

GPP_CLK4P

LAD0

J27

LPC_LAD0

[18,25]

L23

GPP_CLK4N

LAD1

J26

LPC_LAD1

[18,25]

C417

C423

LAD2

H29

LPC_LAD2

[18,25]

P25

H28

*5.6p/50V_4

*22P/50V_4

GPP_CLK5P

LAD3

LPC_LAD3

[18,25]

M25

G28

GPP_CLK5N

LFRAME#

LDRQ0#_SB

LPC_LFRAME#

[18,25]

J25

T50

LDRQ0#

P28

GPP_CLK6N

SERIRQ/GPIO48

AB19

IRQ_SERIRQ

[25]

for EMI suggestion

RTC_X1

N26

GPP_CLK7P

Y5

R148

*10K/F_4

N27

+3V_S5

2

3

GPP_CLK7N

G21

ALLOW_LDTSTP/DMA_ACTIVE#

ALLOW_LDTSTOP

[8]

T29

H21

CPU_PROCHOT#

[2]

GPP_CLK8P

CPU

PROCHOT#

T28

K19

CPU_PWRGD

[2,28]

GPP_CLK8N

LDT_PG

RTC_X2

LDT_STP#

G22

CPU_LDT_STOP#

[2,8]

1

4

L25

LDT_RST#

J24

CPU_LDT_RST# [2]

R384

14M_25M_48M_OSC

32.768KHZ

*20M_6

C1

RTC_X1

R392

20M_6

32K_X1

C396

27p/50V_4

25M_X1

L26

25M_X1

RTC

32K_X2

C2

RTC_X2

C472

C470

2

RTCCLK

D2

INTRUDER_ALERT#

RTC_CLK

[25]

R372

*1M/F_4

18p/50V_4

18p/50V_4

A

B2

+AVBAT

25MHz

R319

25M_X2

L27

25M_X2

INTRUDER_ALERT#

B1

+AVBAT

Y2

1M_4

VDDBT_RTC_G

1

INTRUDER_ALERT# Left not connected

G1

1

SB800 A11

C468

(Southbridge has 50-kohm internal

*SHORT_ PAD1

http://hobi-elektronika.net

pull-up to VBAT).

352-(&7 =4

.1u/10V 4

C395

27p/50V_4

IC CTRL(528P) SB710 A14(218-0660017)

2

4XDQWD &RPSXWHU ,QF

P/N : AJ066000T01

20mil

Size

Document Number

Rev

SB820-PCIE/PCI/CPU/LPC 1/4

3A

Date:

Thursday, March 04, 2010

Sheet

10

of

36

5

4

3

2

1

5

4

3

2

1

D

C

B

A

NC only ,Can't be install

+3V_S5

R368

*2.2K_4

SB_TEST0

T71

SB_PCI_PME#

J2

U21D

R217

*2.2K_4

SB_TEST1

PCI_PME#/GEVENT4#

USBCLK/14M_25M_48M_OSC

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

USB_RCOMP

[25]

SUSB#

F1

SLP_S3#

R210

*2.2K_4

SB_TEST2

SUSC#

H1

EVENTSUP

[25]

SUSC#

SLP_S5#

MISCUSB

SCL0/SDATA0 is 3V tolerance. AMD datasheet define it

SB_TEST2

F6

TEST1/TMS

[25]

DNBSWON#

F2

PWR_BTN#

SB800

[14]

SB_PWRGD_IN

H5

PWR_GOOD

[8]

SUS_STAT#

G6

SUS_STAT#

USB_FSD1P/GPIO186

SB_TEST0

B3

Part 4 of 5

TEST0

USB_FSD1N

SB_TEST1

C4

Clk Gen/ Robson/ TV tuner/ DDR2/ Thermal/ Accelerometer

TEST2

ACPI/ WAKE

USB_FSD0P/GPIO185

[25] SIO_A20GATE

AD21

GA20IN/GEVENT0#

USB_FSD0N

SIO_RCIN#

AE21

USB1.1

[25]

SIO_RCIN#

KBRST#/GEVENT1#

T114

LANLINK_STATE#

K2

+3V

LPC_PME#/GEVENT3#

USB_HSD13P

[25]

SIO_EXT_SMI#

J29

H2

LPC_SMI#/GEVENT23#

USB_HSD13N

[25]

SIO_EXT_SCI#

GEVENT5#

PCLK_SMB

T116

SYS_RST#

J1

SYS_RESET#/GEVENT19#

USB_HSD12P

R150

2.2K_4

[17,18]

PCIE_WAKE#

H6

T117

IR_RX1

F3

WAKE#/GEVENT8#

USB_HSD12N

IR_RX1/GEVENT20#

R147

2.2K_4

PDAT_SMB

SB_THERMTRIP#

J6

T69

THRMTRIP#/SMBALERT#/GEVENT2#

USB_HSD11P

[2,8,14] NB_PWRGD_IN

AC19

NB_PWRGD

USB_HSD11N

G1

SCL1/SDATA1 is 3V/S5 tolerance

[25]

ICH_RSMRST#

RSMRST#

USB_HSD10P

AD19

USB_HSD10N

AMD datasheet define it

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

[10]

SB_GPIO_PCIE_RST#

SB_GPIO_PCIE_RST#

AB21

CLK_REQ3#/SATA_IS1#/GPIO63

USB_HSD9P

+3V_S5

SMARTVOLT1/SATA_IS2#/GPIO50

USB_HSD9N

CLK_PCIE_LAN_REQ#

AC18

[17]

CLK_PCIE_LAN_REQ#

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SB_GPIO59

SATA_IS4#/FANOUT3/GPIO55

USB_HSD8P

R188

10K_4

SB_SMBCLK1

T51

AE19

SATA_IS5#/FANIN3/GPIO59

USB_HSD8N

AF19

[20]

SPKR

SPKR/GPIO66

R215

10K_4

SB_SMBDATA1

PCLK_SMB

AD22

2.0

[5,17,18]

PCLK_SMB

SCL0/GPIO43

USB_HSD7P

PDAT_SMB

AE22

[5,17,18]

PDAT_SMB

SB_SMBCLK1

F5

SDA0/GPIO47

USB

USB_HSD7N

SCL2/SDATA2

is 3V/S5 tolerance.

SCL1/GPIO227

SB_SMBDATA1

F4

SDA1/GPIO228

USB_HSD6P

AMD datasheet define it

[18] CLK_PCIE_2_REQ#

AH21

CLK_REQ2#/FANIN4/GPIO62

USB_HSD6N

AB18

E1

CLK_REQ1#/FANOUT4/GPIO61

GPIO

+3V_S5

IR_LED#/LLB#/GPIO184

USB_HSD5P

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

USB_HSD5N

[6] SP_DDR3_RST#

H4

D5

DDR3_RST#/GEVENT7#

R153

10K_4

SB_SCLK2

GBE_LED0/GPIO183

USB_HSD4P

D7

GBE_LED1/GEVENT9#

USB_HSD4N

R149

10K_4

SB_SDATA2

G5

GBE_LED2/GEVENT10#

K3

E_SB_OSC

GBE_STAT0/GEVENT11#

USB_HSD3P

T109

AA20

CLK_REQG#/GPIO65/OSCIN

USB_HSD3N

+3V

[22]

OC_7#

H3

USB_HSD2P

D1

BLINK/USB_OC7#/GEVENT18#

USB_HSD2N

[22]

OC_6#

USB_OC6#/IR_TX1/GEVENT6#

R195

4.7K_4

SUS_STAT#

T59

SB_PM_THERM#

E4

USB_OC5#/IR_TX0/GEVENT17#

OC

USB_HSD1P

[22]

OC_4#

D4

Eliot (02/26)

SB_JTAG_TDO

E8

USB_OC4#/IR_RX0/GEVENT16#

USB

USB_HSD1N

USB_OC3#/AC_PRES/TDO/GEVENT15#

Current Agesa bios doesnˇt

SB_JTAG_TCK

F7

USB_OC2#/TCK/GEVENT14#

USB_HSD0P

program ALERT_L and SB

SB_JTAG_TDI

E7

wonˇt process alert.

SB_JTAG_RST#

F8

USB_OC1#/TDI/GEVENT13#

USB_HSD0N

+3V

USB_OC0#/TRST#/GEVENT12#

R316

8.2K_4

CLK_PCIE_LAN_REQ#

HD audio interface is +3VS5 voltage

ACZ_BCLK

M3

R178

8.2K_4

CLK_PCIE_2_REQ#

AZ_BITCLK

SCL2/GPIO193

[14]

ACZ_SDOUT

ACZ_SDOUT

N1

AZ_SDOUT

SDA2/GPIO194

ACZ_SDIN0

L2

AUDIO

AZ_SDIN0/GPIO167

SCL3_LV/GPIO195

M2

AZ_SDIN1/GPIO168

SDA3_LV/GPIO196

M1

JTAG DEBUG

AZ_SDIN2/GPIO169

EC_PWM0/EC_TIMER0/GPIO197

M4

ACZ_SYNC

AZ_SDIN3/GPIO170

EC_PWM1/EC_TIMER1/GPIO198

N2

+3V_S5

AZ_SYNC

HD

EC_PWM2/EC_TIMER2/GPIO199

ACZ_RST#

P2

CN13

C279

AZ_RST#

EC_PWM3/EC_TIMER3/GPIO200

10P/50V_4

+3V_S5

R197

10K_4

GBE_COL

T1

KSI_0/GPIO201

1

GBE_COL

KSI_1/GPIO202

2

SB_JTAG_TCK

R191

10K_4

GBE_CRS

T4

GBE_CRS

KSI_2/GPIO203

3

SB_JTAG_TDO

L6

GBE_MDCK

KSI_3/GPIO204

SB_JTAG_TDI

R182

10K_4

GBE_MDIO

L5

4

GBE_MDIO

KSI_4/GPIO205

SB_TEST1

T9

5

GBE_RXCLK

KSI_5/GPIO206

6

U1

GBE_RXD3

KSI_6/GPIO207

SB_JTAG_RST#

U3

7

GBE_RXD2

KSI_7/GPIO208

T2

GBELAN

8

GBE_RXD1

P5

CTRL

U2

GBE_RXD0

KSO_0/GPIO209

*S/W JTAG DEBUG

R196

10K_4

GBE_RXERR

T5

GBE_RXCTL/RXDV

KSO_1/GPIO210

V5

GBE_RXERR

KSO_2/GPIO211

M5

GBE_TXCLK

EMBEDDED

KSO_3/GPIO212

P4

GBE_PHY_PD

KSO_9/GPIO218

To Azalia

T7

GBE_TXD3

KSO_4/GPIO213

GBE_TXD1

KSO_6/GPIO215

P9

GBE_TXD2

KSO_5/GPIO214

P7

GBE_TXD0

KSO_7/GPIO216

M7

GBE_TXCTL/TXEN

KSO_8/GPIO217

ACZ_SDOUT

R200

33_4

R190

10K_4

GBE_PHY_INTR

M9

GBE_PHY_RST#

KSO_10/GPIO219

ACZ_SDOUT_AUDIO

[20]

V7

GBE_PHY_INTR

KSO_11/GPIO220

C283

*10P/50V_4

T49

ADP_PRES0

E23

KSO_12/GPIO221

E24

PS2_DAT/SDA4/GPIO187

CTRL

KSO_13/GPIO222

F21

PS2_CLK/SCL4/GPIO188

KSO_14/GPIO223

ACZ_SYNC

R202

33_4

SPI_CS2#/GBE_STAT2/GPIO166

KSO_15/GPIO224

ACZ_SYNC_AUDIO

[20]

G29

[02/22] AMD FAE and checklist request PL.

FC_RST#/GPO160

EMBEDDED

KSO_16/GPIO225

C284

*10P/50V_4

D27

PS2KB_DAT/GPIO189

KSO_17/GPIO226

F28

PS2KB_CLK/GPIO190

F29

ACZ_BCLK

R203

33_4

PS2M_DAT/GPIO191

ACZ_BITCLK_AUDIO [20]

E27

PS2M_CLK/GPIO192

C285

*10P/50V_4

http://hobi

-elektronika.net

ACZ_RST#

R201

33_4

SB800 A11

ACZ_RST#_AUDIO

[20]

ACZ_SDIN0	ACZ_SDIN0 [20]

A10 G19

J10

H11

H9

J8

B12

A12

F11

E11

E14

E12

J12

J14

A13

B13

D13

C13

G12

G14

G16

G18

D16

C16

B14

A14

E18

E16

J16

J18

B17

A17

A16

B16

D25

F23

B26

E26

F25

E22

F22

E21

G24

G25

E28

E29

D29

D28

C29

C28

B28

A27

B27

D26

A26

C26

A24

B25

A25

D24

B24

C24

B23

A23

D22

C22

A22

B22

USBCLK/41M_25M_48M_OSC pin is CLK input pin when EXT CLKGEN mode. It is output CLK source when INT CLKGEN mode.

USB_14_48M		T110
USB_RCOMP_SB	R169		11.8K/F_6
USB_FDS12P		T63
USB_FSD12N
		T58
USBP13+		[15]	CAMERA
USBP13-		[15]
	USBP12+	[22]	USBX3 board
	USBP12-	[22]
	USBP11+	[22]	USBX3 board
	USBP11-	[22]
	USBP10+	[21]	Card reader
	USBP10-	[21]
USBP9+		[22]	BLUETOOTH
USBP9-		[22]
USBP8+		[22]	USBX3 board
USBP8-		[22]

USBP4+ [18] USBP4- [18]

USBP1+

USBP1- T54

T53

USBP0+ [22]

USBP0- [22]

SB_SCLK2

SB_SDATA2

SB_GPIO195

SB_GPIO196

T48

WLAN Min-Card

On Board USB Connector

Only USB Port0 can be configured as debug port.

GPIO199 [14]

GPIO200 [14]

Check list

SB_GPIO195	R146	10K_4
SB_GPIO196	R144	10K_4

352-(&7 =4

4XDQWD &RPSXWHU ,QF

Size	Document Number
	SB820-ACPI/GPIO/USB 2/4
Date:	Thursday, March 04, 2010		Sheet 11 of

OHCI1 EHCI1/ OHCI2 EHCI2/ OHCI3 EHCI3/

Rev 1A

36

D

C

B

A

5

4

3

2

1