Acer 5517 Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

NCWG0/H0 Schematics Document

AMD S1g1 / RS780MN/ SB710

2009 / 06 / 24

3 3

4 4

LA-5481
Rev:1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2010/03/12

2005/03/08 2010/03/12

2005/03/08 2010/03/12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

147Wednesday, June 24, 2009

147Wednesday, June 24, 2009

147Wednesday, June 24, 2009

of

of

E

of

C

C

C

5

4

3

2

1

Compal confidential

Project Code: NCWG0/H0
File Name : LA-5481P

Thermal Sensor
ADM1032ARM

Clock Generator

SLG8SP626
ICS9LPRS488BKLFT

D D

page 8 page 17

AMD S1g1 CPU

638P PGA

H_A#(3..31) H_D#(0..63)

page 6,7,8,9

HT 16x16 1000MHZ

533/667/800

DDRII DDRII-SO-DIMM X2

page 10,11

Dual Channel

CRT

page 24

ATI-RS780MN

465 BGA

LCD CONN

page 25

page 12,13,14,15,16

A-Link Express

PCIE X1

C C

Mini card
WLAN

10/100 LAN

AR8114 / AR8132

page 26page 31

ATI-SB710

549 BGA

page 18,19,20,21,22

RJ45 CONN

page 27

LPC BUS

B B

ENE KB926

Power On/Off CKT / LID switch / Power OK CKT

page 37

DC/DC Interface CKT.

page 41

CIR/LED

page 38

RTC CKT.

page 18

Ver:D3

page 28

4 x PCIE

Int. KBD

page 29

USB 2.0

HD Audio

SATA0

SATA2

Camera

HDA Codec
ALC272

page 39

MDC Conn.

page 41

HDD Conn.

ODD Conn.

page 23

page 23

SATA1

USB conn
X2

AMP & Audio Jack

TPA6017

page 40

Second HDD/ODD

HDD Conn.

CardReader
RTS5159

HeadPhone
Out

MIC In

Touch Pad

Power Circuit DC/DC

page 42~48

CONN.

page 29

SPI BIOS

page 30

SATA3

ODD Conn.

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/03/08 2010/03/12

2009/03/08 2010/03/12

2009/03/08 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

247Wednesday, June 24, 2009

247Wednesday, June 24, 2009

247Wednesday, June 24, 2009

1

C

C

C

of

of

of

5

4

3

2

1

Voltage Rails

D D

C C

VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDR terminator
+1.2V_HT
+1.5VS
+1.8V 1.8V power rail for DDR ON
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail ON OFF

1.5V switched power rail

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

ON OFF OFF

OFF
OFF

ON
ON

ON
OFF

ON
ON

ON
OFF

ON OFF
ON
ON+RTCVCC

ONRTC power

ON*

OFF
ON*
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7NC

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH

LOW

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

LOWLOWLOW

ON

ON

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

V typ

AD_BID

ON

ON

OFF

OFF

V

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

ON ON

ON

OFF

OFF

OFF

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

LOW

OFF

OFF

OFF

max

BOARD ID Table

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

Board ID

0
1
2
3
4
5

PCB Revision

No Support VaryBright

Support VaryBright

BTO Item BOM Structure
10/100 Lan 8114@
GIGA Lan 8132@
17" ID 17@
15" ID 15@

6
7

B B

EC SM Bus1 address

Device

Smart Battery

Address Address

EC SM Bus2 address

Device

ADM1032

1001 100X b0001 011X b

PROJECT ID Table

SKU ID

0

SKU

NCWG0
1
2
3

NAL00
4
5

SB600 SM Bus 1 address

Device

Clock Generator

A A

DDR DIMM0
DDR DIMM2
Wireless Lan

5

Address

1101 001Xb

1001 000Xb
1001 010Xb

SB600 SM Bus 2 address

Device Address

New Card

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

6
7

2009/03/08 2010/03/12

2009/03/08 2010/03/12

2009/03/08 2010/03/12

NCWH0

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

BTO Option Table

VARY@Support VaryBright

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

347Wednesday, June 24, 2009

347Wednesday, June 24, 2009

347Wednesday, June 24, 2009

of

of

1

of

C

C

C

5

4

3

2

1

DDR_A_CLK[1..2]

DIMMA

D D

CPU CLK
200MHZ

C C

14.31818MHz

EXTERNAL
CLK GEN.
SLG8SP626 / ICS9LPRS488

SBLINK_CLK
100MHZ

NBSRC_CLK
100MHZ

HTREFCLK
66MHZ

NB_OSC

14.318MHZ

CPU
S1G1
SOCKET

ATI
NB
RS780MN

DDR_B_CLK[1..2]

H_CLKO[1:0]H_CLKI[1:0] Host Bus

DIMMB

B B

CLK_PCIE_MINI

100MHZ

Mini PCI Socket
Mini card

A A

5

CLK_PCIE_LAN

100MHZ

LAN
Atheros
AR8114/AR8132

4

CLK_14M_SB

14.318MHZ
SB_OSCIN

14.318MHZ

SBSRC_CLKP
100MHZ

CLK_48M_USB
48MHZ

ATI
SB
SB710

RTC SATA

32.768K Hz

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

25M Hz

2005/10/10 2010/03/12

2005/10/10 2010/03/12

2005/10/10 2010/03/12

CLK_PCI_LPC

33MHZ

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

EC
ENE
KB926D3

32.768K Hz

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

447Wednesday, June 24, 2009

447Wednesday, June 24, 2009

447Wednesday, June 24, 2009

of

of

1

of

C

C

C

5

AC ADAPTOR
19V 65W

D D

BATTERY

11.1V

2.2Ah/6-cell

C C

VIN

BATT+

PU17
BATTERY CHARGER
BQ24751ARHDR

B+

4

PU12
ISL6264CRZ-T

PU18
ISL6228HRTZ-T

PU19
TPS51117RGYR

PU16
ISL6237IRZ-T

+5VALW

3

+CPU_CORE 0.9V

+1.2VALW

+NB_CORE

U46
AO4430

+1.2V_HT

2

PU21
APL5915KAI

+2.5VS

1

CPU

AMD
S1G1 socket

VDDA 2.5V
VDD
VDDIO
VTT
VLDT

0.95V

1.8V

0.9V

1.2V

DDRII SODIMMX2

+1.2VALW

+1.8V

PU22
APL5331KAC

+0.9V

VDD_MEM

VTT_MEM

NB

RS780MN

VDDC
VDD_HT
PLLVDD
VDDPCIE
VDDHTRX

+1.8V

+3VS

+1.2VALW

PU20
APL5912
KAC-TRL

+1.1VS

+1.2VALW

VDDHTTX
AVDDQ
AVDDDI
PLLVDD18
VDDA18HTPLL
VDDA18PCIE
VDDA18PCIEPLL
VDD18
VDDLT18
VDDLTP18
AVDD
VDD33

+3VALW

+3VS

U41
AO4468

+1.8V

U37
AO4430

PU23
APL5915KAI

+1.5VS

+1.8VS

1.8V

0.9V

1.0-1.1V

1.1V

1.2V

1.8V

3.3V

250 mA

24.5 A

3.6 A

1.75 A

500 mA

6.08 A

500 mA

10 A
680 mA
65 mA

2.5 A
680 mA
400 mA
4 mA
20 mA
20 mA
20 mA
700 mA
120 mA
10 mA
300 mA
15 mA
110 mA
60 mA

U7

B B

U4
TPS2061DRG4

+5VS

+USB_VCCA

+3VS

USB X2

+5V
Dual

1.5A

A A

LCD panel

15.6"

B+ 300mA

Audio AMP
TPA6017A2

+5V 25mA

+3.3 350mA

5

FAN Control
APL5607

+5VS 500mA

Audio Codec
ALC272

+5V 45mA
+3.3VS 25mA

Realtek
RTS5159

+3.3VS 300mA

AO4468

+5VS

EC
ENE KB926

+3.3VALW 30mA
+3.3VS 3mA

LAN
Atheros AR8114

+3.3VALW 201mA

Mini Card

+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA

ICS9LPRS488B

+3.3V 400mA
+1.2V

SATA

Security Classification

Security Classification

+5V 3A
+3.3V

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/3/8 2010/03/12

2009/3/8 2010/03/12

2009/3/8 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.2V_HT

2

RTC
Bettary

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

SB710

SB

VDD
S5_1.2V
USB_PHY_1.2V
AVDDCK_1.2V
CKVDD_1.2
PCIE_PVDD
PCIE_VDDR
AVDD_SATA
PLLVDD_SATA_1
S5_3.3V
AVDDC
AVDD TX/RX
VDDQ
VDD33_18
AVDDCK_3.3V
XTLVDD_SATA

VBAT

547Wednesday, June 24, 2009

547Wednesday, June 24, 2009

547Wednesday, June 24, 2009

1

1.2V

3.3V

3V

of

of

of

510mA
113 mA
197 mA
62 mA

43 mA
600 mA
567 mA
93 mA
32 mA
17 mA
658 mA
131 mA
71 mA
47 mA
6 mA

C

C

C

5

4

3

2

1

D D

C C

check AMD

B B

H_CTLIP1<12> H_CTLOP1 <12>
H_CTLIN1<12>

H_CADIP[0..15]<12>

R45 0_0402_5%R45 0_0402_5%
R46 0_0402_5%R46 0_0402_5%

+1.2V_HT

R2 51_0402_1%@R2 51_0402_1%@
R3 51_0402_1%@R3 51_0402_1%@

H_CLKIP1<12>
H_CLKIN1<12>
H_CLKIP0<12>
H_CLKIN0<12>

1 2
1 2

H_CTLIP0<12> H_CTLOP0 <12>
H_CTLIN0<12>

H_CADIP[0..15]
H_CADIN[0..15]

VLDT=500mA

12
12

+1.2V_HT

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CTLIP1_R
H_CTLIN1_R

H_CTLIP0

H_CTLIP1_R
H_CTLIN1_R

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F
CONN@

CONN@

JCPU1A

JCPU1A

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0

HTT Interface

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

Athlon 64 S1
Processor Socket

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CTLON1_R

H_CTLOP0
H_CTLON0H_CTLIN0

H_CADOP[0..15]
H_CADON[0..15]

1 2

C84 4.7U_0805_10V4Z

C84 4.7U_0805_10V4Z

H_CLKOP1 <12>
H_CLKON1 <12>
H_CLKOP0 <12>
H_CLKON0 <12>

1 2

R41 0_0402_5%R41 0_0402_5%

1 2

R44 0_0402_5%R44 0_0402_5%

H_CTLON0 <12>

H_CADOP[0..15] <12>
H_CADON[0..15] <12>H_CADIN[0..15]<12>

H_CTLON1 <12>

Reserve when PVT

40mil

+VCC_FAN1

+VCC_FAN1H_CTLOP1_R

+5VS

12

D13

D13
1SS355_SOD323-2@

1SS355_SOD323-2@

1 2

10U_0805_10V4Z

10U_0805_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K
<BOM Structure>

<BOM Structure>

for cos down

D4 BAS16_SOT23-3@D4 BAS16_SOT23-3@

C97

C97
1 2

C96

C96
1 2

JP12

JP12

1
2
3

CONN@

CONN@

ACES_85205-03001

ACES_85205-03001

LDO FAN

JP38

JP38

1

1

2

2

3

3

4

4

CONN@

CONN@

ACES_85205-0400

ACES_85205-0400

1 2

GND
GND
GND
GND

+3VS

12

FAN1 Conn

8
7
6
5

+3VS

12

R37

R37
10K_0402_5%

10K_0402_5%

1

C91

C91
1000P_0402_50V7K

1000P_0402_50V7K

2

R40

R40
10K_0402_5%

10K_0402_5%
@

@

FANPWN

+5VS

R247

R247
0_0603_5%

0_0603_5%
@

@

+VCC_FAN1

EN_DFAN1<28>

1 2

1 2

R733 0_0402_5%R733 0_0402_5%

@

@

FANPWM<28>

<BOM Structure>

<BOM Structure>

U1

U1
1
2
3
4

1

APL5607KI-TRG_SO8

APL5607KI-TRG_SO8

C760

C760

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

FAN_SPEED1<28>

C92 10U_0805_10V4Z

C92 10U_0805_10V4Z

EN
VIN
VOUT
VSET

PWM FAN

AMD : 49.9 1%
ATI : 51 1%

+1.2V_HT

250 mil

<BOM Structure>

<BOM Structure>

A A

5

VLDT CAP.

1

C86

C86

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

1

C82

C82

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C90

C90

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

4

1

C89

C89

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

Near CPU Socket

1

C83

C83
180P_0402_50V8J

180P_0402_50V8J

2

<BOM Structure>

<BOM Structure>

1

C85

C85
180P_0402_50V8J

180P_0402_50V8J

2

<BOM Structure>

<BOM Structure>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2010/03/12

2007/5/18 2010/03/12

2007/5/18 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

646Wednesday, June 24, 2009

646Wednesday, June 24, 2009

646Wednesday, June 24, 2009

1

C

C

C

of

of

A

B

C

D

E

DDR_B_D[63..0]<11>

DDR_B_DM[7..0]<11> DDR_A_DM[7..0] <10>

DDR_B_DQS7<11>
DDR_B_DQS#7<11>
DDR_B_DQS6<11>
DDR_B_DQS#6<11>
DDR_B_DQS5<11>
DDR_B_DQS#5<11>
DDR_B_DQS4<11>
DDR_B_DQS#4<11>
DDR_B_DQS3<11>
DDR_B_DQS#3<11>
DDR_B_DQS2<11>
DDR_B_DQS#2<11>
DDR_B_DQS1<11>
DDR_B_DQS#1<11>
DDR_B_DQS0<11>
DDR_B_DQS#0<11>

R4

R4

1K_0402_1%

1K_0402_1%

R5

R5

1K_0402_1%

1K_0402_1%

+1.8V

+1.8V

1 2

1 2

DDR_CS3_DIMMA#<10>
DDR_CS2_DIMMA#<10>
DDR_CS1_DIMMA#<10>
DDR_CS0_DIMMA#<10>

DDR_CS3_DIMMB#<11>
DDR_CS2_DIMMB#<11>
DDR_CS1_DIMMB#<11>
DDR_CS0_DIMMB#<11>

DDR_CKE1_DIMMB<11>
DDR_CKE0_DIMMB<11>
DDR_CKE1_DIMMA<10>
DDR_CKE0_DIMMA<10>

DDR_A_MA[15..0]<10>

1

1

C16

C16

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R7

R7

1 2

R6

R6

DDR_A_BS#2<10>
DDR_A_BS#1<10>
DDR_A_BS#0<10>

DDR_A_RAS#<10>
DDR_A_CAS#<10>
DDR_A_WE#<10>

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

C100

C100

1000P_0402_50V7K

1000P_0402_50V7K

+CPU_M_VREF

TP1TP1

(10/10, <1")

39.2_0402_1%

39.2_0402_1%

12

39.2_0402_1%

39.2_0402_1%

+CPU_M_VREF

(15/20, <6")

VTT_SENSE

M_ZN
M_ZP

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

1

C102

C102

1.5P_0402_50V8C

1.5P_0402_50V8C

2

1

C104

C104

1.5P_0402_50V8C

1.5P_0402_50V8C

2

JCPU1B

W17

M_VREF

Y10

VTT_SENSE

AE10

M_ZN

AF10

M_ZP

V19

MA0_CS_L3

J22

MA0_CS_L2

V22

MA0_CS_L1

T19

MA0_CS_L0

Y26

MB0_CS_L3

J24

MB0_CS_L2

W24

MB0_CS_L1

U23

MB0_CS_L0

H26

MB_CKE1

J23

MB_CKE0

J20

MA_CKE1

J21

MA_CKE0

K19

MA_ADD15

K20

MA_ADD14

V24

MA_ADD13

K24

MA_ADD12

L20

MA_ADD11

R19

MA_ADD10

L19

MA_ADD9

L22

MA_ADD8

L21

MA_ADD7

M19

MA_ADD6

M20

MA_ADD5

M24

MA_ADD4

M22

MA_ADD3

N22

MA_ADD2

N21

MA_ADD1

R21

MA_ADD0

K22

MA_BANK2

R20

MA_BANK1

T22

MA_BANK0

T20

MA_RAS_L

U20

MA_CAS_L

U21

MA_WE_L

CONN@ FOX_PZ63823-284S-41F

CONN@ FOX_PZ63823-284S-41F

Athlon 64 S1
Processor
Socket

JCPU1B

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

+0.9V

D10

VTT1

C10

VTT2

B10

VTT3

AD10

VTT4

W10

VTT5

AC10

VTT6

AB10

VTT7

AA10

VTT8

A10

VTT9

DDR_A_CLK2

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

1

2

1

2

Y16

DDR_A_CLK#2

AA16

DDR_A_CLK1

E16

DDR_A_CLK#1

F16

DDR_B_CLK2

AF18

DDR_B_CLK#2

AF17

DDR_B_CLK1

A17

DDR_B_CLK#1

A18

DDR_B_ODT1

W23

DDR_B_ODT0

W26

DDR_A_ODT1

V20

DDR_A_ODT0

U19

DDR_B_MA15

J25

DDR_B_MA14

J26

DDR_B_MA13

W25

DDR_B_MA12

L23

DDR_B_MA11

L25

DDR_B_MA10

U25

DDR_B_MA9

L24

DDR_B_MA8

M26

DDR_B_MA7

L26

DDR_B_MA6

N23

DDR_B_MA5

N24

DDR_B_MA4

N25

DDR_B_MA3

N26

DDR_B_MA2

P24

DDR_B_MA1

P26

DDR_B_MA0

T24

DDR_B_BS#2

K26

DDR_B_BS#1

T26

DDR_B_BS#0

U26

DDR_B_RAS#

U24

DDR_B_CAS#

V26

DDR_B_WE#

U22

C17

C17

1.5P_0402_50V8C

1.5P_0402_50V8C

C105

C105

1.5P_0402_50V8C

1.5P_0402_50V8C

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

DDRII Cmd/Ctrl//Clk

DDRII Cmd/Ctrl//Clk

DDR_A_CLK2 <10>
DDR_A_CLK#2 <10>
DDR_A_CLK1 <10>
DDR_A_CLK#1 <10>

DDR_B_CLK2 <11>
DDR_B_CLK#2 <11>
DDR_B_CLK1 <11>
DDR_B_CLK#1 <11>

DDR_B_ODT1 <11>
DDR_B_ODT0 <11>
DDR_A_ODT1 <10>
DDR_A_ODT0 <10>

DDR_B_MA[15..0] <11>

DDR_B_BS#2 <11>
DDR_B_BS#1 <11>
DDR_B_BS#0 <11>

DDR_B_RAS# <11>
DDR_B_CAS# <11>
DDR_B_WE# <11>

4 4

3 3

2 2

1 1

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11

MB_DATA63

AF11

MB_DATA62

AF14

MB_DATA61

AE14

MB_DATA60

Y11

MB_DATA59

AB11

MB_DATA58

AC12

MB_DATA57

AF13

MB_DATA56

AF15

MB_DATA55

AF16

MB_DATA54

AC18

MB_DATA53

AF19

MB_DATA52

AD14

MB_DATA51

AC14

MB_DATA50

AE18

MB_DATA49

AD18

MB_DATA48

AD20

MB_DATA47

AC20

MB_DATA46

AF23

MB_DATA45

AF24

MB_DATA44

AF20

MB_DATA43

AE20

MB_DATA42

AD22

MB_DATA41

AC22

MB_DATA40

AE25

MB_DATA39

AD26

MB_DATA38

AA25

MB_DATA37

AA26

MB_DATA36

AE24

MB_DATA35

AD24

MB_DATA34

AA23

MB_DATA33

AA24

MB_DATA32

G24

MB_DATA31

G23

MB_DATA30

D26

MB_DATA29

C26

MB_DATA28

G26

MB_DATA27

G25

MB_DATA26

E24

MB_DATA25

E23

MB_DATA24

C24

MB_DATA23

B24

MB_DATA22

C20

MB_DATA21

B20

MB_DATA20

C25

MB_DATA19

D24

MB_DATA18

A21

MB_DATA17

D20

MB_DATA16

D18

MB_DATA15

C18

MB_DATA14

D14

MB_DATA13

C14

MB_DATA12

A20

MB_DATA11

A19

MB_DATA10

A16

MB_DATA9

A15

MB_DATA8

A13

MB_DATA7

D12

MB_DATA6

E11

MB_DATA5

G11

MB_DATA4

B14

MB_DATA3

A14

MB_DATA2

A11

MB_DATA1

C11

MB_DATA0

AD12

MB_DM7

AC16

MB_DM6

AE22

MB_DM5

AB26

MB_DM4

E25

MB_DM3

A22

MB_DM2

B16

MB_DM1

A12

MB_DM0

AF12

MB_DQS_H7

AE12

MB_DQS_L7

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AC25

MB_DQS_H4

AC26

MB_DQS_L4

F26

MB_DQS_H3

E26

MB_DQS_L3

A24

MB_DQS_H2

A23

MB_DQS_L2

D16

MB_DQS_H1

C16

MB_DQS_L1

C12

MB_DQS_H0

B12

MB_DQS_L0

CONN@ FOX_PZ63823-284S-41F

CONN@ FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

JCPU1C

JCPU1C

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14

DDRII Data

DDRII Data

MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] <10>

DDR_A_DQS7 <10>
DDR_A_DQS#7 <10>
DDR_A_DQS6 <10>
DDR_A_DQS#6 <10>
DDR_A_DQS5 <10>
DDR_A_DQS#5 <10>
DDR_A_DQS4 <10>
DDR_A_DQS#4 <10>
DDR_A_DQS3 <10>
DDR_A_DQS#3 <10>
DDR_A_DQS2 <10>
DDR_A_DQS#2 <10>
DDR_A_DQS1 <10>
DDR_A_DQS#1 <10>
DDR_A_DQS0 <10>
DDR_A_DQS#0 <10>

Processor DDR2 Memory Interface

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/5/18 2010/03/12

2007/5/18 2010/03/12

2007/5/18 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

401743

401743

401743

746Wednesday, June 24, 2009

746Wednesday, June 24, 2009

746Wednesday, June 24, 2009

E

0.1

0.1

0.1

of

of

of

5

+1.8VS

R344

R344
300_0402_5%

300_0402_5%

1 2

+1.8VS

+1.8VS

CPU_THERMDA
CPU_THERMDC

+1.8V

R33220_0402_5%@ R33220_0402_5%@

R38220_0402_5%@ R38220_0402_5%@

12

12

5

LDT_RST#

1

C721

C721

0.01U_0402_25V4Z

0.01U_0402_25V4Z
@

@

2

R346

R346
300_0402_5%

300_0402_5%

1 2

H_PWRGD

1

C720

C720

0.01U_0402_25V4Z

0.01U_0402_25V4Z
@

@

2

R342

R342
300_0402_5%

300_0402_5%

1 2

LDT_STOP#

1

C719

C719

0.01U_0402_25V4Z

0.01U_0402_25V4Z
@

@

2

+3VS

C119

C119

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

U3

U3

1

VDD

2

D+

3

ALERT#

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

ADM1032ARMZ-2REEL_MSOP8

<BOM Structure>

<BOM Structure>
F75383M_MSOP8

SMBus Address: 1001110X (b)

AMD: suggest DBREQ need pull high

R36220_0402_5% R36220_0402_5%

R34220_0402_5%@ R34220_0402_5%@

R35220_0402_5%@ R35220_0402_5%@

12

12

12

LDT_RST#<17>

D D

H_PWRGD<17>

C C

B B

A A

LDT_STOP#<13,17>

1 2

C120 2200P_0402_50V7K

C120 2200P_0402_50V7K

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

+2.5VS

150U_D2_6.3VM

150U_D2_6.3VM

CLK_CPU_BCLK<16>

CLK_CPU_BCLK#<16>

8

SCLK

7

SDATA

6
5

JP3

JP3

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@SAMTEC_ASP-68200-07

@

C113

C113

HDT Connector

4

L4

L4

1 2

FCM2012CF-800T06_2P

FCM2012CF-800T06_2P

1

+

+

2

(10/5/5/5/10)

3900P_0402_50V7K

3900P_0402_50V7K

1 2

C109

C109

12

R22

R22
169_0402_1%

169_0402_1%

1 2

C23 3900P_0402_50V7K

C23 3900P_0402_50V7K

EC_SMB_CK2 <28>
EC_SMB_DA2 <28>

HDT_RST#

4

U51

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

U51

<BOM Structure>

<BOM Structure>

4

+2.5VDDA

1

C116

C116

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

<BOM Structure>

<BOM Structure>

+1.2V_HT

+3VS

5

2

P

B

Y

1

A

G

3

VDDA=300mA

3300P_0402_50V7K

3300P_0402_50V7K

1

1

C22

C22

C118

C118

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

2

<BOM Structure>

<BOM Structure>

LDT_RST#
H_PWRGD
LDT_STOP#

R13 300_0402_5%

R13 300_0402_5%

R61 44.2_0402_1%R61 44.2_0402_1%

1 2

R16 44.2_0402_1%R16 44.2_0402_1%

CPU_VCC_SENSE<45>

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

1 2

CPU_DBRDY
CPU_TMS

CPU_TCK CPU_TDO
CPU_TRST#
CPU_TDI

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

(10/10)

LDT_RST#

SB_PWRGD <18,33>

3

2

<15/20>

JCPU1D

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

CPU_SIC

12

CPU_HTREF1
CPU_HTREF0

(5/10, >1")

TP26TP26

TP3TP3

TP5TP5
TP30TP30
TP8TP8 TP9TP9
TP28TP28
TP31TP31

CPU_THERMDC
CPU_THERMDA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F
CONN@

CONN@

3

JCPU1D

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

PSI_L

DBREQ_L

TEST29_L

TEST24
TEST23

MISC

MISC

TEST22
TEST21
TEST20

TEST28_H
TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

2007/5/18 2010/03/12

2007/5/18 2010/03/12

2007/5/18 2010/03/12

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

A5

VID5

C6

VID4

A6

VID3

A4

VID2

C5

VID1

B5

VID0

CPU_PRESENT#

AC6
A3

CPU_DBREQ#

E10

AE9

TDO

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

AE7
AD7
AE8
AB8
AF7

J7
H8
AF8
AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

TP6TP6
TP7TP7

CPU_TEST21_SCANEN

TP29TP29

CPU_TEST26_BURNIN#

CPU_THERMTRIP#_R H_THERMTRIP#

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

CPU_VID5 <45>
CPU_VID4 <45>
CPU_VID3 <45>
CPU_VID2 <45>
CPU_VID1 <45>
CPU_VID0 <45>

PSI_L <45>CPU_VSS_SENSE<45>

80.6_0402_1%

80.6_0402_1%

1 2

300_0402_5%

300_0402_5%

R53

R53

<BOM Structure>

<BOM Structure>

+1.8V

12

R8

R8

CPU_PROCHOT#_1.8

2

+1.8V

12

R18

R18
1K_0402_5%

1K_0402_5%

B

B

2

Q3

Q3

E

E

3 1

C

C

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

300_0402_5%

300_0402_5%

1

+1.8V

VID1: For compatibility

CPU_VID1
CPU_PRESENT#
CPU_TEST26_BURNIN#

CPU_TEST21_SCANEN

+1.8V

R65 510_0402_5%

R65 510_0402_5%

R68 510_0402_5%

R68 510_0402_5%
R69 300_0402_5%

R69 300_0402_5%
R66 300_0402_5%

R66 300_0402_5%

+3VALW

12

R17

R17
10K_0402_5%

10K_0402_5%

+1.8V

12

R20

R20

1 2
R52 0_0402_5%R52 0_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1 2

R24 300_0402_5%

R24 300_0402_5%

1 2

R64 1K_0402_5%

R64 1K_0402_5%

1 2

R27 300_0402_5%

R27 300_0402_5%

1 2

R47 300_0402_5%

R47 300_0402_5%

CPU_TEST25_H_BYPASSCLK_H

12

CPU_TEST25_L_BYPASSCLK_L

12
12
12

+3VALW

E

E

3 1

H_THERMTRIP# <18>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

12

R25

R25

1K_0402_5%@

1K_0402_5%@

B

B

2

Q2

Q2
MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

C

C

@

@

H_PROCHOT_R# <17>

401743

401743

401743

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

MAINPWON <39,41>

1

with future processors

846Wednesday, June 24, 2009

846Wednesday, June 24, 2009

846Wednesday, June 24, 2009

C

C

C

of

of

of

5

VDD(+CPU_CORE) decoupling.

D D

C C

+CPU_CORE

1

+

+

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C26

C26
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

C33

C33
22U_0805_6.3V6M

22U_0805_6.3V6M

<BOM Structure>

<BOM Structure>

C129

C129

0.22U_0603_16V4Z

0.22U_0603_16V4Z

1

+

+

C32

C32
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M
@

@

2

Near CPU Socket

1

C36

C36
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C151

C151

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C34

C34
22U_0805_6.3V6M

22U_0805_6.3V6M

2

<BOM Structure>

<BOM Structure>

+CPU_CORE +CPU_CORE

1

C122

C122

0.01U_0402_25V7K

0.01U_0402_25V7K

2

1

+

+

C27

C27
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

C35

C35
22U_0805_6.3V6M

22U_0805_6.3V6M

2

VDDIO decoupling.

+1.8V

1

C170

C170
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C181

C181
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

B B

+1.8V

1

C157

C157

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C175

C175

0.01U_0402_25V7K

0.01U_0402_25V7K

2

+1.8V

1

A A

2

Between CPU Socket and DIMM

1

C182

C182

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C159

C159

0.01U_0402_25V7K

0.01U_0402_25V7K

2

<BOM Structure>

C76

C76

4.7U_0805_10V4Z

4.7U_0805_10V4Z
<BOM Structure>

<BOM Structure>

<BOM Structure>

1

C167

C167

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+1.8V

1

C124

C124

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

<BOM Structure>

<BOM Structure>

1

C68

C68

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

2

1

2

<BOM Structure>

<BOM Structure>

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

C189

C189
180P_0402_50V8J

180P_0402_50V8J

<BOM Structure>

<BOM Structure>

C187

C187

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C147

C147

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C188

C188

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C136

C136
180P_0402_50V8J

180P_0402_50V8J

2

1

C132

C132

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

4

1

+

+

C28

C28
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

C178

C178
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C47

C47
180P_0402_50V8J

180P_0402_50V8J

2

1

+

+

2

1

C41

C41
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

1

C156

C156
180P_0402_50V8J

180P_0402_50V8J

2

<BOM Structure>

<BOM Structure>

1

+

+

C162

C162
220U_D2_4VM_R15

220U_D2_4VM_R15

2

C29

C29
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

1

C190

C190
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C158

C158
180P_0402_50V8J

180P_0402_50V8J

2

<BOM Structure>

<BOM Structure>

3

+CPU_CORE +CPU_CORE

1

C39

C39
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C128

C128
22U_0805_6.3V6M

22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C155

C155

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

+0.9V

1

C73

C73

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

1

C146

C146

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

<BOM Structure>

<BOM Structure>

Near CPU Socket Right side.

1

C70

C70

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

Near CPU Socket Left side.

1

2

<BOM Structure>

<BOM Structure>

1

2

<BOM Structure>

<BOM Structure>

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F
CONN@

CONN@

Athlon 64 S1
Processor Socket

C66

C66

150U_D2_6.3VM

150U_D2_6.3VM

C184

C184

0.22U_0603_16V4Z

0.22U_0603_16V4Z

C127

C127

0.22U_0603_16V4Z

0.22U_0603_16V4Z

JCPU1E

JCPU1E

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

+

2

1

C173

C173

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C185

C185

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

<BOM Structure>

<BOM Structure>

2

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

1

2

<BOM Structure>

<BOM Structure>

1

2

+1.8V

C72

C72
1000P_0402_50V7K

1000P_0402_50V7K

C164

C164
1000P_0402_50V7K

1000P_0402_50V7K

1

C145

C145
1000P_0402_50V7K

1000P_0402_50V7K

2

<BOM Structure>

<BOM Structure>

1

C163

C163
1000P_0402_50V7K

1000P_0402_50V7K

2

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F
CONN@

CONN@

Athlon 64 S1
Processor Socket

Ground

Ground

1

C180

C180
180P_0402_50V8J

180P_0402_50V8J

2

1

C152

C152
180P_0402_50V8J

180P_0402_50V8J

2

JCPU1F

JCPU1F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

1

C121

C121
180P_0402_50V8J

180P_0402_50V8J

2

<BOM Structure>

<BOM Structure>

1

C179

C179
180P_0402_50V8J

180P_0402_50V8J

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2010/03/12

2007/5/18 2010/03/12

2007/5/18 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

946Wednesday, June 24, 2009

946Wednesday, June 24, 2009

946Wednesday, June 24, 2009

1

C

C

C

of

of

of

5

JDIMM2

JDIMM2

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA<7>
DDR_CS2_DIMMA#<7>

DDR_A_BS#2<7>

DDR_A_BS#0<7>
DDR_A_WE#<7>

DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>

DDR_A_ODT1<7>

B B

A A

SB_CK_SDAT<11,16,18,31>

SB_CK_SCLK<11,16,18,31>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C448

C448

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_AS0A426-M2RN-7F

FOX_AS0A426-M2RN-7F
CONN@

CONN@

DIMM2 REV H:5.2mm (BOT)

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

4

C507
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R12 10K_0402_5%R12 10K_0402_5%

1 2

R10 10K_0402_5%R10 10K_0402_5%

1 2

C507

1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>

DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>

DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>

DDR_A_DQS#[0..7]<7>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>

DDR_A_ODT0 <7>

DDR_CS3_DIMMA# <7>

DDR_A_CLK2 <7>
DDR_A_CLK#2 <7>

3

+1.8V+DIMM_VREF+1.8V+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C503

C503

3

12

R398

R398

1K_0402_1%

1K_0402_1%

12

R397

R397

1K_0402_1%

1K_0402_1%

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

Compal Secret Data

Compal Secret Data

2005/10/11 2010/03/12

2005/10/11 2010/03/12

2005/10/11 2010/03/12

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA2

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12

DDR_A_MA4
DDR_A_MA0
DDR_A_BS#1
DDR_CS0_DIMMA#

DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1

DDR_A_RAS#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#

DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14

2

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

1

+0.9V

RP1

RP1

18

1 2

C81 0.1U_0402_16V4Z

C81 0.1U_0402_16V4Z

27

1 2

36

C139 0.1U_0402_16V4Z

C139 0.1U_0402_16V4Z

45

RP2

RP2

18
27
36
45

RP3

RP3

18
27
36
45

RP4

RP4

18
27
36
45

RP5

RP5

18
27
36
45

RP6

RP6

18
27
36
45

RP7

RP7

18
27
36
45

RP8

RP8

18
27
36
45

1 2

C192 0.1U_0402_16V4Z

C192 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

C88 0.1U_0402_16V4Z

1 2

C117 0.1U_0402_16V4Z

C117 0.1U_0402_16V4Z

1 2

C144 0.1U_0402_16V4Z

C144 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

1 2

C114 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z

1 2

C95 0.1U_0402_16V4Z

C95 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

1 2

C193 0.1U_0402_16V4Z

C193 0.1U_0402_16V4Z

1 2

C125 0.1U_0402_16V4Z

C125 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

1 2

C103 0.1U_0402_16V4Z

C103 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

C99 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

1 2

C107 0.1U_0402_16V4Z

C107 0.1U_0402_16V4Z

1 2

C98 0.1U_0402_16V4Z

C98 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>
<BOM Structure>

<BOM Structure>

1 2

C101 0.1U_0402_16V4Z

C101 0.1U_0402_16V4Z

1 2

C191 0.1U_0402_16V4Z

C191 0.1U_0402_16V4Z

<BOM Structure>

<BOM Structure>

<BOM Structure>

<BOM Structure>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

+1.8V

401743

401743

401743

1

C

C

C

of

of

of

10 46Wednesday, June 24, 2009

10 46Wednesday, June 24, 2009

10 46Wednesday, June 24, 2009

5

4

3

2

1

+DIMM_VREF+1.8V+1.8V

+0.9V

RP9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C202

4.7U_0805_10V4Z

C202

JDIMM1

JDIMM1

1

VREF

3

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB<7>
DDR_CS2_DIMMB#<7>

DDR_B_BS#2<7>

DDR_B_BS#0<7>
DDR_B_WE#<7>

DDR_B_CAS#<7>
DDR_CS1_DIMMB#<7>

DDR_B_ODT1<7>

B B

A A

SB_CK_SDAT<10,16,18,31>

SB_CK_SCLK<10,16,18,31>

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C21

C21

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

FOX_AS0A426-MARG-7F

FOX_AS0A426-MARG-7F
CONN@

CONN@

2

VSS

4

DQ4

6

DQ5

8

VSS

10

DM0

12

VSS

14

DQ6

16

DQ7

18

VSS

20

DQ12

22

DQ13

24

VSS

26

DM1

28

VSS

30

CK0

32

CK0#

34

VSS

36

DQ14

38

DQ15

40

VSS

42

VSS

44

DQ20

46

DQ21

48

VSS

50

NC

52

DM2

54

VSS

56

DQ22

58

DQ23

60

VSS

62

DQ28

64

DQ29

66

VSS

68

DQS3#

70

DQS3

72

VSS

74

DQ30

76

DQ31

78

VSS

80

NC/CKE1

82

VDD

84

NC/A15

86

NC/A14

88

VDD

90

A11

92

A7

94

A6

96

VDD

98

A4

100

A2

102

A0

104

VDD

106

BA1

108

RAS#

110

S0#

112

VDD

114

ODT0

116

NC/A13

118

VDD

120

NC

122

VSS

124

DQ36

126

DQ37

128

VSS

130

DM4

132

VSS

134

DQ38

136

DQ39

138

VSS

140

DQ44

142

DQ45

144

VSS

146

DQS5#

148

DQS5

150

VSS

152

DQ46

154

DQ47

156

VSS

158

DQ52

160

DQ53

162

VSS

164

CK1

166

CK1#

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

SAO

200

SA1

202

GND

DIMM1 REV H:9.2mm (BOT)

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R11 10K_0402_5%R11 10K_0402_5%

1 2

R9 10K_0402_5%R9 10K_0402_5%

1 2

4.7U_0805_10V4Z
1

2

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

DDR_B_D[0..63]<7>
DDR_B_DM[0..7]<7>

DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>

DDR_B_DQS#[0..7]<7>

DDR_CKE1_DIMMB <7>

DDR_B_BS#1 <7>
DDR_B_RAS# <7>
DDR_CS0_DIMMB# <7>

DDR_B_ODT0 <7>

DDR_CS3_DIMMB# <7>

DDR_B_CLK2 <7>
DDR_B_CLK#2 <7>

+3VS

C198

C198

1

2

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/11 2010/03/12

2005/10/11 2010/03/12

2005/10/11 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4

DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#

DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14

2

RP9

47_0804_8P4R_5%

47_0804_8P4R_5%

RP10

RP10

47_0804_8P4R_5%

47_0804_8P4R_5%

RP11

RP11

47_0804_8P4R_5%

47_0804_8P4R_5%

RP12

RP12

47_0804_8P4R_5%

47_0804_8P4R_5%

RP13

RP13

47_0804_8P4R_5%

47_0804_8P4R_5%

RP14

RP14

47_0804_8P4R_5%

47_0804_8P4R_5%

RP15

RP15

47_0804_8P4R_5%

47_0804_8P4R_5%

RP16

RP16

47_0804_8P4R_5%

47_0804_8P4R_5%

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

12

C196 0.1U_0402_16V4Z

C196 0.1U_0402_16V4Z

1 2

C209 0.1U_0402_16V4Z

C209 0.1U_0402_16V4Z

12

C197 0.1U_0402_16V4Z

C197 0.1U_0402_16V4Z

1 2

C211 0.1U_0402_16V4Z

C211 0.1U_0402_16V4Z

12

C205 0.1U_0402_16V4Z

C205 0.1U_0402_16V4Z

1 2

C213 0.1U_0402_16V4Z

C213 0.1U_0402_16V4Z

12

C199 0.1U_0402_16V4Z

C199 0.1U_0402_16V4Z

1 2

C200 0.1U_0402_16V4Z

C200 0.1U_0402_16V4Z

12

C206 0.1U_0402_16V4Z

C206 0.1U_0402_16V4Z

1 2

C201 0.1U_0402_16V4Z

C201 0.1U_0402_16V4Z

12

C210 0.1U_0402_16V4Z

C210 0.1U_0402_16V4Z

1 2

C208 0.1U_0402_16V4Z

C208 0.1U_0402_16V4Z

12

C194 0.1U_0402_16V4Z

C194 0.1U_0402_16V4Z

1 2

C207 0.1U_0402_16V4Z

C207 0.1U_0402_16V4Z

12

C212 0.1U_0402_16V4Z

C212 0.1U_0402_16V4Z

1 2

C195 0.1U_0402_16V4Z

C195 0.1U_0402_16V4Z

Title

Title

Title

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

SCHEMATIC, MB A5481

+1.8V

Compal Electronics, Inc.

401743

401743

401743

1

11 46Wednesday, June 24, 2009

11 46Wednesday, June 24, 2009

11 46Wednesday, June 24, 2009

C

C

C

of

of

of

5

U22B

U22B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

D D

PCIE_PTX_C_IRX_P0<31>
PCIE_PTX_C_IRX_N0<31>

PCIE_PTX_C_IRX_N1<25>

C C

SB_RX0P<17>
SB_RX0N<17>
SB_RX1P<17>
SB_RX1N<17>
SB_RX2P<17>
SB_RX2N<17>
SB_RX3P<17>
SB_RX3N<17>

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

RS780M_FCBGA528

PART 2 OF 6

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

RS780MN-SA00002DR30 Ver:A13

B B

A A

RS780M Display Port Support (muxed on GFX)

DP0

DP1

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

4

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6
AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5
AC8

AB8

C600 0.1U_0402_16V7KC600 0.1U_0402_16V7K

1 2

C601 0.1U_0402_16V7KC601 0.1U_0402_16V7K

1 2

C602 0.1U_0402_16V7KC602 0.1U_0402_16V7K

1 2

C605 0.1U_0402_16V7KC605 0.1U_0402_16V7K

1 2

C259 0.1U_0402_16V7KC259 0.1U_0402_16V7K

1 2

C272 0.1U_0402_16V7KC272 0.1U_0402_16V7K

1 2

C254 0.1U_0402_16V7KC254 0.1U_0402_16V7K

1 2

C252 0.1U_0402_16V7KC252 0.1U_0402_16V7K

1 2

C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K

1 2

C261 0.1U_0402_16V7KC261 0.1U_0402_16V7K

1 2

C248 0.1U_0402_16V7KC248 0.1U_0402_16V7K

1 2

C275 0.1U_0402_16V7KC275 0.1U_0402_16V7K

1 2
1 2

1 2

R29 1.27K_0402_1%R29 1.27K_0402_1%
R32 2K_0402_1%R32 2K_0402_1%

3

Check SW Routing

AN_RS780MN1, Only suggest pair0~3 can
usage for power save.

PCIE_ITX_C_PRX_P0 <31>
PCIE_ITX_C_PRX_N0 <31>
PCIE_ITX_C_PRX_P1 <25>PCIE_PTX_C_IRX_P1<25>
PCIE_ITX_C_PRX_N1 <25>

SB_TX0P <17>
SB_TX0N <17>
SB_TX1P <17>
SB_TX1N <17>
SB_TX2P <17>
SB_TX2N <17>
SB_TX3P <17>
SB_TX3N <17>

+1.1VS

HT Link
When tune trace length, must
keep 1:4 on self-trace

Check AMD

2

WLAN
LAN

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24
B25

H_CADIP0SB_TX2P_C

H_CADIN0

H_CADIP1

H_CADIN1

H_CADIP2

H_CADIN2

H_CADIP3

H_CADIN3

H_CADIP4

H_CADIN4

H_CADIP5

H_CADIN5

H_CADIP6

H_CADIN6

H_CADIP7

H_CADIN7

H_CADIP8

H_CADIN8

H_CADIP9

H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CTLIP0
H_CTLIN0

H_CTLIN1

Place within 1"
layout 4/8

H_CADOP[0..15]<6>
H_CADON[0..15]<6> H_CADIN[0..15] <6>

U22A
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9

H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0<6>
H_CLKON0<6>
H_CLKOP1<6>
H_CLKON1<6>

H_CTLOP0<6>
H_CTLON0<6>
H_CTLOP1<6>
H_CTLON1<6> H_CTLIN1 <6>

Place within 1"
layout 4/8

H_CTLOP0
H_CTLON0
H_CTLOP1 H_CTLIP1
H_CTLON1

R67

R67

1 2

301_0402_1%~D

301_0402_1%~D

U22A

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25

AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

RS780M_FCBGA528

RS780M_FCBGA528

RS780MN-SA00002DR30 Ver:A13

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

H_CADON[0..15]

PART 1 OF 6

PART 1 OF 6

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

1

H_CADIP[0..15] <6>

H_CLKIP0 <6>
H_CLKIN0 <6>
H_CLKIP1 <6>
H_CLKIN1 <6>

H_CTLIP0 <6>
H_CTLIN0 <6>
H_CTLIP1 <6>

R79

R79

1 2

301_0402_1%~D

301_0402_1%~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2010/03/12

2005/03/08 2010/03/12

2005/03/08 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

12 47Wednesday, June 24, 2009

12 47Wednesday, June 24, 2009

12 47Wednesday, June 24, 2009

1

C

C

C

of

of

of

5

4

3

2

1

+3VS

+1.8VS

L25

L25

1 2

C267

C267

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+1.8VS

+3VS

POWER_SEL

POWER_SEL

MBK2012170YZF_0805

MBK2012170YZF_0805

1

2

GMCH_CRT_HSYNC<15,23>
GMCH_CRT_VSYNC<15,23>

GMCH_CRT_CLK<23>
GMCH_CRT_DATA<23>

R319 0_0402_5%R319 0_0402_5%

CLK_SBLINK_BCLK<16>
CLK_SBLINK_BCLK#<16>

R327 10K_0402_5%

R327 10K_0402_5%

1

C78

C78

2

+VDDA18HTPLL

1

C266

C266

2

+VDDA18PCIEPLL

1

C31

C31

2

+NB_PLLVDD

1

C400

C400

2

@

@

1 2

C691

C691

22P_0402_50V8J

22P_0402_50V8J

+NB_HTPVDD+1.8VS

<65mA>

<20mA>

<20mA>

<120mA>

CLK_NB_14.318M

@

@

1 2

R637

R637

10_0402_5%

10_0402_5%

1 2

R55 140_0402_1%R55 140_0402_1%

1 2

R60 150_0402_1%R60 150_0402_1%

1 2

R62 150_0402_1%R62 150_0402_1%

Close to U22 Ball

1 2

+1.1VS

R58

R58

4.7K_0402_5%

4.7K_0402_5%

+1.8VS

MBK2012170YZF_0805

MBK2012170YZF_0805

GMCH_CRT_R
GMCH_CRT_G

GMCH_CRT_B

PLT_RST#<15,17,25,28,31>

NB_PWRGD<18>

NB_PGRGD (SB)
Output, OD

1 2

R43

R43

4.7K_0402_5%

4.7K_0402_5%

L10

L10

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+1.8VS

+1.8VS

+1.1VS

CLK_NB_14.318M<16>

2.2U_0603_6.3V4Z

L24

L24

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L5

L5

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L50

L50

1 2

MBK2012221YZF 0805

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

D D

C C

For EMI

+3VS

R323 4.7K_0402_5%R323 4.7K_0402_5%

1 2

R322 4.7K_0402_5%R322 4.7K_0402_5%

B B

1 2

R488 4.7K_0402_5%R488 4.7K_0402_5%

1 2

R493 4.7K_0402_5%R493 4.7K_0402_5%

1 2

GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA

POWER_SEL<42>

1.1VLOW

HIGH 1.0V

L8

L8

1 2

MBK2012170YZF_0805

MBK2012170YZF_0805

L23

L23

1 2

C265

C265

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+AVDDQ

<4mA>

GMCH_CRT_R<23>
GMCH_CRT_G<23>
GMCH_CRT_B<23>

R59 715_0402_1%R59 715_0402_1%

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

1 2
1 2

R326 300_0402_5%R326 300_0402_5%

CLK_NBHT<16>
CLK_NBHT#<16>

CLK_NBGFX<16>
CLK_NBGFX#<16>

GMCH_LCD_CLK<24>
GMCH_LCD_DATA<24>

@

@

12

R552 2K_0402_1%R552 2K_0402_1%

+AVDD1

C40

C40

22U_0805_6.3V6M

22U_0805_6.3V6M

+AVDD2

1

2

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_CRT_HSYNC
GMCH_CRT_VSYNC

GMCH_CRT_CLK
GMCH_CRT_DATA

1 2

+NB_PLLVDD
+NB_HTPVDD

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

CLK_NB_14.318M

GMCH_LCD_CLK
GMCH_LCD_DATA

1 2

1 2

R320 0_0402_5%@R320 0_0402_5%@

AUX_CAL<15>

Strap pin

<110mA>

1

2

<20mA>

NB_RESET#

U22C

U22C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

RS780M_FCBGA528

PART 3 OF 6

PART 3 OF 6

RS780MN-SA00002DR30 Ver:A13

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

THERMALDIODE_P

THERMALDIODE_N

HPD(NC)

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

<15mA>

<300mA>

R15

R15

1.8K_0402_5%

1.8K_0402_5%

+VDDLT18

VARY_ENBKL

12

12

12

VARY@

VARY@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
R56

R56

R54

R54

@

@

R328 10K_0402_5%

R328 10K_0402_5%
1 2

R48 0_0402_5%R48 0_0402_5%

1 2
R343

R343

GMCH_TXOUT0+ <24>
GMCH_TXOUT0- <24>
GMCH_TXOUT1+ <24>
GMCH_TXOUT1- <24>
GMCH_TXOUT2+ <24>
GMCH_TXOUT2- <24>

GMCH_TZOUT0+ <24>
GMCH_TZOUT0- <24>
GMCH_TZOUT1+ <24>
GMCH_TZOUT1- <24>
GMCH_TZOUT2+ <24>
GMCH_TZOUT2- <24>

GMCH_TXCLK+ <24>
GMCH_TXCLK- <24>
GMCH_TZCLK+ <24>
GMCH_TZCLK- <24>

4.7K_0402_5%

4.7K_0402_5%

12

+VDDLTP18+VDDLTP18

+VDDLT18

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R49 0_0402_5%R49 0_0402_5%

1 2

R50 0_0402_5%R50 0_0402_5%

1 2

R57 0_0402_5%VARY@R57 0_0402_5%VARY@

1 2

R51 0_0402_5%VARY@R51 0_0402_5%VARY@

1 2

SUS_STAT# <18>
SUS_STAT_R# <15>

C115

C115

Strap Pin

1 2

MBC1608121YZF_0603

MBC1608121YZF_0603

1

C449

C449

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1

1

C455

C455

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

2

L51

L51

L49

L49

1 2

MBC1608121YZF_0603

MBC1608121YZF_0603

GMCH_ENVDD <24>
ENBKL <28>
GMCH_INVT_PWM <24>

+1.8VS

+1.8VS

+1.8VS

R28

R28
300_0402_5%

300_0402_5%

1 2

R85 0_0402_5%R85 0_0402_5%

LDT_STOP#<8,17>

LDT_STP# (SB)
Output, OD

A A

5

4

1 2

NB_LDTSTOP#

LDTSTOP# (NB)
In Lagcy mode: Input, 1.8V signal can be used
In CLMC mode: Output, OD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2010/03/12

2005/03/08 2010/03/12

2005/03/08 2010/03/12

ALLOW_LDTSTOP<17>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SB: I/ OD

2

R553 0_0402_5%R553 0_0402_5%

1 2

NB_ALLOW_LDTSTOP

ALLOW_LDTSTOP (NB)
In Lagcy mode: Output,OD
In CLMC mode: Input, 1.8Vsignal can be used

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

Compal Electronics, Inc.

401743

401743

401743

13 47Wednesday, June 24, 2009

13 47Wednesday, June 24, 2009

13 47Wednesday, June 24, 2009

of

of

1

of

C

C

C

5

L14

L22

L22

L21

12

L9

L9

12

22U_0805_6.3V6M

22U_0805_6.3V6M

L14

12

22U_0805_6.3V6M

22U_0805_6.3V6M

C53

C53

+1.1VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

D D

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.2V_HT

C C

+1.8VS

1

2

B B

A A

L21

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

C52

C52
22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

1

C108

C108

2

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C257

C257

C154

C154

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C262

C262

2

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C37

C37

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C249

C249

C131

C131

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C219

C219

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C130

C130

C258

C258

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C58

C58

C55

C55

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.8VS

C398

C398

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C253

C253

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C264

C264

C273

C273

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C171

C171

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C56

C56

2

2

1

2

C126

C126

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C255

C255

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C62

C62

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

+VDDHT

1

U22E

2

+VDDHTRX

0.68A

<680mA>

+VDDHTTX

1

2

+VDDA18PCIE

1

2

<680mA>

<700mA>

<10mA>

+1.8VS +3VS

<25mA> <60mA>

U22E

J17

VDDHT_1

M16
R16

H18
G19

D22

AE25
AD24
AC23
AB22
AA21

W19

U17
R17
M17

M10

R10
AA9

AB9
AD9
AE9
U10

AE11
AD11

K16
L16

P16
T16

F20
E21

B23
A23

Y20
V18
T17
P17

J10
P10
K10

L10
W9

H9

T10

Y9

F9
G9

PART 5/6

PART 5/6

VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS780M_FCBGA528

RS780M_FCBGA528

RS780MN-SA00002DR30 Ver:A13

POWER

POWER

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

3

<1.1A>

+VDDA11PCIE

0.1U_0402_16V4Z

0.1U_0402_16V4Z

L16

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.1VS +NB_CORE

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L16

1 2

C19 22U_0805_6.3V6M

C19 22U_0805_6.3V6M

1 2

C15 22U_0805_6.3V6M

C15 22U_0805_6.3V6M
C42 1U_0402_6.3V4ZC42 1U_0402_6.3V4Z

1 2

C59 1U_0402_6.3V4ZC59 1U_0402_6.3V4Z

1 2

C44 1U_0402_6.3V4ZC44 1U_0402_6.3V4Z

1 2

C38 1U_0402_6.3V4ZC38 1U_0402_6.3V4Z

1 2
1 2

C51 0.1U_0402_16V4ZC51 0.1U_0402_16V4Z

1 2

C43 0.1U_0402_16V4ZC43 0.1U_0402_16V4Z

L7

@ L7

@

L6

@L6

@

<7.6A>

C570.1U_0402_16V4Z C570.1U_0402_16V4Z

1

1

1

C1100.1U_0402_16V4Z C1100.1U_0402_16V4Z

C1120.1U_0402_16V4Z C1120.1U_0402_16V4Z

2

2

2

1

C93

C93

2

1

1

1

C2150.1U_0402_16V4Z C2150.1U_0402_16V4Z

C2560.1U_0402_16V4Z C2560.1U_0402_16V4Z

C1230.1U_0402_16V4Z C1230.1U_0402_16V4Z

2

2

2

1

C61

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C800.1U_0402_16V4Z C800.1U_0402_16V4Z

1

1

C2180.1U_0402_16V4Z C2180.1U_0402_16V4Z

2

2

12

12
12

C1822U_0805_6.3V6M C1822U_0805_6.3V6M

C2022U_0805_6.3V6M C2022U_0805_6.3V6M

2

1

C2510.1U_0402_16V4Z C2510.1U_0402_16V4Z

1

2

2

U22F

U22F

A25

VSSAHT1

D23

E22
G22
G24
G25
H19

J22

L17

L22

L24

+1.1VS

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

1

C10

C10

2

+

+

2

1

M20
N22

R19
R22
R24
R25
H20
U22

W22
W24
W25

AD25

M14
N13

R11
R14

U14
U11
U15

W11
W15

AC12
AA14

AB11
AB15
AB17
AB19
AE20
AB21

AB12
AE16

AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

AD16
AE17
AD17

W12

AD18
AB13
AB18

W14

AE12
AD12

L25

P20

V19

Y21

L12

P12

P15

T12

V12

Y18

K11

V11

Y14

Y12

V14

V15

RS780MN-SA00002DR30 Ver:A13

PART 6/6

PART 6/6

VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

RS780M_FCBGA528

RS780M_FCBGA528

RS780MN-SA00002DR30 Ver:A13

U22D

U22D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

RS780M_FCBGA528

RS780M_FCBGA528

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

PAR 4 OF 6

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

1

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

1 2

R351 0_0402_5%R351 0_0402_5%

+1.8VS

+1.1VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2010/03/12

2005/03/08 2010/03/12

2005/03/08 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

1

C

C

14 47Wednesday, June 24, 2009

14 47Wednesday, June 24, 2009

14 47Wednesday, June 24, 2009

C

of

of

of

5

4

3

2

1

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

D D

GMCH_CRT_VSYNC<13,23>

12

R341 3K_0402_5%R341 3K_0402_5%

12

R337 3K_0402_5%@R337 3K_0402_5%@

+3VS

Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)

DFT_GPIO1: LOAD_EEPROM_STRAPS

AUX_CAL<13>

RS780 DFT_GPIO1

C C

SUS_STAT_R#<13> PLT_RST# <13,17,25,28,31>

1 2

R315 150_0402_1%@R315 150_0402_1%@

@

@

2 1

D22 CH751H-40PT_SOD323-2

D22 CH751H-40PT_SOD323-2

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 use HSYNC to enable SIDE PORT

RS780 use HSYNC to enable SIDE PORT

GMCH_CRT_HSYNC<13,23>

12

R332 3K_0402_5%R332 3K_0402_5%

@

@

12

R331 3K_0402_5%

R331 3K_0402_5%

+3VS

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

0. Enable (RS780)
1 : Disable(RS780)

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/10 2010/03/12

2005/10/10 2010/03/12

2005/10/10 2010/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

SCHEMATIC, MB A5481

401743

401743

401743

15 47Wednesday, June 24, 2009

15 47Wednesday, June 24, 2009

15 47Wednesday, June 24, 2009

1

C

C

C

of

of

of