Acer 3935 Schematics

5

SM30 Block Diagram

4

3

2

1

Project code: 91.4BT01.001
PCB P/N : 48.4BT01.001
Revision : 08239-SA

D D

C C

B B

A A

Crystal

14.318MHz

Mobile CPU

CLK GEN.

ICS 9LPRS929

3

HOST BUS 667/800/1066MHz@1.05V

DDR3

800/1033 MHz

12,13

DDR3

800/1033 MHz

Int MIC

15

MIC In

32

32

Line Out (SPDIF)

32

INT.SPKR

1.5W

http://laptop-motherboard-schematic.blogspot.com/

12,13

X4 DMI
400MHz

Crystal

32.768KHz

Codec

AZALIA

ALC272

30

Active Managemnet Technology(DO)

OP AMP

G1454

5

31

HDD
SATA

ODD SATA

SATA

23

22

Penryn

Cantiga

AGTL+ CPU I/F
DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

6,7,8,9,10,11

C-Link0

ICH9M

6 PCIe ports

PCI/PCI BRIDGE

ACPI 2.0
4 SATA

12 USB 2.0/1.1 ports

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

18,19,20,21

Mini USB
Blue Tooth

Finger
Printer

USB
2 Port

4

24

26

25

4, 5

USB

SMSC

EMC2103

Crystal
25MHz

PCIe

LPC BUS

Camera

USB
1 Port

29

Crystal

32.768KHz

15

CardReader
Realtek
RTS5159

3

LAN

Giga LAN

BCM5764

KBC

Winbond

WPCE773LA0DG

Touch
Pad

33 33

LCD

15

CRT

17

Mini Card

Mini Card

Kedron

SPI

33

INT.
KB

MS/MS Pro/xD
/MMC/SD

5 in 1

TOP

VCC

GND

BOTTOM

TXFM RJ45

a/b/g/n

28

BIOS
(2MB)

34

Launch
Buttom

35

2727

2

PCB STACKUP

S

S

(Robson2/3G)

(WLAN)

LPC

DEBUG
CONN.

Daughter Board

Launch Board

34

08621

UMA 2nd

UMA 2nd

UMA 2nd

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

RT9026

1.5V_S3

G9131

3D3V_S0 2D5V_S0

TPS51117

DCBATOUT 1D8V_S0

CHARGER

DCBATOUT

CPU DC/DC

INPUTS

DCBATOUT

GFX DC/DC

INPUTS

DCBATOUT

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SM30

SM30

SM30

1

1D05V_M(16A)
1D5V_S3(12A)

BQ24750

ISL6266A

OUTPUTS
VCC_CORE

0~1.3V
38A

ISL6263

OUTPUTS

VCC_GFXCORE

0~1.3V

6.5A

145Saturday, October 18, 2008

145Saturday, October 18, 2008

145Saturday, October 18, 2008

OUTPUTS

5V_S5(7A)
3D3V_S5(7A)
5V_AUX_S5
3D3V_AUX_S5

DDR_VREF_S3
(1.2A)

(300mA)

(9.4A)

OUTPUTSINPUTS

CHG_PWR

18V 6.0A

50

51

52

52

54

55

49

53

SA

SA

SA

A

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

HDA_SYNC

4 4

GNT2#/
GPIO53

GPIO20
GNT1#/

GPIO51

GNT3#/
GPIO55

GNT0#:
SPI_CS1#/
GPIO58

SPI_MOSI

3 3

GPIO49

SATALED#

SPKR

TP3

GPIO33/
HDA_DOCK
_EN#

Usage/When Sampled

XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK

PCIE config1 bit0,
Rising Edge of PWROK.

PCIE config2 bit2,
Rising Edge of PWROK.

Reserved
ESI Strap (Server Only)

Rising Edge of PWROK

Top-Block
Swap Override.
Rising Edge of PWROK.

Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.

Integrated TPM Enable,
Rising Edge of CLPWROK

DMI Termination Voltage,
Rising Edge of PWROK.

PCI Express Lane
Reversal. Rising Edge
of PWROK.

No Reboot.
Rising Edge of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Flash Descriptor
Security Override Strap
Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.

ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.

The signal is required to be low for desktop
applications and required to be high for
mobile applications.

Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the
"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.

This signal should not be pull low unless using
XOR Chain testing.

Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

2 2

B

ICH9M Integrated Pull-up

page 92

and Pull-down Resistors

SIGNAL Resistor Type/Value

CL_CLK[1:0]
CL_DATA[1:0]
CL_RST0#
DPRSLPVR/GPIO16
ENERGY_DETECT
HDA_BIT_CLK
HDA_DOCK_EN#/GPIO33
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO[20]
GPIO[49]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI
SPI_MISO
SPKR
TACH_[3:0]
TP[3]
USB[11:0][P,N]

C

Cantiga chipset and ICH9M I/O controller
Hub strapping configuration

ICH9 EDS 642879 Rev.1.5

PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K

The pull-up or pull-down active when configured for native
GLAN_DOCK# functionality and determined by LAN controller

PULL-DOWN 20K

PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 15K

SDVO_CTRLDATA

D

Montevina Platform Design guide 22339 0.5

Pin Name

CFG[2:0]

CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]

CFG5
CFG6

CFG7

CFG9

CFG10 PCIE Loopback enable

CFG[13:12]

CFG16

CFG19

CFG20

L_DDC_DATA

NOTE:

1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

Strap Description

FSB Frequency
Select

Reserved

DMI x2 Select
iTPM Host

Interface

Intel Management
engine Crypto strap

PCIE Graphics Lane

XOR/ALL

FSB Dynamic ODT

DMI Lane Reversal

Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIe

SDVO Present

Local Flat Panel
(LFP) Present

Configuration

000 = FSB1067
011 = FSB667
010 = FSB800
others = Reserved

0 = DMI x2

1 = DMI x4

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher
suite with no confidentiality

1 = TLS cipher suite with
confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enabled (Note 3)

11 = Disabled (default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled
0 = Normal operation(Default):

Lane Numbered in Order

1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Only Digital Display Port
or PCIE is operational (Default)

1 =Digital display Port and PCIe are
operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1= LFP Card Present; PCIE disabled

E

page 218

(Default)

(Default)

SMBus

SMBC_G792

USB Table

USB

0
1
2
3

Device
USB1
USB2
NC
MINIC2(WLAN)

Pair

4 CAMERA
5

NC

1 1

PCIE Routing

LANE1
LANE2
LANE3 MiniCard(Robson2G/3G)

LAN BCM5764
MiniCard WLAN

FingerPrint6

7

BLUETOOTH
NC

8

USB1(IO board)

9
1011MINIC1(IO BOARD)

CARD READER

http://laptop-motherboard-schematic.blogspot.com/

KBC

BAT_SCL

SMB_CLK

ICH9M

SMBC_ICH

Thermal

Media Key

BATTERY

LAN

CK505

DDR

UMA 2nd

UMA 2nd

UMA 2nd

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet of

Date: Sheet of

Reference

Reference

Reference

SM30

SM30

SM30

of

245Saturday, October 18, 2008

245Saturday, October 18, 2008

245Saturday, October 18, 2008

SA

SA

SA

3D3V_S0

R101

R101

1 2

D01R3J-L-GP

D01R3J-L-GP

A

3D3V_48MPWR_S0

12

C181

C181

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

C180

C180

SC1U16V3ZY-GP

SC1U16V3ZY-GP

12

C179

C179

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_S0

R119

R119

1 2

D01R3J-L-GP

D01R3J-L-GP

1008

1006

DY

DY

12

C198

C198

SC1U16V3ZY-GP

SC1U16V3ZY-GP

4 4

SRN33J-5-GP-U

SRN33J-5-GP-U

12

12

R92

R92
Do Not Stuff

Do Not Stuff

GSELGSEL

R109

R109

10KR2J-3-GP

10KR2J-3-GP

2 3
1

SEL_48MSEL_48M

12

R80

R80

1
2
3
4 5

PCLK_KBC33
PCLK_ICH19

PCLKCLK1

R90

3 3

3D3V_S0

2 2

R90

10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

DY

DY

1 2

SATACLKREQ#19
LAN_CLKREQ#35
CLK_MCH_OE#7

RN15

RN15

GSELGSEL

10KR2J-3-GP

10KR2J-3-GP

RN17

RN17

SRN470J-3-GP

SRN470J-3-GP

4

1003

1002

8
7
6

CR#A
CR#B
CR#C

PCLKCLK6
PCLKCLK5

PCLK_FWH34

CPU_SEL24,7
CPU_SEL14,7

45

RLATCH

678

CLK_CPU_BCLK4

CLK_CPU_BCLK#4

CLK_MCH_BCLK6

CLK_MCH_BCLK#6

123

CPU_SEL04,7

CLK_ICH1419

R98 0R2J-2-GPR98 0R2J-2-GP

RN16

RN16

SRN10KJ-6-GP

SRN10KJ-6-GP

CLK48_5158E27
CLK48_ICH19

PLT_RST1#7,19,27,28,33,34,35

3D3V_S0

12

C200

C200

Do Not Stuff

Do Not Stuff

1006

3D3V_S0

1 2

B

12

C204

C204

Do Not Stuff

Do Not Stuff

RN19

RN19

SRN33J-5-GP-U

SRN33J-5-GP-U

RN13

RN13

RN14

RN14

PLT_RST1#_RPLT_RST1#_R

SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

12

C171

C171

TP86

TP86

R93 Do Not Stuff

R93 Do Not Stuff

RN12

RN12

SRN2K2J-2-GP

SRN2K2J-2-GP

1
2 3

R89

R89

33R2J-2-GP

33R2J-2-GP

SRN33J-5-GP-U

SRN33J-5-GP-U

1
2 3

1
2 3

SRN33J-5-GP-U

SRN33J-5-GP-U

CLK_PWRGD19

Do Not Stuff

Do Not Stuff

12

C174

C174

Do Not Stuff

Do Not Stuff

DY

DY

DOC_033
DOC_133

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

1
2
3
4 5
4

12

CLK_PCIE_SATA18

CLK_PCIE_SATA#18

1002

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C172

C172

1
12

1002

CLK_CPU_BCLK_1

4

CLK_CPU_BCLK#_1
CLK_MCH_BCLK_1

4

CLK_MCH_BCLK#_1

R117

R117

DY

DY

1006

Do Not Stuff

Do Not Stuff

DY

DY

12

C196

C196

PCLKCLK0
PCLKCLK2
PCLKCLK5
PCLKCLK6

8

CPU_SEL2_1

7

CPU_SEL1_1

6

CPU_SEL0_1

SEL_48MSEL_48MSEL_48MSEL_48MSEL_48MSEL_48M

PCLKCLK1

PLT_RST1#_R

GSEL

12

CR#A
CR#B
CR#C

1 2

R95 0R2J-2-GPR95 0R2J-2-GP

1 2

R94 0R2J-2-GPR94 0R2J-2-GP

4

RN11

RN11
SRN33J-5-GP-U

SRN33J-5-GP-U

1

2 3

3D3V_CLKPLL_S0

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

12

C215

C215

C214

C214

U17

U17

69

PCICLK0_2X

71

PCICLK2_2X

3

PCICLK5_2X

4

PCICLK6_2X

6

FSLA/USB_48

1

FSLB/PCICLK4_2X

72

FSLC/PCICLK3_2X

7

SEL24_48#/24_48MHZ

70

SEL_STOP/PCICLK1_2X

52

RESET_IN#/RESET#

65

REF0/GSEL

57

CPUT_L0

56

CPUC_L0

54

CPUT_L1F

53

CPUC_L1F

12

SATACLKT_LR

13

SATACLKC_LR

16

VTT_PWRGD/PD#/WOL_STOP#

48

CR#A

49

CR#B

50

CR#C

ICS9LPRS929AKLFT-GP

ICS9LPRS929AKLFT-GP

71.09929.003

71.09929.003

RLATCH

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C186

C186

DOC_0_1
DOC_1_1

C

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

51

D

SMBC_ICH 12,13,21

GEN_XTAL_IN

63

68

GND

73

GEN_XTAL_OUT

X262X1

GND

SMBD_ICH 12,13,21

CL=20pF±0.2pF

C166

C166

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

17

PCIET_LR0

18

PCIEC_LR0

20

PCIET_LR1

21

PCIEC_LR1

23

PCIET_LR2

24

PCIEC_LR2

27

PCIET_LR3

28

PCIEC_LR3

29

PCIET_LR4

30

PCIEC_LR4

33

PCIET_LR5

32

PCIEC_LR5

35

PCIET_LR6

34

PCIEC_LR6

37

PCIET_LR7

36

PCIEC_LR7

40
39

DREFSSCLK_1

42

PCIET_LR9
PCIEC_LR9

SEL2
FSLC

41
9

10

DREFSSCLK_1#

DREFCLK_1
DREFCLK_1#

1
00
0
00

GEN_XTAL_IN

1 2

12

X1

X1

X-14D31818M-35GP

C167

C167

1 2

SEL1
FSLB

X-14D31818M-35GP

GEN_XTAL_OUT_R

82.30005.891

82.30005.891

2nd = 82.30005.891

2nd = 82.30005.891

CLK_PCIE_MINI2 35
CLK_PCIE_MINI2# 35

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

CLK_PCIE_LAN 35
CLK_PCIE_LAN# 35

CLK_PCIE_MINI1 28
CLK_PCIE_MINI1# 28

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

PM_STPPCI# 19
PM_STPCPU# 19

RN21

SEL0
FSLA

RN21

4

SRN0J-6-GP

SRN0J-6-GP

RN20

RN20

1

SRN0J-6-GP

SRN0J-6-GP

23

1
2 3

4

01

1
11
1

000

Do Not Stuff

Do Not Stuff

R96

R96

DY

DY

1 2

0R2J-2-GP

0R2J-2-GP

R97

R97

CPU FSB

100M
133M
166M
200M
266M

12

R102 0R2J-2-GPR102 0R2J-2-GP

R99 0R2J-2-GPR99 0R2J-2-GP

VDDSATA

GND

1 2

1 2

SMBD_ICH_GEN

SMBC_ICH_GEN

61

60

55

59

SCLK

SDATA

VDDREF

VDDCPU

PCIET_LR8/CPU_STOP#

PCIEC_LR8/PCI_STOP#

DOT96T_LR/PCIET_LR10

DOT96C_LR/PCIEC_LR10

GND

GND

GND

GND

GND

GND

GND

GND

15

25

GND

38

43

47

19

31

58

64

3D3V_48MPWR_S0

14

45

22

26

2

5

VDD44VDD

VDD

VDD

VDD48

VDDPCI

GND

25MHZ

RLATCH

DOC_066DOC_1

8

11

46

67

GEN_XTAL_OUT

DREFSSCLK 7
DREFSSCLK# 7

DREFCLK 7
DREFCLK# 7

E

X
533M
667M
800M
1067M

GSEL

0
1

1 1

DOT Freq

100MHZ
96MHZ

SEL_STOP

SEL24_48#/24_48MHZ

http://laptop-motherboard-schematic.blogspot.com/

A

Selects pin 39/40

PCI_STOP#/CPU_STOP#

0
1

0
1

PCIEX outputs

OUTPUT

24MHZ
48MHZ

B

DOC_0

0
1

DOC_1

0
1

Real Time Frequency

Normal
Frequency will transition

to a preprogrammed
value in the I2C

Real Time Frequency

Normal
Frequency will transition

to a preprogrammed
value in the I2C

C

UMA 2nd

UMA 2nd

UMA 2nd

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Clock Generator

Clock Generator

Clock Generator

Taipei Hsien 221, Taiwan, R.O.C.

SM30

SM30

SM30

E

SA

SA

SA

of

345Monday, October 27, 2008

of

345Monday, October 27, 2008

of

345Monday, October 27, 2008

A

B

C

D

E

H_A#[35..3]6

4 4

H_ADSTB#06
H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#18

H_FERR#18

H_IGNNE#18

H_STPCLK#18

2 2

1 1

H_INTR18
H_NMI18
H_SMI#18

TP81Do Not Stuff TP81Do Not Stuff

http://laptop-motherboard-schematic.blogspot.com/

H_A#[35..3]

R45

R45

1 2

Do Not Stuff

Do Not Stuff

A

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_STPCLK#_R

1 OF 4

1 OF 4

CPU1A

CPU1A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT-8-GP-U3

BGA479-SKT-8-GP-U3

62.10053.401

62.10053.401

2nd: 62.10053.401

H1

ADS#

E2

BNR#

ADDR GROUP 0

ADDR GROUP 0

ADDR GROUP 1

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL
THERMAL

THERMAL

PROCHOT#

ICH

ICH

THERMTRIP#

HCLK

HCLK

RESERVED

RESERVED

XDP_TMS
XDP_TDI
XDP_BPM#5

H_CPURST#

XDP_TCK
XDP_TRST#

G5

BPRI#

H5

DEFER#

F21

DRDY#

E1

DBSY#

F1

BR0#

D20

IERR#

B3

INIT#

H4

LOCK#

C1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

G6

HIT#

E4

HITM#

AD4

BPM0#

AD3

BPM1#

AD1

BPM2#

AC4

BPM3#

AC2

PRDY#

AC1

PREQ#

AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6

TRST#

C20

DBR#

D21
A24

THRMDA

B25

THRMDC

C7

A22

BCLK0

A21

BCLK1

R62 54D9R2F-L1-GPR62 54D9R2F-L1-GP

1 2

R55 54D9R2F-L1-GPR55 54D9R2F-L1-GP

1 2

R66 54D9R2F-L1-GPR66 54D9R2F-L1-GP

1 2

R64 Do Not Stuff

R64 Do Not Stuff

1 2

DY

DY

R47 54D9R2F-L1-GPR47 54D9R2F-L1-GP

1 2

R42 54D9R2F-L1-GPR42 54D9R2F-L1-GP

1 2

All place within 2" to CPU

H_RS#0
H_RS#1
H_RS#2

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

B

TP77 Do Not StuffTP77 Do Not Stuff

H_ADS# 6
H_BNR# 6

H_BPRI# 6

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_BREQ#0 6

H_IERR#

H_INIT# 18
H_LOCK# 6

H_CPURST# 6

H_TRDY# 6
H_HIT# 6

H_HITM# 6

TP68 Do Not StuffTP68 Do Not Stuff
TP71 Do Not StuffTP71 Do Not Stuff

1

TP79 Do Not StuffTP79 Do Not Stuff
TP67 Do Not StuffTP67 Do Not Stuff
TP72 Do Not StuffTP72 Do Not Stuff
TP76 Do Not StuffTP76 Do Not Stuff
TP63 Do Not StuffTP63 Do Not Stuff
TP64 Do Not StuffTP64 Do Not Stuff
TP73 Do Not StuffTP73 Do Not Stuff
TP66 Do Not StuffTP66 Do Not Stuff
TP62 Do Not StuffTP62 Do Not Stuff
TP51 Do Not StuffTP51 Do Not Stuff

CPU_PROCHOT#_1

H_THERMDA 29
H_THERMDC 29

R46

R46

1 2

Do Not Stuff

Do Not Stuff

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

1D05V_S0

1D05V_S0

12

R23

R23
56R2J-4-GP

56R2J-4-GP

H_RS#[2..0] 6

1D05V_S0

Place testpoint on
H_IERR# with a GND

0.1" away

H_THERMDA

H_THERMDC

12

R20

R20
68R2-GP

68R2-GP

R19

R19

1 2

Do Not Stuff

Do Not Stuff

DY

DY

PM_THRMTRIP-A# 7,18,36

PH @ page48

Layout Note:
"CPU_GTLREF0"

0.5" max length.

2KR2F-3-GP

2KR2F-3-GP

12

C364

C364
Do Not Stuff

Do Not Stuff

DY

DY

CPU_PROCHOT#_R 38

should connect toPM_THRMTRIP#
without T-ingICH9 and MCH

1D05V_S0

1KR2F-3-GP

1KR2F-3-GP
R257

R257

1 2
12

C363

C363

R256

R256

R21 Do Not Stuff

R21 Do Not Stuff

R17 Do Not Stuff

R17 Do Not Stuff

1 2

DY

DY

1 2

DY

DY

C377

C377

DY

DY

Do Not Stuff

Do Not Stuff

C

Do Not Stuff

Do Not Stuff

12

12

DY

DY

TEST1

TEST2

TEST4

H_D#0

E22

H_D#1

F24

H_D#2

E26

H_D#3

G22

H_D#4

F23

H_D#5

G25

H_D#6

E25

H_D#7

E23

H_D#8

K24

H_D#9

G24

H_D#10

J24

H_D#11

J23

H_D#12

H22

H_D#13

F26

H_D#14

K22

H_D#15

H23

TEST1
TEST2

TEST4

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H26
H25

M24
M23

R24

N25
M26

N24

AD26

C23
D25
C24

AF26

AF1

C21

J26

N22
K25
P26
R23
L23

L22
P25

P23
P22
T24

L25
T25

L26

A26
B22

B23

H_DSTBN#06
H_DSTBP#06
H_DINV#06

H_DSTBN#16
H_DSTBP#16
H_DINV#16

CPU_GTLREF0

RSVD_CPU_12

TP49Do Not Stuff TP49Do Not Stuff

RSVD_CPU_13

TP151Do Not Stuff TP151Do Not Stuff

RSVD_CPU_14RSVD_CPU_11

TP135Do Not Stuff TP135Do Not Stuff

CPU_SEL03,7
CPU_SEL13,7
CPU_SEL23,7

Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
H_INIT#
H_CPURST#

Place these TP on button-side,
easy to measure.

2 OF 4

2 OF 4

CPU1B

CPU1B

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

BGA479-SKT-8-GP-U3

BGA479-SKT-8-GP-U3

62.10053.401

62.10053.401

TP50 Do Not StuffTP50 Do Not Stuff
TP156 Do Not StuffTP156 Do Not Stuff
TP47 Do Not StuffTP47 Do Not Stuff
TP61 Do Not StuffTP61 Do Not Stuff
TP60 Do Not StuffTP60 Do Not Stuff
TP157 Do Not StuffTP157 Do Not Stuff
TP75 Do Not StuffTP75 Do Not Stuff

D

DATA GRP0 DATA GRP1

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

DATA GRP2DATA GRP3

DSTBN2#
DSTBP2#

DSTBN3#
DSTBP3#

MISC

MISC

DPRSTP#

PWRGOOD

H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]

H_D#32

Y22

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#

DINV2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPSLP#

DPWR#

SLP#

PSI#

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1
E5

B5
D24
D6
D7
AE6

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

UMA 2nd

UMA 2nd

UMA 2nd

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
H_D#[63..0] 6

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

R254 27D4R2F-L1-GPR254 27D4R2F-L1-GP

1 2

R255 54D9R2F-L1-GPR255 54D9R2F-L1-GP

1 2

R71 27D4R2F-L1-GPR71 27D4R2F-L1-GP

1 2

R72 54D9R2F-L1-GPR72 54D9R2F-L1-GP

1 2

H_DPRSTP# 7,18,38
H_DPSLP# 18
H_DPWR# 6
H_PWRGD 18,36
H_CPUSLP# 6
PSI# 38

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

CPU (1 of 2)

CPU (1 of 2)

SM30

SM30

SM30

E

445Saturday, October 18, 2008

445Saturday, October 18, 2008

445Saturday, October 18, 2008

SA

SA

SA

A

B

C

D

E

VCC_CORE

4 4

3 3

AA10
AA12

2 2

1 1

AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

CPU1C

CPU1C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AB9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

BGA479-SKT-8-GP-U3

BGA479-SKT-8-GP-U3

62.10053.401

62.10053.401

3 OF 4

3 OF 4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCCA
VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCC_CORE

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

C59

C59

C133

C133

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

VCC_CORE

12

VCC_CORE

12

C65

C65

Do Not Stuff

Do Not Stuff

DY

DY

VCC_CORE

G3

G3

1 2

G4

G4

1 2

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

H_VID[6..0] 38

12

R38

R38
100R2F-L1-GP-U

100R2F-L1-GP-U

R40

R40
100R2F-L1-GP-U

100R2F-L1-GP-U

12

12

C73

C73

DY

DY

12

1D05V_S0

12

C116

C116

C132

Do Not Stuff

Do Not Stuff

DY

DY

C79

C79

1D5V_VCCA_S0

C132

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

DY

DY

12

12

C100

C100

C118

Do Not Stuff

Do Not Stuff

layout note: "1D5V_VCCA_S0"
as short as possible

Layout Note:

VCCSENSE and VSSSENSE lines
should be of equal length.

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

C118

Do Not Stuff

Do Not Stuff

12

12

C362

C362

C359

C359

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

VCC_SENSE 38

VSS_SENSE 38

Do Not Stuff

Do Not Stuff

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

L11

L11

C62

C62

Do Not Stuff

Do Not Stuff

12

C99

C99

1D5V_S0

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

C61

C61

Do Not Stuff

Do Not Stuff

A11
A14
A16
A19

M22
M25

A23
AF2

B11
B13
B16
B19
B21
B24

C11
C14
C16
C19

C22
C25

D11
D13
D16
D19
D23
D26

E11
E14
E16
E19
E21
E24

F11
F13
F16
F19

F22
F25

G23
G26

H21
H24

K23
K26

N23
N26

J22
J25

L21
L24

TP149Do Not Stuff TP149Do Not Stuff

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

C68

C68

C80

C80

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

12

C63

C63

C60

C60

Do Not Stuff

Do Not Stuff

12

C86

C86

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C128

C128

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C112

C112

DY

DY

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C131

C131

12

12

C113

C113

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C129

C129

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Do Not Stuff

Do Not Stuff

12

C119

C119

C67

C67

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C57

C57

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

12

C69

C69

C85

C85

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D05V_S0

4 OF 4

4 OF 4

CPU1D

CPU1D

A4

VSS

A8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

B6

VSS

B8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

C5

VSS

C8

VSS
VSS
VSS
VSS
VSS

C2

VSS
VSS
VSS

D1

VSS

D4

VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

E3

VSS

E6

VSS

E8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

F5

VSS

F8

VSS
VSS
VSS
VSS
VSS

F2

VSS
VSS
VSS

G4

VSS

G1

VSS
VSS
VSS

H3

VSS

H6

VSS
VSS
VSS

J2

VSS

J5

VSS
VSS
VSS

K1

VSS

K4

VSS
VSS
VSS

L3

VSS

L6

VSS
VSS
VSS

M2

VSS

M5

VSS
VSS
VSS

N1

VSS

N4

VSS
VSS
VSS

P3

VSS

BGA479-SKT-8-GP-U3

BGA479-SKT-8-GP-U3

62.10053.401

62.10053.401

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

TP150

TP150
Do Not Stuff

Do Not Stuff

TP137

TP137
Do Not Stuff

Do Not Stuff
TP82

TP82
Do Not Stuff

Do Not Stuff

TP136

TP136
Do Not Stuff

Do Not Stuff
TP140

TP140
Do Not Stuff

Do Not Stuff

http://laptop-motherboard-schematic.blogspot.com/

A

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

B

C

D

Date: Sheet of

CPU (2 of 2)

CPU (2 of 2)

CPU (2 of 2)

SM30

SM30

SM30

E

SA

SA

545Monday, October 27, 2008

545Monday, October 27, 2008

545Monday, October 27, 2008

SA

5

H_SWING

H_RCOMP

1D05V_S0

12

R74

R74
221R2F-2-GP

221R2F-2-GP

12

R73

R73
100R2F-L1-GP-U

100R2F-L1-GP-U

D D

H_SWING routing Trace width and
Spacing use 10 / 20 mil

H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )

12

C154

C154

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C C

H_RCOMP routing Trace width and
Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

24D9R2F-L-GP

R69

R69

Place them near to the chip ( < 0.5")

B B

1D05V_S0

R344

R344
1KR2F-3-GP

1KR2F-3-GP

1 2

12

R343

R343
2KR2F-3-GP

2KR2F-3-GP

4

H_AVREF

H_D#[63..0]

H_CPURST#4
H_CPUSLP#4

12

C439

C439
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

M11

N12

P13

N10

AD14

Y10
Y12
Y14

AA8

AA13

AA9
AA11
AD11
AD10
AD13
AE12

AE9

AA2

AD8

AA3

AD3

AD7
AE14

AF3

AC1

AE3

AC3
AE11

AE8

AG2
AD6

C12

E11

A11

B11

F2

G8

F8
E6

G2

H6
H2
F6
D4
H3

M9

J1
J2

J6
P2
L2
R2
N9
L6

M5

J3
N2
R1
N5
N6

N8
L7

M3

Y3
Y6

Y7

W2

Y9

C5
E3

H_D#[63..0]4

3

NB1A

NB1A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

HOST

HOST

1 OF 10

1 OF 10

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

2

H_A#[35..3]

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_DEFER# 4

H_DBSY# 4

CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3

H_DPWR# 4

H_DRDY# 4
H_HIT# 4
H_HITM# 4

H_LOCK# 4
H_TRDY# 4

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

1

H_A#[35..3] 4

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

A A

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

UMA 2nd

UMA 2nd

UMA 2nd

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Cantiga (1 of 6)

Cantiga (1 of 6)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Cantiga (1 of 6)

SM30

SM30

SM30

1

645Saturday, October 18, 2008

645Saturday, October 18, 2008

645Saturday, October 18, 2008

SA

SA

SA

5

Strap Pin Table

CFG[2:0] FSB Freq select

000 = FSB 1067MHz
010 = FSB 800MHz

011 = FSB 667MHz
Others = Reserved

CFG4:3; 8; 11; 14:15; 17; 18 Reserved

Low = DMI x 2CFG5 (DMI select)

CFG6 (ITPM Host Interface)

CFG7 (Intel Management Engine
Crypto Strap)

D D

CFG9 (PCIE Graphics Lane) Low = Reverse Lanes, 15->0, 14->1 etc...

CFG10 (PCIE Loopback enable) Low = Enabled

CFG12 (ALLZ) Low = ALLZ mode Enabled

CFG13 (XOR) Low = XOR mode Enabled

CFG16 (FSB Dynamic ODT) Low = Dynamic ODT Disabled

CFG19 (DMI Lane Reversal) Low = Noraml operation: Lane Numbered in Order

CFG20 (Digital Display Port (SDVO/DP
/iHDMI) Concurrent with PCIE)

SDVO_CTRLDATA
(SDVO Present)

C C

L_DDC_DATA (Local Flat Panel
(LFP) Present)

DDPC_CTRLDATA
(Digital Display Present)

3D3V_S0

R48 Do Not Stuff

R48 Do Not Stuff

1 2

DY

DY

R59 Do Not Stuff

R59 Do Not Stuff

1 2

DY

DY

R52 Do Not Stuff

R52 Do Not Stuff

1 2

DY

DY

R54 Do Not Stuff

R54 Do Not Stuff

1 2

DY

DY

R51 Do Not Stuff

R51 Do Not Stuff

1 2

DY

DY

R77 Do Not Stuff

R77 Do Not Stuff

1 2

DY

DY

R56 Do Not Stuff

R56 Do Not Stuff

1 2

DY

DY

R63 Do Not Stuff

R63 Do Not Stuff

1 2

DY

DY

R70 Do Not Stuff

R70 Do Not Stuff

B B

1 2

DY

DY

R78 Do Not Stuff

R78 Do Not Stuff

1 2

DY

DY

R79 Do Not Stuff

R79 Do Not Stuff

1 2

DY

DY

R58 Do Not Stuff

R58 Do Not Stuff

1 2

DY

DY

R49 Do Not Stuff

R49 Do Not Stuff

1 2

DY

DY

R41 Do Not Stuff

R41 Do Not Stuff

1 2

DY

DY

R44 Do Not Stuff

R44 Do Not Stuff

1 2

DY

DY

R57 Do Not Stuff

R57 Do Not Stuff

1 2

DY

DY

R60 Do Not Stuff

R60 Do Not Stuff

1 2

DY

DY

R67 Do Not Stuff

R67 Do Not Stuff

1 2

DY

DY

A A

http://laptop-motherboard-schematic.blogspot.com/

High = The ITPM Host Interface is disabled

Low = The ITPM Host Interface is enabled

Low = Intel Management Engine Crypto Transport
Layer Security (TLS) cipher site with
no confidentiality
High = Intel Management Engine Crypto TLS Cipher
suite with confidentiality

High = Normal operation:Lane Numbered in Order

High = Disabled

High = Disabled

High = Disabled

High = Dynamic ODT Enabled

High = Reverse Lanes
DMI x 4 mode[MCH->ICH]: (0->3, 2->1, 1->2 and 0->3)
DMI x 2 mode[MCH->ICH]: (3->0, 2->1)

Low = Only Digital Display Port (SDVO/iHDMI)
or PCIE is operational

High = Digital Display Port (SDVO/DP/iHDMI)
and PCIE are operating simulatneously
via the PEG port

Low = No SDVO Card Present
High = SDVO Card Present

Low = LFP Disabled
High = LFP Card Present; PCIE disabled

Low = DisplayPort Disabled
High = DisplayPort Device Present

CFG18
CFG19
CFG20
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

5

High = DMI x 4

1D5V_S3

12

12

R276

R276
80D6R2F-L-GP

80D6R2F-L-GP

M_RCOMPP

M_RCOMPN

R277

R277
80D6R2F-L-GP

80D6R2F-L-GP

PLT_RST1#3,19,27,28,33,34,35

CLK_MCH_OE#

PM_EXTTS#0
PM_EXTTS#1

*

*

TP54 Do Not StuffTP54 Do Not Stuff
TP56 Do Not StuffTP56 Do Not Stuff
TP52 Do Not StuffTP52 Do Not Stuff

*

TP53 Do Not StuffTP53 Do Not Stuff

*

*

*

*

*

*

*

*

*

*

CPU_SEL03,4
CPU_SEL13,4
CPU_SEL23,4

PM_SYNC#19
H_DPRSTP#4,18,38

PM_EXTTS#012,13

R32

R32

R61

R61

DY

DY

1 2

Do Not Stuff

Do Not Stuff

RN40

RN40

4

SRN10KJ-5-GP

SRN10KJ-5-GP

1 2

Do Not Stuff

Do Not Stuff

1 2

R25

R25

0R2J-2-GP

0R2J-2-GP

Do Not Stuff

Do Not Stuff

3D3V_S0

3D3V_S0

1
23

PWROK19,36

PM_THRMTRIP-A#4,18,36

PM_DPRSLPVR19,36,38

C87

C87

DY

DY

R87

R87

1 2

Do Not Stuff

Do Not Stuff

PM_EXTTS#1
PWROK_GD

12

RSTIN#
NB_THERMTRIP#

4

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

4

ME_TCK
ME_TDI
ME_TDO
ME_TMS

NB1B

NB1B

M36

RESERVED#M36

N36

RESERVED#N36

R33

RESERVED#R33

T33

RESERVED#T33

AH9

RESERVED#AH9

AH10

RESERVED#AH10

AH12

RESERVED#AH12

AH13

RESERVED#AH13

K12

RESERVED#K12

AL34

RESERVED#AL34

AK34

RESERVED#AK34

AN35

RESERVED#AN35

AM35

RESERVED#AM35

T24

RESERVED#T24

B31

RESERVED#B31

B2

RESERVED#B2

M1

RESERVED#M1

AY21

RESERVED#AY21

BG23

RESERVED#BG23

BF23

RESERVED#BF23

BH18

RESERVED#BH18

BF18

RESERVED#BF18

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC#BG48

BF48

NC#BF48

BD48

NC#BD48

BC48

NC#BC48

BH47

NC#BH47

BG47

NC#BG47

BE47

NC#BE47

BH46

NC#BH46

BF46

NC#BF46

BG45

NC#BG45

BH44

NC#BH44

BH43

NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

3

2 OF 10

2 OF 10

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

RSVD

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_DRAMRST#

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CLK

CFG

CFG

DMI

DMI

PM

PM

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

NC

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

MISC

SB_CKE_1
SA_CS#_0

SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36
BA17

AY16
AV16
AR13

BD17
AY17
BF15
AY13

BG22
BH21

BF28
BH28

AV42
AR36
BF17
BC36

B38
A38
E41
F41

F43
E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

M_RCOMPP
M_RCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_REXT

GFXVR_EN

CLPWROK_R

MCH_CLVREF

MCH_TSATN#

M_CLK_DDR0 12
M_CLK_DDR1 12
M_CLK_DDR2 13
M_CLK_DDR3 13

M_CLK_DDR#0 12
M_CLK_DDR#1 12
M_CLK_DDR#2 13
M_CLK_DDR#3 13

M_CKE0 12
M_CKE1 12
M_CKE2 13
M_CKE3 13

M_CS0# 12
M_CS1# 12
M_CS2# 13
M_CS3# 13

M_ODT0 12
M_ODT1 12
M_ODT2 13
M_ODT3 13

R278 499R2F-2-GPR278 499R2F-2-GP

1 2

DREFCLK# 3

DREFSSCLK# 3

CLK_MCH_3GPLL 3

CLK_MCH_3GPLL# 3

DMI_TXN0 19
DMI_TXN1 19
DMI_TXN2 19
DMI_TXN3 19

DMI_TXP0 19
DMI_TXP1 19
DMI_TXP2 19
DMI_TXP3 19

DMI_RXN0 19
DMI_RXN1 19
DMI_RXN2 19
DMI_RXN3 19

DMI_RXP0 19
DMI_RXP1 19
DMI_RXP2 19
DMI_RXP3 19

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4

R31

R31

1 2

0R2J-2-GP

0R2J-2-GP

TP155

TP155
TPAD14-GP

TPAD14-GP

3

DREFCLK 3

DREFSSCLK 3

GFXVR_EN 42

CLK_MCH_OE# 3
MCH_ICH_SYNC# 19

SM_PWROK 36

0.75V

DDR3_DRAMRST# 12,13

GFX_VID[4..0] 42

CL_CLK0 19

CL_DATA0 19
PWROK 19,36
CL_RST#0 19

C108

C108

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1009

R262 1KR2F-3-GPR262 1KR2F-3-GP

12

R263

R263
3K01R2F-3-GP

3K01R2F-3-GP

R280

R280
1KR2F-3-GP

1KR2F-3-GP

1 2

DDR_VREF_S3

12

C77

C77

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D05V_S0

R34

R34
1KR2F-3-GP

1KR2F-3-GP

1 2

12

12

R33

R33

499R2F-2-GP

499R2F-2-GP

FOR Cantiga:500 ohm
Teenah: 392 ohm

1D5V_S3

12

12

C375

C375
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

C376

C376
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

GMCH_LCDVDD_ON15

GMCH_BLUE17

GMCH_GREEN17

GMCH_RED17

GMCH_DDCCLK17
GMCH_DDCDATA17

GMCH_HSYNC17
GMCH_VSYNC17

12

12

layout take note

L_BKLTCTL15
GMCH_BL_ON33

CLK_DDC_EDID15
DAT_DDC_EDID15

TP154Do Not Stuff TP154Do Not Stuff

GMCH_TXACLK-15
GMCH_TXACLK+15

GMCH_TXAOUT0-15
GMCH_TXAOUT1-15
GMCH_TXAOUT2-15

GMCH_TXAOUT0+15
GMCH_TXAOUT1+15
GMCH_TXAOUT2+15

GMCH_DDCCLK
GMCH_DDCDATA

2 3
1

RN8

RN8

SRN33J-5-GP-U

SRN33J-5-GP-U

1 2

R347 1K02R2F-1-GPR347 1K02R2F-1-GP

FOR Cantiga: 1.02k_1% ohm
Teenah: 1.3k ohm

CRT_IREF routing Trace
width use 20 mil

SM_RCOMP_VOH

C369

C369
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SM_RCOMP_VOL

C370

C370
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

2

LCTLA_CLK

LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID

GMCH_LCDVDD_ON

LIBG
L_LVBG

TV_DACA

TV_DACB

TV_DACC

GMCH_BLUE
GMCH_GREEN
GMCH_RED

GMCH_HS

GMCH_VS

4

CRT_IREF

2

L32
G32
M32

M33
K33

J33

M29
C44
B43
E37
E38
C41
C40
B37
A37

H47
E46
G40
A40

H48
D45

F40
B40

A41
H38
G37

J37
B42

G38

F37
K37

F25
H25
K25

H24

C31
E32

E28
G28

J28
G29
H32

J32

J29
E29

L29

LCTLA_CLK
LCTLB_DATA

GMCH_BLUE
GMCH_GREEN

GMCH_RED

TV_DACA
TV_DACB
TV_DACC

NB1C

NB1C

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK

CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

RN38

RN38

4

SRN10KJ-5-GP

SRN10KJ-5-GP

RN6

RN6

1
2
3
4 5

SRN150F-1-GP

SRN150F-1-GP

RN10

RN10

1
2
3
4 5

SRN75J-3-GP

SRN75J-3-GP

1

Close to GMCH as 500 mils.

3 OF 10

3 OF 10

PEG_CMP

T37

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11

LVDS

LVDS

PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4

TV VGA

TV VGA

3D3V_S0

1
23

8
7
6

8
7
6

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

GMCH_BL_ON
GMCH_LCDVDD_ON

GFXVR_EN

LIBG

Cantiga (2 of 6)

Cantiga (2 of 6)

Cantiga (2 of 6)

SM30

SM30

SM30

R43

R43

T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN9

RN9

1
2
3
4 5

SRN100KJ-5-GP

SRN100KJ-5-GP

R337

R337

1 2

2K37R2F-GP

2K37R2F-GP

745Saturday, October 18, 2008

745Saturday, October 18, 2008

745Saturday, October 18, 2008

49D9R2F-GP

49D9R2F-GP

8
7
6

of

of

of

1D05V_S0

12

SA

SA

SA

5

NB1D

M_A_DQ[63..0]12

D D

C C

B B

M_A_DQ[63..0]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

NB1D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

4 OF 10

4 OF 10

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6

M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8

M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_BS#0 12
M_A_BS#1 12
M_A_BS#2 12

M_A_RAS# 12

M_A_CAS# 12

M_A_WE# 12

M_A_DM[7..0] 12

M_A_DQS[7..0] 12

M_A_DQS#[7..0] 12

M_A_A[14..0] 12

3

NB1E

M_B_DQ[63..0]13

M_B_DQ[63..0]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

NB1E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

2

5 OF 10

5 OF 10

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

M_B_DM0

AM47

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8

M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

M_B_RAS# 13
M_B_CAS# 13
M_B_WE# 13

1

M_B_BS#0 13
M_B_BS#1 13
M_B_BS#2 13

M_B_DM[7..0] 13

M_B_DQS[7..0] 13

M_B_DQS#[7..0] 13

M_B_A[14..0] 13

A A

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

http://laptop-motherboard-schematic.blogspot.com/

5

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

Cantiga (3 of 6)

Cantiga (3 of 6)

Cantiga (3 of 6)

SM30

SM30

SM30

845Saturday, October 18, 2008

845Saturday, October 18, 2008

845Saturday, October 18, 2008

1

SA

SA

SA

5

4

3

2

1

7 OF 10

1D5V_S3

D D

C C

VCC_GFXCORE

B B

A A

VCC_AXG_SENSE42
VSS_AXG_SENSE42

NB1G

NB1G

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

VCC_SM

BB32

VCC_SM

BA32

VCC_SM

AY32

VCC_SM

AW32

VCC_SM

AV32

VCC_SM

AU32

VCC_SM

AT32

VCC_SM

AR32

VCC_SM

AP32

VCC_SM

AN32

VCC_SM

BH31

VCC_SM

BG31

VCC_SM

BF31

VCC_SM

BG30

VCC_SM

BH29

VCC_SM

BG29

VCC_SM

BF29

VCC_SM

BD29

VCC_SM

BC29

VCC_SM

BB29

VCC_SM

BA29

VCC_SM

AY29

VCC_SM

AW29

VCC_SM

AV29

VCC_SM

AU29

VCC_SM

AT29

VCC_SM

AR29

VCC_SM

AP29

VCC_SM

BA36

VCC_SM/NC

BB24

VCC_SM/NC

BD16

VCC_SM/NC

BB21

VCC_SM/NC

AW16

VCC_SM/NC

AW13

VCC_SM/NC

AT13

VCC_SM/NC

Y26

VCC_AXG

AE25

VCC_AXG

AB25

VCC_AXG

AA25

VCC_AXG

AE24

VCC_AXG

AC24

VCC_AXG

AA24

VCC_AXG

Y24

VCC_AXG

AE23

VCC_AXG

AC23

VCC_AXG

AB23

VCC_AXG

AA23

VCC_AXG

AJ21

VCC_AXG

AG21

VCC_AXG

AE21

VCC_AXG

AC21

VCC_AXG

AA21

VCC_AXG

Y21

VCC_AXG

AH20

VCC_AXG

AF20

VCC_AXG

AE20

VCC_AXG

AC20

VCC_AXG

AB20

VCC_AXG

AA20

VCC_AXG

T17

VCC_AXG

T16

VCC_AXG

AM15

VCC_AXG

AL15

VCC_AXG

AE15

VCC_AXG

AJ15

VCC_AXG

AH15

VCC_AXG

AG15

VCC_AXG

AF15

VCC_AXG

AB15

VCC_AXG

AA15

VCC_AXG

Y15

VCC_AXG

V15

VCC_AXG

U15

VCC_AXG

AN14

VCC_AXG

AM14

VCC_AXG

U14

VCC_AXG

T14

VCC_AXG

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC GFX NCTF

VCC GFX NCTF

7 OF 10

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

VCC SM LF

VCC SM LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCC_GFXCORE

VCC_GFXCORE

SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH

12

TC7

TC7

Do Not Stuff

Do Not Stuff

DY

DY

12

12

C93

C93

C378

C378

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C122

C122

C109

C109

Do Not Stuff

Do Not Stuff

DY

DY

Place on the Edge Coupling CAP

12

12

C78

C78

C72

C72

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

place near Cantiga

http://laptop-motherboard-schematic.blogspot.com/

5

4

1D05V_S0

12

C92

C92

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

FOR VCC SM

C71

C71

C75

C75

12

12

Do Not Stuff

Do Not Stuff

DY

DY

12

12

C102

C102

C55

C55

SCD47U16V3ZY-3GP

SCD47U16V3ZY-3GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

12

C137

C137

DY

DY

C66

C66

12

Do Not Stuff

Do Not Stuff

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

Place on the Edge

12

C58

C58

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

3

12

12

C103

C103

Do Not Stuff

Do Not Stuff

12

C56

C56
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

FOR VCC CORE

12

C111

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C111

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C95

C95

Coupling CAP 370 mils from the Edge

Do Not Stuff

Do Not Stuff

DY

DY

12

C125

C125

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C91

C91
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C130

C130

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

Coupling CAP

12

C114

C114

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_S3

12

C98

C98

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

C110

C110

12

12

C105

C105

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C81

C81

DY

DY

1 2

Do Not Stuff

Do Not Stuff

12

Do Not Stuff

Do Not Stuff

G5

G5

2

C121

C121

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VCC_GMCH_35

6 OF 10

NB1F

NB1F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

VCC CORE

VCC CORE

POWER

POWER

Cantiga (4 of 6)

Cantiga (4 of 6)

Cantiga (4 of 6)

SM30

SM30

SM30

6 OF 10

1D05V_S0

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

VCC NCTF

VCC NCTF

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

of

945Monday, October 27, 2008

945Monday, October 27, 2008

945Monday, October 27, 2008

1

SA

SA

SA

5

5V_S0

EC19

EC19

12

SC1U16V3ZY-GP

SC1U16V3ZY-GP

D D

1D05V_S0

1D05V_S0

C C

R35

R35
Do Not Stuff

Do Not Stuff

1 2

SBK160808T-100Y-N-GP

SBK160808T-100Y-N-GP

1 2

L14

L14

120ohm 100MHz

SBK160808T-121Y-N-GP

SBK160808T-121Y-N-GP

1 2

L12

L12

120ohm 100MHz

1D05V_S0

B B

1 2

FCM1608CF-221T02-GP

FCM1608CF-221T02-GP

220ohm 100MHz

1D5V_S0

1 2

Do Not Stuff

Do Not Stuff

A A

180ohm 100MHz

http://laptop-motherboard-schematic.blogspot.com/

Imax = 300 mA

U42

U42

1

VIN

2

GND
EN3NC#4

RT9198-33PBR-GP

RT9198-33PBR-GP

74.09198.G7F

74.09198.G7F

2nd = 74.09198.G7F

2nd = 74.09198.G7F

65mA

R336

R336

12

0R3-0-U-GP

0R3-0-U-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

65mA

R335

R335

12

C427

0R3-0-U-GP

0R3-0-U-GP

L16

L16

R68

R68

L1

L1

1 2

PBY160808T-181Y-GP

PBY160808T-181Y-GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

C427

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D05V_SUS_MCH_PLL2

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C144

C144

3D3V_S0_DAC

5

VOUT

4

12

C430

C430

C413

C413

C403

C403

1D5VRUN_TVDAC

C153

C153
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

M_VCCA_HPLL

12

DY

DY

M_VCCA_MPLL

12

1D05V_RUN_PEGPLL

12

C120

C120
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

5

DY

DY

DY

DY

12

12

C443

C443

12

EC17

EC17

SC1U16V3ZY-GP

SC1U16V3ZY-GP

12

M_VCCA_DPLLA

12

C431

C431

Do Not Stuff

Do Not Stuff

M_VCCA_DPLLB

12

C428

C428
Do Not Stuff

Do Not Stuff

24mA

C412

C412
Do Not Stuff

Do Not Stuff

139.2mA

12

C402

C402
Do Not Stuff

Do Not Stuff

DY

DY

35mA

12

C151

C151
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5VRUN_QDAC

C143

C143
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

100mA

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_S0_DAC

R76

R76
0R3-0-U-GP

0R3-0-U-GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

3D3V_S0_DAC

R348

R348

1 2

HFB1608VF-102-GP

HFB1608VF-102-GP

68.00331.011

68.00331.011

1D5V_S0

1D05V_S0

C76

C76

Do Not Stuff

Do Not Stuff

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D05V_SUS_MCH_PLL2

12

C107

C107

4

12

C159

C159

5mA

12

C441

C441
SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1D8V_TXLVDS_S0

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

R36

R36

1 2

Do Not Stuff

Do Not Stuff

12

DY

DY

1D05V_S0

12

C82

C82

3D3V_S0_DAC

1 2

157.2mA

1D8V_S0

30mA

4

12

C88

C88

C83

C83

C149

C149

12

DY

DY

12

DY

DY

1 2

0R2J-2-GP

0R2J-2-GP

R346

R346
Do Not Stuff

Do Not Stuff

12

12

VCCA_PEG_BG

12

C117

C117
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

R349

R349

50mA

R53

R53

1 2

0R2J-2-GP

0R2J-2-GP

C152

C152

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_CRTDAC_S0

C158

C158
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

M_VCCA_DAC_BG

M_VCCA_DPLLA
M_VCCA_DPLLB
M_VCCA_HPLL
M_VCCA_MPLL

10mA

1D05V_RUN_PEGPLL

750mA

12

C96

C96
Do Not Stuff

Do Not Stuff

DY

DY

38mA

12

C90

C90
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5VRUN_TVDAC
1D5VRUN_QDAC

1D05V_RUN_PEGPLL

12

C124

C124
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D8V_SUS_DLVDS

12

50mA

79mA

VCC_HDA

12

C142

C142
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

NB1H

NB1H

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

3

3

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

A CK

A CK

TV

TV

HDA

HDA

D TV/CRT

D TV/CRT

LVDS

LVDS

AXF

AXF

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

SM CK

SM CK

VCC_TX_LVDS

HV

HV

PEG

PEG

DMI

DMI

VTTLF

VTTLF

8 OF 10

8 OF 10

VTT

VTT

VCC_AXF
VCC_AXF
VCC_AXF

VCC_HV
VCC_HV
VCC_HV

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF
VTTLF
VTTLF

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47
C35

B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

106mA

VTTLF1
VTTLF2
VTTLF3

2

2

12

C136

C136

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

322mA

1D8V_TXLVDS_S0

3D3V_HV_S0

DY

DY

C415

C415

1

1

1

1

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

2

2

2

12

12

C138

C138

C139

C139

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

12

C157

C157

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C70

C70

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

1782mA

12

C123

C123

Do Not Stuff

Do Not Stuff

456mA

DY

DY

C438

C438

C147

C147

1

1

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

2

2

2

1

1D05V_S0

852mA73mA

12

1

1

C146

C146

C127

C127

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD47U6D3V2KX-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

1D05V_S0

C442

C442
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SCD47U6D3V2KX-GP

2

2

D23

D23

1

BAT54-5-GP

BAT54-5-GP

3

2nd = 83.BAT54.D81

2nd = 83.BAT54.D81

1D05V_S0

150mA

R275

R275

1 2

1R2F-GP

1R2F-GP

80mA

12

C148

C148

1D05V_S0

12

12

C106

C106

12

C421

C126

C126
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Do Not Stuff

Do Not Stuff

C421

DY

DY

Do Not Stuff

Do Not Stuff

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C145

C145
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D05V_HV_S0

2

1D5V_S3

1D5V_SUS_SM_CK_RC

12

C150

C150

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C424

C424

DY

DY

Do Not Stuff

Do Not Stuff

C399

C399

1014

3D3V_S0 3D3V_HV_S0

R350

R350

12

1 2

Do Not Stuff

Do Not Stuff

10R2J-2-GP

10R2J-2-GP

C368

C368

1 2

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D8V_S0

R50

R50
0R3-0-U-GP

0R3-0-U-GP

12

1D05V_S0

12

C407

C407
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (5 of 6)

Cantiga (5 of 6)

Cantiga (5 of 6)

SM30

SM30

SM30

1

R345

R345

C440

C440

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SA

SA

10 45Monday, October 27, 2008

10 45Monday, October 27, 2008

10 45Monday, October 27, 2008

SA

5

NB1I

NB1I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

VSS

AD47

VSS

AB47

VSS

D D

C C

B B

A A

http://laptop-motherboard-schematic.blogspot.com/

5

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

VSS

VSS

9 OF 10

9 OF 10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

4

4

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

10 OF 10

NB1J

NB1J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

M17

H17

C17
BA16
AU16

AN16

N16

K16

G16

E16
BG15
AC15

W15

A15
BG14
AA14

C14
BG13
BC13
BA13

AN13

AJ13

AE13

N13

L13

G13

E13

BF12

AV12

AT12
AM12
AA12

J12

A12
BD11
BB11
AY11
AN11
AH11

Y11

N11

G11

C11
BG10
AV10

AT10

AJ10
AE10
AA10

M10

BF9
BC9
AN9

AM9

AD9

G9

B9
BH8
BB8
AV8
AT8

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

3

VSS
VSS
VSS
VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

NCTF_VSS_SCB#BH48

NCTF_VSS_SCB#BH1

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

NCTF TEST PIN:

A3,C1,A48,BH1,BH48

VSS SCB

VSS SCB

10 OF 10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS NCTF

VSS NCTF

VSS_NCTF
VSS_NCTF

NCTF_VSS_SCB#A48

NCTF_VSS_SCB#C1

NCTF_VSS_SCB#A3

NC#E1
NC#D2
NC#C3
NC#B4
NC#A5

NC#A6
NC#A43
NC#A44
NC#B45
NC#C46

NC

NC

NC#D47
NC#B47
NC#A46

NC#F48
NC#E48
NC#C48
NC#B48

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

TP153 Do Not StuffTP153 Do Not Stuff

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Cantiga (6 of 6)

Cantiga (6 of 6)

Cantiga (6 of 6)

SM30

SM30

SM30

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SA

SA

11 45Saturday, October 18, 2008

11 45Saturday, October 18, 2008

11 45Saturday, October 18, 2008

1

SA

A

Κ

M_A_A[14..0]8

DDR3 SOCKET_1

4 4

M_A_BS#28
M_A_BS#08

M_A_BS#18

M_A_DQ[63..0]8

3 3

Layout NoteΚNear Pin 126

2 2

1 1

DDR_VREF_S3

12

12

C38

C38

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C40

Layout Note

DDR_VREF_S3

C49

C49

Near Pin 1

12

12

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C40
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C50

C50
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

DDR_VREF_S3

DDR3_DRAMRST#7,13

12

http://laptop-motherboard-schematic.blogspot.com/

A

TP20TP20

M_ODT07
M_ODT17

DDR_VREF_S3
DDR_VREF_S3

12

C54

C54

C37

C37

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

B

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_A15

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

B

DM1

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-36-GP

DDR3-204P-36-GP

62.10017.M61

62.10017.M61

High 6mm

RAS#

WE#

CAS#
CS0#

CS1#
CKE0

CKE1

CK0#

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA

EVENT#
VDDSPD

NC#77

NC#122

NC#125/TEST

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C

NP1

NP1

NP2

NP2

110
113
115

114
121

73
74

101

CK0

103
102

CK1

104

M_A_DM0

11

M_A_DM1M_A_DM1

28

M_A_DM2M_A_DM2

46

M_A_DM3M_A_DM3

63

M_A_DM4M_A_DM4

136

M_A_DM5M_A_DM5

153

M_A_DM6M_A_DM6

170

M_A_DM7M_A_DM7

187

SMBD_ICH

200

SMBC_ICH

202

SCL

198
199

DDRA_SA0

197

SA0

DDRA_SA1

201

SA1

77
122

1D5V_S3_DDR

125
75

76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

M_A_RAS# 8
M_A_WE# 8
M_A_CAS# 8

M_CS0# 7
M_CS1# 7

M_CKE0 7
M_CKE1 7

M_CLK_DDR0 7
M_CLK_DDR#0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

SMBD_ICH 3,13,21
SMBC_ICH 3,13,21

PM_EXTTS#0 7,13

RN3

RN3

2 3
1

SRN10KJ-5-GP

SRN10KJ-5-GP

1D5V_S3

R14

R14

1 2

D02R6F-GP

D02R6F-GP

C

M_A_DM[7..0] 8

4

1D5V_S3_DDR

1007

3D3V_S0_VDDSPD1

12

12

C51

C51

C44

C44

Do Not Stuff

Do Not Stuff

DY

DY

DY

DY

12

12

C43

C43

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C47

C47

12

C42

C42

C52

C52

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C48

C48

R244

R244

1 2

D01R3J-L-GP

D01R3J-L-GP

Do Not Stuff

Do Not Stuff

12

C41

C41

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

C39

C39

DY

DY

D

3D3V_S0

12

C45

C45

Do Not Stuff

Do Not Stuff

DY

DY

C46

C46

Do Not Stuff

Do Not Stuff

12

DY

DY

D

1014

12

C53

C53

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

DY

DY

Do Not Stuff

Do Not Stuff

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

DDR3 Socket

DDR3 Socket

DDR3 Socket

SM30

SM30

SM30

E

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

12 45Monday, October 27, 2008

12 45Monday, October 27, 2008

12 45Monday, October 27, 2008

E

SA

SA

SA

A

DDR3 SOCKET_2

4 4

3 3

Layout NoteΚNear Pin 126

DDR_VREF_S3

2 2

Layout NoteΚNear Pin 1

DDR_VREF_S3

1 1

12

12

C19

C19

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C18

C18
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

12

C28

C28

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C30

C30
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

M_B_A[14..0]8

M_B_DQ[63..0]8

M_B_DQS#[7..0]8

M_B_DQS[7..0]8

DDR_VREF_S3

M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_A15

TP19TP19

M_B_BS#28
M_B_BS#08

M_B_BS#18

DDR3_DRAMRST#7,12

12

C36

C36

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_ODT27
M_ODT37

DDR_VREF_S3
DDR_VREF_S3

12

C23

C23

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8

M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

http://laptop-motherboard-schematic.blogspot.com/

A

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9

B

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

62.10017.M71

62.10017.M71

B

DM2

DM2

DDR3-204P-37-GP

DDR3-204P-37-GP

High 6mm

RAS#

WE#

CAS#

CS0#
CS1#

CKE0
CKE1

CK0#

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA

EVENT#
VDDSPD

NC#1
NC#2

NC#/TEST

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

C

NP1

NP1

NP2

NP2

110
113
115

114
121

73
74

101

CK0

103
102

CK1

104

M_B_DM0

11

M_B_DM1

28

M_B_DM2

46

M_B_DM3

63

M_B_DM4

136

M_B_DM5

153

M_B_DM6

170

M_B_DM7

187
200

202

SCL

198
199

DDRB_SA0

197

SA0

DDRB_SA1

201

SA1

77
122

1D5V_S3_DDR

125
75

76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

PM_EXTTS#0 7,12

10KR2J-3-GP

10KR2J-3-GP

R15

R15
R16

R16

10KR2J-3-GP

10KR2J-3-GP

1D5V_S3

1 2

M_B_RAS# 8
M_B_WE# 8
M_B_CAS# 8

M_CS2# 7
M_CS3# 7

M_CKE2 7
M_CKE3 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

M_B_DM[7..0] 8

SMBD_ICH 3,12,21
SMBC_ICH 3,12,21

12
12

1D5V_S3_DDR

R13

R13
D02R6F-GP

D02R6F-GP

3D3V_S0_VDDSPD2

DY

DY

12

1007

C

3D3V_S0

R243

R243

1 2

D01R3J-L-GP

D01R3J-L-GP

DY

DY

12

C35

C35

C31

C31

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

12

12

12

12

12

C27

C27

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C32

C32

DY

DY

C26

C26

C29

C29

Do Not Stuff

Do Not Stuff

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C33

C33

Do Not Stuff

Do Not Stuff

DY

DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C21

C21

C20

C20

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

12

C16

C16

C17

C17

D

E

1014

DY

DY

12

12

C22

C22

TC2

Do Not Stuff

Do Not Stuff

TC2

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

D

Date: Sheet

DDR3 Termination Resistor

DDR3 Termination Resistor

DDR3 Termination Resistor

Taipei Hsien 221, Taiwan, R.O.C.

SM30

SM30

SM30

E

SA

SA

SA

of

13 45Monday, October 27, 2008

13 45Monday, October 27, 2008

13 45Monday, October 27, 2008

5

4

3

2

1

D D

C C

B B

SW-TACT-172-GP

SW-TACT-172-GP

62.40012.101

62.40012.101

Cover Up Switch

HALL1

HALL1

5

1
2

3
4

6

ETY-CON4-25-GP

ETY-CON4-25-GP

20.F1261.004

1016

TOUCH_BTN1

TOUCH_BTN1

1

2 4

20.F1261.004

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

74.00268.A7B

74.00268.C7B

3
5

TOUCH_BTN#_1

EC40

EC40

3D3V_AUX_S5

1 2

3D3V_S0

12

R356

R356
10KR2J-3-GP

10KR2J-3-GP

R355

R355

470R2J-2-GP

470R2J-2-GP

12

R253

R253
10KR2J-3-GP

10KR2J-3-GP

Do Not Stuff

Do Not Stuff

SW-TACT-172-GP

SW-TACT-172-GP

62.40012.101

62.40012.101

12

12

DY

DY

LID_CLOSE#

EC39

EC39

LEFT_BTN1

LEFT_BTN1

1

2 4

TP_LOCK_BTN# 33

C447

C447
Do Not Stuff

Do Not Stuff

1 2

DY

DY

3
5

1008

LID_CLOSE# 33

1

2 4

SW-TACT-172-GP

SW-TACT-172-GP

62.40012.101

62.40012.101

1

2 4

SW-TACT-172-GP

SW-TACT-172-GP

62.40012.101

62.40012.101

KBC_PWRBTN#_CN

PWR1

PWR1

3
5

RIGHT_BTN1

RIGHT_BTN1

3

TP_RIGHT 33TP_LEFT 33

5

KBC_PWRBTN#_CN

3D3V_AUX_S5

12

R320

R320
10KR2J-3-GP

10KR2J-3-GP

A A

http://laptop-motherboard-schematic.blogspot.com/

5

KBC_PWRBTN#_CN

KBC_PWRBTN#_CN

4

R322

R322

470R2J-2-GP

470R2J-2-GP

12

12

KBC_PWRBTN# 33

C400

C400
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

D18

D18

3

Do Not Stuff

Do Not Stuff

3

3D3V_AUX_S5

2

DY

DY

1

2

UMA 2nd

UMA 2nd

UMA 2nd

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

SWITCH / Button

SWITCH / Button

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

SWITCH / Button

SM30

SM30

SM30

1

14 45Monday, October 27, 2008

14 45Monday, October 27, 2008

14 45Monday, October 27, 2008

SA

SA

SA