3Com 3C505 Developers Guide

D

E

EVE

THE

LOP

R

LIN

3 C 5 0 5

E R I S

X

P L U S

G U

IDE

Revision

3Com

May 2.1,

3.0

Corporation

1986

PREFACE

This

document engineers will the

talk card.

to

microcomputer through

User's

the

Manual

Intel).

The

CH1~PTER

CHAPTER 2

APPENDIX A

manual

1

CHAPTER 3

who

the The

Intel

is

intended

will

3C505,

user

systems.

80186

before

divided

HARDWARE

Provides system

HARDWARE

Describes control, 3C505.

COMMAND

Describes level

80186

Provides configure

for

either

is

be

or

software

expected

It

is

Data

Sheet

beginning

into

the

EXTERNAL

a

description

resources

INTERFACE

the configure,

INTERFACE

the

interface

PERIPHERAL

the

values

the

80186

use

writing

by

application

that

to

have

recommended

and

the

(they

following

REFERENCE

and

functional

SPECIFICATION

chapters:

of

the

programmable

and

SPECIFICATION

function

software

CONTROL

used

and

supplied

BLOCK

in

internal

sophisticated

software will a

are

actually strong that Intel

background

the

Lan

available

SPECIFICATION

3C505

architecture,

operation.

registers

communicate

use

of

with

PROGRAMMING

the

3C505

resources.

software

reside

user

browse

Components

through

(ERS)

used with

the

command card.

firmware

that

on in

to

the

to

APPENDIX B

APPENDIX C

APPENDIX E

APPENDIX F

APPENDIX G

82586

Provides

configure

3CSOS DIAGNOSTIC

Describes

utility

3D

Describes

mode

running

3C50S

Describes accompanies

REVISION

Describes

REVISION

Describes

CONFIGURATION

the the

the

program.

DEBUGGER

a

host

of

the

on

the

DEVELOPER'S

the

2.0

changes

3.0

changes

values

82586.

3C505

card.

ROM

used

operation

program

to

assist

SOFTWARE

contents developer's

made

in

by

the

of

the

that

uses

in

DISKETTE

of

the

kit.

Revision

3C505

firmware

3C505

a

special

debugging

diskette

2.0

ROM

3.0

ROM

to

diagnostic

debug

programs

that

code.

TABLE

OF

CONTENTS

CHAPTER 1 -

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.S

1.9

1.10

1.11

1.12

1.13

1.14

1.15

HARDWARE

Introduction Resources Architecture Address

1.3.1

1.3.2

1.3.3 80186 82586 Network

1.6.1

1.6.2

1.6.3 Adapter Adapter

Maps Adapter Adapter

Host Microprocessor Ethernet

Interface

82586 8023 Transceiver

Firmware

RAM

Host-Adapter

1.9.1

1.9.2

1~9.3

1.9.4

1.9.5 Adapter

1.10.1

1.10.2 Host

Command Data Data DMA Status

Interrupts

Internal External

Interrupts Resetting Ethernet

LED

Indicators

Host

Address

ROM

EXTERNAL

I/O

memory

I/O

Coprocessor

Serial

Manchester

Interface

Register Register Register

Transfers

Flags

Interrupts Interrupts

the

Adapter

REFERENCE

map

Interface

ROM

configuration

map

Converter

SPECIFICATION

Page

1

1 1

3

3 3

4 4

5 5 5 5

6

9 9

9

10

11

12 13 13 13

14

15 15 15 16

#

CHAPTER 2 -

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

HARDWARE

Introduction Conunand

Data Host Host Host Adapter Adapter

Register Register Control status Aux

Control

status

INTERFACE

Register

DMA

Register

SPECIFICATION

Register

17

1S

18 19 21 23 23 25

CHAPTER 3 -

COMMAND

INTERFACE SPECIFICATION

LIST

3.0

3.1

Introduction Primary

3.1.1

3.1.2

3.1.3

3.2

PCB Commands

3.2.1

3.2.2

3.3

System

3.3.1

3.3.2,

3.3.3

3.3.4

3.3.5

3.3.6

3.3.7

3.3.8

3.3.9

OF FIGURES

Fiqure Figure

Command status Host Adapter

Host 3C505 ROM

Utilities Host Network

Flag

to

I/O

Block

Adapter to

Host

3C505

Host support:

I/O Configuration/S\ Timer Download

Support:

Program PCB Command Packet

Idle

PCB

1-1:

1-2:

Processor

Vector:

Enqueue

3C505 DRAM

Elock

Refresh

structure

Usage

for

PCB

Transfer Request Request

PCB

Formats

PCB

Formats INT

S~·;,>,\:i"rt~

~lS.

INT

83H

Support:

Processor:

vector:

INT

87H

Vector:

or

SOH

INT

INT 82H

INT 85H

INT

8SH

SlH

INT

Diagram

Response

84H

86H

28 28

30 30 31 32 32 37 41 41 44 45

47 48 49 50 51 51

2

8

APPENDIX

APPENDIX APPENDIX APPENDIX

A~PENDI:X

APPENDIX APPENDIX

A B -

C -

D -

E 3C50S" DEVERLOPER' S

F -

80186

82586

3CSOS DIAGNOSTIC

3D

REVISION

G -

REVISION

PERIPHERAL CONFIGURATION

DEBUGGER

2.0

3.0

CONTROL

ROM ROM

BLOCK

SOFTWARE

PROGRAMMING

DISKETTE '

52

54 55

60

65 68

72

CHAPTER

1

1.0

The

adapter bit bytes highly particularly workstation

1.1

INTRODUCTION

EtherLink

for

microprocessor,

of

RESOURCES

• 8 Mhz

*

82586

*

16K

•

128K

HARDWARE

Plus,

IBM

PCs

user

integrated

applications.

to

RAM,

well-suited

80186

multi-packet

128K

to

512K

EXTERNAL

3C505,

and

16

bytes

compatibles.

an

82586

a

high

on-board

bit

EPROM

bytes

REFERENCE

is

a

high

Ethernet

speed

for

microprocessor buffer

packet

16

bit transceiver. server

Ethernet

buffer/program

SPECIFICATION

performance

It

consists

coprocessor,

host

and

coprocessor

interface, high

no

wait

The

memory

Ethernet

of

an

up

to

3C505

performance

states

80186

512K

and

16

a

is

*

8/16

*

20

*

On-board

* 8K

1.2

The Ethernet of

initialization, 128K well 82586 network functions The transfers

flexible, allows

ARCHITECTURE 3C505

on-board

RAM, as

offloading

performs

diagnostics.

host

ample

bit

byte

bytes

is

I/O

expandable

and,

interface as

yet

FIFO

a

channel

in

well

simple,

processing

host

"Thin

host

firmware

program

all

interface

to

EPROM

16

bit

and

to

of

application Data

a

typical

supports

as

Ethernet"

- PIO

maximize

microcomputer

an

contain download, 512K,

Link

It

performs

environment,

programmed allowing power,

host/adapter transceiver/802.3

IBM

PC

allows

programs

functions,

high

for

even

or

DMA

with

AT

interface.

software

and

diagnostic

for

protocol

from

as

all

packet

will

speed,

I/O.

easy

on a heavily

The programming.

data

a

high

that

the

well

buffer

not

8

"drop"

or

interface

loaded

transfer

connector

performance

The

software.

processing host

16

16K

supports',

PC.

as

powerful:

management

packets.

bit,

is The network.

bytes

The

a.s

The

DMA

very

8 Mhz

1

8

88UJ6

..,An

tfhs

NO

stAtES

I

--

HOLD

INt

CA

ACt:

0259G

-

ETHEPNET

COPROCESSOR

-

9123

t1ttNCHE'TER

COllEC

XCUR

7996

AND

POIIER

SUPPLY

082.3

nn

COHHECTOR

H

EnfERtfET

COHHECIDR

1291(

DRAH

I I

I

N

3941C

:

OPTIOtt

I

RNt

, I

, ,

,

:

,

~-------~

-------

..................................................................... _ .............................

· .

~--~~.--

FIGURE

OCSftS BLOCK 01

REGISTERS REl1lStERS

1-1

· .

ADAPTF.R

COHTROL

AHO

S"MlUS

ncR,,"

............

16-120X

EPROH

ETHERHF.T

ADDRESS

UOST

COHTROL

AHO

STA'TUS

:

r---~.--~--~~--~

•.•••••.•••••••••.••••.•..•

1

'"A

REQ

DATA

REGIST'Dt

FIFO

28

IYtES?

•

..,ORDt

!

..•••.... _ .................................................................

~

11ft,.

REO

9

OR

16

BIT

HOST 1 HTJ:RFACE

DATA

IHT

.

ADAPTER

COHttAHD

REGISTER

j

~

PAm

HOST

COt1HAtfO

REGISTER

~

INT

OX

EPJOt

~

r

1.3

ADDRESS

MAPS

1.3.1

HEX

ADAPTER

Address

o

100 102 102 102 104 180-18F FFOO-FFFF

1.3.2

HEX

OOOOO-lFFFF 20000-3FFFF 40000-5FFFF 60000-7FFFF FCOOO-FFFFF

EOOOO-FFFFF

ADAPTER

Address

X/O

MAP

Byte/Word

NA

(see

Low High

High Word

Wo-:r:d

MEMORY

Low

Byte

Byte Byte

Byte

MAP

text)

Read

write

Description 82586

Adapter Adapter Adapter Adapter Data Ethernet

Peripheral

Description

128K 128K 128K 128K 16K 128K

(If

Bytes Bytes Bytes Bytes

Bytes

27512s

CA

Command Control status

Control

Register

address

system option option option

system

are

Register Register

Register

Control

RAM: RAM: RAM: RAM:

ROM

installed)

Register

(6

Bytes)

Block

Bank Bank Bank Bank

*

1 2 3 4

*

Address

Initialization

1.3.3

HEX

Address

Base Base Base Base Base

**

***

address address Address address address

The address the

The slot

(AT).

HOST

address

card.

Data

lines

Z/O

(factory

+ 0 + 2 + 2 + 4 + 6

which

(PC,

A20-A23

Root

MAP

(300) (302)

(302)

(304)

(306)

is

The

Register

factory

XT,

is

set)

Read write

Read

given set

is

or

of

located

**

as

using

set

a

byte

AT)

3

the

Description

Host Host Host

Data

Host

an

the

base

wide

and

word

82586 at

FFFF6

Command status Control

Register

Control

offset

I/O address

wide

are

from

address

register

ignored

in

system

Register Register Register

Register

the

is

in

a

***

jumpers

300H.

in

an

16

and

I/O

bit

ROM.

base

8

slot

the

on

bit

1.4

80186

MICROPROCESSOR

The

3C505

integrated

interrupt

with The

divider

the

80186

8086.

generates timing. nanoseconds, second.

1.5

The

All

82586

processor

frame

The

reception

82586

communicate

in

system data section

from

1.6,

the

nanoseconds.

uses

controller

All

has

the

Intel

16

bit

processor

on

timing

is

generated

an

80186

with

DMA

transfers

ETHERNET COPROCESSOR

is

a

bus

a

high

resRonsible

and

two

with

RAM;

the

transmission,

interfaces: the

and

network.

Network

8

Mhz

system

80186

chip.

8Mhz

cycles

system

require

performance,

for

80186

a

serial

Interface.

Microprocessor.

with

3

timers,

The

by

a 16Mhz

clock

output

are

memory

2

all

network

error

a

parallel

and

to

interface

The

serial

The

clock

and

80186

which

4

clock bandwidth bus

cycles,

intelligent

related logging,

retrieve

to

interface

82586

all

2

DMA

is

software

crystal.

is

cycles

of

system

and

transmit bus

bus

This

is

channels,

compatible

An

used

for

long,

2

Megawords

or

1

microsecond.

communications

tasks,

and

diagnostics.

bus

store

interface

packet

and

is

described

interface

cycles

a

highly

and

internal

system

or

500 per

including

data

receive

operates are

500

an

to

in

The using

detail only

80186

the

in

one

of interprocessor can

initiate

Attention)

00

will

cause initiates

The

82586

instances:

1.

2.

3.

When

of

To To To

read

transmit receive

receiving

the

system execution

The state

in

Adapter

the

Adapter

un.til

and

the

HOLD/HOLDA

the

Intel

the

processors

communications

a

transaction

input

a

transaction can

to

an

active

require

or

update a

packet.

a

packet.

or

transmitting,

bandwidth,

and

DMA

(80186)

transfers,

Control

this

bit

82586

protocol.

Lan

Components

the

82586. transition

by

the

can

reset

Register.

is

cleared.

operate

This

can

use

are

asserting

bus

SCB

or

although

the

in

a

configuration User's the

via

by

asserting

A

read

on

the

to

access

(System

the

715

82586

The

shared

Manual.

system

the

system

or

the

CA

80186

system

Control

82586

uses

KW/second.

slowed,

by

asserting

82586

bus

the

write

input.

INT1

Block).

approximately

do

remains

configuration

is

described

In

this

at

a

time.

RAM.

The

CA

to

I/O

The

input.

RAM.

Thus

not

halt. the

in

mode,

80186

(Channel

location

82586

in

three

program

R586

the

reset

in

All

35%

bit

4

~.6

NETWORK

INTERFACE

The the

3C505

Intel Converter, Transceiver

~.6.1

The parallel reception. the serializes destination

outputs

link

standard. preamble

station

so,

in

the

1.6.2

The

decoding

transceiver.

clocks

the

milliseconds,

approximately

network

82586 and IC.

82586

Adapter

the

management

and

address

the

serial

Adapter

8023

of

to

the

IC

prevents

interface

LAN

controller,

an

perfo~s

convers~on

During RAM the

bit

on-board

SERIAL INTERFACE

all

transmit,

through

data,

fields,

appends

stream.

algorithm

During

compares

bit

to

see stream

reception,

the

if

RAM.

MANCHESTER

is

responsible

the

It

serial

also

82586

CONVERTER

serial

continuous

thus

3lk

limiting

bytes.

consists

the

transceiver

parallel

during

parallel

the

82586

inserts

a

CRC

The

82586 according

destination the

is

converted

for

bit

stream

supplies

interface.

of

the

SEEQ

8023

using

to

serial

packet

data

bus

interface.

the

preamble,

field

also

the

82586

address

frame

should

into

the

Manchester

between

the

transmit

transmission

the

maximum

serial

Manchester

the

and

transmission

is

retrieved

to

the performs to

the strips

field

be

received.

bytes

the

A

watchdog

of

more

packet

interface

AMD

serial

The

source

"packet",

the

CSMA/CD

IEEE

off with

and

encoding 82586

and

and receive

timer

than size

on

Code

7996

to

and

from

82586

and and

802.3

the the

If

stored

and the

on 25 to

For

diagnostic

mode"

the

whereby

receive transceiver Loopback 3C505

~.6.3

The to

Hardware

TRANSCEIVER

3C505

the necessary detection.

bit

onboard

"Thin

signal

purposes, the

transmitted

section. problems. in

the

Adapter

Interface

transceiver

Ethernet"

the

8023

This

Enable

Control

Specification,

coax

conditioning

5

can

be

data

is

useful

loopback

Register.

physically

cable.

as

placed

internally

for

by

Chapter

connects

It

well

in

"loopback

routed

isolating

clearing

Refer

2.

the

performs

as

collision

the

to

the

3C505

the

to

The

user

network

3CI02.

and

enable card. must The

EtherLink

3C505,

can

through

If

so,

To

be

moved

illustrates

the

do

also

an

the

15

so,

from

Plust

connect external

user

pin the

must

connecter transceiver

the

Installation

this

procedure.

BNC

the

3C505

transceiver

disable

on

position

Guide,

to

the the

select

to

a

thick

such

onboard

backplate

plug

the

DIX

included

Ethernet

as

the

transceiver

in

the position.

with

of

3Com

the

card

the

:1,,7

The

2764 27512

ADAPTER

3C505

type ROMs

a maximum

The

3C505 configuration, command

block

Host/Adapter

downloaded

Specification, The

FFFFFH and

to

1.8

The

system

82586.

fetch

ADAPTER

3C505

64K x

if

the

16 installed consists

of installed second

U44,

additional

and

locations

maximum

time "CAS

RAS

of

75

before currently Instruments,

FIRMWARE

contains

ROMs.

for

up

to

address

ROM

access

firmware and interface, I/O,

programs.

Chapter

ROM

128k

The

is

mapped

bytes

82586

initialization

RAM

contains configuration.

for

256K,

four

in

64K x 4

socketed

bank

U46.

U41,

The

U43, access nanoseconds.

RAS

available

and

Mitsubishi.

ROM

16K

bytes

These

128k

DRAM

network

Refer

3,

are

only

128K

384K,

10cations"-U31," must

third

U45,

time

of

refresh",

from

of

ROMs

can

bytes

time

of

performs

refresh.

a

to

for

more

to

address

used)

accesses

root.

bytes

Three

or

DRAMs.

be

additional

and 150 In

Hitachi,

firmware

be

replac~d

of

firmware.

250

nanoseconds

self-test,

It

set

of

interfacing

the

details.

space

and

is

accessible

ROM

of

dynamic

additional

512K

The

bytes

first

soldered

U47.

nanoseconds

addition,

described

NEC,

contained

by

27128,

The

ROMs

or

initialization

also

provides,

functions

and

which execution

3C505 Command

FCOOOH-FFFFFH

to

following

memory

128K

of

RAM

an

organized

banks

memory.

additional

U33,

into

bank

These

below.

must

and

these

U35,

and

locations

be

soldered

devices

maximum RAMs

These

Fujitsu,

in

less.

through

both

82586

bank

U40,

must

parts

Intel,

two

8Kx8,

27256,

must

support

Interface

(EOOOOH-

the

reset

in

can

Each

must

"037'.

have

CAS

access

support

Texas

or

have

and

a

of

80186

a

be

bank

be

The

U42,

into

a

are

The for

system

both partitioning into

the IFFFFH, 5FFFFH,

and

RAM

packet

or Adapter bank

2

bank

is

accessible

buffering protection memory

occupying

4

occupying

to

the

and

program

mechanism

space

0-7FFFFH,

20000-3FFFFH,

60000-7FFFFH.

6

80186

is

used. with bank

and

82586

storage.

bank

3

and No

The

RAM

1

occupying

is

physical

is

mapped

40000-

used

0-

Software

initialization locations Data

loss

initialization To

facilitate the the before that

A

cycle Chip before

To RAM

"CAS

RAMs the

read

Select

increase

refresh,

RAS or

in

RAS

Channel causes

a performs cycle

refreshes programmed initialized,

this The burst

technique,

timer

mode

must

in

will

before

generate

cycle,

all

cycle,

reliability

0

to

DMA

an

cycle I/O

to

generated refresh

perform

and

refresh.

each

bank

occur

procedure

refresh,

RAS"

CAS

before

to banks output

read

the

refresh

the

refresh

and

the

I/O

location

simultaneously.

is

or

3C505

automatically

to

occur

read

two

"stop

will

and

memory

on

continue

refresh

DMA

cannot

two

functions

must

if

To

refresh

be

refresh

depends

3C505

feature

address

internal

RAS

cycle

80H

programmed

write,

and

to

free

firmware

generate every

write

to

locations.

terminal

without

consumes

will

be

only

used.

for

accessed

is

on

the

contains

of

internally

address

will

The

for

this

does

not

the uses

refresh

30

microseconds.

location count"

any

3.3%

produce

proper

the

RAM, every not

refresh

hardware

the

DRAMs. counter

refresh

produce

80186

range.

corrupt

80186

80H.

The

DMA

so CPU of

the one

RAM

256

4

consecutive

milliseconds. performed. technique

which

In

after

increments

the

a

PCSl

NOTE:

RAM

from

Timer

data.

involvement

2

cycles.

Each

Thus

controller

that

refresh,

involvement.

memory

DMA

cycle

operation:

The

used.

utilizes

this

each

mode,

CAS

address.

before

RAS

Peripheral

A

CAS

and

The

DMA

each

timer

cycle

is

DY~

DMA not

once

Using

bandwidth.

so

that

so

in

Upon perform

is

to location is

not

the

installed

power-up,

8

RAM

be

used,

80H)

used,

the

80186

"initialization"

then

will

then

banks

8

initialize

8

reads

of

memory

must

refresh

or

wait

cycles.

cycles

all

writes

will

200

RAM.

to

initialize

microseconds

If

CAS

before

(a

read

If

CAS

before

any

location

the

or

write

RAM.

and

RAS RAS

in

refresh

to

refresh

each

then

I/O

of

7

8 t1HZ

DHA

CPU

CLOCK

DIUIDE

REQUEST

DHA

DIVI~ED

, r

88186

TIHER 2

I"

(15

88186

CHAHHEL

BY

4

2.8

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8

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REFRESH

READ

BE~ORE

DUMMV

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3C5BS

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11'0

FIGURE

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n

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8

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REFRESH

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DUMM~

P.AS

I

11'0

1.9

HOST-ADAPTER

XNTERFACE

The

Host registers: addition,

whare

are configuring. is

found

2. space.

The

Jumpers

1.9.1

The used the the Register

status interrupt

Host

into interrupts

1.9.2

and

the

each

used A

in

the

interface

COMMAND

Command to

Host

transfer and

Command

Registers.

or the

DATA

the

Adapter

Command

side

has

for

detailed

3C505

requires

are

used

REGISTER

Register

the

Register

Full

(ACRF

driven,

Adapter

Command for

more

REGISTER

communicate

Register

a

Control

transfer

bit

Hardware

16

to

position

is

commands

Adapter.

and

Alternately,

so

that

when

the

Register.

information.

level

Interface

locations

a

full

and

The

Empty

HCRF)

an opposing

through

and

the

Register

handshaking

description

Specification,

in

the

base

duplex

small

amounts

register

(ACRE

bits

the

and in

Command

interrupt

side

Refer

two

Data

and

a

of

the

Host

address.

byte-wide

can

HCRE)

the

Host

is

generated

has

to

section

I/O

Register. status and these

I/O

of

data

be

polled and and

Register

loaded

mapped

Register

interface

registers

Chapter address

register

between

using Command Adapter

can

to

a

byte

1.10

In

be

the

on

The high

Data

speed Adapter. the

DIR cleared which set

is

(1), referred in

both

The

Data transfers. Register bit The the

(HRDY

meaning

state

Register The

bit

in

(0),

referred

data

to

an

the

Host

Register

can

and of

bulk

direction

the data

to

transfer

upload.

and

In

polled

be

determined

ARDY)

of

the

DIR

is

a

data

Host

transfer

as

Adapter supports

in

the

Ready

Bit.

half

duplex transfers of

the

Control

is a

data

is

from

The

state

status

both

operation,

by

reading

Host

Bit

20

between

data

transfer

Register.

from

download.

the

of

Registers.

polled

and

Adapter

is

determined

byte

the

Host

Adapter

the

DIR

I/O

the

state Data

FIFO

is

If

the to

If

the

to

bit

status by

designed

Host

and

controlled

DIR

the

Adapter,

DIR

the

Host

can

and

of

DMA the

Register

registers.

its

state

bit bit be

Ready

for the

~y

~s

is

and

read

data Data

and

9

TRANSFER I DIR I

---------1-----1-------1-------1-------------------

PIO

DOWNLOAD

I I 1 1 X 1 REGISTER

1 0 1-------1-------1-------------------

I 1 X 1 1 1 REGISTER

HRDY

I

ARDY

I DESCRIPTION

NOT

FULL

EMPTY

---------1-----1-------1-------1-------------------

PIO

UPLOAD

I 1 1-------1-------1-------------------

I 1 1 I X 1 REGISTER

I X I 1 I REGISTER

NOT NOT

FULL EMPTY

---------1-----1-------1-------1-------------------

To

clear

that

(Flush) used. Register

in the DIR

Careful

Incorrect correctly. enabling bit the FIFO part

changes word

completed

the

Adapter

Bit.

from

Adapter

is

of

REGISTER REGISTER

a

stuck

register

bit

By FIFO

attention

empty. the

a command

in

setting

Ready

and

DMA

download

the

execution

Flag

is

not

can

use

confusing

The

transfers.

has

actually

One

command

DIR

bit

NOT NOT

byte

the

actually

this

should

DIR

to solution

after

block.

of

FULL

EMPTY

from

is

in Host and

resetting

is

forced

bit,

be

must

upload,

block

the

--->

....

->

the

Data

a known

and

Adapter

to

cleared).

regardless

paid

results

be

in

its

When

completed

the

This

changing the

is

to

sequence.

Adapter

indicates

last

command

WRITE

!<Lj:~D

the

in

occur

change

DATA

Register,

empty

Control

the

Host

empty

the

correct

the

has

FLSH

if

download,

DATA

state,

Either of

use

the

must

the

The

accepted that block.

Bit,

state the

of

the

bit state state

make

DIR 3C505

the

or

to the

Register

the

(the

the

Host

state

DIR

is

prior of sure i.e.,

bit

firmware

the

Adapter

not the

only

ensure

FLSH

is Data data

or

of

the

bit.

set

to

DIR

that

the

as

first

has

1.9.3

To FIFO, permitted the bytes where configured does 16

The

installed transfers bit

the

Data

bit

DATA

10

deep,

it

not

slot.

Data

AT

REGISTER CONFIGURATION

Adapter,

words

(AO

Register

or

is

and

need

R7gister

1n

are

DMA

channels

the deep.

and

BHE is

a

16

installed.

no

jumpers

to

know

is

a

16

permitted

Data

are

configured

bit

(5,6,7)

Register

Only

ignored).

FIFO,

The

need

whether

configured

I/O

(AO

and

10

16

as 10

be

it

slot

BHE

can

is

bit

However,

either

words

register

set.

is

installed

as

a of are

be

used.

always

data

an

deep,

is

Also,

16

bit an ignored)

a

16

transfers

to

8

bit depending

automatically

the

in

an

register

AT.

Only

and

bit the

FIFO,

Adapter

8

only

wide

are

Host,

20

on

or

when word

16

a

In

a

PC, configured performs performs performance always

Adapter presence

in

presence. conversion direction indicates

the

transfer

register

XT,

as

byte

word

is

Data of

words,

In

is

because

the

or

an a

to

word

I/O

not

an

Register

because Adapter performed.

presence

8

bit

20

byte

conversion

to reduced even

the

not

number bytes. to Host

of

slot

FIFO

the

in

Ready

the

Host A

Data

bytes.

of

an

to

the

so

Data

8

bit

of

bytes flag An

odd

Adapter

transfers,

byte

cannot

Registe~

AT,

the

Host.

that

Register

systems.

to

(ARDY)

byte will

Data

the

The

the

will

not

get

Ready

Register The 80186 and

Host

register;

indicates

get

know

word

stuck

flag

register

always

Adapter

must

"stuck"

of

to

byte

in

this

(HRDY)

is

the the

its

~.9.4

DMA enabled Since caution PC When same

TRANSFER I

transfers

DMA

the

DMA

TRANSFER

using

the controller

DMA

should

DMAE

channel.

by

the be

bit

DIR

the

Host

DMAE

channel

taken

is

not

is

cleared,

I

HRDY

to

and

bit to

enabled

floats

ensure

I

in

ARDY

from the when

until

another

Host

this

that

the

this

the

I/O

I DESCRIPTION

Data

Control

bit

channel

DMAE

card

Register

Register.

is

cleared,

in

bit

may

is

use

---------1-----1-------1-------1-------------------------

DMA

DOWNLOAD

---------1-----1-------1-------1-------------------------

DMA

tJJ?WAD

I 1 1 I X I

1 0 1-------1-------1-------------------------

1 1 X 1 1 1

1 I X I 1 I

,I

1 i

-----'--'

1 I 1 I X 1

f

'-------

WRITE

READ WRITE

'I

-------------------------

READ

REQUEST

TO

ADAPTER

TO

HOST

ADAPTER

---------1-----1-------1-------1-------------------------

are

the

set.

the

The

3C505 Host TCEN on

~he

Register Enable programming Channel

after

bit

interrupts

Adapter

in

and 1

can

the the

on

the registers

input

be

programmed last Host

for

more

performs 80186

to

DY~

DMA

the

cycle Control

DONE 80186

of

information.

DMA Channell.

internal

to

generate

a

Host

Register.

transfers

interrupt

is

never

to

DMA

Refer

to

Both

are

the

in

an

interrupt

transfer

to

and

a

from

the

controlled

80186. floating

using

the

DMA

to

section

Data

Channel

The state.

the the

by

DY~

Note:

the

independent

while

the uses

the

Adapter

DMA.

Adapter of

one

other

to

use

and

another.

performs

polled

the

DMA. I/O

Host That

and

may

is,

There

the

perform one

may

is

little

3C505

DMA use

polled

reason

firmware

transfers

I/O for

always

The DMA Burst 3C505

DMA Host will

Burst has

DMAE

go

1.

2.

3C505

transfers

(BRST)

will channel to

refresh

then

bit

no

effect

bit

inactive

The The depending

3.

The

occured

1.9.5

The status

ASF3,

and Host

STATOS FLAGS

Host

Flags.

which

directly

has programmed through used

codes,

the

hardware

the

for

and

contains

in

PCs

bit

in

transfer

for

one

its

transfer

is

set,

is

set,

under

entire

Data

Burst

since

and

Adapter

if

single

the

Host

Register

bn

the

bit

another this

the

The

are

programmed

observable

two

by

status

the

Adapter

synchronization,

other

in

assorted

any

hardware where

the

9

bytes/words

host

own

system pause

cycle

DMA

following

DMA

transfer

is

not

last

also

Adapter

by

Flags,

Host

status

way.

to

support

this

Aux

mode

DMA

Register

and

CPU

cycle.

DRAM

9

bytes/words,

will

DMA

request

not is

inp~t

conditions:

is

FIFO

is

direction.

set

and

DMA

pause.

communicate

has

three

by

the

Host HSFl

Control

Register

Register.

command

tasks.

Host

is

supported.

is

then

This

if

necessary.

and

occur.

used.

to

completed temporarily

9

DMA

using

flags,

Adapter

status

and

The

HSF2,

status

execution

They

are

"demand

not

relinquish

will

so

on.

The

ThUS,

the

host

transfers

general

ASF1,

Control

Register.

and

not

decoded

mode"

If

set,

the the the

allow

The Burst

PC

3C505

If

if

the the

bit the

will

full/empty

have

purpose

ASF2,

and

Register

The

which

are observable Flags

are completion

by

12

1.10

ADAPTER

(80186)

INTERRUPTS

The

80186

internal

1.10.1

A

internal software Sheet

1.10.2

There Command

Attention

there

the disabled, the

80186. can

positive

microprocessor

and

external

INTERNAL INTERRUPTS

brief

description

interrupts

generated

for

programming

DMA

This

Timer

An

Timer

cycle

Channel

is of

Interrupt

interrupt

o.

counting

EXTERNAL INTERRUPTS

are

three

Register

(NMI).

is

no

cause

of

the

appropriate

These

be

enabled edge

sources.

1

used a

DMA

The

and

timeouts.

sources

Since need the

for

interrupt.

interrupts

bit

inputs

at

triggered.

in

the

follows.

interrupts.

details.

Done

to

Interrupt

generate

transfer

is

generated

interrupt

of

Full

each

a

corresponding

in

the

never

any

time.

3C505 may

of

how

These

to

external

(INT

interrupt

Except

are

enabled

Interrupt

"float"

the

an

interrupt

or

every

is

0),

All

be

3C505

include

Refer

from

the

10

used

for

interrupts 82586

has

status

for

NMI,

or

Mask

so

that

channels

interrupted

firmware

Timer,

to

the

after Data

millisecond

general

to Int a

(INT1), unique bit

which

disabled

Register

these are

by

both

uses

DMA,

80186

the

Data

last

Register.

from

purpose

the

80186:

channel,

to

indicate

cannot

by

setting in

channels

programmed

and

be

the

Command

I£

enabled, when This

Command register. status from

82586

This

82586.

the

.

Refer

82586

Register

the condition

Register

bit

the

Command

INT

(INT1)

input

If

after

to

the

an

Host

The

are

is

enabled, 82586

Full

interrupt

loads

is

also

Full)

Command

cleared Register

tied

the

directly SCB

data

13

(INTO)

will

a

byte

reflected

bit Register when

the

has sheet

be

in

the

to

80186

been

for

generated

the

command by the Full

80186

the

INT will modified

more

to

the

HCRF

adapter

interrupt

reads

output

be

interrupted

by

the

information.

the

80186

register.

(Host

status

the

byte

on

82586

and

the

by

.

Attention

When an a

the NMI "soft"

state positive brought

(NMI)

ATTN

is

generated

after

edge

from

bit

reset

low

to

an

interface

triggered

to

is

set

in

the

bring

high

in

80186.

the

error and

to

the

adapter

force

Host

occurs.

the

Control

This

back

ATTN

NMI.

NMI

to The

bit

Register,

is

used

a

known

NMI

must

as

is

be

1.11

The

HOST

3C505 situations: interrupt

Host

By

Control

after

Register.

enabled,

used

interrupt.

cleared

enable)

Command

By Register, the DMA

Command

should

The when

INTERRUPTS

can

DMA

channel

DMA

setting

Register,

the

to

bit

Register

setting

Adapter Done

be

Command

the

be complete

is

Done

the

last If

the

Done

determine

The

by

disabling in

the an

interrupt

writes

interrupt

Register

used Register

Host

reads

programmed

and

used.

TCEN

cycle

the

(Terminal

an

interrupt

of

Command

bit

if

DMA

Done the

the

Host

Full

CMDE

(Command

a

byte is

Full)

to

determine

Full

the

Command

a

DMA

in

the

a

DMA

interrupt

DMA

Control

will

in

also

bit

interrupt

byte

to

interrupt

Register

Count will transfer

Register

host Done

channel

Register.

Enable) be

generated

the

enabled,

in

the

from

Enable)

be

generated

to

Full

status

was

the

and

using

bit

Command

Host

source

and

ACRF

the

Command

the Full.

bit

or

interrupt

register

source

Done

the

in

the

to

the

Register.

the

ACRF

status

of

the bit

Register.

Host

in

Only

in

the

to

the

from

the

is

should

of

status

bit

DMAE

Host

Control

Host

(Adapter

Register

inte~rupt.

are

cleared

one

Host

when

If

two

PC

Host Data

also

be the are

(DMA

the

Care

must interrupts. interrupt

the turn

PC

the enable both used

3C505

by

channel

PIC

3C505

another

be

taken

If

channel

interrupts

I/O

both

is

when

floated

not off

are

card.

enabling

interrupt

and

also

before

disabled,

sources

can

disabled.

disabling

enabling

14

and

cause

the

disabling

are

spurious

To

prevent

3C505

the

PIC

interrupt

the

disabled,

interrupts

this,

interrupts,

channel.

channel

3C505

the

if

always

and

When

can

be

When

3,4,5,6,7 equivalent channel

installed

can

or

to

9

should

channel

be

used.

in

a

PC,

be

2.

XT, used.

In

or

an

a-bit In

a

AT

this

16-bit

slot, situation,

AT

interrupt

slot,

channel

any

channels

9

interrupt

is

1.12

Note:

firmware

several transition Visually,

1.13

RESETTING

Power Upon

80186 status

Registers Adapter The

both Register.

that

will

ETHERNET

On power

Host

the

the remain

After

performs

seconds.

this

THE

Reset

up,

and

82586

indicate

are

Reset

can

ATTN

This

Host

either

in

the

is

ADDRESS

ADAPTER

the

are

empty,

cleared.

reset

bit

reset

Control

reset

configuration The

indicated

until

of

the

completion

Host

status

3C505 reset,

and

the

and is

adapter

the

similar

Register

the

above

by

is both

ATTN

"hard"

and

of

Flags

LED

put

the

FLSH

to

is

self-test these

#1

in

reset

Command

Host

by

simultaneously

bit

in

the

power

not

affected.

and

FLSH

resets,

tasks from turning

state

state.

and

Data

and

Adapter

the

on

bits

the

routines

is

3

to

off.

Both

Registers

Host

reset

The

are

reset.

adapter

which

indicated

state

the

Control

setting Control

except

Adapter

last by

o.

a

The Adapter byte

1.14

The

LED2 high bit

Adapter

turns

The

I/O

of

the

LED

bits

so

LED

and turned software debug

INDICATORS

that

the

t1

3C505

initialization

Ethernet

space.

six

contains

in

the setting LED

off

may

and

The

consecutive

two

Adapter

the

off.

firmware

at

the

call

status

station

twelve

words

LEDs Control

bit

turns

following conclusion 3C505

indications.

firmware

address

digits

which

turns

this

15

resides

are

starting

are

Register.

the

LED

on

a

hard

of

these

routines

contained

at

location

enabled

The

on

during

reset.

routines.

in

by

and

to

a

PROM

the

LEDs

clearing

the

The

use

in

the

in

the

180H.

LEDl

are

self

Application the

and

active

the

t.est

LED LED

low

is

for

LED

'2

The a 1

visual

stop is

3C505

HZ

blinking,

not

recommended

indicator

CAUTION! When control ROM.

1.

15

A

socket

resides

applications time The

ROM

execute The

space. memory

DMA

access

the

Otherwise

:i}:~ST

ROM

is in

for

these

is

from

ROM

can The address

to

provided

the

such

only

8

base

firmware

rate.

using

LEOs

by

incorrect

Host

as

devices

accessible

bit

ROMs

be

mapped

address

jumpers

this

ROM.

It

that

a

software

3C505 calls

on

memory

BIOS

turns

this

serves

the

that

application

firmware,

to

operation

the

card

extensions.

must

not

to

on

I/O

on

any

for

on

the

Incorrect

as

a card or

hardware

the

for

space.

be the cards.

8K

the

card.

data

LED

on "heartbeat" is

alive.

software

downloaded

firmware

will

an

SK

This

The

greater

Host.

boundary ROM

is The will

or

off

at signal If

error

has

routines

result.

x S

ROM

(2764)

can

maximum

than

Note

in

~50

-

the

programmed

3C505

be

does

read.

approximately

and

the

LED

occurred.

use

this

software

provided

ROM

be

used

address

nanoseconds.

The

PC

AT

Host

using

not

is

should

It

LED.

must

in

which

for

access

will

address

the

support

a

To ON

is

enable

(0)

position.

present,

the

place

ROM,

If the

set

no

jumper

the ROM

Enable

is

present,

should

jumper

in

the

or

on

to off

the

disable

(1)

card

position.

must a

ROM

to

the

which

16

CHAPTER

2

2.0

The

the

3C505

Briefly, Command, duplex

is channel allows Register The

relative

INTRODUCTION

3C505 3C505

processor.

a

half

Host

Hardware

interface

the

Data,

and

used

duplex,

for

efficient

programmed

contains and

Adapter

to

a

base

Command Data status Control Control

AUX

DMA

HARDWARE

Interface registers

Host status,

and

for

command

16-bit

configuration

interface

I/O

Base

I

Host

-----------------------------------1

I 0 I 0 I

I 4 I 4 I

I 2 I 3 I

I 6 I 3 I I

6 I 2 I

I 2 I X I

INTERFACE

3C505

and

control.

wide

bulk

access

address:

Offsets

I

Adapter

specification accessible

communicate

block

FIFO,

data

transfer.

of

state

these

SPECIFICATION

describes

by

the

using

The

Command

transfers.

and

the

flags

registers

I

can-be

The

interface.

and

programmable

in

Access

Read/Write Read/Write Read write Read write

only

The

PC

host

four

Register

Data

used

Control

their

I

* I

I

in

detail

and

registers:

is

Register

with

Register

The

I/O

the

full

a

DMA

status

flags.

space

The

Host Adapter Address

Refer Chapter

architecture. Specification interface

*

The Registers.

base Maps,

to

Host

base

the

1

can

I/O

address

for 3C505

for

in

be

and

address

is

more

a

And

Chapter

programmed.

Adapter

detail.

Hardware more

also

can

fixed

detailed

refer

will

be at

External

3

for

read

17

modified

100

hex.

Reference

explanation

to

the a

the

contents

with

Refer

3C505

description

jumpers,

to

section

Specification of

Command

of

the of

their

while

1.3,

hardware Interface how

own

this

Control

the

in

2.1

COMMAND

REGISTER

+------+------+------+------+------+------+------+------+

I

CMD7 I CMD6 I CMDS I CMD4 I CMD3 I CMD2 I CMD1 I CMDO

I

+------+------+------+------+------+------+------+------+

The

register Host used

2.2

Command and

the

to

read/write

DATA

+------+------+------+------+------+------+-----~+----

I

DR1S

I

Register

used

REGISTER

3C50S.

DR14

for

I

passage

Programmed

this

DR13

(CMDR)

of

register;

I

••••

is

primary

and

DMA

•

•••

a

bidirectional

command

interrupt

is

not

I

DR2 I DR1

blocks

driven

supported.

I

8-bit

between

I/O

can

--+

DRO

I

data

the

be

+------+------+------+------+------+------+------+------+

The

high used

supported. 8-bit

transferred.

appears

transfers

Data speed

to

wide

Register

data

read/write

.

From register.

To

as

a

16-bit

are

supported.

(DR)

transfers.

this

an

8-bit

the

Adapter

wide

is

a

register;

Host,

Only

register

half

DMA

an or

duplex,

or

programmed

interrupt

the

Data

even

to

a

16-bit

(10

20

Register

number

words

byte

I/O

driven

of Host, deep)

FIFO methods

bytes and

used

I/O

appears the

only

for

can

is

not

as

can

register

word

be an

be

18

2.3

The Host DMA signals of cleared

HOST

Host

to

requests

this

CONTROL

Control

cause

between

register

upon

REGrSTER

Register

3C505

to

the

the can

power-up.

hard Host,

PC be

(HCR)

or

Host read

soft

and

back

is

resets,

to

3C505

an

8-bit

provide

processors.

by

the

register

to

control

synchronization

Host.

This

used

interrupt

The

contents

register

by control

+------+------+------+------+------+------+------+------+

I

ATTN

I FLSH I

DMAE

I DIR I

TCEN I CMDE

I HSF2 I HSF1 I

+------+------+------+------+------+------+------+------+

the and

is

ATTN

FLSH

****

Attention When

the

generated

Control affected. "soft state

Flush

reset", ready

Data Setting Register bit.

actual remains

Reset When

a~apter

the

adapter Register, Host

Status S0186 internal reset

will bits

stay

are

Host

to

and

The to

Reqister

the

FLSH

regardless

The

FIFO

data

in

this

Host hardware

Adapter

Register

processor

registers

location.

in

cleared.

sets status

the

ATTN, Adapter's

Registers

interpretation

where

accept

bit

the

Adapter

commands.

flushes

of

assumes

the

state

FIFO

until

is

simultaneously

decodes

status

are

is

generated

and

transfers

The

82586

this

reset

a

non-maskable

80186

on resets

all

the

an

state

empty

unchanged.

the

FLSH

sets

it

as

a

and

Control

reset.

is

also

state

processor.

the

of

NMI

data

of

words the

condition,

bit

both

"hard

A

reset

which

control

reset.

until

interrupt

Adapter

is

intended

itself

from

DIR

The

Data

is

cleared.

ATTN

and

reset".

Registers,

signal

resets

to

the

ATTN

(NMI)

The

are

to

into

an

the

(direction)

although

Register

FLSH,

The

and

to

all

the

The

powerup

Adapter

and

is

Host

not

be

idle

Data

the

Data

the the

80186

FLSH

19

DMAE

DMA

enable

Used

transfers the bit and

Host cleared, another

in

conjunction to

can

or occur

I/O

from

the

card

with

the only DMA

may

the

Data

if

this

request

use

DIR

Register.

bit

output

the

channel.

bit,

is

to

DMAE

set.

the

DMA

enables

requests with Host

DMA

the

DMAE

"floats"

to

DiR

TCEN

CMDE

Direction The

Host half-duplex transfers data

transfp-s

CAUTiONl

sure

that empty) This

c~n

network

Terminal TCEN a

DMA

enables

transfer

Command The when

CMDE

the neither

interrupt float.

flag

has

Data

are

After

the

before

take

activity

Count

an

Register

control

Adapter

TCEN

nor

channel

exclusive

Register.

to

the

are completing

Adapter

changing 1

to

occurring

interrupt

to

or

interrupt

bit

has

CMDE

because

Adapter

to

the

has

30

from

allows

written

are

control

of

If

(download).

Host a

(upload)~

download,

completed

the

DIR

bit

microseconds,

on

the

Adapter.

enable

to

the

Host

Data

enable

the

Host

the

Command set, the

the

interrupt

the

direction

DIR

the

its

to

the depending

at

the

Register.

to

Host

should request

is

clear,

If

DIR

Host

transfer

upload

completion

be

Register.

of

data

is

set,

must

make

(FIFO

state.

on

interrupted

When

disable

line

will

the

of

the

HSFl HSF2

Host The

status

HSFl

Adapter

nature drivers completion

and

status

and

to

Flags

HSF2

Register. can synchronize

.status.

1

and

status

be

used

2

20

bits by

data

are They Host

transfer

routed

are

and

directly

general

Adapter

or

purpose

pass

to

interface

command

the

in

2.4

HOST

STATUS REGISTER

The Host

and

synchronize

Host

to Command

+------+------+------+------+------+------+------+------+

I

HRDY I HCRE I ACRF

status

determine

Register

the

Register

causes

Host

(HSR)

of

programmed

and

3C505

I DIR I

is

an

interrupts,

processors.

DONE

B-bit

check

I/O,

I ASFJ I ASF2 I ASF1 I

register

and

status

provide

used of

a

both

+------+------+------+------+------+------+------+------+

HRDY

HCRE

Data

The

full

the means more

Register

HRDY

or

Host

that

data. Adapter, empty,

Host

The the the

Command

HCRE Command Host

indicating has that

read the

not

HRDY

i.e.,

flag

the

register

ready

bit

indicates

empty,

is

downloading

the

Data

When

set

input

Register

is

Register

writes

the

register

Co~~and

depending Register

the

means

data

empty

used

to

from

the

Command Register,

is

empty.

whether

data

is

Host

is

that

is

available.

handshake

the

is

not

the

on

the

to

the

not

full, uploading the

Data

data

Host

to

Register,

empty.

HCRE

Data

Register

Direction

Adapter,

i.e.,

data

Register

transfer

the

HCRE When

is

set,

Flag.

HRDY ready from

Adapter.

is

the

indicating

by

the

Data

way

is

to

not

When

set for

the

is

not

through

When

cleared

Adapter

ACRF

Adapter

The the the

ACRF

Command

Adapter indicating Command register

Command

flag

Register

writes

the

Register,

is

not

Register

is

used

register

ACRF

full.

from

the

full

to

handshake

Command

is

21

the

Adapter

full.

cleared,

data

to

Register,

When

indicating

transfer

the

ACRF

the

Host

Host.

reads that

through

When

is

set,

the the

DIR

Direction

The bit

DIR

in direction Register. to

the from also

the

determines

flaq

status the

Host

data

When DIR

Adapter

the

bit

is Control is

allowed

(download).

Adapter

how

HRDY

the

is

to

current

Register.

clear,

When DIR

the

Host

should

value

to

pass

transfers

(upload).

be

of

the

It

specifies

through

are

is

set,

interpreted.

DIR

in

the

from

the

transfers

The

DIR

control

which

Data

Host

are

bit

DONE

ASF1 ASF2

ASF3

DMA

The Host

Adapter

done

DONE

and

the

COt,trol clearing

The

ASF1, Host They and or

are

Adapter

pass

flag Data

will

Register

the

status

general

command

CAUTION! to bits if

the

while the

Host

simultaneously.

~

ASF2 - 0

ASF2=O,

you transition state the of flag

slower Adapter more

than

in

transition.

is

Register

also

DMAE

Flags

2

and

Register

interface

These

processor they state

and

could

to

ASFl

than

status

one

set

when a DMA

is

be

generated

is

set.

bit

in

1,

3

status

from

purpose

drivers

completion

bits

are

For

in

of

example,

you

are

transition. more

are actully = ASF2

the

ASF1

Register

flag

to

complete.

the

2 , 3

bits

the

in

nature

status.

set

and

it

testing

read

=1,

flag. twice

insure

transfer

An

if

the

TCEN

The

DONE

Host

are

bi~

Cont~ol

routed

Adapter

and

to

synchronize

asynchronously

is

possible

This

than

if

the

one

present

for

this

if

state the The

when

that

you

between

interrupt

bit

is

Register.

directly

Control

can

be

data

with

to

is

only

flag

state

during

ASF2

flag solution checking

have

the

in

the

cleared

Register.

used

transfer

read

a

is

ASF1=1

is

the

not

Host

to

the

Host

by

to

the

by

Host

respect

these

problem

tested

is

ASFl

and

a

state changed to

read

state read

a

22

2.5

HOST

AUX

DMA

REGISTER

The transfers.

Host

Aux

This

DMA

Register

register

is

used

cleared

to

upon

support

power-up.

demand

mode

DMA

+-----+-------+-------+-------+-------+--------+-------+-------+

I 0 I 0 I 0 I 0 I 0 I 0 I 0 I BRST I

+-----+-------+-------+-------+-------+--------+-------+-------+

BRST

CAUTION! Do PC's.

2.6

DMA

If

the·

refresh such single

Data

ADAPTER

Burst

the

errors

Burst

Host

will

its

pause

cycle not

CONTROL

bit

pause

dynamic

will

DMA

use will

demand

REGISTER

is

not

every RAMs.

occur.

transfers.

occur!

set,

mode

demand

9

transfers If

This

DMA

the

B~rst

bit

uploads

has

mode

to

no

in

DMA allow bit

effect

PC's

transfers

the

is

set,

or

XT

by

PC

to no

during

type

The

the the PC be

up.

Adapter

LEDs,

Host

read

and

back

Control

to

and

3C505

by

reset set

the

Register

the the processor.

Adapter.

82586,

state

(ACR)

of

The

This

is

flush

synchronization

contents

register

an the

8-bit

Data

is

register

flags

of

this

cleared

used

Register,

between

register

upon

+------+------+------+------+------+------+------+------+

I LPBK I FLSH I

R586

I LED2 I

LEDl

I ASF3 I ASF2 I

ASFl

+------+------+------+------+------+------+------+------+

LPBK

Loopback LPBK

is

Adapter.

Code

specifies

not

Converter.

control

placed

This

a

diagnostic

on

the

controls

If

network,

CLEAR,

mode

loopback

but

in

at

which

is

looped

the

mode

transmitted

back

8023

is

enabled.

into

Manchester

by

blink

the

can

power-

I

data

the

23

FLSH

Flush Setting

Register

bit. actual remains

Data

The

data

in

Register

the

FLSH'

regardless

FIFO

in

this

bit

of

assumes

the

FIFO

state

flushes

the

an is

until

all

state

empty

data of condition,

unchanged.

the

FLSH

the

bit

words

DIR

The

is

from

(direction)

although

Data

cleared.

the

Data

the

Register

R586

LED2

LEDl

ASF1 ASF2 ASF3

Reset

When

the

82586

the

82586

components

until

R586

Channel

LED LED2 the

LED LED1 the

control

determines

LED

control

determines

LED

Adapter The Host

and

ASF1,

Status

can synchronize status.

Adapter

coprocessor

are

is

Attention

bit

and

on,

bit

on,

and

status

2

and

Register.,

be

used

data

sets

reset

cleared.

signal

2 the clearing

1

the

clearing

Flags

3

status

by

transfer

R586,

to

state

1,

Host

chip. an

before

of

the

of

the

2

and

bits

They

and

a

hardware

All

inactive

The

82586 completing

LED bit

3 are

are

general

Adapter

or

major

state

2. turns

1. turns

routed

pass

reset

and

then

Setting

the

Setting

the

directly

purpose

interface

command

is

applied

82586

hardware

remain

waits

for

initialization.

the

LED

the

bit

off.

bit

off.

to

in

nature

drivers

completion

to

reset

the

turns

the

to

24

2.7

ADAPTER

STATUS REGISTER

The the

both

to

'ARDY

ACRE

Adapter Adapter

Data

synchronize

+------+------+------+------+------+------+------+------+

I

ARDY I ACRE I HCRF

+------+------+------+------+------+-----~+------+----

Data The full the means data the full,

Adapter The the the

indicating reads the

status to

and

Command

Register ARDY or Host

that

is

Host,

i.e.,

ACRE

Command

Adapter

the

register

Register

determine

the

Host

ready

bit

not

empty,

is

downloading

the

available.

ARDY

ready

Command

flag

Register

writes

that

Command

is

causes

Register

and

I DIR I

indicates

depending

Data

Register When

set

means

to

Reqister

is

used

the

Register,

empty.

(ASR)

of

programmed

3C505

8/16

whether

data the

accept

empty

to

handshake

from

Command

register

is

an

8-bit

interrupts,

processors.

I

SWTC

the

on

the

to

the

is

not

Adapter

that

more

the

data.

Adapter Register,

is

not

ACRE

is

register

check

I/O,

and

I HSF2 I HSF1 I

Data

provide

Register

Direction

Adapter~

empty, is

uploading

Data

data

Register

transfer

to

the

ACRE empty. set,

When

indicating

used

status

--+

is

Flag.

ARDY

~.e.,

data is

through

Host.

is

cleared, the

by of

a

way

not

When

set

input

to

not

When Host

that

ECRF

Host The the the

Command HCRF Command Host

indicating

the

COmInand

register

flag

writes

the

Register,

is

not

Register

is

used

Register

register

full.

the

full

to

handshake

from

Command is

HCRF

25

the

full. is

Host

Register,

cleared,

data

to

the

When

indicating

transfer

Adapter.

HCRF

the

Adapter

through

When

is

set,

reads

that

the

DI:R

Direction The

DIR allowed is

settable Control the

Host

from

the

flaq

status

to

pass

only

Register.

to

the

Adapter

bit

specifies

through

by

the When DIR

Adapter.

to

the

Host

When

Host.,

in

Data

using

is

which Register.

the clear, DIR

is

direction DIR

bit

transfers

set,

data

The

direction

in

the are

transfers

is

Host

from

are

8/16

SWTC

8/16 The

bit

8/16

installed

bit

IBM

is

AT

External

The

the TEST

1.

SWTC

state jumper

Ignore

detected

from is

the

2.

Ignore is changing

3.

Install known

unused

slave occurs,

with

bit

in

an

set,

the

or

AT-compatible.

switch

flag

of is

powerup

during

entering useful NMI

vector

ROM

when

checksum

convenient

frequently. 3D

as

"exceptions"

interrupt

in

the

3D

the

3D

flag 8

or

16

Adapter

in

the

set

TEST to

memory

powerup

the

main

using

location

not

interrupt

vectors

Revision

becomes

Debugger

indicates

bit

expansion

is

in

Adapter

jumper

one,

the

test

ROM

ICE

in

error.

to

vectors.

(basically

active

program.

whether

a

sixteen

status on

the

Revision

error.

normally

idle

systems

order

During

checksum

are

made

2.0

ROM.

and

attempts

slot.

Register Adapter.

prevent

loop.

that

to

since

The

INT 0

to

the

bit

3.0

slot,

ROM Memory

Ignoring need

operate. ROM

development,

interrupt

to

point

When

to

Adapter

If

the

i.e.,

represents

When

code

the

Adapter

to

the

code

vectors

7)

and

to

an

the

exception

communicate

is

8/16

p~

the

will:

errors

modify

it is

all

3D

26

HSFl HSF2

Host The Host

and

status

HSF1

Control

can synchronize status.

and

be

Flags

HSF2 Register.

used

by

data

1

and

status

Host

transfer

2

bits

They

and

are

routed

are

general Adapter or

pass

directly purpose

interface

command

from

in

nature

drivers

completion

the

to

CAUTION! the are both

80186 in

flags

present

state

HSF1=1

during

flag is

the

flag

changed

to

state

in

These

and

transition.

is

state

and

a

state

read

of

the both

transition.

bits

it

is

tested

is

HSF1 = HSF2 = 0

HSF2=0,

transition

slower

Host

flags

are

set

asynchronously

possible

This

is

to

only

simultaneously.

we

could

to

HSFl = HSf2

than

status

to

Register

insure

read

the

a

problem and

actully

HSF1

that

these

For

we

twice

you

with

bits

if example, are

read

=1,

flag.

when

have

respect while

the

state

testing

this

if

the

The

solution checking

not

they

if

state

HSF2

read

to

of

the

for

a

27

CHAPTER

3

3.0

The support

After programs Adapter sections access utilities

INTRODUCTION

16K

*

Bootup

*

Software

*

Network

*

Packet

*

Host

*

System

*

Host

bytes the

Adapter

through the

following:

I/O PC

or

3.1

described

COMMAND

of

EPROM

initialization

memory

I/O

buffer timer

primary

drivers

and

Adapter

control

bootup the

primary

3.2. in

INTERFACE SPECIFICATION

on

the

refresh

command

initialization,

can

Programs

resources

section

3C505

and

interface

access

command

Adapter

diagnostics

the

network

block

downloaded

directly

3.3.

contain

host-based

or

resources

interface

into

or

through

firmware

application

described

the

Adapter

a

of

set

that

the

in

can

of

3.1

The

(PCB)

command/response

The Register. command, data to

The is command is Table

PRIMARY

3C505

from

PCB PCB PCB

PCB

field,

set

up

maximum

64

bytes.

62

bytes 1

COMMAND

firmware the

command data data

code

and

is

An

a the

long. are

length

(variable

length and

PCB or

PC

sequences.

code

passed

example

a

82586

size

The

the explained

BLOCK

idles

Host.

(byte)

length)

using

PCB

field

data

coprocessor.

the

PCB

length The

that

field

Adapter

data

valid

in

STRUCTURE

waiting

The

PCB

The

programmed might

length

field

counts

that

PCB

detail

format

contain

can

itself.

command

structure

has

for

a of

I/O

the

configuration

accept

field

in

section

Primary

is

a

PCB

through

an

82586

number

in

does

The

codes

Command

expected

is:

of

this

not

include

maximum

are

3.2.

Block

during

the configuration bytes

data

version

summarized

Command

in

the

data

needed

field

the

ROM

PCB

in

28

TABLE

1:

PCB

COMMAND

CODE

SUMMARY

HOST

00: 01: 02: 03: 04: 05: 06: 07: 08: 09: Oa: Ob: Oc: Od: Oe: Of: 10: 11: 12:

: I

2f:

->

3C505

configure configure Ethernet download upload download upload receive transmit network load clear download execute self-test set adapter reserved

reserved

multicast

downloaded

Ethernet

COMMANDS

adapter

82586

address

data

packet statistics

program

to

data

to

packet

program

address

info

to

Host

to

Host

list

memory

3C505 3C505

programs

(set (set (get (download (upload (download (upload (receive (transmit (includes (perform (release

(download

(execute (perform (set (get

adapter 82586 adapter

Ethernet

adapter

buffer

receive

Ethernet

using

to

Host

using

to

Host

a

packet)

a

packet)

82586

download

program

3C505

information)

mode)

3C505

using

3C505 using

error

MC-setup

program to

in

self-test)

address

requirements)

address) DMA)

3C505 PIO) 3C505

counts)

3C505)

in

DMA) PIO)

command)

memory)

82586)

3CS05 30:

31: 32: 33: 34: 35: 36: 37: 38: 39: 3a:

31:>

:

3c: 3d: 3e: 3f: 40: 41: 42:

.

5f:

->

HOST

configure configure address download upload n/a n/a receive transmit network load clear download execute self-test set adapter reserved

multicast

program

address

I

reserved

adapter 82586

response

data

packet

statistics

program

response

info

response

request

complete

response

memory

response

.

(returns

(returns (request

(request

(receive (transmit (returns (returns (returns (returns (returns (returns (returns (returns

success success

Ethernet

DMA

download

DMA

upload

packet

packet network success success

program variable

self-test success adapter

or

failure)

or

failure)

address)

to

Host)

request

request statistics) or

failure)

or

failure)

id)

length

results)

or

failure)

information)

3C505)

complete)

data)

29

3.1.1

STATUS

FLAG

USAGE

FOR

PCB

TRANSFER

The

byte

Adapter

stream protection transfers), complete state should PCB

can included its

status

PCB" The

when

Adapter

always the Host uses the

PCB,

signals

status

Host, similarly

In

summary,

following

Adapter

uses

against

the

until

11.

be

in

be

in

flags

sending

be

able

the

flag it

to

the

conventions:

or

a

64-byte

sent

through

stray

Adapter

the

Host

Simultaneously,

the

Command calculated. the

PCB

data

is

to

(ASF2

a

always

accept

Adapter

PCB

and

to

ready

uses

end-of-PCB.

state

10.

expects

signal

Bost

acceptance

Adapter

Status

uses

circular

the

bytes

does

status

Register

(This

length

ASF1) the

to

it.

status

To

indicate

When

the

Host

and

Flaq

not Flags

the

Host.

read

To

or

buffer

Command

(from

consider

(HSF2

TOTAL

so

the

last

total field.) similarly

a

PCB

indicate

flag-state

rejection,

the

Adapter

to

set

rejection.

expects

to

Register.

Host

a

and

length

true

length

The

to

but

the

its

the

Host

store

the

aborted

PCB

transfer

HSFl)

of

the

beginning Adapter

signal

it

might

acceptance

01

after

the

sends

a

status

to

host

For PCB

go

to

PCB

of

is

NOT

uses

"end

of

not

of

the

Adapter

PCB

to

flags

use

the

SF2

The

just

10

is

3.1.2

The the

-

Load will Host

-

Poll Status within

SFl

o o

1

state

o

1

o

1

11

transmitted.

used

BOST

to

following

3C505

Adapter:

the

PCB

interrupt

for

the

Register.

40

ms.

Undefined

PCB

accepted

PCB

End

is

rejected of

PCB

accompanied

After

signal

TO

ADAPTER REQUEST

method

command

the

data

Command

acceptance

is

byte

3C505

transfer.

Register Abort

by

a

PCB

suggested

into

Adapter,

Empty

the

I/O

the

total

is

received,

or

rejection

to

transmit

the

Command

synchronizing

(HCRE)

if

it

length

flag

does

of

the

state

of

·the

a

Host

Register;

it

to

the

in

not

go

the

PCB.

PCB

the

PCB

01

or

to

this

PC

Host

empty

30

-

output timeout context

-

After

Host

the

to

state

-

wait

a

reject

to

must PCB

for

the

remainder

period

read

the

last

send

(excluding

11

before

adapter

if

a

to PCB

actual

one

SOms

of

SOOus.

data.

last

byte

this

writing state

timeout

the

PCB

byte).

the

01

The

(accept)

occurs.

PCB

similarly,

Adapter

data

byte

signifying

set

length.

is

the

or

remains

transferred,

the

TOTAL

Host

10

(reject).

reducing

in

interrupt

length

status

the

of

flags

Assume

3.1.3

The

3C505 Adapter Adapter host

The the

-

request.

following

Host:

Load

interrupts

the

-

data

Poll status within

-

Output timeout

context

-

After Adapter the

PCB.

before

ADAPTER

Adapter needs usually

the

PCB

the

transfer.

the

Command

Register.

20

ms. the

to

read

the

last

sends

The

writing

TO

HOST

to

read

sends

method

command PC

Host,

Register

Abort

remainder SOous.

PCB

data.

actual

one

last

Adapter

the

length.

REQUEST

to

PC

or

write

a

response

is

used

byte

synchronizing

of

The

PCB

byte

Host

to

into

Empty

the

the Host

data signifying

status

OR

RESPONSE

request

a

block PCB

transmit

the

(ACRE)

I/O

if

PCB

similarly,

should

byte

Flags

is

of

host

after

it

an

Command

it

to

flag

it

does

remain

is

transferred,

the

are

made

memory.

has

adapter

Register; the

in

not

reducing in

TOTAL

set

to

when

executed

PCB

Adapter

the

Adapter

go

interrupt

length

state

the The

a

to

this

for

empty

the

of

11

or

The

10

Adapter

(reject).

waits

for

Host

31

status

Flag

state

01

(accept)

3.2

PCB

COMMANDS

3.2.1 01H:

HOS~

Confiqure

for multicast buffers, and the

in coprocessor buffers management buffers command shown adapter

db db

dw dw dw dw dw dw

TO

3C505

the

receive maximum adapter

is is

in

response

01 OC

? ? ?

?

PCB

A~apter

PCB

address

and

command size

when

of

and

fixed

not

parentheses

command

download

memory

1.6kb

issued,

FORMATS Memory.

list,

program

queue

PCB

of to

in

multicast are

DMA

overhead.

at

one

the

below.

PCB31H

;command ;length

;# ;#

;#

multicast

;#

;*

;#

The queue, 82586

entry

64

bytes.

be

loaded alwp:

and

is

Adapter

to

confirm

code

of command receive

frame receive download

descriptors

Adapter

receive

frame

data

is

A

mode.

is

iJ.sei:'

The

not The

data

queue queue

addresses

buffers

programs

allocates

command

descriptors,

structures.

large

multicast

confiqurable. uses Host

execution.

portion

enough

into

Receive

tQ

number

the should

entries entries

the

decrease

default

of

to

list and of

expect

PCB (10) (20)

(0) (20) (20)

(10)

memory

queue,

receive

Each

buffer

is

kept

82586

transmit

buff,~r

transmi~

If

this

values

PCB

LAN

the

02H:

Confiqure 82586 configure default should execution.

db db

dw

LAN

82586. coprocessor command

values

expect

02 02H

?

is

shown

the

Instructs

into

not

adapter

;command ;length ;receive

,

·

,

·

,

·

,

·

,

·

,

·

,

·

the

issued,

in

parentheses

bit

the

Adapter

given

response

code

of

data

mode

2,1,0:

000

=

001

=

010 = multicast 100

00 01

10

=

= =

4,3

receive

the

Adapter

PCB

portion

receive station plus

promiscuous

loopback

none

82586 82586

to

configure

mode.

below.

32Hto

of

mode only

broadcast

mode

(default)

internal external

will

PCB

(000)

(00)

the

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this

use

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loopback loopback

the

Host

confirm

32

03B:

Ethernet

address PROM

address

Address.

stored

in

PCB

Requests

its

address

33H.

Adapter

PROM.

to

The

return

Adapter

the

Ethernet

sends

the

04H:

OSH:

db db

Download download

bit

the

up

required PCB

db db

dw dw dw

Upload

DMA

direction

issuing Adapter given

for

must

command.

the

for

channel

number

this

03

00

Data data be

set

DMA

this

04

06

? ? ?

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this sets

command.

transfer

number

command.

to

bit

of

To

3CSOS.

through

to

If

the

of

To

Host.

upload

must

command.

up

the

bytes.

:command ;length

the

bytes.

be

download

command

and

expects

;command ;length ;data ;Adapter

,

·

DMA

block

"

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data

set

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code

of

data

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data

through to

register.

is

accepted,

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code

of

data

byte

destination

the

command

expects

is

portion

the

direction

the

Host

is

no

portion

length

"

the

Adapter

the

upload

the

no

adapter

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the

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offset segment

data

direction

is

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of

PCB

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before

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to

supply

of

PCB

(must

to

register. accepted,

to

response

to

direction

issuing

sets

response

be

even)

use

before

read

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the

its The

the the PCB

06H:

db

dw

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except

instead download no

db db

dw ? dw ? dw ?

that

adapter

05

06

? ? ?

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the

of

direction

response

06 06

To Adapter

DMA.

icommand ;length idata ;Adapter

,

·

"

3C50S.

uses

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direction

before

PCB

for

icommand ilength ;data ;Adapter

,

·

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code

of

data

block

source

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programmed

issuing

this

code

of

data

block

destination

portion

byte

length offset segment

as

bit

this

command.

portion

length

of

command

input/output

must

be

command.

offset segment

PCB

(must

set

of

PCB

(must

be

code

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be

to

even)

04H,

(PIO)

the

is

even)

33

07H:

Upload except direction

issuing for

this

Data that

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bit

this

command.

Host.

must

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be

set

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uses

to

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PIO

the

is

as

instead upload no

adapter

command

of

direction

response

code DMA.

05H,

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before

PCB

OSH:

09H:

db db

dw

07 06

?

dw ?

dw

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complete, should

?

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packet.

by the

set

up response. the

Data

db db

dw dw dw dw

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packet.

download the

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08

?

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the

transmit

39H.

the to

The

the

packet

is

icommand

i

length idata iAdapter

;

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Configure

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input

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icommand ;length ;offset ;segment iHost itimeout

i

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PCB

data

complete,

of

block

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packet

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responds

the

packet

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of of

receive

no

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is

accepted,

through

the

code

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portion

byte

source

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type

offset segment

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of

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with

data

DMA

upload

code

PCB

data

of

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receive

buffer

in

10ms

maximum

the

Adapter

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of

length

to

interest

the

PCB

and

the

3aH.

then

packet

portion

buffer

receive

length

increments

is to

the

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responds

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rece:l're is

buffer

32767

transmit

should

be

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d~fined

receive

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accept

through

in

bytes

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ticks)

with

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is

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the

is

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dw dw dw

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the counters through with

command

after

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statistics.

cumulative

kept

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sending

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by

the command code

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;command ilength

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82586

command

error

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register

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icommand ilength

34

code

of

PCB

of

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of

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length

statistics

in

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code

of

PCB

data

transmit

in

requests

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the

data

portion

transmit

bytes

values

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clears

portion

buffer

(must

the

and

are response

all

be

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the

packet

returned

statistics

even)

to

PCB

OBB:

Load of

Multicast

multicast

zero

multicast

create of

addresses

contain

length

lists

command

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list

addresses

greater

in

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completion

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and

than

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to

cause

is

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the

the multiple ten

entries. ten. status.

will

82586

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PCB's

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add

multicast

can

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response

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given

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to

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be

issued

maximum

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list

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all

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number

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db

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adapter

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adapter

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the

program.

containing paragraph

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code

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memory

available. code

of

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buffers

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to

each

be

code

of

length

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data

address address This

command

to

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contain

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programs

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system

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responds

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reset

data

in

portion

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the

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program.

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portion

bytes

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number

adapter

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relative

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in

responds

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length

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section

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to

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sequence

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portion

to

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to

function

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list

the

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when

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execute

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its 3FH.

self-test.

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db db

set

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command station from

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configure

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information

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address.

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responds

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code

of

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address

code

of

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address

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adapter

with

code

of

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data

portion

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specifying

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not

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data

portion

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configuration.

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41H.

data

portion

issue

used,

to

an

an'

the

is

send

lA-setup Ethernet

address

used

general

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to

36

3.2.2

3C505

TO

HOST

PCB

FORMATS

31H:

32H:

33H:

Configure initialized address

db db

dw Configure

ized

the

command, db

db dw

Ethernet Ethernet previously stored

db

into

db

Adapter storage 3lH

02

?

82586

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responds 32H

02

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address

been

memory.

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dupe?)

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area,

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coprocessor

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in read

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command

it

responds

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;length

;

status

using

with

status

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this

response

from

icommand

;length

iEthernet

of

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0 =

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code

of

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the

code

of

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address

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queue

with

data

successful

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parameters

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this

data

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data

the and status

portion

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portion

returns

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address

portion

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the

in

has

in

the

address

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the

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has

and

34H:

3SH:

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the

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will

use

register.

db

db dw dw

dw

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the

command

transfer db

db dw dw dw

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34H

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the

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3CS05.

download

command

to

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upload

is

accepted,

appropriate

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a

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transfer

icommand ilength idata iHost

block data

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this

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code

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byte

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byte

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the

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through

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NETWORK

I/O

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INT

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82856.

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44

3.3.3

CONFIGURATION/STATUS:

INT

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01H:

memory multicast

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46

3.3.4

TIMER SUPPORT:

INT

83B

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3C505

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microprocessor.

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3.3.5

The

and downloaded allocated kiloword programs

DOWNLOAD

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command

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memory stack should

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48

3.3.6

PCB

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PROCESSOR: INT aSH

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Register

and

section

loop PCB

is

stored

is

command

subroutine

PCB's

can

the

current

a

pointer

opportunity

If

program

In

values

creating

ISR

places

3.3.7)

into

monitors

is

passed

in

this

given

an

number

is

for

the

with

and

chain

command

immediately

to interrupt to

itself.

(not the must

this are

program

pass case

not

new commands

(interrupt

all

PCB's

a command

and

dequeues

to

a

PCB

interrupt

ES:BX

to

key

pointer

into

addresses.

also

passed

slibroutine).

numbers

this

vector; vector

necessarily

does

it

to

the

program

modified.

or

service

except

Command

a

not

returns

Then

the

not

want

command

must

This

replacing

queue.

each

vector.

to

jump

The

the

PCB

The

defined

that

contents

the

downloaded

first)

to

be becomes

routine)

rece~ve

The

PCB

for

Processor

The

the

PCB

table

selected

(often

Command

to

is,

the

and

execute

processor

careful

existing

of

in

to

a

49

3.3.

PACKET

PROCESSOR

VECTOR:

INT 86H

This Packet and packets. performed program

software

Processor.

queuing

can

The

outside

replace specialized below.

As

mentioned

packet

Regi',~;ter

Processor

01H:

ax es:bx

A

separately

When with

the packet The

command

Enqueue

-=

1

packets

a

double

frame

from

idle

ISR

with:

command

pointer

and

loop

interrupt

of

host

management

scheme

in

section are

gives

Receive

managed

are

received,

word

exits.

the

gives

The

the this than

placed

the

code to

PCB

lSus

Network

the

vector Packet receive

of Packet vector the

ROM-based

3.3.6, into receive

Command

Receive

the

time

The

foreground

I/O

packet

defines

Processor

command the,82S86

Processor.

in

order

all

PCB's

a

PCB

command

PCB

Command

82S86

and

updates

vector

to

the

the centralizes PCB's

LAN

to functions

queue.

Queue

ISR

time

idle

INT

Packet

address

and

coprocesser

A

implement

EXCEPT

to

is tags

global

loop

SlH

Processor

of handling received

downloaded

a

described

the

The

the

receive

Command

Packet

built.

the

pointers

obtains

function

the

is

more

frame

to

a

2.

with:

02H:

ax

= 2

es:bx cx:dx

di

The

a the is

firmware

pending

Host,

returned

enqueued

be

replaced

and

process

since

idle

with:

Enqueue

receive

packet

and

receive

loop

Receive

command pointer double packet

builds

data to processing

by

downloaded

all

incoming

commands

needs

Packet

code to

receive

word

time

length

a

queue

command,

is

the

system.

have

to

periodically

buffer

tag

of

a

receive

DMA

uploaded,

is

done.

programs

packet.

timeout

(high:

receive

Otherwise,

This

enabling

call

low)

packets.

response

and

vector/function

values,

the

PCB

the

packet

the

them

the

Packet

If

there

is

sent

buffer

packet

to

receive

foreground

Processor

is

to

is

can

so

03H:

ax

- 3

so

that

queue

has

timed

formatted

No

Operation

it

to

check out, and

NOP

has

an

if

a

sent

opportunity any

request

receive

to

the

response

Host.

to has

scan

timed

PCB

the

with

out.

failure

receive

If

command

a

request

status

is

3.3.8

The

idle chance

To save to

IDLE VECTOR:

Idle

loop.

to

chain

the.current

itself.

control

Remember

entry

and

program The

that

In Idle

vector

that

default

determines

a

situation

vector

routine,

the

through

3.3.9

PCB

vector

Programs

execute. to

(using

thau

restored

in

the

download

the

main

ENQUEUE

the

It SS,

ROM

but

is

vector,

vector

is

a

far

chain

Idle

whether

where

never

this

3C505

INT

called

chained

also

jump)

SP,

on

DS

exit.

has

vector

a

download

passes

flag

program

ROM

VECTOR:

87K

every

through

a

downloaded

before

important to

the

and

an

oppurtunity

routine

the

Idle

is

never

will

idle

XNT

sOms

replacing

should

In

this

vector

program

control

cleared.

be

loop.

88H

from this

program

that

program way,

to

clears

to

called

the

vector

it

with

the

always

each

execute.

a

should

has

chained

the

en

main

will

should

a

program

in

the

be

downloaded

global

be

default The

every

3CsOs

have

first

pointer

chain.

saved

called. to

effect

ROM

a

pass

on

flag

the

Idle

is

pass

The

system loop The

PCB

and

calling

es:bx

Return:

The this

Command

vector program it,

it ex,ecutien. this

vector

Enqueue

queue.

given

sequence

pointer

carry

Register

has

read

should

Alternatively,

to

Vector

to

ciear set

after

use

receive

PCB's the

to

a

PCB

is

called

are

PCB

for

this

PCB

if

successful

if

error,

interrupt

it

receives

from

this

PCB's

51

to

dequeued

Command

function

ax -error

service

a PCB.

the

Host vector a

downloaded from

add

by

Processor

is:

and

to

enqueue

the

Command

a

PCB

the

foreground for

code

routine

If

does

program

entry

execution.

(ISR)

a

downloaded

not

recognize

it

for

can

Register

into

later

chain

ISR.

the

idle

uses

to

APPENDIX A

,

·

reloc umcs

lmcs-cont mmcs-cont mpcs-cont pacs-cont

i

,

·

i

pic

,

·

level level-int1 level-int2

level-int3 level-dmaO level-dma1 level-timer

,

·

:

,

·

pic pic-dmao pic-dmal-cont pic-into-cont pic-int1-cont pic-int2-cont

pic:int3:cont

,

·

i

,

·

t2cnt

t2maxra

t2cntrl-cont

,

·

i

,

·

tOcnt

tOmaxra

tOmaxrb-cont

tOcntrl-cont

,

·

;

reg

cont-

priority

into

initialization

timer

cont

initialization and

Hi

RES

cont

initialization

cont

80186

cont

PERIPHERAL

equ

assignment:

equ equ

equ

equ equ equ equ

of

equ equ equ equ equ equ

equ

of

Timer

equ equ equ

of

equ equ equ equ

pic

timer

CONTROL

OOffh' Ofc3ch 3ffch

81fch

OaObch 003ch

4

2

5

6

o

3

1

control

level level-dmaO level-dma1

level-into level-intl OOOdh-

OOOeh 2

registers;

iinitialization

ichip

iinto iint1

inot inot

idmaO idma1

itimer registers timer

o

30 OcOOlh

0

registersi

o

20000jt2maxra_cont

o

Oe029h

BLOCK

selects

priority,

priority, used used

priority, priority,

priority

15

10

PROGRAMMING

constant

Command interrupt

DRAM Data

microsecond

millisecond

of

Register

refresh

Register

for

DRAM

interrupt

form

Full

82586

refresh

52

;

:

initialization

of

timer

1

registers;

Hi

res

system

Timer

tlcnt tlmaxra tOmaxrb-cont tOcntrl

;

initialization

I

·

I

·

dmaOsrclo dmaOsrchi-cont dmaOdstlo-cont dmaOdsthi-cont dmaOcnt dmaOcntrl

;

DMA

I

·

dmal dmal=to_dr

cent

-

1.

from

cont cont

cont

control

dr

cntrl

equ equ equ equ

of

dmaO

equ equ equ equ equ equ

'register

equ equ

0 Offffh 0 Oe029h

registers;

0000 OOOOh 0800h 0OO8h Offffh 0157fh

values

Oa347h 1787h

DRAM

iDMA iDMA

refresh

input

output

from

to

host

53

APPENDIX B

This 82586 User's

FIFO

BYTE EXT INT

PREAM

AT ADDR SAV SRDY

INTERFRAME BOF ACR LIN RETRY SLOT TIME CDT CDTF CRS CRSF PAD BT CRC16 NCRC TONO MANCH/NRZ BC

PRM

MIN FRM

LIM

CNT LP LP

LOC

LEN

BF

MET

PRIO

SRC

STF

INS

CRS

DIS

is

LAN

Manual"

BCK BCK

LEN

NOM

LEN

an

example

Coprocessor.

for

the

= = =

= 0 =

= 1

= 6 = 0

=

SPACING = 60H

= = =

= 0

= = = = = = = =

=

of

the

parameters

Please

description

6 OCH

0

2

1

0 0 0

OFH

200H

0

0 0

0

(reconfigurable

1

0

40H

refer

of

used

to

the

to

the

by

"Intel

abbreviations

host

configure

LAN

command)

the

Intel

Components

used.

54

APPENDIX C

3CSOS DIAGNOSTIC

The

3C505

EtherLink

3C505.EXE,

problems This

tools on

appendix

how

to

required

3C505.EXE AT)

from displaying pass

count.

hardware

o

1

2

3

When

are run

require

from from

the each

the

performed

individually

producing

polluting

Adapter

test

EtherLink

Plus

which

on

the

describes

use

the

takes

start

the

error

Adapter

Preliminary DMA Packet

standard

the

use

is

follows:

card

can

3C505.

to

run

diagnostic.

about

to

finish.

name The is

of

test

detected.

self

test

3C505.EXE in and of

sequence.

must

a

erroneous

the

network.

connected

Diagnostic includes

be

the

used

the

3C505.EXE

program,

twelve

As

the

group

stops

test

program

be

loopback

test

to

the

Diskette

a

to

minutes

it

runs,

of

and

displays

4

5

6

7

Test

specified

plug

results,

Tests

network.

supplied

diagnostic

help

you

program,

program

identify

the

and a step-by-step

or

it

tests

less

reports

(five

being

an

error

performed

Recognizer

is

Message

Passive

NS

echo

run,

5

through

Test

exchange receive server

0

separately.

to

prevent

5

through

and

A

to

7

must

brief

network keep

with

equipment

procedure

minutes

its

progress

message

test

through

Test Tests

test be

run

description

your

called

hardware

and

in

an by

and

if

test

Test

7

3

are

and

activity

packets

while

of

a a

4 4

TEST 0

Test

0 executed. and

internal back Host

to and

displayed.

TEST 1

Test

1

tests

Programmed

resets

These

the

Adapter

I/O

and

Host

the

data

the

Adapter

include

external

and

can

interface

transfers.

causing 80186 loopback

displayed.

not

be

between

the

and

82586

tests.

If

communication

established,

the

55

self-test

initialization,

The

an

Host

and

routines results error

the

are

between

message

Adapter

to

be

memory

passed

the

is

using

TEST 2

Test DMA

TEST 3

Test

2

data

3 test. 82586

LAN

compares

TEST ..

Test The

4

receiver

multicast,

differing ability tested.

TEST 5

Test

5 network. network.

(echo)

tests

the

transfers.

performs

The

transmit

controller

the

tests

received

the

broadcast,

destination

of

the

performs

The

A

back

to

interface

a

transmit

following

82586

is

configured

Adapter

packet

PC

transmits

responding

the

PC

between

test

checks

packets

LAN

controller

and

promiscuous. address to

reject

exchange

server

under

and,

transmits.

with

to

and

an

the

test.

the

for

those

various

size

or

with

"echo or

PC

Host

if

successful,

the

transmitted.

address

In are

accept

another

request

will

and

correct

Loopback

matching

modes;

each

transmitted

packets

PC

transmit

the

Adapter

status

station

mode,

or

packet"

a

loopback from

test

functions.

packets

properly

server

into

the

using

further

only,

and

on

packet

the

of

the

is

the the

TEST ,

Test This

6

tests

diagnostic This the

TEST 7

test

transmit

Designates packets

until

a

detects

is

this

with

key

legal

the

tool

for

"passive"

capability

PC

PCs

is

depressed.

packets

adapter's

locating

as

an

running

to of

"echo

Test

on receive problems

the

network

another

server",

5.

56

the

PC

network

function elsewhere and

on

which

The

PC

can

the

remains

and

and on

be

used

network.

is

used

counts

provides

the

to

in

network.

to

exchange

this

them.

a

check

mode

FORMAT

3C505

PROGRAM

Ix

Test

Interrupt

Dx

Bxxx

Test Sets

hexadecimal

address

The Enter

S 6 7 -

E

Used

remote should servers

3C50S this EtherSeries network

[-Ix][-Dx][-Bxxx](-#][-E][-T]

PARAMETERS

uses

interrupt

3.

uses

the

default

Message

Passive

NS

with

option

DMA

jumpers

5,

6

echo

nodes

be

or

running

will

channel

base

address

digits). value

or

7

to

exchange

receive server

test

during

used

if

there

3C505

is

not

echo

reply

x,

This

on

the

is

300

select

test

S

only. the

on a Xerox

is

-7

specified,

requests,

using

x,

default

of

the

option EtherLink hex.

one

of

Use

message

NS another to

reply

and any

EtherSeries

is

DMA

EtherLink

should

card

the

NS

following

echo

exchange

8000

PC

to

the

network

with

the

diagnostic

EtherSeries

protocol.

(factory

1. card

be

have

protocol

test.

a

echo

to

used

been

that

3Com

setting)

xxx

if

the changed.

test.

to

This

have

EtherLink

request.

will

generate

server

is

(three

I/O

access option

echo

If

on

the

T

Specifies requires

Requirements

For

1.

2.

testing, A

loopback

Another server

The packets

second

over

for

you

IBM

that PC

the

that

special

Testing

need:

plug;

PC

is

will

network

the

Host

treatment.

on

the

connected

be

used

with

computer

network

to

as

an the

57

the

network.

echo

computer

is

a

OR

an

server,

TI

Professional

EtherSeries

which

under

test.

will

which

network

exchange

RUNNING THE

3CSOS.EXE

PROGRAM

To

start network, diskette

A> 3CSOS

Remember were

changed.

indicating

it

detects

o

To

1.

thru

:run

4

Tes-~

An

OR

2.

the

Another

server

A> 3CSOS

OR

the

3C505.EXE

attach

in

drive

to

give

which

an

error,

mentioned

5,

connect

EtherSeries

PC,

running

-7

a

loopback

A:

and

the test

As

option the

is

the

above

network

with

an

3C505.EXE

program,

type:

program

being

test

will

the

PC

EtherLink

plug

-I, performed

stops

start to

server

on

disconnect

to

the

-D, runs,

one

the

3C505

this

ENC

connector,

-B

if

it

and

displays

after

.l:Ai:'.d;;'work

as

a

diskette

your

the

factory

prints

the

progress.

another.

with

echo

by

PC

a

message.

either:

server.

typing:

from insert

settings

a

message

the the

Once Test

start

3.

Another

echo

specific

If

the

If

the

server.

EtherLink

A>

3C501

echo

A>

3C50S

echo

A>

3C505

PC

7

server

-5

server

-5

with

Use

-E

the

such

is

another

diagnostic

as

case

type

the

3C501

2

mentioned

3

mentioned

of

3Com program and

EtherLink

type:

above,

supplied

then

acting

type:

with

as

that

an

58

3C501

/

3C505

DIAGNOSE

PROGRAM

DIFFERENCES

The

3C505.EXE 3C501.EXE familiar DMA,

Echo The the

in

o o

Packet, server) actual

3C505

the

3C505

there

command channel,

o

tests

Packet,

(i.e.,

o

tests exchange,

After

system

use

running

or

download

expected.

diagnostic

(or

DIAGNOSE.COM

with

the

Recognizer,

have

interpretation

are,

however,

diagnostic,

is

an

additional

line

_0

etc.

through

for

Recognizer)

you

0

cannot

through

Passive

3C505.EXE,

reinitializethe

software

3C501 been

carried

switches

the

4-'

use

4

are receive,

or

is

modeled

in

earlier

diagnostic,

Message

forward

and

implementation

very

test

different.

0

(to

test)

are

(Adapter

are

always

tt3C505

skipped

NS

you

might

3C505.

if

a

particular

exchange,

(Adapter

set

always

Self

tt

-3

to

when

Echo

find

This

after

versions).

all

test

into

It

self

adapter

preceded

test,

executed

run test server)

it

is

3C505

the

For types Passive

the

3C505

of

these

is

worth

test)

base

Preliminary

one

Packet 5,

6,

is

selected.

necessary

especially

configuration

3C501

version,

those

(Preliminary,

receive, diagnostic.

tests

noting

;

address,

by

a

dash

after

test

or

only);

7

reboot

true

of

you

NS

for

that

DMA

It-"i

"

DMA,

another

(Message

your

if

you

is

59

APPENDIX D

3D

DEBUGGER

3D

the

is

3C505

PC-DOS; Register can set,

3D

start, and

requires Mouse the

Compaq

COM2 beware version

3C50S

Slave

interrupt

single

3D

divides these tile

registers, control

typein

status

a

program

adapter.

the

with

clear

Systems

port.

of

conflicts.

of

can

to

install

vectors

step

are

tile

area

of from

and

3D

the

stop,

breakpoints;

an

IBM

PC

portable

Recall

3D

must

also

and

the

area, is I/O

the

3CSOS.

the

error

for

loading 3D

Host

"slave",

and

PC

mouse.

and that

be

set

itself

will

to

use

display

for

display

registers,

user.

messages

runs

program

a

single-step

download,

with

2S6K

3D

Zenith

COM2

The

base

set

to

the

at

boot

point

breakpoints

into

menu

The

bar,

typein

The

from

and

on

an

debugging

IBM

communicates

small

program the

of

memory,

also

runs

Z-lS0.

always

I/O

310

hex.

"1"

position;

time.

to

the

will

four

regions!

typein,

and

alteration

and

memory.

area

message

3D.

programs

PC

(or

compatible), through in

the

3C505's

modify,

one

on

IBM

Attach

uses

address~of

interrupt

The

80186

and

serial

compatibles

the the

TEST

this

All

3D

"exception" Slave. be

enabled.

from

and

message

of

The

displays

area

is

for

3C505

examine

jumper

causes

The

top

3C50S

menu

the

that

the

run

Command

ROM.

processor;

memory.

port,

such

mouse

to

level

3CS05

in on the

and

ability

to

area.

internal

bar

accumulated

display

under

and

3

this

unused

bottom

is

on

3D

a

as

the

so

the

3D to

The

for

of

*AX *BX

ex

DX

*40:8

40:0A 40:0C 40:0E 40:10 40:12 40:14

40:16 40:18

40:1A 40:1C 40:1! 40:20 40:22 40:24

Boot!

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64

APPENDIX E

The

3C505

diagnostic utility program Appendix

subroutines range

of

drivers

All Macro

assembly

Assembler

subroutines conventions

In

the

file

ASM

SM8086.MAC

Software

PSEG ENDPS DSEG EN

DDS

EtherLink

subroutines

that

C

uses and

are

functions

or

standalone

language

adhere

required

files,

Diskette).

defines defines

-

defines

-

defines

3CSOS

program,

the the

all

written

(Version

to you

(which

start

end start end

USER

Developer's and

definition

utilities.

3D

Debugger

in

that

can

programs.

subroutines

3.00)

the

object

by

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will

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of of

see

is

not

defines

of

program

of

data

SOFTWARE

Software

the

3D

The

in

assembly

be

incorporated

are

conventions.

code,

Lattice

references

on

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following segment

segment

DISKETTE

Diskette

Debugger,

files,

diagnostic

Appendix

language

,coded

linkage,

C

Compiler

to

3C505

a

and

an

is

D.

and

in

resident

using

-In

addition,

and

(Version

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Lattice

EtherLink

macros:

contains

collection

example

discussed The

implement

the

Microsoft

function

Developer's

host

utility

device

many

call

2.14).

C

macro

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of

in

a

If

you

suit

do

your

constant

far

calls

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following

IO.ASK

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file

3C505.

base

I/O implement Chapter

subroutines

DMA.ASK

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file

variables

should the

be

IBM PC completion

not particular

LPROG.

be

EtherLink

files:

contains

The

address

the

4

of that

contains

for

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interrupts

use

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used.

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subroutines

subroutine

of

Primary

the

Software

manage

an

IBM first

plus

5-7

Lattice needs. set,

Developer's

IO

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3C505.

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the

all PC

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C

Compiler,

The LPROG define

that

INIT

Block Developer's state

DMA IBM

AT

the

IBM

handled

file specifies

it

Software

perform

should

The

of

DMA

channel AT). in

define

SM8086.MAC

that

or

remove

Diskette

programmed

be

called

subroutines

(PCB)

protocol

Manual.

the

Host

subroutines

The

number

DMA

this

module.

these

also

long

it

as

pointers needed.

contains

first OUTPCB

described

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subroutine

to

transfers

macros

defines

I/O

to

with

and are

Register.

and

global

DMA_INIT

use

(0-3

and

to the and

the

the the

INPCB

in

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on

DMA

65

INT.ASM

.

This

IBM

file

PC first allowed

subroutines this

CMD.ASM

file.

or

with

on

contains

IBM

AT

the

to

host.

interrupt

IBM

PC

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subroutines

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vector

plus

9-15

disable,

to

handle

subroutine

number

on

the and

INT

to-use

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3C505

INIT

AT)

interrupts

(channel

•

acknowledge

should

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interrupts

be

3-7

are

in

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called

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in

Command

Register subroutine pointers. main buffer

UTIL.ASM

This

Lattice

HOSTIO.DEF

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interrupt

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contains

C

programs.

is

the registers included IBM

ADAPTER.DEF

PC

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for

and

definition

SOH-SSH.

interrupts

CMD

When a Command

INIT

handler,

must

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Register

CMDINT

PCB. -

and IBM

general

definition to

each

the

AT.

file

DMA

purpose

file bit and

in interrupt

equates

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are

serviced

called

is

utility

that

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names

for

first interrupt called

subroutines

equates

register.

controller

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vector

in to

this initialize is

to

read

names

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received

callable

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registers

soft

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module.

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locally

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interrupt defined.

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from

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structures

PCB.H

Definition structures

the

definition

for

file

for

each

for

PCB.

file PCB

that from

C-Ianguage

66

contains

Chapter

programs

the

3.

assembly

that

contains

language

the

DOWN.C

C-lanquage

program

DOWN.EXE

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syntax

3D.EXE

This mode

card.

connected base Appendix

program

of

down

is

of

I/O

source

files

to

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its

usage

[-revg)[-b<base»[-d<dma»

the

file

3C505.

a

is:

I I I I I I I I I I I I I I I I I -

I I I I

debug

verbose

execute hard

Debugger

to

assist

Debugger

host

information

of

PC's

the

The

to

D

1111111_

j'-

3D 3C505 3D the

address

for

DOS

mode;

mode: program

reset

program

requires COM2 3C505 on

the

file

adapter

in

how

DOWN.EXE

to

the

DMA Adapter

dump

all

show

after

that

debugging

a

port.

is

set

to

use

program

3C505

channel

base

PCBs

load

before

address,

download

controls

programs

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to

310

3D.

download

which

adapter

number

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a

special running

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hex.

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address

on PC that Refer

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debug

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mouse

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to

3CSOS.EXE

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describes

is

the

in

3C505

detail

diagnostic

how

to

use

utility

it

67

and

program what

it

file.

tests.

Appendix

C

APPENDIX F

1.

configure In

Revision Configure Revision values

are

pcb_queue rcvycb_queue mc

list

frame

rcv

desc

buffer prog_table rcv

a.

buf

- -

The

desc

number

b.

The

number

equals

Adapter

1.0,

Adapter

2.0, changed.

Size

~536

of

receive

of

the

number

REVISION

2.0

Memory

certain

m~n~mums

Memory command

the

minimums

Rev

l..0

Default 64 14

5

32

6 0 0

22

40 40

8

10 Frame

10 40

Descriptors

buffers.

Receive

of

Buffer

Receive

ROM

are

Rev

2.0

Default

10 20

20 20 10 20

Descriptors

Buffers

must

as

detailed

enforced

Min

should

specified.

be

and

Notes 2 2

o

~

2 2 1 2

normally

allocated

used

below.

the

e e

a,d d

b

in

default

equal

the

In·

the

always

2.

3.

c.

Revision bytes

always

1.

d.

The

is

value really

least

allocated.

e.

One queue-empty

Timeout The

maximum

commands Revision Revision

Timestamp Revision

doubleword wrong.

tick

instead

per equals

4

entry

Values

and

2.0

1.0. and

2.0

timestamp

Also,

2.0

has

entry).

the

is

the

not

Frame

in

and

timeout

system

to

Timer corrects

the

of

25us.

an

additional

The

number

minimum

sufficient

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this

circular

queue-full

value

ROM

32767

ticks

Resolution

a

problem

in

timer

number

of

Receive

that

the

for

and

queue

checking.

that

service

(lOms

where

the

receive

resolution

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of

firmware network

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is

can

routines

per

packet

is

Buffer

entries

Buffers

buffers

wasted

be

specified

tick)

the

high

changed

in specified

will

operation.

to

is

increased from

word

response

to

Queue

the

accept should

simplify

15us

queue

in

127

of PCB

(12-

plus

but

At

be

PCB

in in

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is

per

68

4.

DMA

The

i.e., DMA

Revision

immediately completion

before

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Adapter

int

downloads

80H

transfer

1.0,

after

status.

sending

Proqrams

function and

does

a

successful DMA

the

response

programs

5.

not

initiation

Revision

This

wait

2.0

PCB.

using

DMA

function

for

download

without

waits

utilities

only

it

response

for

initiates

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71

APPEND:IX G

1.

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72

firmware

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at

73

3Com 3C505 Developers Guide

Specifications and Main Features

Frequently Asked Questions

User Manual