ZILOG Z86L8708FSC, Z86L8708PSC, Z86L8708VSC, Z86L8808PSC, Z86L8808SSC Datasheet
...
DS96LV00800
P R E L I M I N A R Y
1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86L88/81/86/87/89/73
1
IR/L
OW
-V
OLTAGE
M
ICROCONTROLLER
FEATURES
■
Low Power Consumption - 40 mW (Typical)
■
Three Standby Modes
– STOP
– HALT
– Low V oltage
■
Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:
– One Programmable 8-Bit Counter/Timer with Two
Capture Registers
– One Programmable 16-Bit Counter/Timer with
One 16-Bit Capture Register
– Programmable Input Glitch Filter for Pulse
Reception
■
Five Priority Interrupts
– Three External
– Two Assigned to Counter/Timers
■
Low Voltage Detection and Standby Mode
■
Programmable Watch-Dog/Power-On Reset Circuits
■
Two Independent Comparators with Programmable
Interrupt Polarity
■
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC (Mask Option), or External Clock
Drive
■
Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3
– All Eight Port 2 Bits at One Time or Not
– Pull-Ups Automatically Disabled Upon Selecting
Individual Pins as Outputs.
■
Maskable Mouse/Trackball Interface on P00 Through
P03.
■
32 kHz Oscillator Mask Option
GENERAL DESCRIPTION
The Z86LXX family of IR (Infrared) CCP
™
(Consumer Controller Processor) Controllers are ROM/ROMless-based
members of the Z8
®
single-chip microcontroller family with
256 bytes of internal RAM. The differentiating factor between these devices is the availability of ROM, and package options. For the 40 and 44-pin devices the use of external memory enables these Z8 microcontrollers to be
used where code flexibility is required. Zilog’s CMOS microcontrollers offers fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation
capabilities, automated pulse generation/reception, and in-
ternal key-scan pull-up resistors. The Z86LXX product line
offers easy hardware/software system expansion cost-effective and low power consumption.
The Z86LXX architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The CCP offers a flexible I/O
scheme, an efficient register and address space structure,
and a number of ancillary features that are useful in many
Device
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Voltage
Range
Z86L88 16 237 23 2.0V to 3.9V
Z86L81 24 237 23 2.0V to 3.9V
Z86L86 32 237 23 2.0V to 3.9V
Z86L87 16 236 31 2.0V to 3.9V
Z86L89 24 236 31 2.0V to 3.9V
Z86L73 32 236 31 2.0V to 3.9V
Note: *General-Purpose
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
2
P R E L I M I N A R Y
DS96LV00800
GENERAL DESCRIPTION (Continued)
consumer, automotive, computer peripheral, and battery
operated hand-held applications.
There are four basic address spaces available to support
a wide range of configurations: Program Memory, Register File, Expanded Register File, and External Memory.
The register file is composed of 256 bytes of RAM. It includes four I/O port registers, 16 control and status registers and the rest are General Purpose registers. The Expanded Register File consists of two additional register
groups (F and D). External Memory is not available on 28pin versions.
To unburden the program from coping with such real-time
problems as generating complex waveforms or receiving
and demodulating complex waveform/pulses, the Z86LXX
family offers a new intelligent counter/timer architecture
with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two
on-board comparators to process analog signals with separate reference voltages (Figure 2).
Notes: All Signals with a preceding front slash, "/", are ac-
tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
Figure 1. Counter/Timers Diagram
HI16
LO16
16-Bit
T16
TC16H
TC16L
HI8 LO8
And/Or
Logic
Clock
Divider
Glitch
Filter
Edge
Detect
Circuit
8-Bit
T8
TC8H
TC8L
8
8
16
8
Input
SCLK
1
2
48
Timer 16
Timer 8/16
Timer 8
8
8
8
8
8
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800
P R E L I M I N A R Y
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1
Figure 2. Functional Block Diagram
Port 0
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
Pref1
P31
P32
P33
/AS
/DS
R/W
/RESET
Port 3
Port 1
Port 2
Register File
256 x 8-bit
ROM
24K/32K x 8
Z8 Core
Register Bus
Internal
Address Bus
Internal Data Bus
Expanded
Register
File
Expanded
Register Bus
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
Machine
Timing
&
Instruction
Control
Power
XTAL
VDD
VSS
P34
P35
P36
P37
4
4
8
I/O Bit
Programmable
R//RL
(44-Pin)
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
4
P R E L I M I N A R Y
DS96LV00800
PIN DESCRIPTION
Figure 3. 28-Pin DIP
Pin Assignments
Figure 4. 28-Pin SOIC
Pin Assignments
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1
P36
P37
P35
28
Z86L88/86/81
DIP
1
14 15
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1
P36
P37
P35
28
Z86L88/86/81
SOIC
1
14 15
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800
P R E L I M I N A R Y
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1
Figure 5. 40-Pin DIP
Pin Assignments
R//W
P25
P26
P27
P04
P05
P06
P14
P15
P07
VDD
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
/AS
/DS
P24
P23
P22
P21
P20
P03
P13
P12
VSS
P02
P11
P10
P01
P00
Pref1
P36
P37
P35
/RESET
40
Z86L73/89/87
DIP
1
20 21
Figure 6. 44-Pin PLCC
Pin Assignments
Z86L73/89/73
PLCC
7
17
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XTAL2
XTAL1
P20
P03
P13
P12
VSS
VSS
P02
P11
P10
P01
P00
1
2818
40
39
29
6
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
6
P R E L I M I N A R Y
DS96LV00800
PIN DESCRIPTION (Continued)
Figure 7. 44-Pin QFP
Pin Assignments
34
44
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XTAL2
XTAL1
P20
P03
P13
P12
VSS
VSS
P02
P11
P10
P01
P00
1
2333
Z86L73/89/87
QFP
11
22
12
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800
P R E L I M I N A R Y
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Table 1. Pin Identification
40-Pin
DIP #
44-Pin
PLCC #
44-Pin
QFP # Symbol Direction Description
26 40 23 P00 Input/Output Port 0 is Nibble Programmable.
27 41 24 P01 Input/Output Port 0 can be configured as
30 44 27 P02 Input/Output A15-A8 external program
34 5 32 P03 Input/Output ROM Address Bus.
5 17 44 P04 Input/Output Port 0 can be configured as a
6 18 1 P05 Input/Output mouse/trackball input.
7 19 2 P06 Input/Output
10 22 5 P07 Input/Output
28 42 25 P10 Input/Output Port 1 is byte programmable.
29 43 26 P11 Input/Output Port 1 can be configured as
32 3 30 P12 Input/Output multiplexed A7-A0/D7-D0
33 4 31 P13 Input/Output external program ROM
8 20 3 P14 Input/Output Address/Data Bus.
9 21 4 P15 Input/Output
12 25 8 P16 Input/Output
13 26 9 P17 Input/Output
35 6 33 P20 Input/Output Port 2 pins are individually
36 7 34 P21 Input/Output configurable as input or output.
37 8 35 P22 Input/Output
38 9 36 P23 Input/Output
39 10 37 P24 Input/Output
2 14 41 P25 Input/Output
3 15 42 P26 Input/Output
4 16 43 P27 Input/Output
16 29 12 P31 Input IRQ2/Modulator input
17 30 13 P32 Input IRQ0
18 31 14 P33 Input IRQ1
19 32 15 P34 Output T8 output
22 36 19 P35 Output T16 output
24 38 21 P36 Output T8/T16 output
23 37 20 P37 Output
20 33 16 /AS Output Address Strobe
40 11 38 /DS Output Data Strobe
1 13 40 R//W Output Read/Write
21 35 18 /RESET Input Reset
15 28 11 XTAL1 Input Crystal, Oscillator Clock
14 27 10 XTAL2 Output Crystal, Oscillator Clock
11 23,24 6,7 V
DD
Power Supply
31 1,2, 34 17,28,29 V
SS
Ground
25 39 22 Pref1 Input Comparator 1 Reference
12 39 R//RL Input ROM/ROMless
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
8
P R E L I M I N A R Y
DS96LV00800
PIN DESCRIPTION (Continued)
Table 2. Pin Identification
28-Pin
DIP & SOIC Symbol Direction Description
19 P00 Input/Output Port 0 is Nibble Programmable
20 P01 Input/Output Port 0 can be configured as
21 P02 Input/Output A15-A8 external program
23 P03 Input/Output ROM Address Bus.
4 P04 Input/Output
5 P05 Input/Output Port 0 can be configured as a
mouse/trackball input.
6 P06 Input/Output
7 P07 Input/Output
24 P20 Input/Output Port 2 pins are individually
25 P21 Input/Output configurable as input or output.
26 P22 Input/Output
27 P23 Input/Output
28 P24 Input/Output
1 P25 Input/Output
2 P26 Input/Output
3 P27 Input/Output
18 Pref1 Input Analog Ref Input
11 P31 Input IRQ2/Modulator input
12 P32 Input IRQ0
13 P33 Input IRQ1
14 P34 Output T8 output
15 P35 Output T16 output
17 P36 Output T8/T16 output
16 P37 Output
10 XTAL1 Input Crystal, Oscillator Clock
9 XTAL2 Output Crystal, Oscillator Clock
8V
DD
Power Supply
22 V
SS
Ground
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800
P R E L I M I N A R Y
9
1
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 8).
CAPACITANCE
T
A
= 25 ° C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Symbol Description Min Max Units
V
CC
Supply V oltage
(*)
–0.3 +7.0 V
T
STG
Storage Temp. –65 °
+150 °
C
T
A
Oper. Ambient
Temp.
†C
Notes: :
* Voltage on all pins with respect to GND.
† See Ordering Information.
Figure 8. Test Load Diagram
From Output
Under Test
150 pFI
Parameter Max
Input capacitance 12 pF
Output capacitance 12 pF
I/O capacitance 12 pF
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
10
P R E L I M I N A R Y
DS96LV00800
DC CHARACTERISTICS
Preliminary
T
A
= 0 ° C to +70 ° C
Typ @
Sym Parameter
V
CC
Min Max 25°C Units Conditions Notes
Max Input Voltage 2.0V
3.9V
7
7
VVIIN <250 µA
I
IN
<250 µA
V
CH
Clock Input
High Voltage
2.0V
3.9V
0.8 V
CC
0.8 V
CC
VCC + 0.3
V
CC
+ 0.3
VVDriven by External
Clock Generator
Driven by External
Clock Generator
V
CL
Clock Input
Low V oltage
2.0V
3.9V
VSS – 0.3
V
SS
– 0.3
0.2 V
CC
0.2 V
CC
VVDriven by External
Clock Generator
Driven by External
Clock Generator
V
IH
Input High Voltage2.0V
3.9V
0.7 V
CC
0.7 V
CC
VCC + 0.3
V
CC
+ 0.3
0.5V
CC
0.5V
CC
V
V
V
IL
Input Low Voltage 2.0V
3.9V
VSS – 0.3
V
SS
– 0.3
0.2 V
CC
0.2 V
CC
0.5V
CC
0.5V
CC
V
V
V
OH1
Output High
Voltage
2.0V
3.9V
VCC – 0.4
V
CC
– 0.4
1.7
3.7
VVI
OH
= –0.5 mA
I
OH
= –0.5 mA
V
OH2
Output High
Voltage (P36,
P37,P00, P01)
2.0V
3.9V
VCC - 0.8
V
CC
- 0.8
VVI
OH
= –7 mA
I
OH
= –7 mA
V
OL1
Output Low
Voltage
2.0V
3.9V
0.4
0.4
0.1
0.2
VVIOL = 1.0 mA
I
OL
= 4.0 mA
V
OL2*
Output Low
Voltage
2.0V
3.9V
0.8
0.8
0.5
0.3
VVIOL = 5.0 mA
I
OL
= 7.0 mA
V
OL2
Output Low
Voltage(P36,
P37,P00,P01)
2.0V
3.9V
0.8
0.8
0.3
0.2
VVIOL = 10 mA
I
OL
= 10 mA
V
RH
Reset Input
High Voltage
2.0V
3.9V
0.8 V
CC
0.8 V
CC
V
CC
V
CC
1.5
2.0
V
V
V
Rl
Reset Input
Low V oltage
2.0V
3.9V
VSS – 0.3
V
SS
– 0.3
0.2 V
CC
0.2 V
CC
0.5
0.9
V
V
V
OFFSET
Comparator Input
Offset V oltage
2.0V
3.9V
25
25
10
10
mV
mV
I
IL
Input Leakage 2.0V
3.9V
-1
-1
1
1
< 1
< 1µAµA
VIN = OV, V
CC
VIN = OV, V
CC
I
OL
Output Leakage 2.0V
3.9V
–1
–1
1
1
< 1
< 1µAµA
VIN = OV, V
CC
VIN = OV, V
CC
I
IR
Reset Input PullUp Current
2.0V
3.9V
–230
–400
-90
–220µAµA
VIN = O
V
VIN = OV‘
I
CC
Supply Current 2.0V
3.9V
10
15
410mA
mA
@ 8.0 MHz
@ 8.0 MHz
1,2
1,2
2.0V
3.9V
250
850
100
500µAµA
@ 32 kHz
@ 32 kHz
1,2,7
1,2,7
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800 P R E L I M I N A R Y 11
1
TA = 0°C to +70°C
Typ @
Sym Parameter
V
CC
Min Max 25°C Units Conditions Notes
I
CC1
Standby Current
(WDT Off)
2.0V
3.9V
3
5
1
4
mAmAHALT Mode
VIN = OV, V
CC
@
8.0 MHz
HALT Mode
V
IN
= OV, V
CC
@ 8.0 MHz
1,2
1,2
2.0V
3.9V
2
4
0.8
2.5
mAmAClock Divide-by-
16 @ 8.0 MHz
Clock Divide-by16 @ 8.0 MHz
1,2
1,2
I
CC2
Standby Current 2.0V
3.9V
8
10
2
3
µAµASTOP Mode
VIN = OV, V
CC
WDT is not
Running
STOP Mode
VIN = OV, V
CC
WDT is not
Running
3,5
3,5
2.0V
3.9V
500
800
310
600
µAµASTOP Mode
VIN = OV, V
CC
WDT is Running
3,5
T
POR
Power-On Reset 2.0V
3.9V
12
5
75
20
18
7
ms
ms
Vram Static RAM Data
Retention V oltage
Vram 0.8 0.5 V 6
V
LV
(Vbo)
V
CC
Low Voltage
Protection
2.15 1.7 V 8 MHz max
Ext. CLK Freq.
4
Notes:
I
CC1
Crystal/Resonator
External Clock Drive
Typ
3.0 mA
0.3 mA
Max
5
5
Unit
mA
mA
Frequency
8.0 MHz
8.0 MHz
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF
3. Same as note [4] except inputs at V
CC
.
4. The V
LV
increases as the temperature decreases.
5. Oscillator stopped.
6. Oscillator stops when VCC falls below Vlv limit
7. 32 kHz clock driver input.
* All Outputs excluding P00, P01, P36, and P37.
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
12 P R E L I M I N A R Y DS96LV00800
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
Figure 9. External I/O or Memory Read/Write Timing
R//W
9
12
18
3
16
13
4
5
8 11
6
17
10
1514
21
Port 0, /DM
Port 1
/AS
/DS
(Read)
Port 1
/DS
(Write)
A7 - A0 D7 - D0 IN
D7 - D0 OUTA7 - A0
19
20
7
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IR/Low-Voltage Microcontroller
DS96LV00800 P R E L I M I N A R Y 13
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AC CHARACTERISTICS
Preliminary
External I/O or Memory Read and Write Timing Table
TA = 0°C to +70°C
8.0MHz
No Symbol Parameter
V
CC
Min Max Units Notes
1 TdA(AS) Address Valid to
/AS Rising Delay
2.0V
3.9V
55
55
ns
ns
2
2 TdAS(A) /AS Rising to Address
Float Delay
2.0V
3.9V
70
70
ns
ns
2
2
3 TdAS(DR) /AS Rising to Read
Data Required Valid
2.0V
3.9V
400
400
ns
ns
1,2
4 TwAS /AS Low Width 2.0V
3.9V
80
80
ns
ns
2
5 Td Address Float to
/DS Falling
2.0V
3.9V
0
0
ns
ns
6 TwDSR /DS (Read) Low Width 2.0V
3.9V
300
300
ns
ns
1,2
7 TwDSW /DS (Write) Low Width 2.0V
3.9V
165
165
ns
ns
1,2
8 TdDSR(DR) /DS Falling to Read
Data Required Valid
2.0V
3.9V
260
260
ns
ns
1,2
9 ThDR(DS) Read Data to /DS Rising
Hold Time
2.0V
3.9V
0
0
ns
ns
2
10 TdDS(A) /DS Rising to Address
Active Delay
2.0V
3.9V
85
95
ns
ns
2
11 TdDS(AS) /DS Rising to /AS
Falling Delay
2.0V
3.9V
60
70
ns
ns
2
12 TdR/W(AS) R//W Valid to /AS
Rising Delay
2.0V
3.9V
70
70
ns
ns
2
13 TdDS(R/W) /DS Rising to
R//W Not Valid
2.0V
3.9V
70
70
ns
ns
2
14 TdDW(DSW) Write Data Valid to /DS
Falling (Write) Delay
2.0V
3.9V
80
80
ns
ns
2
15 TdDS(DW) /DS Rising to Write
Data Not Valid Delay
2.0V
3.9V
70
80
ns
ns
2
16 TdA(DR) Address Valid to Read
Data Required Valid
2.0V
3.9V
475
475
ns
ns
1,2
17 TdAS(DS) /AS Rising to
/DS Falling Delay
2.0V
3.9V
100
100
ns
ns
2
18 TdDM(AS) /DM Valid to /AS
Falling Delay
2.0V
3.9V
55
55
ns
ns
2
19 TdDS(DM) /DS Rise to
/DM V alid Delay
2.0V
3.9V
70
70
ns
ns
20 ThDS(A) /DS Rise to Address
Valid Hold Time
2.0V
3.9V
70
70
ns
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
14 P R E L I M I N A R Y DS96LV00800
AC CHARACTERISTICS
Additional Timing Diagram
Figure 10. Additional Timing
Clock
1
3
4
8
2 2 3
T
IRQ
IN
N
6
5
7 7
Clock
Setup
10
9
Stop
Mode
Recovery
Source
11
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800 P R E L I M I N A R Y 15
1
AC CHARACTERISTICS
Preliminary
Additional Timing Table
TA = 0°C to +70°C
8.0MHz
No Sym Parameter
V
CC
Min Max Units Notes
1 TpC Input Clock Period 2.0V
3.9V
121
121
DC
DC
ns
ns
1
1
2 TrC,TfC Clock Input Rise
and Fall Times
2.0V
3.9V
25
25
ns
ns
1
1
3 TwC Input Clock Width 2.0V
3.9V
37
37
ns
ns
1
1
4 TwTinL Timer Input
Low Width
2.0V
3.9V
100
70
ns
ns
1
1
5 TwTinH Timer Input
High Width
2.0V
3.9V
3TpC
3TpC
1
1
6 TpTin Timer Input
Period
2.0V
3.9V
8TpC
8TpC
1
1
7 TrTin,TfTin Timer Input Rise
and Fall Timers
2.0V
3.9V
100
100
ns
ns
1
1
8A TwIL Interrupt Request
Low Time
2.0V
3.9V
100
70
ns
ns
1,2
1,2
8B TwIL Interrupt Request
Low Time
2.0V
3.9V
5TpC
5TpC
1,3
1,3
9 TwIH Interrupt Request
Input High Time
2.0V
3.9V
5TpC
5TpC
1,2
1,2
10 Twsm Stop-Mode Recovery
Width Spec
2.0V
3.9V
2.0V
3.9V
12
12
5 TpC
5 TpC
ns
ns
ns
ns
7
7
6
6
11 T ost Oscillator
Start-Up Time
2.0V
3.9V
5TpC
5TpC
4
4
12 T wdt Watch-Dog Timer
Delay Time (5 ms)
(10 ms)
(20 ms)
(80 ms)
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
12
5
25
10
50
20
225
80
75
20
150
40
300
80
1200
320
ms
ms
ms
ms
ms
ms
ms
ms
Notes:
1. Timing Reference uses 0.9 V
CC
for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
16 P R E L I M I N A R Y DS96LV00800
AC CHARACTERISTICS
Handshake Timing Diagrams
Figure 11. Port Input Handshake Timing
Data In
1
3
4
5 6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
2
Figure 12. Port Output Handshake Timing
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8 9
10
11
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800 P R E L I M I N A R Y 17
1
AC CHARACTERISTICS
Preliminary
Handshake Timing Table
T
A
= 0°C to +70°C
Data
No Sym Parameter
V
CC
Min Max Direction
1 TsDI(DAV) Data In Setup Time 2.0V
3.9V
0
0
IN
IN
2 ThDI(DAV) Data In Hold Time 2.0V
3.9V
0
0
IN
IN
3 TwDAV Data Available Width 2.0V
3.9V
155
110
IN
IN
4 TdDAVI(RDY) DAV Falling to RDY
Falling Delay
2.0V
3.9V
160
115
IN
IN
5 TdDAVId(RDY) DAV Rising to RDY
Falling Delay
2.0V
3.9V
120
80
IN
IN
6 TdRDYO(DAV) RDY Rising to DAV
Falling Delay
2.0V
3.9V
0
0
IN
IN
7 TdDO(DAV) Data Out to DAV
Falling Delay
2.0V
3.9V
63
63
OUT
OUT
8 TdDAV0(RDY) DAV Falling to RDY
Falling Delay
2.0V
3.9V
0
0
OUT
OUT
9 TdRDY0(DAV) RDY Falling to DAV
Rising Delay
2.0V
3.9V
160
115
OUT
OUT
10 T wRDY RD Y Width 2.0V
3.9V
110
80
OUT
OUT
11 TdRDY0d(DAV) RDY Rising to DAV
Falling Delay
2.0V
3.9V
110
80
OUT
OUT
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
18 P R E L I M I N A R Y DS96LV00800
PIN FUNCTIONS
/DS (Output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (Output, active Low). Address Strobe is pulsed once
at the beginning of each machine cycle. Address output is
through Port 0/Port 1 for all external programs. Memory
address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance
state along with Ports 0 and 1, Data Strobe, and
Read/Write.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.
R//W Read/Write (output, write Low). The R//W signal is
Low when the CCP is writing to the external program or
data memory.
R//RL (input). This pin, when connected to GND, disables
the internal ROM and forces the device to function as a
ROMless Z8. (Note that, when left unconnected or pulled
high to V
CC
, the part functions normally as a Z8 ROM ver-
sion.)
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address
port for interfacing external memory. The output drivers
are push-pull. Port 0 can be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are
used as the handshake control /DAV0 and RDY0. Handshake signal function is dictated by the I/O direction of the
Port 0 upper nibble P07-P04. The lower nibble must have
the same direction as the upper nibble.
For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If
the address range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as I/O while
the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured
by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port.
Port 0 is set in the high-impedance mode (if selected as an
address output) along with Port 1 and the control signals
/AS, /DS, and R//W through P3M bits D4 and D3(Figure
13).
A ROM mask option is available to program 0.4 V
DD
CMOS trip inputs on P00-P03. This allows direct interface
to mouse/trackball IR sensors.
An optional 200 kOhms pull-up is available as a mask option on all Port 0 bits with nibble select.
Note: Internal pull-ups are disabled on any given pin or
group of port pins when programmed into output mode.
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800 P R E L I M I N A R Y 19
1
Figure 13. Port 0 Configuration
Z86LXX
MCU
4
4
Port 0 (I/O or A15 - A8)
Optional
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Out
In
PAD
200 kΩ
* Mask Selectable
Refer to the Z86C17 specification for
application information in utilizing these
inputs in a mouse or trackball application.
Mask
Option
In
0.4 VDD
Trip Point Buffer
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
20 P R E L I M I N A R Y DS96LV00800
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is a multiplexed Address (A7-A0)
and Data (D7-D0), CMOS compatible port. Port 1 is dedicated to the Zilog ZBus®-compatible memory interface.
The operations of Port 1 are supported by the Address
Strobe (/AS) and Data Strobe (/DS) lines, and by the
Read/Write (R//W) and Data Memory (/DM) control lines.
Data memory read/write operations are done through this
port (Figure 14). If more than 256 external locations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z86LXX to
share common resources in multiprocessor and DMA applications. Port1 can also be configured for standard port
output mode..
Figure 14. Port 1 Configuration
Port 1
(I/O or AD7 - AD0)
Optional
Handshake Controls
/DAV1 and RDY1
(P33 and P34)
Z86LXX
MCU
8
OEN
Out
In
PAD
Auto Latch
R ≈ 500 KΩ
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