ZILOG Z86L7908PSC, Z86L7908SSC, Z86L8008PSC, Z86L8008SSC Datasheet
DS97LVO0601
P R E L I M I N A R Y
3-1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86L79/L80
1
L
OW
-V
OLTAGE
M
ICROCONTROLLER
FEATURES
■
Three Standby Modes (Typical)
– STOP - 2 µ A
– HALT - 0.8 mA
– Low Voltage Standby (<V
LV
)
■
Expanded Register File Control Registers
■
Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:
– One Programmable 8-Bit Counter/Timer with Two
Capture Registers
– One Programmable 16-Bit Counter/Timer with
One Capture Register
– Programmable Input Glitch Filter for Pulse
Reception
■
Five Priority Interrupts
■
Low Voltage Detection and Standby Mode
■
Watch-Dog/Power-On Reset Circuits
■
Two Independent Comparators with Programmable
Interrupt Polarity
■
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
■
Mask Selectable 200 kOhm Pull-Ups on Ports 0, 2, 3
– All Eight Port 2 Bits at One Time or Not
– Pull-Ups Automatically Disabled Upon
Selecting Individual Pins as Outputs.
■
Maskable SingleTrip Point Inputs on P00 Through P03.
■
Permanently Enabled WDT Option (Maskable)
■
28-Pin DIP and SOIC Packages
GENERAL DESCRIPTION
The Z86L79/L80 family of IR (InfraRed) Controllers are
ROM-based members of the Z8
®
MCU
single-chip microcontroller family with 237 bytes of general-purpose RAM.
The only differentiating factor between these two versions
is the availability of ROM. Zilog's CMOS microcontrollers
offer fast execution, efficient use of memory, sophisticated
interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and easy hardware/software system expansion along with cost-effective
and low power consumption.
The Z86L7X architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z8
®
MCU offers a flexible
I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in
many consumer, automotive, computer peripheral, and
battery operated hand-held applications.
Part
ROM
(KB)
RAM*
(Bytes) I/O Voltage Range
Z86L79 4 237 24 2.0V to 3.9V
Z86L80 8 237 24 2.0V to 3.9V
Note: *General-Purpose
Z86L79/80
Low-Voltage Microcontroller Zilog
3-2
P R E L I M I N A R Y
DS97LVO0601
GENERAL DESCRIPTION (Continued)
Z8
®
applications demand powerful I/O capabilities. The
Z86L79/80 fulfills this with two package options with 24
pins of dedicated input and output. These lines are
grouped into three ports. Each port consists of eight lines
and is configurable under software control to provide timing, status signals, and parallel I/O.
There are three basic address spaces available to support
a wide range of configurations: Program Memory, Register
File, and Expanded Register File. The Register File is
composed of 256 bytes of RAM. It includes four I/O port
registers, ten control and status registers, and the rest are
general purpose registers. The Expanded Register File
consists of three register groups.
To unburden the program from coping with such real-time
problems as generating complex waveforms or receiving
and demodulating complex waveform/pulses, the Z86L7X
family offers a new intelligent counter/timer architecture
with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two
on-board comparators to process analog signals with separate reference voltages (Figure 2).
Notes: All Signals with a preceding front slash, "/", are ac-
tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
Figure 1. Counter/Timer Block Diagram
HI16
LO16
16-Bit
T16
TC16H
TC16L
HI8 LO8
And/Or
Logic
Clock
Divider
Glitch
Filter
Edge
Detect
Circuit
8-Bit
T8
TC8H
TC8L
8
8
16
8
Input
SCLK
1
2
48
Timer 16
Timer 8/16
Timer 8
8
8
8
8
8
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y
3-3
1
Figure 2. Functional Block Diagram
Port 0
P00
P01
P02
P03
P04
P05
P06
P07
Pref1
P31
P32
P33
Port 3
Register File
256 x 8-Bit
ROM
4K/8K x 8
Z8 Core
Register Bus
Internal
Address Bus
Internal Data Bus
Expanded
Register
File
Expanded
Register Bus
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
Machine
Timing
&
Instruction
Control
Power
XTAL2
VDD
VSS
P34
P35
P36
P37
P20
P21
P22
P23
P24
P25
P26
P27
Port 2
Two Analog
Comparators
Interrupt Control
XTAL1
I/O Bit
Programmable
Z86L79/80
Low-Voltage Microcontroller Zilog
3-4
P R E L I M I N A R Y
PIN DESCRIPTION
Figure 3. 28-Pin DIP Pin Assignments
P24
P25
P26
P27
P03
P04
P05
P06
VDD
XTAL2
XTAL1
P31
P32
P00
P23
P22
P21
P20
P02
P01
P37
PREF1
VSS
P36
P35
P34
P33
P07
28
Z86L79/80
DIP
1
14 15
Figure 4. 28-Pin SOIC Pin Assignments
P24
P25
P26
P27
P03
P04
P05
P06
VDD
XTAL2
XTAL1
P31
P32
P00
P23
P22
P21
P20
P02
P01
P37
Pref1
VSS
P36
P35
P34
P33
P07
28
Z86L79/80
SOIC
1
14 15
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y
3-5
1
Table 1. Pin Identification
28-Pin DIP &
SOIC Symbol Direction Description
14 P00 Input/Output Port 0 is Nibble Programmable.
23 P01 Input/Output
24 P02 Input/Output
5 P03 Input/Output
6 P04 Input/Output Port 0 can be configured as a 0.4 V
DD
single-trip point
7 P05 Input/Output
8 P06 Input/Output
15 P07 Input/Output
25 P20 Input/Output Port 2 pins are individually configurable
as input or output.
26 P21 Input/Output
27 P22 Input/Output
28 P23 Input/Output
1 P24 Input/Output
2 P25 Input/Output
3 P26 Input/Output
4 P27 Input/Output
21 Pref1 Input Analog Ref Input
12 P31 Input IRQ2/Modulator input
13 P32 Input IRQ0
16 P33 Input IRQ1
17 P34 Output T8 output
18 P35 Output T16 output
19 P36 Output T8/T16 output
22 P37 Output
11 XTAL1 Input Crystal, Oscillator Clock
10 XTAL2 Output Crystal, Oscillator Clock
9V
DD
Power Supply
20 V
SS
Ground
Z86L79/80
Low-Voltage Microcontroller Zilog
3-6
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 5).
CAPACITANCE
T
A
= 25 ° C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Sym Description Min Max Units
V
CC
Supply V oltage (*) –0.3 +7.0 V
T
STG
Storage Temp. –65 ° +150 °
C
T
A
Oper. Ambient
Temp.
†C
Notes:
* Voltage on all pins with respect to GND.
† See Ordering Information.
Figure 5. Test Load Diagram
From Output
Under Test
150 pFI
Parameter Max
Input capacitance 12 pF
Output capacitance 12 pF
I/O capacitance 12 pF
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y
3-7
1
DC CHARACTERISTICS
T
A
= 0 ° C to +70 ° C
Typical
Sym Parameter
V
CC
Min Max @ 25 ° C Units Conditions Notes
Max Input Voltage 2.0V
3.9V
7
7
VVI
IN
<250 µ A
I
IN
<250 µ A
V
CH
Clock Input
High V oltage
2.0V
3.9V
0.9 V
CC
0.9 V
CC
V
CC
+ 0.3
V
CC
+ 0.3
V Driven by
External Clock
Generator
V
CL
Clock Input
Low V oltage
2.0V
3.9V
V
SS
– 0.3
V
SS
– 0.3
0.2 V
CC
0.2 V
CC
VVDriven by
External Clock
Generator
V
IH
Input High Voltage 2.0V
3.9V
0.7 V
CC
0.7 V
CC
V
CC
+ 0.3
VCC + 0.3
1.3
2.5
V
V
V
IL
Input Low Voltage 2.0V
3.9V
VSS – 0.3
V
SS
– 0.3
0.2 V
CC
0.2 V
CC
0.5
0.9
V
V
V
OH1
Output High Voltage 2.0V
3.9V
VCC – 0.4
V
CC
– 0.4
1.7
3.7
VVI
OH
= –0.5 mA
I
OH
= –0.5 mA
V
OH2
Output High Voltage
(P36, P37)
2.0V
3.9V
VCC - .8
V
CC
- .8
VVI
OH
= –7 mA
I
OH
= –7 mA
10
V
OL1
Output Low Voltage 2.0V
3.9V
0.4
0.4
0.2
0.1
VVIOL = 1.0 mA
I
OL
= 1.0 mA
V
OL2
Output Low Voltage 2.0V
3.9V
0.8
0.8
0.3
0.3
VVIOL = 2.0 mA
I
OL
= 2.0 mA
V
OL2
Output Low Voltage
(P20-P22, P36, P00,
P01, P07)
2.0V
3.9V
0.8
0.8
0.3
0.5
VVIOL = 10 mA
I
OL
= 10 mA
2 O/P only
9
V
OFFSET
Comparator Input
Offset V oltage
2.0V
3.9V
25
25
10
10
mV
mV
I
IL
Input Leakage 2.0V
3.9V
–1
–1
1
1
<1
<1
µAµAVIN = OV, V
CC
VIN = OV, V
CC
I
OL
Output Leakage 2.0V
3.9V
–1
–1
1
1
<1
<1
µAµAVIN = OV, V
CC
VIN = OV, V
CC
I
IR
Reset Input Current 2.0V
3.9V
–45
–55
–20
–30
µA
µA
I
CC
Supply Current 2.0V
3.9V
2.0V
3.9V
10
15
100
300
4
10
10
10
mA
mA
µA
µA
@ 8.0 MHz
@ 8.0 MHz
@ 32 kHz
@ 32 kHz
4, 5
4,5,11,12
I
CC1
Standby Current 2.0V
3.9V
2.0V
3.9V
3
5
2
4
1
4
0.8
2.5
mA
mA
mA
mA
HALT Mode
VIN = OV, V
CC
@ 8.0 MHz
Clock Divide-by16 @ 8.0 MHz
4,5
4,5
I
CC2
Standby Current 2.0V
3.9V
8
10
1
2
µAµASTOP Mode
VIN = OV, V
CC
WDT is not
Running
6,8
Z86L79/80
Low-Voltage Microcontroller Zilog
3-8 P R E L I M I N A R Y DS97LVO0601
DC CHARACTERISTICS (Continued)
I
CC2
2.0V
3.9V
500
800
310
600
µAµASTOP Mode
VIN = OV, V
CC
WDT is Running
6,8
V
ICR
Input Common Mode
Voltage Range
2.0V
3.9V
0
0
VCC-1.0V
V
CC
-1.0V
V
V
12
T
POR
Power-On Reset 2.0V
3.9V
7.5
2.5
75
20
13
7
ms
ms
V
LV
VCC Low Voltage
Protection
2.15 1.7 V 8 MHz max
Ext. CLK Freq
7
Notes:
1. GND = 0V
2. 2.0V to 3.9V
3. All outputs unloaded, I/O pins floating, inputs at rail.
4. CL1 = CL2 = 100 pF
5. Same as note [4] except inputs at V
CC
.
6. The V
LV
increases as the temperature decreases.
7. Oscillator stopped.
8. Two outputs at a time, independent to other outputs.
9. One at a time.
10. 32 kHz clock driver input.
11. WDT not running.
12. For analog comparator, inputs when analog comparators are enabled.
TA = 0°C to +70°C
Typical
Sym Parameter
V
CC
Min Max @ 25°C Units Conditions Notes
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y 3-9
1
AC CHARACTERISTICS
Additional Timing Diagram
Figure 6. Additional Timing
Clock
1
3
4
8
2 2 3
T
IRQ
IN
N
6
5
7 7
Clock
Setup
10
9
Stop
Mode
Recovery
Source
11
Z86L79/80
Low-Voltage Microcontroller Zilog
3-10 P R E L I M I N A R Y
AC CHARACTERISTICS
Additional Timing Table
T
A
= 0°C to +70°C
No Symbol Parameter
V
CC
Min Max Units Notes
1 TpC Input Clock Period 2.0V
3.9V
121
121
DC
DC
ns
ns
1
1
2 TrC,TfC Clock Input Rise
and Fall Times
2.0V
3.9V
25
25
ns
ns
1
1
3 TwC Input Clock Width 2.0V
3.9V
37
37
ns
ns
1
1
4 TwTinL Timer Input Low
Width
2.0V
3.9V
100
70
ns
ns
5 TwTinH Timer Input
High Width
2.0V
3.9V
3TpC
3TpC
1
1
6 TpTin Timer Input Period 2.0V
3.9V
8TpC
8TpC
1
1
7 TrTin,TfTin Timer Input Rise
and Fall Timers
2.0V
3.9V
100
100
ns
ns
1
1
8A TwIL Interrupt Request
Low Time
2.0V
3.9V
100
70
ns
ns
1,2
1,2
8B TwIL Int. Request
Low Time
2.0V
3.9V
3TpC
3TpC
1,3
1,3
9 TwIH Interrupt Request
Input High Time
2.0V
3.9V
3TpC
3TpC
1,2
1,2
10 Twsm Stop-Mode
Recovery
Width Spec
2.0V
3.9V
2.0V
3.9V
12
12
5TpC
5TpC
ns
ns
8
8
7
7
11 Tost Oscillator
Start-up Time
2.0V
3.9V
5TpC
5TpC
4
4
12 Twdt Watch-Dog Timer
Delay Time (5 ms)
2.0V
3.9V
12
5
75
20
ms
ms
D0 = 0 [5]
D1 = 0 [5]
15 ms 2.0V
3.9V
25
10
150
40
ms
ms
D0 = 1 [5]
D0 = 1 [5]
25 ms 2.0V
3.9V
50
20
300
80
ms
ms
D0 = 0 [5]
D0 = 0 [5]
100 ms 2.0V
3.9V
225
80
1200
320
ms
ms
Notes:
1. Timing Reference uses 0.9 V
CC
for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0
5. Reg. WDTMR
6. 2.0V to 3.9V
7. Reg. SMR – D5 = 0
8. Reg. SMR – D5 = 1
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y 3-11
1
AC CHARACTERISTICS
Handshake Timing Diagram
Figure 7. Port I/O with Input Handshake Timing
Data In
1
3
4
5 6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
2
Figure 8. Port I/O with Output Handshake Timing
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8 9
10
11
Z86L79/80
Low-Voltage Microcontroller Zilog
3-12 P R E L I M I N A R Y
AC CHARACTERISTICS
Preliminary
Handshake Timing Table
TA = 0°C to +70°C
8 MHz Data
No Symbol Parameter
V
CC
Min Max Direction
1 TsDI(DAV) Data In Setup Time 2.0V
3.9V
0
0
IN
IN
2 ThDI(DAV) Data In Hold Time 2.0V
3.9V
160
115
IN
IN
3 TwDAV Data Available Width 2.0V
3.9V
155
110
IN
IN
4 TdDAVI(RDY) DAV Falling to RDY
Falling Delay
2.0V
3.9V
160
115
IN
IN
5 TdDAVId(RDY) DAV Rising to RDY
Falling Delay
2.0V
3.9V
120
80
IN
IN
6 TdRDYO(DAV) RDY Rising to DAV
Falling Delay
2.0V
3.9V
0
0
IN
IN
7 TdDO(DAV) Data Out to DAV
Falling Delay
2.0V
3.9V
63
63
OUT
OUT
8 TdDAV0(RDY) DAV Falling to RDY
Falling Delay
2.0V
3.9V
0
0
OUT
OUT
9 TdRDY0(DAV) RDY Falling to DAV
Rising Delay
2.0V
3.9V
160
115
OUT
OUT
10 TwRDY RDY Width 2.0V
3.9V
110
80
OUT
OUT
11 TdRDY0d(DAV) RDY Rising to DAV
Falling Delay
2.0V
3.9V
110
80
OUT
OUT
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y 3-13
1
PIN FUNCTIONS
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers
are push-pull in this configuration.
Using single trip point ROM mask option, Port 00-03 can
be programmed to allow direct interface to applications
that require single point comparison like mouse/trackball
IR sensors. ROM mask option will enable the 0.4 VDD trip
Point Buffers on these inputs.
An optional 200 kOhms (port wide) pull-up is available as
a mask option on all bits for the L79/L80 versions.
These pull-ups are disabled when configured (bit by
bit) as an output.
Figure 9. Port 0 Configuration
Z86L7X
MCU
4
4
Port 0 I/O
OEN
Out
In
PAD
200 kΩ
**Mask Selectable
Mask
Option
In
0.4 VDD
Trip Point Buffer
**
0.5 VDD
Trip Point Buffer
Z86L79/80
Low-Voltage Microcontroller Zilog
3-14 P R E L I M I N A R Y DS97LVO0601
PIN FUNCTIONS (Continued)
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS
compatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask
option is available to connect eight 200 kOhms (±50%)
pull-up resistors on this port. Bits programmed as outputs
are globally programmed as either push-pull or opendrain. Port 2 may be placed under handshake control. In
this configuration, Port 3 lines, P31 and P36 are used as
the handshake controls lines /DAV2 and RDY2. The hand-
shake signal assignment for Port 3, lines P31 and P36 is
dictated by the direction (input or output) assigned to Bit 7,
Port 2 (Figure 6). The CCP wakes up with the eight bits of
Port 2 configured as inputs with open-drain outputs.
Port 2 also has an 8-bit input NOR and an NAND gates
which can be used to wake up the part from STOP mode
(Figure 38). P20 can be programmed to access the edge
selection circuitry (Figure 10).
Figure 10. Port 2 Configuration
Open-Drain
OEN
Out
In
PAD
Port 2 (I/O)
Optional
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
Z86L7X
MCU
VCC
200 kΩ
Mask
Option
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y 3-15
1
Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three
fixed input and four fixed output port. Port 3 consists of
three fixed input (P33-P31) and four fixed output (P37P34), and can be configured under software control for Input/Output, Interrupt, Port handshake, Data Memory functions and output from the counter/timers. P31, P32, and
P33 are standard CMOS inputs; outputs are push-pull, except for P34, 35 which are controlled by P3M, D0.
Two on-board comparators process analog signals on P31
and P32 with reference to the voltage on Pref1 and P33.
The analog function is enabled by programming the Port 3
Mode Register (bit 1). P31 and P32 are programmable as
rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the edge detection circuit is
through P31 or P20. Handshake lines Ports 0, 1, and 2 are
available on P31 through P36.
Port 3 provides the following control functions: handshake
for Ports 0, and 2 (/DAV and RDY); four external interrupt
request signals (IRQ3-IRQ0). (See Table 2).
Port 3 also provides output for each of the counter/timers
and the AND/OR Logic. Control is performed by programming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.
Comparator Inputs. Port 3, P31 and P32 all have a comparator front end. The comparator reference voltages are
on P33 and Pref1. The internal P33 register and its corresponding IRQ1 is connected to the Stop-Mode Recovery
source selected by the SMR. In this mode, any of the StopMode Recovery sources can be used to toggle the P33 bit
or generate IRQ1. In digital mode, P33 can be used as a
Port 3 register input or IRQ1 for P33 (Figure 8).
Note: The comparators are disabled in STOP mode.
Comparator Outputs. These may be programmed to be
outputted on P34 and P37 through the PCON register (Figure 11).
Table 2. Pin Assignments
Pin I/O C/T Comp. Int. P0 HS P2 HS
Pref1 IN RF1
P31 IN ISP AN1 IRQ2 D/R
P32 IN AN2 IRQ0 D/R
P33 IN RF2 IRQ1
P34 OUT T8 A01
P35 OUT T16 R/D
P36 OUT T8/16 R/D
P37 OUT A02
Notes:
1. HS = Handshake Signals
2. D = /DAV
3. R = RDY
Z86L79/80
Low-Voltage Microcontroller Zilog
3-16 P R E L I M I N A R Y DS97LVO0601
PIN FUNCTIONS (Continued)
Figure 11. Port 3 Comparator Configuration
P34 OUT
P37 OUT
P32
+
-
REF2
(P33)
0 = P34, P37 Standard Output
1 = P34, P37 Comparator Output
PCON
D0
P31
+
-
Pref1
P37
PAD
P34
PAD
*
T8
P34 OUT
0 Normal Control*
1 8-bit Timer output active
CTR0
D0
Counter/Timer
Reset condition.
*
Z86L79/80
Zilog Low-Voltage Microcontroller
P R E L I M I N A R Y 3-17
1
Reset. Program execution begins at location 000CH, 5-10
TpC cycles after the RST is released. For Power-On Reset, the typical reset output time is 5 ms. The Z86L7X does
not reset WDTMR, SMR, P2M or P3M registers on a StopMode Recovery operation either from WDT or the programmed STOP mode recovery source.
Figure 12. Port 3 Configuration
Port 3
(I/O or Handshake)
Z86L7X
MCU
Pref1
P31
P32
P33
P34
P35
P36
P37
Note:
P31, 32, 33 have a 200 KΩ
mask option.
200 KΩ
Mask
Option
D1
R247 = P3M
P31 (AN1)
P32 (AN2)
P33 (REF2)
From Stop-Mode
Recovery Source
1 = Analog
0 = Digital
IRQ2, P31 Data Latch
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
DIG.
AN.
-
+
-
+
Pref1
Z86L79/80
Low-Voltage Microcontroller Zilog
3-18 P R E L I M I N A R Y DS97LVO0601
PIN FUNCTIONS (Continued)
Figure 13. Port 3 Configuration
VDD
Out P34
T8_Out
CTR0, D0
Pad
Out P35
T16_Out
CTR2, D0
Out P36
T8/16_Out
CTR1, D6
P34
VDD
Pad
P35
VDD
Pad
P36
MUX
MUX
MUX
P3M D0
open-drain
P3M D0
open-drain
* Default after reset output is push-pull.
*
*
*
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