XILINX XCV812E-8FG900I, XCV812E-8FG900C, XCV812E-8BG560I, XCV812E-8BG560C, XCV812E-7FG900I Datasheet

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DS025-1 (v1.4) April 2, 2001 www.xilinx.com Module 1 of 4

Preliminary Product Specification 1-800-255-7778 1

Features

• Fast, Extended Block RAM, 1.8 V FPGA Family

- 560 Kb and 1,120 Kb embedded block RAM

- 130 MHz internal performance (four LUT levels)

- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz

• Sophisticated SelectRAM+™ Memory Hierarchy

- 294 Kb of internal configurable distributed RAM

- Up to 1,120 Kb of synchronous internal block RAM

- True Dual-Port™ block RAM

- Memory bandwidth up to 2.24 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)

- Designed for high-performance Interfaces to
external memories

· 200 MHz ZBT* SRAMs

· 200 Mb/s DDR SDRAMs

• Highly Flexible SelectIO+™ Technology

- Supports 20 high-performance interface standards

- Up to 556 singled-ended I/Os or up to 201
differential I/O pairs for an aggregate bandwidth of
>100 Gb/s

• Complete Industry-Standard Differential Signalling
Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Al I/O signals can be input, output, or bi-directional

- LVPECL and LVDS clock inputs for 300+ MHz
clocks

• Proprietary High-Performance SelectLink™
Technology

- 80 Gb/s chip-to-chip communication link

- Support for Double Data Rate (DDR) interface

- Web-based HDL generation methodology

• Eight Fully Digital Delay-Locked Loops (DLLs)

• IEEE 1149.1 boundary-scan logic

• Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

- Internet Team Design (Xilinx iTD™) tool ideal for

million-plus gate density designs

- Wide selection of PC or workstation platforms

• SRAM-based In-System Configuration

- Unlimited re-programmability

• Advanced Packaging Options

- 1.0 mm FG676 and FG900

-1.27mm BG560

• 0.18

m

m 6-layer Metal Process with Copper

Interconnect

• 100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

Introduction

The Virtex™-E Extended Memory (Virtex-EM) family of
FPGAs is an extension of the highly successful Virtex-E
family architecture. The Vi rtex-EM family (devices shown in

Table 1) incl udes all of the features of Vir tex-E, plus addi-

tional block RAM, useful for applications suc h as network
switches and high-performance video graphic systems.

Xilinx developed the Virtex-EM product family to enable
customers to d es ign sy ste ms requiring high me mory band­width, such as 160 Gb/s network switches. Unlike traditional
ASIC devices, this family also supports fast time-to-market
delivery, because the development engineering is alre ady
completed. Just complete the design and program the
device. There is no NRE, no silicon production cycles, and no

additional del ays fo r design re-work. In additio n, designers
can update the design over a network at any time, providing
product upgr a de s or up d at es to cu st om ers even sooner.

The Virtex-EM family is the result of more than fifteen years
of FPGA design experience. Xilinx has a history of support­ing customer applic ations by providing the highest level of
logic, RAM, and features available in the industr y. The Vir­tex-EM family, first FPGAs to deploy copper interconnec t,
offers the performance and high memory bandwidth for
advanced system integration without the initial investment,
long development cycles, and inventory risk expected in tra­ditional ASIC development.

0

Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays

DS025-1 (v1.4) April 2, 2001

00

Preliminary Product Specification

R

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

R

Module 1 of 4 www.xilinx.com DS025-1 (v1.4) April 2, 2001
2 1-800-255-7778 Preliminary Product Specification

Virtex-E Compared to Virtex Devic es

The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.

I/O performance is increased to 622 Mb/s using Source
Synchronous data transm iss ion ar chite ctures and sy nchr o­nous system performance up to 240 MHz using sin­gled-ended SelectI/O technology. Additional I/O stan dards
are supporte d, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pin s can be use d
for these new standards.

Virtex-E devices have up to 640 Kb of faster (250MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Vir tex devices. Each indi­vidual DLL is slightly improved with easier clock mirro ring
and 4x frequency multiplication.

V

CCINT

, the supply voltage for the inter nal logic and mem­ory, is 1.8 V, instead of 2.5 V for Vir tex devices. Advanced
processing and 0.18

m

m design rules have resulted in

smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an

external 100

W

resistor. PCI 5 V is not supported. With th e
addition of appropr ia te external resistors, any pin can to ler ­ate any voltage desired.

Banking rules are different. With Virtex devices, all input
buffers are powered by V

CCINT

. With Vir tex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V

CCO

.

The Virtex-E family is not bitstream-compatible with the Vir­tex family, but Vir tex designs can be compiled into equiva­lent Virtex-E devices.

The same device in the same package for the Virt ex-E and
Virtex families are pin-compatible with some minor excep­tions. See the data sheet pinout section for details.

General Description

The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18

m

m CMOS process. These

advances make Virtex-E FPGAs powerful and flexible alter-

natives to mask-programmed gate arrays. The Virtex-E fam­ily includes the nine members in Table 1.

Building on experience gain ed from Vir tex FPGAs, the Vir­tex-E family is an evolutionary step forward in programma­ble logic design. Combining a wide variety of programmable
system features, a rich hi erarchy of fast, flexible intercon­nect resources, and advanced process te chnology, the Vir­tex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.

Virtex-E Archite cture

Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur­rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile r outing
resources. The abundance of routing resources permits the
Virtex-E family to acco mmodate even the largest a nd most
complex designs.

Virtex-E FPGAs are SRAM-based, a nd are customized by
loading configuratio n data into inte rnal memor y cells. Con­figuration data can be read from an external SPROM (mas­ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).

The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Vi rtex-E, covering every aspect fr om b ehavioral
and schematic entr y, through simulation, auto matic design
translation and implementati on, to the creation and down­loading of a configuration bit stream.

Higher Performance

Virtex-E devices provide bette r performance than previous
generations of FPGAs. Designs c an achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech­tures. Virtex-E I/Os comp ly fully with 3.3 V PCI specifica­tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.

While performance is design-dependent, many designs
operate internall y at spe eds in excess of 133 MHz an d can
achieve over 311 MHz. Table 2, page 3, shows perfor-
mance data for representative circuits, using worst-case
timing parameters.

Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members

Device Logic Gates CLB Array

Logic

Cells

Differential

I/O Pairs User I/O

BlockRAM

Bits

Distributed

RAM Bits

XCV405E 129,600 40 x 60 10,800 183 404 573,440 153,600
XCV812E 254,016 56 x 84 21,168 201 556 1,146,880 301,056