XILINX XC95144XV Product Specification

查询XC95144XV供应商

0

R

DS051 (v2.2) August 27, 2001

01

Features

• 144 macrocells with 3,200 usable gates

• Available in small footprint packages

- 100-pin TQFP (81 user I/O pins)

- 144-pin TQFP (117 user I/O pins)

- 144-pin CSP (117 user I/O pins)

• Optimized for high-perfo rmance 2.5V systems

- Low power operation

- Multi-voltage operation

• Advanced syste m features

- In-system programmable

- Two separate output banks

- Superior pin-locking and routability with
FastCONNECT II™ switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with
individual product-term allocation

- Local clock inversion with three global and one
product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin
inputs

- Bus-hold ciruitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase
cycles

- 20 year data retention

- ESD protection exceeding 2,000V

Description

The XC95144XV is a 2.5V CPLD targeted for high-perfor­mance, low-voltage applications in leading-edge communi­cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 4 ns.

XC95144XV High-Performance
CPLD

Advance Product Specification

Power Estimation

Power dissipation in CPLDs can vary substantially depend­ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In ad di­tion, unused product-terms and macrocells are automati­cally deactivated by the software to further conserve power.

For a general estimate of I
used:

(mA ) =

I

CC

(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f

MC

HP

Where:
MC

= Macrocells in high-performance (default) mode

HP

MC

= Macrocells in low-power mode

LP

MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.

Figure 1 shows the above estimation in a graphical form.

200

150

(mA)

100

CC

High Performanc

w

o

Typical I

50

0120200

L

Figure 1: Typical ICC vs. Frequency for XC95144XV

, the following equation may be

CC

CC

120 MHz

e

ower

P

Clock Frequency (MHz)

value varies

200 MHz

16040 80

DS051_01_012501

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS051 (v2.2) August 27, 2001 www.xilinx.com 1

Advance Product Specificati on 1-800-255-7778

XC95144XV High-Performance CPLD

R

JTAG Port

I/O/GCK
I/O/GSR

I/O/GTS

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O

3

1

JTAG

Controller

In-System Programming Controller

54

18

Function

Block 1

Macrocells

1 to 18

54

18

Function

Block 2

Macrocells

I/O

1 to 18

Blocks

54

18

Function

Block 3

Macrocells

FastCONNECT II Switch Matrix

1 to 18

3
1

18

4

54

Function

Block 4

Macrocells

1 to 18

54

18

Function

Block 8

Macrocells

1 to 18

DS051_02_041000

Figure 2: XC95144XV Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2 www.xilinx.com DS051 (v2.2) August 27, 2001

1-800-255-7778 Advance Product Specification

R

XC95144XV High-Performance CPLD

Absolute Maximum Ratings

Symbol Description Value Units

V

CC

V

CCIO

V

IN

V

TS

T

STG

T

SOL

T

J

Notes:

1. Maximum DC unders hoot bel ow GND must be l imit ed to ei ther 0. 5V or 10 m A, whi chever is easi er to a chie v e . Durin g tra nsitions , the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operation of t he device at these or any other condit ions beyond those list ed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliab ility.

Supply voltage relative to GND –0.5 to 2.7 V
Supply voltage for output drivers –0.5 to 3.6 V
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient) –65 to +150
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
Junction temperature +150

(1)

(1)

–0.5 to 3.6 V
–0.5 to 3.6 V

o
o
o

C
C
C

Recommended Operation Conditions

Symbol Parameter Min Max Units

V

CCINT

V

CCIO

Supply voltage for internal logic
and input buffers

Supply voltage for output drivers for 3.3V operation 3.13 3.46 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V

Commercial TA = 0oC to +70oC2.372.62 V
Industrial T

= –40oC to +85oC2.372.62

A

Supply voltage for output drivers for 1.8V operation 1.71 1.89 V

V

IL

V

IH

V

O

Low-level input volt ag e 0 0.8 V
High-level input voltage 1.7 3.6 V
Output voltage 0 V

CCIO

Quality and Reliability Characteristics

Symbol Parameter Min Max Units

V

T
N

ESD

DR

PE

Data retention 20 - Years
Program/Erase cycles (endurance) 10,000 - Cycles
Electrostatic Discharge (ESD) 2,000 - Volts

V

DS051 (v2.2) August 27, 2001 www.xilinx.com 3

Advance Product Specificati on 1-800-255-7778