XILINX XC95144 Product Specification
查询XC95144供应商
1
December 4, 1998 (Version 4.0)
11*
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
to 111 MHz
CNT
• 144 macrocells with 3,200 usable gates
• Up to 133 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
XC95144 In-System Programmable
CPLD
Product Specification
Operating current for each design can be approximated for
specific operating conditions using the following equation:
(mA) =
I
CC
(1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
MC
HP
Where:
= Macrocells in high-performance mode
MC
HP
= Macrocells in low-power mode
MC
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure1 shows a typical calculation for the XC95144
device.
600
(480)
400
(mA)
CC
(300)
200
Typical I
(160)
050
High Performance
Low Power
Clock Frequency (MHz)
(320)
100
X5898B
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
Figure 1: Typical I
vs. Frequency for XC95144
cc
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
December 4, 1998 (Version 4.0) 1
XC95144 In-System Programmable CPLD
JTAG Port
I/O/GCK
I/O/GSR
I/O/GTS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
1
3
1
2
JTAG
Controller
I/O
Blocks
In-System Programming Controller
36
18
36
18
36
18
FastCONNECT Switch Matrix
36
18
Function
Macrocells
Function
Macrocells
Function
Macrocells
Function
Macrocells
Block 1
1 to 18
Block 2
1 to 18
Block 3
1 to 18
Block 4
1 to 18
36
18
Function
Block 8
Macrocells
1 to 18
X5922
Figure 2: XC95144 Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2 December 4, 1998 (Version 4.0)
XC95144 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol Parameter Value Units
V
CC
V
IN
V
TS
T
STG
T
SOL
Warning:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Supply voltage relative to GND -0.5 to 7.0 V
DC input voltage relative to GND -0.5 to VCC + 0.5 V
Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
Storage temperature -65 to +150 °C
Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260 °C
Recommended Operation Conditions
1
Symbol Parameter Min Max Units
V
CCINT
V
CCIO
Supply voltage for internal logic and input buffer 4.75
(4.5)
5.25
(5.5)
Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
V
IL
V
IH
V
O
Low-level input voltage 0 0.80 V
High-level input voltage 2.0 V
Output voltage 0 V
+0.5 V
CCINT
CCIO
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol Parameter Min Max Units
t
N
DR
PE
Data Retention 20 - Years
Program/Erase Cycles 10,000 - Cycles
V
V
December 4, 1998 (Version 4.0) 3
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