XILINX XC5200 User Manual

0

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XC5200 Series
Field Programmable Gate Arrays

November 5, 1998 (Version 5.2)

Features

• Low-cost, regi ster/latch rich, SRAM based

07*

Product Specification

- Footprint compatibility in co mm o n pa ck ag es within

- Over 150 devi ce/package combinations, including

reprogrammable architecture

-0.5µm three-layer metal CMOS process technology

- 256 to 1936 logic cells (3,000 to 23,000 “gates”)

- Price competitive with Gate Arrays

• System Level Features

- System performance beyond 50 MHz

• Fully Supported by Xilinx Development System

- Automatic place and route software

- Wide selection of PC and Workstation platforms

- Over 100 3rd-party Allian ce inte rf aces

- Supported by shrink-wrap Foundation software

- 6 levels of interconnect hierarchy

™

- VersaRing

I/O Interface for pin-locking

Description

- Dedicated carry logic for high-speed arithmetic
functions

- Cascade chain for wide input functions

- Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins

- Internal 3-state bussin g ca pa bilit y

- Four dedicated low-skew clock or signal distribution
nets

• Versatile I/O and Packaging

™

- Innovative VersaRing

I/O interface provides a high

logic cell to I/O ratio, with up to 244 I/O signals

- Programmable output slew-rate cont rol maximizes
performance and reduces noise

- Zero Flip-Flop hold time for input registers simplifies
system timing

- Independent Output Enables for external bussing

The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami­lies, the XC5200 family brings a robust feature set to pro­grammable logic design. The VersaBlock

the VersaRing I/O interface, and a rich hierarchy of inter­connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through t he familia r Xilinx soft ­ware environme nt. The XC52 00 fa mily is f ully suppo rted on
popular workstation and PC platforms. Popular design
entry methods are fully supported, in cluding ABEL, sche­matic capture, VHDL, and Verilog HDL synthesis. Design­ers utilizing logic s ynthesis can use th eir existing tools to
design with the XC5200 devices.

.

Table 1: XC5200 Field-Programmable Gate Array Family Members

the XC5200 Series and with the XC4000 Series

advanced BGA, TQ, and VQ packaging avail able

™

logic module,

7

Device XC5202 XC5204 XC5206 XC5210 XC5215

Logic Cells 256 480 784 1,296 1,936
Max Logic Gates 3,000 6,000 10,000 16,000 23,000
Typical Gate Range 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
VersaBlock Array 8 x 8 10 x 12 14 x 14 18 x 18 22 x 22
CLBs 64 120 196 324 484
Flip-Flops 256 480 784 1,296 1,936
I/Os 84 124 148 196 244
TBUFs per Longline 1014162024

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XC5200 Series Field Programmable Gate Arrays

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XC5200 Family Compared to

XC4000/Spartan™ and XC3000
Series

For readers alrea dy familiar with the XC4000/Spa rtan and
XC3000 FPGA Families, this section describes sig nificant
differences between them and the XC5200 family. Unless
otherwise indicated, comparisons refer to both
XC4000/Spartan and XC3000 devi ces.

Configurable Logic Block (CL B ) Resources

Each XC5200 CLB cont ai n s four i nde pe nde nt 4- inp ut fu nc­tion generators and four registers, which are configured as

four indepe ndent L ogic Ce lls™ ( LCs). T he regi sters in eac h
XC5200 LC are optionally configurable as edge-triggered
D-type flip-flops or as transparent level-sensitive latches.

The XC5200 CLB includes dedicated carry logic that pro­vides fast arithmetic ca rry capability. The dedicated carry
logic may also be used to cascade function generators for
implementing wide arithmetic functions.

XC4000 family:

decoders. Wide decoders are implemented using cascade
logic. Although sa crificing s peed for s ome desig ns, lack of
wide edge decoders reduces the die area and hence cost
of the XC5200.

XC4000/Spartan family:

differs from that o f the XC4000/Spar tan family in that the
sum is generated in an additional function generator in the
adjacent column. This design reduces XC5200 die size and
hence cost for many applications. Note, however, that a
loadable up/down counter requires the same number of
function gener ators in bo th families . XC3000 has no d edi­cated carry.

XC4000/Spartan family:

mized for cost and hence cannot implement RAM.

Input/Output Block (IOB) Resources

The XC5200 family maintains footprint compatibility with
the XC4000 family , but not with the XC3000 family.

T o minimize cost and maximize the number of I/O per Logic
Cell, the XC5200 I/O does not include flip-flops o r latches.

For high performance paths, the XC5200 family provides
direct connections from each IOB to the registers in the
adjacent CLB in order to emulate IOB registers.

Each XC5200 I/O Pin provides a programmable delay ele­ment to contro l input s et-up tim e. This element ca n be used
to avoid potential hold-time problems. Each XC5200 I/O
Pin is capable of 8-mA source and sink currents.

IEEE 1149.1-type boundary scan is supported in each
XC5200 I/O.

XC5200 devices have no wide edge

XC5200 dedicated carry logic

XC5200 lookup tables are opti-

Table 2: Xilinx Field-Programmable Gate Array
Families

Parameter XC5200 Spartan XC4000 XC3000

CLB function
generators

CLB inputs 20 9 9 5
CLB outputs 12 4 4 2
Global buffers 4 8 8 2
User RAM no yes yes no
Edge decoders no no yes no
Cascade chain yes no no no
Fast carry logic yes yes yes no
Internal 3-state yes yes yes yes
Boundary scan yes yes yes no
Slew-rate control yes yes yes yes

4332

Routing Resources

The XC5200 family provides a flexible coupling of logic and
local routing res ourc es cal led the VersaB lock . The XC520 0
Ver saBlock elemen t incl udes t he CLB, a Loc al Inte rconne ct
Matrix (LIM), and direct connects to neighboring Versa­Blocks.

The XC5200 provides four global buffers for clocking or
high-fanout co ntro l s igna l s. E a ch buffer may be sou rc ed by
means of its dedicated pad or from any internal source.

Each XC5200 TBUF ca n dr i ve up t o t wo h ori zo nt al a nd t wo
vertical Longlines. There are no internal pull-ups for
XC5200 Longlines.

Configuration and Readback

The XC5200 supports a new configuration mode called
Express mode.

XC4000/Spartan family:

global reset but not a global set.
XC5200 devices use a different configuration process than

that of the XC 30 00 f ami ly, but use t he same p ro ce ss as t he
XC4000 and Spartan families.

XC3000 family:

fer, XC5200 devices may be used in daisy chains with
XC3000 devices.

XC3000 family:

gle-function input pin that overrides all other inputs. The
PROGRAM pin does not exist in XC3000.

Although their configuration processes dif-

The XC5200 PROGRAM pin is a sin-

The XC5200 family provides a

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XC5200 Series Field Programmable Gate Arrays

XC3000 family:

XC5200 devices support an additional pro-

gramming mode: Peripheral Synchronous.

XC3000 family:

The XC5200 family does not support
Power-down, but off ers a Gl obal 3- sta te input that does not
reset any flip-flops.

XC3000 family:

The XC5200 family does not provide an
on-chip crystal oscillato r amplifier, but it does provide an
internal oscillator fro m which a variet y of fre quencie s up to
12 MHz are available.

Architectural Overview

Figure 1 presents a simplified, conceptual overview of the

XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs, program­mable logic blocks, and programmable interconnect. Unlike
other FPGAs, however, the logic and local routing
resources of th e XC5200 family are combin ed in flexible
VersaBlocks (Figure 2). General-purpose routing connects
to the VersaBlock through the General Routing Matrix
(GRM).

VersaBlock: Abundant Local Routing Plus
V ersatile Logic

The basic logic elemen t in ea ch VersaBlock structure is the
Logic Cell, shown in Figure 3. Each LC contains a 4-input
function generator (F), a storage device (FD), and control
logic. There are five independent inputs and three outputs
to each LC. The independence of the inputs and outputs
allows the software to maximize the resource utilization
within each LC. Each Logic Cell also contains a direct
feedthrough path that does not sacrifice the use of either
the function gen erator or the register ; this featu re is a fi rst
for FPGAs. The st orage devic e is configu rable as eit her a D
flip-flop or a latch. The control logic consists of carry logic
for fast implementation of arithmetic functions, which can
also be configured as a cascade chain allowing decode of
very wide input functions.

Input/Output Blocks (IOBs)

VersaRing

GRM

GRM

VersaRing

GRM

Versa-

Block

Versa-

Block

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

VersaRing

GRM

GRM

GRM

Versa-

Block

Versa-

Block

Versa-

Block

Figure 1: XC5200 Architectural Overview

GRM

24

24

4
4

44

TS

CLB

LC3
LC2
LC1
LC0

44

Direct Connects

4

4
4

LIM

Figure 2: VersaBlock

VersaRing

X4955

7

X5707

CO

DI

DQ

F4
F3

F

F2
F1

CI CE CK CLR

DO

FD

X

X4956

Figure 3: XC5200 Logic Cell (Four LCs per CLB)

November 5, 1998 (Version 5.2) 7-85

XC5200 Series Field Programmable Gate Arrays

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The XC5200 CLB consists of four LCs, as shown in

Figure 4. Each CLB has 20 independent inputs and 12

independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The chal­lenge of FPGA implementation software has always been
to maximize the usage of logic resources. The XC5200
family addresses this issue by surrounding each CLB with

two types of local inter connect — the Local Interconne ct
Matrix (LIM) and direct connects. These two interconnect
resources, combine d with the CLB, form the VersaBlock,
represented in Fi gure 2.

CO

DO

DQ

FD

X

DI

F4
F3
F2
F1

LC3

F

LC2

DI

DQ

F4
F3

F

F2
F1

DO

FD

X

LC1

DI

F4
F3
F2
F1

DI

F4
F3
F2
F1

LC0

LC0

DQ

F

DQ

F

CI CE CK CLR

DO

FD

X

DO

FD

X

X4957

Figure 4: Configurable Logi c Block

The LIM provides 100% connectivity of the inputs and out­puts of each LC in a given CLB. The benefit of the LIM is
that no general routing resources are required to connect
feedback paths within a CLB. The LIM connects to the
GRM via 24 bidirectional nodes.

The direct connects allow immediate connections to neigh­boring CLBs, once again without using any of the general
interconnect. These two layers of local routing resource
improve the granularity of the architecture, effectively mak­ing the XC5200 family a “sea of logic cells.” Each
Versa-Block has four 3-state buffers that share a common
enable line and directly drive horizontal and vertical Lon­glines, creating robust on-chip bussing capability. The
VersaBlock allows fast, local impleme ntation of log ic func­tions, effectively imple menting us er designs in a hier archi­cal fashion. These resources also minimize local routing
congestion and improve the efficiency of the general inter­connect, which is used for connecting larger groups of
logic. It is this combination of both fine-grain and
coarse-grain architecture attributes that maximize logic uti ­lization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with mini­mal routing rest rictions.

VersaRing I/O Interface

The interface between the IOBs an d core logic has been
redesigned in the XC5200 family. The IOBs are completely
decoupled from the core logic. The XC5200 IOBs contain
dedicated boundary-scan logic for added board-level test­ability, but do not include input or output registers. This
approach allows a maximum number of IOBs to be placed
around the device, improving the I/O-to-gate ratio and
decreasing the cost per I/O. A “freeway” of interconnect
cells surrounding the device forms the VersaRing, which
provides connec tions from the IOBs to the internal lo gic.
These incremental routing resources provide abundant
connections from each IOB to the nearest VersaBlock, in
addition to Longline connections surrounding the device.
The VersaRing eliminates the historic trade-off between
high logic utilization and pin placement flexibility. These
incremental edge re so urce s giv e u se rs incre ase d fle xibilit y
in preassigning (i.e., locking) I/O pins before completing
their logic designs. Th is ability acce lerates tim e-to-mar ket,
since PCBs and other system components can be manu­factured concurrent with the logic design.

General Routing Matrix

The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight cou­pling to the logic resources contained in the VersaBlocks.
Advanced simulation tools were used during the develop­ment of the XC5200 architecture to determine the optimal
level of routing resources required. The XC5200 family
contains six levels of interconnect hierarchy — a series of

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XC5200 Series Field Programmable Gate Arrays

single-length lines, double-length lines, and Longlines all
routed through the GRM. The direct connects, LIM, and
logic-cell feedthrough are contained within each
Versa-Block. Throughout the XC5200 interconnect, an effi­cient multiplexing sc heme, in c ombination with thre e layer
metal (TLM), w as used to imp rove the overall efficiency of
silicon usage.

Performance Overview

The XC5200 family has been benchmarked with many
designs running synchronous clock rates beyond 66 MHz.
The performance of an y design depe nds on the circui t to be
implemented, a nd t he d ela y th ro ug h th e co m binat or ial and
sequential logic elements, plus the delay in the intercon­nect routing. A rough estimate of timing can be made by
assuming 3-6 ns per logic level, which includes direct-con­nect routing delays, depending on speed grade. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.

Tak ing Ad van tage of Reconfiguration

FPGA devices can be recon figured to ch ange logi c fu nction
while resident in the s ystem. T his capab ility gives the sys­tem designer a new degree of freedom not available with
any other type of logic.

Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products alrea dy in the fie ld. A n FPG A ca n ev en be re co n­figured dynamically to perform different functions at differ­ent times.

Reconfigurable logic can be used to implement system
self-diagnostics, creat e systems capable of being reconfig­ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli­fies hardware design and debugging and shortens product
time-to-market.

Detailed Functional Description

Configurable Logic Blocks (CLBs)

Figure 4 shows the logic in the XC5200 CLB, which con-

sists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a
D-Type flip-flop or latch with c ommon cloc k, clock enable ,
and clear, but individually selectable clock polarity. Addi­tional logic features provided in the CLB are:

• An independent 5-input LUT by combining two 4-input
LUTs.

• High-speed carry propagate logic.

• High-speed pattern decoding.

• High-speed direct connection to flip-flop D-inputs.

• Individual selection of either a transparent,

level-sensitive latch or a D flip-flop.

• Four 3-state buffers with a shared Output Enable.

5-Input Functions

Figure 5 illustrates how the outputs from the LUTs from

LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.

CO

DI

I1
I2
I3
I4

I5

F4
F3
F2

F

F1

F5_MUX

DI

F4
F3

F

F2
F1

CI

5-Input Function

CKCE

D

D

CLR

DO

Q

FD

X

LC1

DO

FD

LC0

out

Q

Qout

X

X5710

7

Figure 5: Two LUTs in Parallel Combined to Create a
5-input Function

November 5, 1998 (Version 5.2) 7-87

XC5200 Series Field Programmable Gate Arrays

carry out

A3
or
B3

A3 and B3
to any two

A2
or
B2

A2 and B2
to any two

A1
or
B1

A1 and B1
to any two

A0
or
B0

A0 and B0
to any two

0

CI

CO

D

CY_MUX

DQ

CY_MUX

D

CY_MUX

D

CY_MUX

CKCE CLR

carry in

DI

F4
F3

XOR

F2
F1

DI

F4
F3

XOR

F2
F1

DI

F4
F3

XOR

F2
F1

DI

F4
F3

XOR

F2
F1

FD

FD

FD

FD

DO

LC3

DO

LC2

DO

LC1

DO

LC0

carry3

Q

half sum3

X

carry2

half sum2

X

carry1

Q

half sum1

X

carry0

Q

half sum0

X

R

DI

F4
F3

XOR

F2
F1

CO

DO

Q

D

FD

sum3

X

LC3

DI

F4
F3

XOR

F2
F1

DO

DQ

FD

sum2

X

LC2

DI

F4
F3

XOR

F2
F1

DO

D

Q

FD

sum1

X

LC1

DI

F4
F3
F2

XOR

F1

CK

CI

CE CLR

DO

Q

D

FD

sum0

X

LC0

F=0

CY_MUX

Initialization of
carry chain (One Logic Cell)

X5709

Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate

Carry Function

The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A c arry m ultiple xer (CY_ MUX) sym­bol is used to indicate the XC5200 carry logic. This symbol
represents the dedicated 2:1 multiplexer in each LC that
performs the one-bit high-speed carry propagate per logic
cell (four bits per CLB).

While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic func­tion. Figure 6 represents an example of an adder function.
The carry propagate is performed on the CLB shown,

which also gener ates the hal f-su m for the four -bit ad der . An
adjacent CLB is responsible fo r XORing the half-su m with
the corresponding carry-out. Thus an adder or counter
requires two LCs per bit. Notice that the carry chain
requires an initialization stage, which the XC5200 family
accomplishes using the carry initialize (CY_INIT) macro
and one additional LC. The carry chain can propagate ver­tically up a column of CLBs.

The XC5200 library contains a set of Relationally-Placed
Macros (RPMs) and arithmetic func tions designed to take
advantage of the dedicated carry logic. Using and modify­ing these macros m akes it much easie r to implement cus-

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XC5200 Series Field Programmable Gate Arrays

tomized RPMs, freeing the designer from the need to
become an expert on architectures.

cascade out

A15
A14
A13
A12

A11
A10
A9
A8

CO

DI

F4
F3

AND

F2
F1

DI

F4
F3

AND

F2
F1

DI

A7

F4

A6

F3
A5
A4

A3
A2
A1
A0

AND

F2

F1

DI

F4

F3

AND

F2

F1

F=0

CY_MUX

CY_MUX

CY_MUX

CY_MUX

CI

cascade in

CY_MUX

Initialization of
carry chain (One Logic Cell)

CK

CE CLR

DO

Q

D

FD

X

LC3

DO

DQ

FD

X

LC2

DO

D

Q

FD

X

LC1

DO

Q

D

FD

X

LC0

out

X5708

Figure 7: XC 5200 CY_MU X Used f or Decoder Cascade
Logic

Cascade Function

Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4- input func tion gene rator s can be con­figured to take advantage of these four cascaded
CY_MUXes. Note th at AND an d OR casca ding ar e speci fic
cases of a general decode. In AND cascading all bits are
decoded equal to logic one, while in OR cascading all bits
are decoded equ al to logic ze ro. The flexibility of the LUT
achieves this result. The XC5200 library contains gate
macros desig ned to take advantag e of this function.

CLB Flip-Flops and Latches

The CLB can pass the combinatorial output(s) to the inter­connect network, but can also store the combinatorial

results or other incoming data in flip-flops, and connect
their outputs to the interconnect network as well. The CLB
storage elements can also be configured as latches.

Table 3: CLB Storage Element Functionality
(active rising edge is shown)

Mode CK CE CLR D Q

Power-Up or

GR

XXXX0
XX1X0

Flip-Flop

__/

1* 0* D D

0X0*XQ

Latch

11*0*XQ
01*0*DD

Both X 0 0* X Q

Legend:

X

__/

0*
1*

Don’t care
Rising edge
Input is Low or unconnected (default value)
Input is High or unconnecte d (default value)

Data Inputs and Outputs

The source of a storage element data input is programma­ble. It is driven by the function F, or by the Direct In (DI)
block input. The flip-flops or latches drive the Q CLB out­puts.

Four fast feed-through paths from DI to DO are available,
as shown in Figure 4. This bypass is sometimes used by
the automated router to repower internal signals. In addi­tion to the storage element (Q) and direct (DO) outputs,
there is a combinatorial output (X) that is always sourced
by the Lookup Table.

The four edge-triggered D-type flip-flops or level-sensitive
latches have common clock (CK) and clock enable (CE)
inputs. Any of the clock inputs can also be permanently
enabled. Storage element functionality is described in

Table 3.

Clock Input

The flip-flops ca n b e trig g ered o n e ith er th e risin g or fa lling
clock edge. The clock pin is shared by all four storage ele­ments with individual polarity control. Any inverter placed
on the clock input is automatically absorbed into the CLB.

Clock Enable

The clock enable signal (CE) is active High. The CE pin is
shared by the four storage elements. If left unconnected
for any, the clock enable for that storage element defaults
to the active state. CE is not invertible within t he CLB.

Clear

An asynchrono us st orage ele ment i nput ( CLR) ca n be us ed
to reset all four flip- flops or latches in t he CLB. This input

7

November 5, 1998 (Version 5.2) 7-89

XC5200 Series Field Programmable Gate Arrays

Figure 8: Schematic Symbols for Gl obal Reset

R

can also be indep en den tly dis ab l ed for any fl ip -f lop . C LR i s
active High. It is not invertible within the CLB.

STARTUP

PAD

IBUF

GR
GTS

CLK

Q2
Q3

Q1Q4

DONEIN

X9009

Global Reset

A separate Global Reset line clears each storage element
during power-up, reconfiguration, or when a dedicated
Reset net is driven active. This global net (GR) does not
compete with other routing resources; it uses a dedicated
distribution networ k.

GR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GR pin of the ST ARTUP symbol. (See Figure 9.) A specific
pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program­mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Reset signal.
Alternatively, GR can be driven from any internal node.

Using FPGA Flip-Flops and Latches

The abundance of flip-flops in the XC5200 Series invites
pipelined desi gns. This is a po werful way of i ncreas in g per­formance by breaking the function into smaller subfunc­tions and e xecuting them in parallel, pa ssing on the re sults
through pipe li ne f li p- f lops . This me th od sh ould be se rio us l y
considered wherever throughput is more important than
latency.

To include a CLB flip-flop, place the appropriate library
symbol. For example, FD CE is a D-t y pe f li p-fl o p wit h cl ock
enable and asynchronous clear. The corresponding latch
symbol is called LDCE.

In XC5200-Series devices, the flip-flops can be used as
registers or shift registers without blocking the function
generators from performing a different, perhaps unrelated
task. This ability increases the functional capacity of the
devices.

The CLB setup time is specified between the function gen­erator input s and the clock input CK. Therefore, the speci­fied CLB flip-flop setup time includes the delay through the
function generator .

Three-State Buffers

The XC5200 family has four dedicated Three-State Buffers
(TBUFs, or BUFTs in the sche matic library) per CLB (see

Figure 9). The four buffers are individually configurable

through four configuration bits to operate as simple
non-inverting buffers or in 3-state mode. When in 3-state
mode the CLB output enable (TS) control signal drives the
enable to all four buffers. Each TBUF can drive up to two
horizontal an d/or t wo vertic al Lon glines . These 3- state buf f­ers can be used to implement multiplexed or bidirectional
buses on the horizontal or vertical longlines, saving logic
resources.

The 3-state buffer e nable is an active -High 3-sta te (i.e. an
active-Low enable), as shown in Table 4.

Table 4: Three-State Buffer Functionality

IN T OUT

X1Z

IN 0 IN

Another 3-stat e buffer with similar ac cess is located near
each I/O block al ong the right and left edges of the arra y.

The longlines driven by the 3-state buffers have a weak
keeper at each end. This circuit prevents undefined float­ing levels. However, it is overridden by any driver. To
ensure the lon glin e go es high when no bu ffers ar e on , a dd
an additional BUFT to drive the output Hi gh duri ng al l of t he
previously undefined states.

Figure 10 shows how to use the 3-state buffers to imple-

ment a multiplexer. The selection is acco mplished by the
buffer 3-state signal.

TS

CLB

CLB

LC3

LC2

LC1

LC0

Horizontal
Longlines

X9030

7-90 November 5, 1998 (Version 5.2)

Figure 9: XC5200 3-State Buffers

R

I

O

T

PAD

Vcc

X9001

Input

Buffer

Delay

Pullup

Pulldown

Slew Rate

Control

Output
Buffer

XC5200 Series Field Programmable Gate Arrays

• A + DB • B + DC • C + DN • N

Z = D

~100 k

Ω

A

D

N

"Weak Keeper"

D

A

ABCN

BUFT BUFT BUFT BUFT

D

B

D

C

Figure 10: 3-State Buffers Implement a Multip lexer

Input/Output Blocks

User-configurable input/output blocks (IOBs) provide the
interface betwee n external package pins and the intern al
logic. Each IOB controls one package pin and can be con­figured for input, output, or bidirectional si gnals.

The I/O block, shown in Figure 11, consists of an input
buffer and an output buffer. The output driver is an 8-mA
full-rail CMOS buffer with 3-state control. Two slew-rate
control modes are supported to minimize bus transients.
Both the o utput bu ffer and the 3-state cont ro l a re in ve rt ibl e .
The input buffer has globally selected CMOS or TTL input
thresholds. T he input bu ffer is invertib le and also provides a
programmable delay line to assure reliable chip-to-chip
set-up and hold times. Minimum ESD protec tion is 3 KV
using the Human Body Model.

Figure 11: XC5200 I/O Block

IOB Input Signals

The XC5200 inputs can be globally configured for either
TTL (1.2V) or CMOS thresholds, using an option in the bit­stream generation software. There is a slight hysteresis of
about 300mV.

The inputs of XC5200-Series 5-Volt devices can be driven
by the outputs o f any 3. 3-V olt device, if the 5- V olt inputs ar e
in TTL mode.

Supported sources for XC5200-Series device inputs are
shown in Table 5.

November 5, 1998 (Version 5.2) 7-91

Table 5: Supported Sources for XC520 0-Series Device
Inputs

XC5200 Input Mode

Source

Any device , Vcc = 3.3 V,
CMOS outputs

Any device, Vcc = 5 V,
TTL outputs

Any device, Vcc = 5 V,
CMOS outputs

5 V,

TTL

√

√

√√

Optional Delay Guarantees Zero Hold Time

XC5200 devices do no t have st orage el ements in the IOB s.
However, XC5200 IOBs can be efficiently routed to CLB
flip-flops or latches to store the I/O signals.

The data input to the re gister can o ption ally be delaye d by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increa sed so tha t normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.

The input flip-flop setup time is defined between the data
measured at the de vice I/O pin and the clock inpu t at the
CLB (not at the clock pin). Any routing delay from the
device clock pin to the clock input of the CLB must, there­fore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
specified setup time might, therefore, result in a negative
setup time at the device pins, i.e., a positive hold-time
requirement.

When a delay is i nser t ed on th e data l ine , mor e c loc k de lay
can be tolerated without causing a positive hold-time
requirement. Sufficient de lay eliminat es the poss ibility of a
data hold-time requirement at the external pin. The maxi­mum delay is therefore inserted as the software default.

The XC5200 IO B has a one-ta p delay elemen t: either the
delay is insert ed (defau lt), or i t is not. The dela y guarante es
a zero hold time with respect to clocks routed through any
of the XC5200 global clock buffers. (See “Global Lines” on

page 96 for a description of the global clock buffers in the

XC5200.) For a shorter input register setup time, with

X6466

5 V,

CMOS

Unreliable

Data

7

XC5200 Series Field Programmable Gate Arrays

Figure 12: Open-Drain Output

R

non-zero hold, attach a NODELAY attribute or property to
the flip-flop or input buffer.

IOB Output Signals

Output signals can be optionally inverted within the IOB,
and pass directly to the pad. As with the inputs, a CLB
flip-flop or latch can be used to store the output signal.

An active-High 3-state signal can be used to place the out­put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently
configured for each IOB.

The XC5200 devi ces p rovid e a gua rant eed out put sink c ur­rent of 8 mA.

Supported destinations for XC5200-Series device outputs
are shown in Table 6.(For a detailed disc ussion of how to
interface between 5 V and 3.3 V devices, see the 3V Prod­ucts section of

The Programmable Logic Data Book

An output can be co nfi gure d as ope n-dr ain (open -coll ect or)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure12.)

Table 6: Supported Destinations for XC5200-Series
Outputs

XC5200 Output Mode

Destination

XC5200 device, V

=3.3 V,

CC

CMOS

CMOS-threshold inputs
Any typical devi ce, V

CMOS-threshold inputs

= 3.3 V,

CC

some

Any device, VCC = 5 V,
TTL-threshold inputs

Any device, V

CC

= 5 V,

CMOS-threshold inputs

1. Only if destination device has 5-V tolerant input s

OPAD

OBUFT

X6702

.)

5 V,

√

1

√

√

For XC5200 devices, maximum total capacitive load for
simultaneous fast mode switching in the sam e direction is
200 pF for all packag e pins between eac h Power/Ground
pin pair. For some XC5200 devices, additional internal
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce.

For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC5200 devices. This maxi­mum capacitive load should not be exceeded, as it can
result in ground bounce of grea ter than 1. 5 V amplitud e and
more than 5 ns duration. This level of ground bounce may
cause undesired transient behavior on an output, or in the
internal logic. This r estriction is comm on to all high-spe ed
digital ICs, and is not particular to Xilinx or the XC5200
Series.

XC5200-Series devices have a feature called “Soft
Start-up,” de signed to r educe gr ound bo unce when al l ou t­puts are turned on simultaneously at the end of configura­tion. When the configuration process is finished and the
device starts up, the first activation of the outputs is auto­matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual configuration option for
each IOB.

Global Three-State

A separate Global 3-State line (not shown in Figure 11)
forces all FPGA outputs to the high-impedance state,
unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com­pete with othe r rou tin g resou rces ; it u ses a dedic ate d di stri­bution network.

GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca­tion can be assigned to this input using a LOC attribute or
property, just as with any ot her us er-prog rammabl e pad. A n
inverter can optionally be inserted after the input buffer to
invert the sens e of the Gl obal 3- State si gnal. Us ing GTS is
similar to Global Reset. See Figure 8 on page 90 for
details. Alternatively, GTS can be driven from any internal
node.

Other IOB Options

There are a number of other programmable options in the
XC5200-Series IOB.

Output Slew Rate

The slew rate of each output buffer is, by default, reduced,
to minimize power bus tran sient s when switching no n-cr iti­cal signals. For critical sig nals, attach a FAST attribute or
property to the output buffer or flip-flop.

7-92 November 5, 1998 (Version 5.2)

Pull-up and Pull-down Resistors

Programmable IOB pull-up and pull-down resistors are
useful for tying unused pins to Vcc or Ground to minimize
power consumption and reduce noise sensitivity. The con­figurable pull-up resistor is a p-channel transistor that pulls

R

to Vcc. The confi gurabl e pull-d own resi stor is an n-chan nel
transistor that pulls to Ground.

The value of these resistors is 20 kΩ − 100 kΩ. This high
value makes them uns uitable as wired-AND pu ll-up resis­tors.

The pull-up resi stor s for most u ser-pr ogrammabl e IOBs ar e
active during th e configuration process. See Table 13 on

page 124 for a list of pins with pull-ups ac tive before and

during configuration.
After configuration, voltage levels of unused pads, bonded

or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis­tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to th e net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.

JTAG Support

Embedded logic attached to the IOBs contains test struc­tures compatible with IEEE Standard 1149.1 for boundary
scan testing, simplifying board-level testing. More informa­tion is provided in “Boundary Scan” on page 98.

Oscillator

XC5200 devices include a n internal os cillator. This oscilla­tor is used to clock the powe r-on time-ou t, cl ear co nfigu ra­tion memory, and source CCLK in Master configuration
modes. The oscillator ru ns at a nom in al 1 2 M Hz fr e quen cy
that varies with process, Vcc, and temperature. The output
CCLK frequency is selectable as 1 MHz (default), 6 MHz,
or 12 MHz.

The XC5200 oscillator divides the internal 12-MHz clock or
a user clock. The user then has the choice of dividing by 4,
16, 64, or 256 for the “OSC1” output and dividing by 2, 8,
32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out­put. The division is specified via a “DIVIDEn_BY=x”
attribute on the symbol, where n=1 for OSC1, or n=2 for
OSC2. These frequencies can vary by as much as -50% or
+ 50%.

The OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see Figure 13).

XC5200 Series Field Programmable Gate Arrays

OSCS

CK_DIV

Figure 13: XC5200 Oscillator Macros

OSC1
OSC2

OSC1
OSC2

5200_14

VersaBlock Routing

The General Routing Matrix (GRM) connects to the
Versa-Block via 24 bidirectional ports (M0-M23). Excluding
direct connections, global nets, and 3-statable Longlines,
all VersaBlo ck i np ut s and ou tp ut s con nect to th e GR M vi a
these 24 ports. Four 3-statable unidirectional signals
(TQ0-TQ3) drive out of the VersaBlock directly onto the
horizontal and vertical Longlines. Two horizontal global
nets and two vertical global nets connect directly to every
CLB clock pin; the y can conn ect to other CLB inpu ts via th e
GRM. Each CLB also has four unidirectional direct con­nects to each of its four neighboring CLBs. These direct
connects can also feed directly back to the CLB (see

Figure 14).

In addition, ea ch C LB ha s 1 6 dir ec t in p ut s, four direct co n ­nections from each of the neighboring CLBs. These direct
connections provide high-speed local routing that
bypasses the GRM.

Local Interconnect Matrix

The Local Inter connec t Matrix (L IM) is b uilt from in put and
output multiplexers. The 13 CLB outputs (12 LC outputs
plus a V
outputs via the output multiplexers, which consist of eight
fully populated 13-to-1 multiplexers. Of the eight

VersaBlock outputs, four signals drive each neighboring
CLB directly, and provide a di rect feedba ck path to the input
multiplexers. The four remaining multiplexer outputs can
drive the GRM through four TBUFs (TQ0-TQ3). All eight
multiplexer outputs can connect to the GRM through the
bidirection al M0- M23 s ign al s. A ll eigh t s igna l s a l so c onne ct
to the input multiplexers and are potential inputs to that
CLB.

/GND signal) connect to the eight VersaBlock

cc

7

November 5, 1998 (Version 5.2) 7-93

XC5200 Series Field Programmable Gate Arrays

To GRM
M0-M23

R

Direct West

Global Nets

North

South

East

West

Direct North

4

4

4

4

4

4

4

4

Feedback

4

24

Input

Multiplexers

8

TS

CLK
CE
CLR

4

C

OUT

CLB

5

5

5

5

LC3

LC2

LC1

LC0

C

IN

3

3

V

/GND

CC

3

3

Output

Multiplexers

8

To
Longlines

4

and GRM
TQ0-TQ3

Direct to

4

East

4

Direct South

Figure 14: VersaBlock Details

CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers,
and the four signals from the CLB output multiplexers.
Unlike the output multiplexers, the input mu ltiplexers are
not fully populated; i.e., only a subset of the available sig­nals can be con nected to a give n CL B input. The flexibility
of LUT input swapping and LUT mapping compensates for
this limitation. For example, if a 2-input NAND gate is
required, it can be mapped into any of the four LUTs, and
use any two of the four inputs to the LUT.

Direct Connects

The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB input and out­put multiple xe r ar ra ys, and th us bypa ss t he g ene ra l rou t ing
matrix altogether. These lines increase the routing channel
utilization, while simultaneously reducing the delay
incurred in speed-critical connections.

X5724

The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce pin-to-pin set-up time, clock-to-out, and combi­national prop agation delay. Direct connects from the input
buffers to the CLB DI pin (direct flip-flop input) are only
available on the left and right edges of the device. CLB
look-up table inputs and combinatorial/registered outputs
have direct connects to input/output buffers on all four
sides.

The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro per­formance, and leaves the other routing channels intact for
improved routing. Direct connects can also route through a
CLB using one of th e four cell-fee dthrough paths.

General Routing Matrix

The General R outing Matrix, shown in Figure 15, provide s
flexible bidirectio nal connect ions to th e Local Int erconnect

7-94 November 5, 1998 (Version 5.2)

R

Matrix through a hierarchy of different-length metal seg­ments in both the horizontal and vertical directions. A pro-

XC5200 Series Field Programmable Gate Arrays

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

Six Levels of Routing Hierarchy

1

2

3

4

LIM5

6

Single-length Lines

Double-length Lines

Direct Connects

Longlines and Global Lines

Local Interconnect Matrix
Logic Cell Feedthrough

Path (Contained within each
Logic Cell)

GRM

GRM

GRM

Versa-

Block

Versa-

Block

Versa-

Block

GRM

4
4

GRM

Versa-

Block

GRM

Versa-

Block

1

2

GRM

Versa-

Block

44

24

24

TS

CLB

LC3

4

LC2
LC1

6

LC0

44

LIM

3

4

4
4

7

5

Direct Connects

X4963

Figure 15: XC5200 Interconnect Structure

grammable interconnect point (PIP) establishes an electri­cal connection between two wire segments. The PIP, con­sisting of a pass transisto r switch controlled by a mem ory
element, provides bidirectional (in some cases, unidirec­tional) connection between two adjoining wires. A collec­tion of PIPs inside the General Routing Matrix and in the
Local Interconnect Matrix provides connectivity between
various types of metal segments. A hierarchy of PIPs and

associated routing segments combine to provide a power­ful interco nnect hierarchy:

• Forty bidi rectional single-length segments per CLB

provide ten routing channels to each of the four
neighboring CLBs in four directions.

• Sixteen bidirectional double-length segments per CLB

provide four r outing channels to each of four other
(non-neighbor ing ) CL B s in fou r direc tio ns.

• Eight horizontal and eight vertical bidirectional Longline

November 5, 1998 (Version 5.2) 7-95

XC5200 Series Field Programmable Gate Arrays

R

segments span the width and height of the chip,
respectively.

Two low-skew horizontal and vertical unidirectional glo­bal-line segments span each row and co lumn of the chip,
respectively.

Single- and Double-Length Lines

The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The dou­ble-length lines hop across every other CLB to reduce the
propagation del ays i n spe ed-cri tic al ne ts. R egenerat ing the
signal strength is recommended after traversing three or
four such segm ents. X ilinx place- and-route software a uto­matically connects buffers in the path of the signal as nec­essary. Single- and double-len gth lines cannot drive onto
Longlines and global lines; Longlines and global lines can,
however, drive onto single- and double-length lines. As a
general rule, Longline and global-line connections to the
general routing matrix are unidirectional, with the signal
direction from these lines toward the routing matrix.

Longlines

Longlines ar e used for hig h-fan-o ut sig nals, 3 -state b usses,
low-skew nets, and faraway destinations. Ro w and column
splitter PIP s in the mid dle of the ar ray ef fecti vely doub le the
total number of Longlines by electrically dividing them into
two separated half-lines. Longlines are driven by the
3-state buffers in ea ch CLB, and are driv en by similar buff­ers at the periphery of the array from the VersaRing I/O
Interface.

Bus-oriented desi gns ar e easil y impl emented by using Lon­glines in conju ncti on wi th t he 3 -st ate buf fers in th e CLB and
in the VersaRing. Additionally, weak keeper cells at the
periphery reta in the last valid logic level on the Longlin es
when all buffers are in 3-state mode.

Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not possible.
Again, as a general rule, long- and global-line connections
to the General Routing Matrix are unidirectional, with the
signal direction from these lines toward the routing matrix.

carry/cascade logic described above, implementing a wide
logic function in p lace of the wired func tion. In the c ase of
3-state bus a pplicat ions, t he user must in sure th at all s tates
of the multiplexing function are defined. This process is as
simple as adding an additional TBUF to drive the bus High
when the previously undefined states are activated.

Global Lines

Global buffers in Xilinx FPGAs are special buffers that drive
a dedicated routing network called Global Lines, as shown
in Figure 16. This network is intended for high-fanout
clocks or other c ontrol signals , to maxim ize spe ed and min­imize skewing while distributi ng the signal to many loads.

The XC5200 family has a total of four global buffers (BUFG
symbol in the library), each with its own dedicated routing
channel. Two are distributed vertically and two horizontally
throughout the FPGA.

The global lines provide direct input only to the CLB clock
pins. The global lines also connect to the General Routing
Matrix to provide ac cess from these lines to the function
generators and other control signa ls.

Four clock input pads at the corners of the chip, as shown
in Figure16, provide a high-spe ed, low -skew c lock net work
to each of the four global-line buffers. In addition to the ded­icated pad, the global lines can be sourced by internal
logic. PIPs from several routing channels within the Ver­saRing can also be configured to drive the global-line buff­ers.

Details of all the programmable interconnect for a CLB is
shown in Figure 17.

GCK1

GCK4

The XC5200 famil y h as no p ull -u ps o n t he e nds o f t he Lon ­glines sourced by TBUFs, unlike the XC4000 Series. Con­sequently, wired functions (i. e. , WAND and WORAND) and
wide multiplexing functions requiring pull-ups for undefined
states (i.e ., b us ap pli c ati on s) must be imp l eme nt ed i n a dif ­ferent way. In the case of the wired functions, the same
functionality can be achieved by taking advantage of the

GCK2

Figure 16: Global Lines

GCK3

X5704

7-96 November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

.

x9010

SINGLE LONG

CARRY

DOUBLEGLOBAL

DIRECT

CLB

7

DIRECT

DIRECT

LONG

GLOBAL

DOUBLE

SINGLE

Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CL B

November 5, 1998 (Version 5.2) 7-97

XC5200 Series Field Programmable Gate Arrays

R

VersaRing Input/Output Interface

The VersaRing, shown in Figure 18, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The Ver­saRing decouples the core logic from the I/O pads. Each
VersaRing Cell provides up to four pad-cell connections on
one side, and connects directly to the CLB ports on the
other side.

VersaRing

2

8

8

2

2

GRM

VersaBlock

2

2

GRM

VersaBlock

2

10

8

10

8

Interconnect

4
4

Interconnect

4
4

2

2

Figure 18: VersaRing I/O Interfac e

8

Pad

Pad

Pad

Pad

8

Pad

Pad

Pad

Pad

8

X5705

Boundary Scan

The “bed of nails” has been the trad itional method of test ing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti­cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE boundary scan standard

1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary sca n-compatib le IC. IEEE 1149.1-compatibl e
devices may be serial daisy- chaine d toget her , connec ted in
parallel, or a combination of the two.

XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple­ment the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP can also s upport two USERCODE
instructions. When the boundary scan configuration option
is selected, three normal user I/O pins become dedicated
inputs for these functions. Another user output pin
becomes the dedicated boundary scan output.

Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. R etaining the bidirection al test capability
after configura tion provides flexibility for interconnect te st­ing.

Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused out­puts in IOBs used as unidirectional input pins. This tech­nique partially compensates for the lack of INTEST
support.

The user can serially load commands and data into these
devices to control the driving of their outputs and to exam­ine their inputs. This method is an improvement over
bed-of-nails testing. It avoids the need to over-drive device
outputs, and it reduces the user interface to four pins. An
optional fift h pin, a rese t for the c ontrol lo gic, is describe d in
the standard but is not implemented in Xilinx devices.

The dedicated on-chip logic implementing the IEEE 1149.1
functions in cl udes a 16- st a te machi n e, an ins tr uc t ion r eg i s­ter and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
discussed in the Xilinx application note XAPP 017:

“Bound-

ary Scan in XC4000 and XC5200 Series devices”

Figure 19 on page 99 is a diagram of the XC5200-Series

boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 11 49.1 Tes t Access Port controller, and
the Instruction Register with decodes.

The public boundary-scan instructions are always available
prior to confi gurati on. Afte r config uration, the pub lic ins truc­tions and any USERCODE instructions are only available if
specified in the design. While SAMPLE and BYPASS are
available during configuration, it is recommended that
boundary-scan operations not be performed during this
transitory period.

In addition to the test instructions outlined above, the
boundary-sca n circui try can be used t o config ure the FPGA
device, and to read back the configuration data.

All of the XC4000 boundary-scan modes are supported in
the XC5200 family. Three additional outputs for the User­Register are provided (Reset, Update, and Shift), repre-

7-98 November 5, 1998 (Version 5.2)

R

senting the decoding of the corresponding state of the
boundary-scan internal state machine.

XC5200 Series Field Programmable Gate Arrays

DATA IN

IOB IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

TDI

M
U

TDO

X

IOB

IOB

IOB

IOB

IOB

IOB

IOB IOB

IOB IOB IOB IOB IOB

IOB IOB IOB

BYPASS

REGISTER

INSTRUCTION REGISTER

INSTRUCTION REGISTER

BYPASS

REGISTER

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

1

D Q

0

IOB.O

IOB.T

IOB.I

IOB.O

M

TDO
U
X

TDI

IOB.T

IOB.I

IOB.O

SHIFT/

CAPTURE

1

D Q

0

1

D Q

0

1

D Q

0

1

D Q

0

1

D Q

0

1

D Q

0

DATAOUT UPDATE EXTEST

CLOCK DATA

REGISTER

sd

DQ

LE

sd

DQ

LE

sd

DQ

LE

sd

DQ

LE

sd

DQ

LE

sd

DQ

LE

sd

DQ

LE

1
0

0
1

1
0

1
0

0
1

1
0

0
1

7

X1523_01

Figure 19: XC5200-Series Boundary Scan Logic

November 5, 1998 (Version 5.2) 7-99

XC5200 Series Field Programmable Gate Arrays

R

XC5200-Seri es devi ces c an a lso be conf igu red t hrou gh t he
boundary scan logic. See XAPP 017 for more information.

Data Registers

The primary data register is the boundary scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In , Out and 3-State Contro l. Non-IOB pins
have appropriate partial bit population for In or Out only.
PROGRAM
boundary scan register. Each EXTEST CAPTURE-DR
state captur es all In, Out, and 3-State pins.

The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data regi ster. These three bound­ary scan bits are special-purp ose Xilinx te st sig na ls.

The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.

The FPGA provide s two additional data regis ters that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user ins truction s, USER1 an d USER2.
For these instructions, two corresponding pins
(BSCAN.TDO1 and B SCAN.TDO 2) allow user scan data to
be shifted out on TDO. The data register clock
(BSCAN.DRCK) is available fo r control of test logic which
the user may wish to implement with CLBs. The NAND of
TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

, CCLK and DONE are not included in the

Instruction Set

The XC5200-Series boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 7.

Table 7: Boundary Scan Instructions

Instruction I2

I1 I0

0 0 0 EXTEST DR DR
0 0 1 SAMPLE/PR

0 1 0 USER 1 BSCAN.

0 1 1 USER 2 BSCAN.

1 0 0 READBACK Readback

1 0 1 CONFIGURE DOUT Disabled
1 1 0 Reserved ——

1 1 1 BYPASS Bypass

Test

Selected

ELOAD

TDO Source

DR Pin/Logic

TDO1

TDO2

Data

Register

I/O Data

Source

User Logic

User Logic

Pin/Logic

—

Bit Sequence

The bit sequence within each IOB is: 3-State, Out, In. The
data-register cells for the TAP pins TMS, TCK, and TDI
have an OR-gate that permanently disables the output
buffer if boundary-scan operation is selected. Conse­quently , it is im possi ble for t he outp uts in IO Bs used b y TAP
inputs to conflict with TAP operation. TAP data is taken
directly from the pin, and cannot be overwritten by injected
boundary-scan data.

The primary global clock inputs (PGCK1-PGCK4) are
taken directl y f ro m t he pin s, a nd ca nno t be ov er wri tte n w i th
boundary-scan data. However, if necessary, it is possible to
drive the clock input from boundary scan. The external
clock source is 3-stated, and the clock net is driven with
boundary scan data through the output driver in the
clock-pad I OB. If t he cloc k-pad I OBs are u sed for non-cl ock
signals, the data may be overwritten normally.

Pull-up and pull-down resistors remain active during
boundary scan. Before and during configuration, all pins
are pulled up. After configuration, the choice of internal
pull-up or pull-down resistor must be taken into account
when designing test vectors to detect open-circuit PC
traces.

From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Ta ble 8 .
The device-specific pinout tables for the XC5200 Series
include the boundary scan locations for each IOB pin.

Table 8: Boundary Scan Bit Sequence

Bit Position I/O Pad Location

Bit 0 (TDO) Top-edge I/O pads (right to left)

Bit 1 ...

... Left-edge I/O pa ds (top to bottom)
... Bottom-edge I/O pads (left to right)
... Right-edge I/O pads (bottom to top)

Bit N (TDI) BSCANT.UPD

BSDL (Boundary Scan Description Language) files for
XC5200-Series devices are available on the Xilinx web site
in the File Download area.

Including Boundary Scan

If boundary sc an is o nly to be use d duri ng con fig urat ion, n o
special eleme nts nee d be incl uded i n the sch ematic or HDL
code. In this case, the special boundary scan pins TDI,
TMS, TCK and TDO can be used for user function s after
configuration.

T o in dicate that boundary scan remain enable d after conf ig­uration, incl ude the BSCAN library symbol and connect pad
symbols to the TDI, TMS, TCK and TDO pins, as shown in

Figure 20.

7-100 November 5, 1998 (Version 5.2)

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Figure 20: Boundary Scan Schematic Example

From

User Logic

Optional

TDI
TMS
TCK
TDO1
TDO2

IBUF

BSCAN

RESET

UPDATE

SHIFT

TDO

DRCK

IDLE
SEL1
SEL2

To User

Logic

To User
Logic

X9000

Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be rout ed to inter nal logic. C are must be take n not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep
TMS High, and then apply whatever signal is desired to TDI
and TCK.

XC5200 Series Field Programmable Gate Arrays

Typically, a 0.1 µF capacitor connected near the Vcc and
Ground pins of the package will provid e adequate decou ­pling.

Output buf fers capa ble of driv ing/sink ing the spe cified 8 mA
loads under specified worst-case conditio ns may be cap a­ble of driving/sinking up to 10 times as much current under
best case conditions.

Noise can be reduced by minimizing external load capaci­tance and reducing simultaneous output transitions in the
same direction. It may also be b eneficia l to loca te heav ily
loaded output buf fers ne ar t he Gro und p ads. The I/O Blo ck
output buffers have a slew-rate limited mode (default)
which should be used where output rise and fall times are
not speed-critical.

GND

Ground and
Vcc Ring for
I/O Drivers

Avoiding Inadvertent Boundary Sca n

If TMS or TCK is used as user I/O, care must be taken to
ensure that at le ast on e of th ese p ins is held co nsta nt du r­ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.

To prevent activation of boundary scan during configura­tion, do either of the following:

• TMS: Tie High to put the Test Access Port controller
in a benign RESET state

• TCK: Tie High or Low—do not toggle this clock input.

For more information regarding boundary scan, refer t o the
Xilinx Application Note XAPP 017, “

XC4000 and XC5200 Devices

.“

Boundary Scan in

Power Distribution

Power for the FPGA is di str ibute d thro ugh a gri d to achi eve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur­rounding the logic array provides power to the I/O drivers,
as shown in Figure 21. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.

This power distribu tion grid provides a stable supply an d
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.

Vcc

GND

Vcc

Logic
Power Grid

X5422

Figure 21: XC5200-Series Power Distribution

Pin Descriptions

There are three types of pins in the XC5200-Series
devices:

• Permanently dedicated pins

• User I/O pins that can have sp ecial functions

• Unrestricted user-programmable I/O pins.
Before and dur ing conf igurat ion, al l outpu ts not used fo r the

configuration process are 3-stated and pulled high with a
20 kΩ - 100 kΩ pull-up resistor.

After configuration, if an IOB is unused it is configured as
an input with a 20 kΩ - 100 kΩ pull-up resistor.

Device pins for XC5200-Series devices are described in

Ta ble 9. Pin functions during configuration for each of the

seven configuration modes are summarized in “Pin Func-

7

November 5, 1998 (Version 5.2) 7-101

XC5200 Series Field Programmable Gate Arrays

tions During Co nf igu ra ti o n” on p ag e 124, in the “Configura-

tion Timing” section.

Table 9: Pin Descriptions

R

I/O

After

Config. Pin Description

Pin Name

I/O

During

Config.

Permanently Dedicated Pins

Five or more (depe nding on package) connecti ons to th e nominal +5 V supply vo ltage.

VCC I I

All must be connected, and each mus t be decoupled with a 0.01 - 0.1 µF capacitor to
Ground.

GND I I

Four or more (de pending on package type) connectio ns to Ground. All must be con­nected.

During confi guration, Configuratio n Clock (CCLK) is an output in Ma ster modes or A syn­chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and

CCLK I or O I

can be selected as the Readback Clock. There is no CCLK High time restriction on
XC5200-Series devices, except during Readback. See “Violating the Maximum High

and Low Time Specif icatio n for the Read back Clo ck” on pag e 113 for an explanation of

this exception.
DONE is a bidire cti onal s ignal with an opt ional inter nal pull- up res isto r. As a n out put, it

indicates the completion of the configuration p r ocess. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-

DONE I/O O

puts.
The exact tim ing, the clock source for the Low-to-High transition, and the optional
pull-up resi stor are s elected as opti ons in the program t hat creat es the co nfigurat ion bit ­stream. The resistor is included by default.

PROGRAM

PROGRAM

II

ory. It is us ed t o i ni t iat e a co nf igur at i on cy cle . W he n PR OG RAM
executes a complete clear cycle, before it goes into a WAIT state and releases INIT

is an active Low input that forces the FP GA to clear its configuratio n mem-

The PROGRAM

User I/O Pins That Can Have Special Functions

During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-

RDY/BUSY

OI/O

chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY
RDY/BUSY

is pulled High with a high-impedance pull-up prior to INIT going High.

During Master Parallel configuration, each change on the A0-A17 outputs is preceded

RCLK

OI/O

by a rising edge on RCLK
PROMs. It is rarely used during configuration. After configuration, RCLK
grammable I/O pin.

As Mode inputs, these pins are sampl ed before the start of configuration to determine
the configu r ation mode to be used. After configuration, M0, M1, and M2 become us-

M0, M1, M2 I I/O

er-programmable I/O.
During configu ration, these pins hav e weak pull -up res istors. For the most popul ar con­figuration m ode, Slave Serial, the mode pin s can thus b e left un connecte d. A pull-d own
resistor value of 3.3 kΩ is recommended for other modes.

If boundary scan is used, this pi n is the Test D ata Outpu t. If boundar y scan i s not used,
this pin is a 3-state output, after configuration is completed.

TDO O O

This pin can be user output only when called out by specia l schematic defini tions. To
use this pin, pla ce the libra ry c ompon ent TDO inst ead of the us ual pad sy mbol. An o ut­put buffer must still be used.

goes High, the FPGA

.

pin has an optional weak pull-up after configuration.

is a user-programma ble I/O pi n.

, a redundant out put signal. RCLK is us eful for clocked

is a user-pro-

7-102 November 5, 1998 (Version 5.2)

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Table 9: Pin Descriptions (Continued)

XC5200 Series Field Programmable Gate Arrays

I/O

After

Config. Pin Description

I

(JTAG)

Pin Name

TDI, TCK,

TMS

During

Config.

HDC O I/O

LDC

INIT

GCK1 -

GCK4

CS0

WS

, CS1,

, RS

OI/O

I/O I/O

Weak

Pull-up

I or I/O

II/O

A0 - A17 O I/O

D0 - D7 I I/O

DIN I I/O

DOUT O I/O

I/O

If boundary scan is used, these pi ns are Test Data I n, Test Clock, and Test Mode Select
inputs respe ctively . They com e direct ly from t he pads, bypassing the IOBs . These pi ns
can also be used as inputs to the CLB lo gic after configuration is completed.

I/O

If the BSCAN symbo l is no t pl a ced i n t he de sig n, al l bou nd ar y s ca n fu nct i ons ar e i nhi b-

or I

ited once configuration is completed, and these pins become user-programmable I/O.
In this case, t hey must be called ou t by special sche matic definit ions. To use these pi ns,
place the l ibrary com ponen ts TDI , TCK, and TM S ins tead of th e us ual pa d sy mbols. In ­put or output buffers must still be used.

High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.

Low During Configuration (LDC

) is driven Low unt il the I/ O go activ e. It is av ailable as a

control out put indicating that configura tion is not yet completed. After configuration,

is a user-programmable I/O pin.

LDC
Before and d uring configur ation, INIT

is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT

is held Low during the power stabilization and
internal clearing of the configuration memory. As an ac tive-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configura tion. Master
mode devices stay in a WAIT state an addition al 50 to 250 µs after INIT

has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. Af ter the I/O go active, INIT

is a user-programmable I/O pin.

Four Global inputs each drive a dedicated internal global net with short delay and min­imal skew. These inter nal global net s can also be drive n from internal logic. If not use d
to drive a global net, any of these pi ns is a user-programmable I/O pin.
The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input
pad symbol connected directly to the input of a BUFG symbol is automatically placed on
one of these pins.

These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0
(WS
on Read Strobe (RS

is Low and CS1 is High. While the chip is selected, a Low on Write Strobe

) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low

) changes D7 in to a s ta tu s out pu t — H igh i f Read y , L ow i f Bu sy —
and drives D0 - D6 High.
In Express mode, CS1 is used as a seri al-enable signal for daisy-chaining.

and RS should be mutu ally exc lusive, but if b oth are Low si mult aneously , the Wr ite

WS
Strobe overrides. After configuration, these ar e user-programmabl e I/O pins.

During Master Parallel configuration, these 18 output pins address the configuration
EPROM. After configuration, they are user-programma ble I/O pins.

During Master Parallel , Perip heral, a nd Expres s conf igurati on, thes e eight i nput pins re­ceive configuration data. After configuration, they are user-programmable I/O pins.

During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configurati on, DIN is a user-programmable I/O pin.

During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of dais y-chain ed slav e FPGAs. DOUT dat a chan ges
on the falling edge of CCLK.
In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enabl e and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.

7

November 5, 1998 (Version 5.2) 7-103

XC5200 Series Field Programmable Gate Arrays

Table 9: Pin Descriptions (Continued)

R

I/O

During

Pin Name

Unrestricted User-Programmable I/O Pins

I/O

Config.

Weak

Pull-up

I/O

After

Config. Pin Description

These pins ca n be configur ed to be inp ut and/or ou tput after c onfigurat ion is comple ted.

I/O

Before confi guration is co mpleted, these pi ns have an internal high-value pull-up resis­tor (20 kΩ - 100 kΩ) that defines the logic level as High.

Configuration

Configuration is the proc ess of loading design-specific pro­gramming dat a into one or more FPGAs to define the fu nc­tional operation of the internal blocks and their
interconnections. T his is somewhat like loading the com­mand registers of a programmable peripheral chip.
XC5200-Series dev ic es use s e ve ral hun dr ed b i ts o f c on fig ­uration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls e i th er a f un ct ion loo k- u p t ab le b i t, a m u lti­plexer input, or an interconnect pass transistor. The devel­opment system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.

Special Purpose Pins

Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary I/O
connections. The development system does not use these
resources unless they are explicitly specified in the design
entry. This is done by placing a special pad symbol called
MD2, MD1, or MD0 instead of the input or output pad sym­bol.

In XC5200-Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Sl ave S e rial m ode is se lec te d, whi c h is t he m ost
popular configuration mode. Therefore, for the most com­mon configuration mode, the mode pins can be left uncon­nected. (Note, howeve r, that the int ernal pull-up resistor
value can be as high as 100 k Ω.) After configuratio n, th ese
pins can individually have weak pull-up or pull-down resis­tors, as specified in the design. A pull-down resistor value
of 3.3kΩ is recommended.

These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.

Configuratio n Modes

XC5200 devices have seven configuration modes. These
modes are sel ected b y a 3 -bit input cod e appli ed t o th e M2,

M1, and M0 inputs . There are thr ee self-loading Master
modes, two Periph er a l modes, and a Serial Slave mo d e,

Table 10: Configuration Modes

Mode M2 M1 M0 CCLK Data

Master Serial 0 0 0 output Bit-Serial
Slave Serial 1 1 1 input Bit-Serial
Master

Parallel Up

Master
Parallel Down

Peripheral
Synchronous*

Peripheral
Asynchronous

Express 0 1 0 input Byte-Wide
Reserved 001 ——

Note :*Peripheral Synchronous can be considered byte-wide
Slave Parallel

which is use d prim ari ly f o r d ai sy -c ha i ned dev i ce s. T he se v­enth mode, called Express mode, is an additional slave
mode that allows high-speed parallel configuration. The
coding for mode selection is sh own in Table 10.

Note that the smallest package, VQ64, only supports the
Master Serial, Slave Serial, and Express modes.A det ailed
description of each configuration mode, with timing infor­mation, is included la ter in t his da ta sh eet. Du ring configu ­ration, some of the I/O pins are used temporarily for the
configuration process. All pins used during configuration
are shown in Table 13 on page 124.

1 0 0 output Byte-Wide,

increment

from 00000

1 1 0 output Byte-Wide,

decrement

from 3FFFF

0 1 1 input Byte-Wide

1 0 1 output Byte-Wide

Master Modes

The three Master modes use an internal oscillator to gener­ate a Configur ati on Cl ock ( CCLK) for dri ving pote nti al sl ave
devices. They also generate address and timing for exter­nal PROM(s) containing the config uration data.

Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel
data. The data is internally serialized into the FPGA
data-frame format. The up and down selection generates
starting addresses at either zero or 3FFFF , for compatibility
with different microprocessor addressing conventions. The

7-104 November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Master Seria l mode gener ates CCLK and r ecei ves t he c on­figuration data in serial f orm from a Xilinx s erial-co nfigura­tion PROM.

CCLK speed is sel ectabl e as 1 M Hz (def ault) , 6 MHz, or 12
MHz. Configuration always starts at the default slow fre­quency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +50%.

Peripheral Modes

The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY
nal. In Asynchronous Peripheral mode, the internal oscilla­tor generates a CCLK burst signal that serializes the
byte-wide dat a. CCLK can al s o dr iv e s lav e de vi ce s. I n t he
synchronous mode, an externally supplied clock input to
CCLK serializes the data.

status is available as a handshake sig-

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial configura­tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.

Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.

Serial Daisy Chain

Multiple devices with different configurations can be con-

nected together in a “daisy c hain,” and a s ingle combine d
bitstream used to configure the chain of slave devices.

To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 28 on page

114. Connect the DOUT of each device to the DIN of the

next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its re quired number of data frames.

After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied afte r memory initializa tion equals the value
of the 24-bit length count, the FPGA s begin the start-up
sequence and become operational together. FPGA I/O are
normally rel eased two CCLK cycl es after the la st confi gura­tion bit is received. Figure 25 on page 109 shows the
start-up timing for an XC5200-Series device.

The daisy-chained bitstream is not simply a concatenation
of the individual bitstr eam s. T he PR OM f ile fo rma tter must
be used to combin e t he bit str eams f or a dai sy-c hained con ­figuration.

Multi-Family Daisy Chain

All Xilinx FPGAs of the XC2000, XC3000, XC4000, and
XC5200 Series use a compa tib le bi tstre am fo rmat and can,
therefore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. If the chain
contains XC5 200 -Se ri es d ev i ce s, t h e ma st e r n orm all y can­not be an XC2000 or XC3000 device.

The reason for t his r ule i s show n in F igur e25 on page 109.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of

Figure 25. The master device then generates additional

CCLK pulses until it reaches its finish point F. The diff erent
families generate or require different numbers of additional
CCLK pulses until they reac h F. Not reaching F me ans that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the
XC5200-Series device, not reaching F means that read­back cannot be initiated and most boundary scan instruc­tions cannot be used.

The user has some control over the relative timing of these
events and can , there fore , make sure that they occur a t th e
proper time and the finish point F is reached . Timi ng is con­trolled using options in the bitstream generation software.

XC5200 devices always have the same number of CCLKs
in the power up delay, independent of the configuration
mode, unlike t he XC3 000/ XC400 0 Ser ies d evice s. To guar­antee all devices in a daisy chain have finished the
power-up delay, tie the INIT pins together, as shown in

Figure 27.

XC3000 Master with an XC5200-Series Slave

Some designers want to use an XC3000 lead device in
peripheral mode and have the I/O pins of the
XC5200-Series devices all available for user I/O. Figure 22
provides a solution for that case.

This solution requires one CLB, one IOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be config­ured with late Internal Reset, which is the default option.

One CLB and one IOB in the lead XC3000-family device
are used to generat e the addition al CCLK pulse required by
the XC5200-Series devices. When the lead device
removes the internal RESET signal, the 2-bit shift register
responds to its clock input and generates an active Low
output signal for the duration of the subsequent clock
period. An exte rnal connection between this output and
CCLK thus creates the extra CCLK pulse.

7

November 5, 1998 (Version 5.2) 7-105